meson_spifc.c 8.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
  4. * Copyright (C) 2018 BayLibre, SAS
  5. * Author: Neil Armstrong <narmstrong@baylibre.com>
  6. *
  7. * Amlogic Meson SPI Flash Controller driver
  8. */
  9. #include <common.h>
  10. #include <log.h>
  11. #include <spi.h>
  12. #include <clk.h>
  13. #include <dm.h>
  14. #include <regmap.h>
  15. #include <errno.h>
  16. #include <asm/io.h>
  17. #include <linux/bitfield.h>
  18. #include <linux/bitops.h>
  19. /* register map */
  20. #define REG_CMD 0x00
  21. #define REG_ADDR 0x04
  22. #define REG_CTRL 0x08
  23. #define REG_CTRL1 0x0c
  24. #define REG_STATUS 0x10
  25. #define REG_CTRL2 0x14
  26. #define REG_CLOCK 0x18
  27. #define REG_USER 0x1c
  28. #define REG_USER1 0x20
  29. #define REG_USER2 0x24
  30. #define REG_USER3 0x28
  31. #define REG_USER4 0x2c
  32. #define REG_SLAVE 0x30
  33. #define REG_SLAVE1 0x34
  34. #define REG_SLAVE2 0x38
  35. #define REG_SLAVE3 0x3c
  36. #define REG_C0 0x40
  37. #define REG_B8 0x60
  38. #define REG_MAX 0x7c
  39. /* register fields */
  40. #define CMD_USER BIT(18)
  41. #define CTRL_ENABLE_AHB BIT(17)
  42. #define CLOCK_SOURCE BIT(31)
  43. #define CLOCK_DIV_SHIFT 12
  44. #define CLOCK_DIV_MASK (0x3f << CLOCK_DIV_SHIFT)
  45. #define CLOCK_CNT_HIGH_SHIFT 6
  46. #define CLOCK_CNT_HIGH_MASK (0x3f << CLOCK_CNT_HIGH_SHIFT)
  47. #define CLOCK_CNT_LOW_SHIFT 0
  48. #define CLOCK_CNT_LOW_MASK (0x3f << CLOCK_CNT_LOW_SHIFT)
  49. #define USER_DIN_EN_MS BIT(0)
  50. #define USER_CMP_MODE BIT(2)
  51. #define USER_CLK_NOT_INV BIT(7)
  52. #define USER_UC_DOUT_SEL BIT(27)
  53. #define USER_UC_DIN_SEL BIT(28)
  54. #define USER_UC_MASK ((BIT(5) - 1) << 27)
  55. #define USER1_BN_UC_DOUT_SHIFT 17
  56. #define USER1_BN_UC_DOUT_MASK (0xff << 16)
  57. #define USER1_BN_UC_DIN_SHIFT 8
  58. #define USER1_BN_UC_DIN_MASK (0xff << 8)
  59. #define USER4_CS_POL_HIGH BIT(23)
  60. #define USER4_IDLE_CLK_HIGH BIT(29)
  61. #define USER4_CS_ACT BIT(30)
  62. #define SLAVE_TRST_DONE BIT(4)
  63. #define SLAVE_OP_MODE BIT(30)
  64. #define SLAVE_SW_RST BIT(31)
  65. #define SPIFC_BUFFER_SIZE 64
  66. struct meson_spifc_priv {
  67. struct regmap *regmap;
  68. struct clk clk;
  69. };
  70. /**
  71. * meson_spifc_drain_buffer() - copy data from device buffer to memory
  72. * @spifc: the Meson SPI device
  73. * @buf: the destination buffer
  74. * @len: number of bytes to copy
  75. */
  76. static void meson_spifc_drain_buffer(struct meson_spifc_priv *spifc,
  77. u8 *buf, int len)
  78. {
  79. u32 data;
  80. int i = 0;
  81. while (i < len) {
  82. regmap_read(spifc->regmap, REG_C0 + i, &data);
  83. if (len - i >= 4) {
  84. *((u32 *)buf) = data;
  85. buf += 4;
  86. } else {
  87. memcpy(buf, &data, len - i);
  88. break;
  89. }
  90. i += 4;
  91. }
  92. }
  93. /**
  94. * meson_spifc_fill_buffer() - copy data from memory to device buffer
  95. * @spifc: the Meson SPI device
  96. * @buf: the source buffer
  97. * @len: number of bytes to copy
  98. */
  99. static void meson_spifc_fill_buffer(struct meson_spifc_priv *spifc,
  100. const u8 *buf, int len)
  101. {
  102. u32 data = 0;
  103. int i = 0;
  104. while (i < len) {
  105. if (len - i >= 4)
  106. data = *(u32 *)buf;
  107. else
  108. memcpy(&data, buf, len - i);
  109. regmap_write(spifc->regmap, REG_C0 + i, data);
  110. buf += 4;
  111. i += 4;
  112. }
  113. }
  114. /**
  115. * meson_spifc_txrx() - transfer a chunk of data
  116. * @spifc: the Meson SPI device
  117. * @dout: data buffer for TX
  118. * @din: data buffer for RX
  119. * @offset: offset of the data to transfer
  120. * @len: length of the data to transfer
  121. * @last_xfer: whether this is the last transfer of the message
  122. * @last_chunk: whether this is the last chunk of the transfer
  123. * Return: 0 on success, a negative value on error
  124. */
  125. static int meson_spifc_txrx(struct meson_spifc_priv *spifc,
  126. const u8 *dout, u8 *din, int offset,
  127. int len, bool last_xfer, bool last_chunk)
  128. {
  129. bool keep_cs = true;
  130. u32 data;
  131. int ret;
  132. if (dout)
  133. meson_spifc_fill_buffer(spifc, dout + offset, len);
  134. /* enable DOUT stage */
  135. regmap_update_bits(spifc->regmap, REG_USER, USER_UC_MASK,
  136. USER_UC_DOUT_SEL);
  137. regmap_write(spifc->regmap, REG_USER1,
  138. (8 * len - 1) << USER1_BN_UC_DOUT_SHIFT);
  139. /* enable data input during DOUT */
  140. regmap_update_bits(spifc->regmap, REG_USER, USER_DIN_EN_MS,
  141. USER_DIN_EN_MS);
  142. if (last_chunk && last_xfer)
  143. keep_cs = false;
  144. regmap_update_bits(spifc->regmap, REG_USER4, USER4_CS_ACT,
  145. keep_cs ? USER4_CS_ACT : 0);
  146. /* clear transition done bit */
  147. regmap_update_bits(spifc->regmap, REG_SLAVE, SLAVE_TRST_DONE, 0);
  148. /* start transfer */
  149. regmap_update_bits(spifc->regmap, REG_CMD, CMD_USER, CMD_USER);
  150. /* wait for the current operation to terminate */
  151. ret = regmap_read_poll_timeout(spifc->regmap, REG_SLAVE, data,
  152. (data & SLAVE_TRST_DONE),
  153. 0, 5 * CONFIG_SYS_HZ);
  154. if (!ret && din)
  155. meson_spifc_drain_buffer(spifc, din + offset, len);
  156. return ret;
  157. }
  158. /**
  159. * meson_spifc_xfer() - perform a single transfer
  160. * @dev: the SPI controller device
  161. * @bitlen: length of the transfer
  162. * @dout: data buffer for TX
  163. * @din: data buffer for RX
  164. * @flags: transfer flags
  165. * Return: 0 on success, a negative value on error
  166. */
  167. static int meson_spifc_xfer(struct udevice *slave, unsigned int bitlen,
  168. const void *dout, void *din, unsigned long flags)
  169. {
  170. struct meson_spifc_priv *spifc = dev_get_priv(slave->parent);
  171. int blen = bitlen / 8;
  172. int len, done = 0, ret = 0;
  173. if (bitlen % 8)
  174. return -EINVAL;
  175. debug("xfer len %d (%d) dout %p din %p\n", bitlen, blen, dout, din);
  176. regmap_update_bits(spifc->regmap, REG_CTRL, CTRL_ENABLE_AHB, 0);
  177. while (done < blen && !ret) {
  178. len = min_t(int, blen - done, SPIFC_BUFFER_SIZE);
  179. ret = meson_spifc_txrx(spifc, dout, din, done, len,
  180. flags & SPI_XFER_END,
  181. done + len >= blen);
  182. done += len;
  183. }
  184. regmap_update_bits(spifc->regmap, REG_CTRL, CTRL_ENABLE_AHB,
  185. CTRL_ENABLE_AHB);
  186. return ret;
  187. }
  188. /**
  189. * meson_spifc_set_speed() - program the clock divider
  190. * @dev: the SPI controller device
  191. * @speed: desired speed in Hz
  192. */
  193. static int meson_spifc_set_speed(struct udevice *dev, uint speed)
  194. {
  195. struct meson_spifc_priv *spifc = dev_get_priv(dev);
  196. unsigned long parent, value;
  197. int n;
  198. parent = clk_get_rate(&spifc->clk);
  199. n = max_t(int, parent / speed - 1, 1);
  200. debug("parent %lu, speed %u, n %d\n", parent, speed, n);
  201. value = (n << CLOCK_DIV_SHIFT) & CLOCK_DIV_MASK;
  202. value |= (n << CLOCK_CNT_LOW_SHIFT) & CLOCK_CNT_LOW_MASK;
  203. value |= (((n + 1) / 2 - 1) << CLOCK_CNT_HIGH_SHIFT) &
  204. CLOCK_CNT_HIGH_MASK;
  205. regmap_write(spifc->regmap, REG_CLOCK, value);
  206. return 0;
  207. }
  208. /**
  209. * meson_spifc_set_mode() - setups the SPI bus mode
  210. * @dev: the SPI controller device
  211. * @mode: desired mode bitfield
  212. * Return: 0 on success, -ENODEV on error
  213. */
  214. static int meson_spifc_set_mode(struct udevice *dev, uint mode)
  215. {
  216. struct meson_spifc_priv *spifc = dev_get_priv(dev);
  217. if (mode & (SPI_CPHA | SPI_RX_QUAD | SPI_RX_DUAL |
  218. SPI_TX_QUAD | SPI_TX_DUAL))
  219. return -ENODEV;
  220. regmap_update_bits(spifc->regmap, REG_USER, USER_CLK_NOT_INV,
  221. mode & SPI_CPOL ? USER_CLK_NOT_INV : 0);
  222. regmap_update_bits(spifc->regmap, REG_USER4, USER4_CS_POL_HIGH,
  223. mode & SPI_CS_HIGH ? USER4_CS_POL_HIGH : 0);
  224. return 0;
  225. }
  226. /**
  227. * meson_spifc_hw_init() - reset and initialize the SPI controller
  228. * @spifc: the Meson SPI device
  229. */
  230. static void meson_spifc_hw_init(struct meson_spifc_priv *spifc)
  231. {
  232. /* reset device */
  233. regmap_update_bits(spifc->regmap, REG_SLAVE, SLAVE_SW_RST,
  234. SLAVE_SW_RST);
  235. /* disable compatible mode */
  236. regmap_update_bits(spifc->regmap, REG_USER, USER_CMP_MODE, 0);
  237. /* set master mode */
  238. regmap_update_bits(spifc->regmap, REG_SLAVE, SLAVE_OP_MODE, 0);
  239. }
  240. static const struct dm_spi_ops meson_spifc_ops = {
  241. .xfer = meson_spifc_xfer,
  242. .set_speed = meson_spifc_set_speed,
  243. .set_mode = meson_spifc_set_mode,
  244. };
  245. static int meson_spifc_probe(struct udevice *dev)
  246. {
  247. struct meson_spifc_priv *priv = dev_get_priv(dev);
  248. int ret;
  249. ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap);
  250. if (ret)
  251. return ret;
  252. ret = clk_get_by_index(dev, 0, &priv->clk);
  253. if (ret)
  254. return ret;
  255. ret = clk_enable(&priv->clk);
  256. if (ret)
  257. return ret;
  258. meson_spifc_hw_init(priv);
  259. return 0;
  260. }
  261. static const struct udevice_id meson_spifc_ids[] = {
  262. { .compatible = "amlogic,meson-gxbb-spifc", },
  263. { }
  264. };
  265. U_BOOT_DRIVER(meson_spifc) = {
  266. .name = "meson_spifc",
  267. .id = UCLASS_SPI,
  268. .of_match = meson_spifc_ids,
  269. .ops = &meson_spifc_ops,
  270. .probe = meson_spifc_probe,
  271. .priv_auto_alloc_size = sizeof(struct meson_spifc_priv),
  272. };