kirkwood_spi.c 7.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2009
  4. * Marvell Semiconductor <www.marvell.com>
  5. * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  6. *
  7. * Derived from drivers/spi/mpc8xxx_spi.c
  8. */
  9. #include <common.h>
  10. #include <dm.h>
  11. #include <log.h>
  12. #include <malloc.h>
  13. #include <spi.h>
  14. #include <asm/io.h>
  15. #include <asm/arch/soc.h>
  16. #ifdef CONFIG_ARCH_KIRKWOOD
  17. #include <asm/arch/mpp.h>
  18. #endif
  19. #include <asm/arch-mvebu/spi.h>
  20. struct mvebu_spi_dev {
  21. bool is_errata_50mhz_ac;
  22. };
  23. struct mvebu_spi_platdata {
  24. struct kwspi_registers *spireg;
  25. bool is_errata_50mhz_ac;
  26. };
  27. struct mvebu_spi_priv {
  28. struct kwspi_registers *spireg;
  29. };
  30. static void _spi_cs_activate(struct kwspi_registers *reg)
  31. {
  32. setbits_le32(&reg->ctrl, KWSPI_CSN_ACT);
  33. }
  34. static void _spi_cs_deactivate(struct kwspi_registers *reg)
  35. {
  36. clrbits_le32(&reg->ctrl, KWSPI_CSN_ACT);
  37. }
  38. static int _spi_xfer(struct kwspi_registers *reg, unsigned int bitlen,
  39. const void *dout, void *din, unsigned long flags)
  40. {
  41. unsigned int tmpdout, tmpdin;
  42. int tm, isread = 0;
  43. debug("spi_xfer: dout %p din %p bitlen %u\n", dout, din, bitlen);
  44. if (flags & SPI_XFER_BEGIN)
  45. _spi_cs_activate(reg);
  46. /*
  47. * handle data in 8-bit chunks
  48. * TBD: 2byte xfer mode to be enabled
  49. */
  50. clrsetbits_le32(&reg->cfg, KWSPI_XFERLEN_MASK, KWSPI_XFERLEN_1BYTE);
  51. while (bitlen > 4) {
  52. debug("loopstart bitlen %d\n", bitlen);
  53. tmpdout = 0;
  54. /* Shift data so it's msb-justified */
  55. if (dout)
  56. tmpdout = *(u32 *)dout & 0xff;
  57. clrbits_le32(&reg->irq_cause, KWSPI_SMEMRDIRQ);
  58. writel(tmpdout, &reg->dout); /* Write the data out */
  59. debug("*** spi_xfer: ... %08x written, bitlen %d\n",
  60. tmpdout, bitlen);
  61. /*
  62. * Wait for SPI transmit to get out
  63. * or time out (1 second = 1000 ms)
  64. * The NE event must be read and cleared first
  65. */
  66. for (tm = 0, isread = 0; tm < KWSPI_TIMEOUT; ++tm) {
  67. if (readl(&reg->irq_cause) & KWSPI_SMEMRDIRQ) {
  68. isread = 1;
  69. tmpdin = readl(&reg->din);
  70. debug("spi_xfer: din %p..%08x read\n",
  71. din, tmpdin);
  72. if (din) {
  73. *((u8 *)din) = (u8)tmpdin;
  74. din += 1;
  75. }
  76. if (dout)
  77. dout += 1;
  78. bitlen -= 8;
  79. }
  80. if (isread)
  81. break;
  82. }
  83. if (tm >= KWSPI_TIMEOUT)
  84. printf("*** spi_xfer: Time out during SPI transfer\n");
  85. debug("loopend bitlen %d\n", bitlen);
  86. }
  87. if (flags & SPI_XFER_END)
  88. _spi_cs_deactivate(reg);
  89. return 0;
  90. }
  91. static int mvebu_spi_set_speed(struct udevice *bus, uint hz)
  92. {
  93. struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
  94. struct kwspi_registers *reg = plat->spireg;
  95. u32 data;
  96. /* calculate spi clock prescaller using max_hz */
  97. data = ((CONFIG_SYS_TCLK / 2) / hz) + 0x10;
  98. data = data < KWSPI_CLKPRESCL_MIN ? KWSPI_CLKPRESCL_MIN : data;
  99. data = data > KWSPI_CLKPRESCL_MASK ? KWSPI_CLKPRESCL_MASK : data;
  100. /* program spi clock prescaler using max_hz */
  101. writel(KWSPI_ADRLEN_3BYTE | data, &reg->cfg);
  102. debug("data = 0x%08x\n", data);
  103. return 0;
  104. }
  105. static void mvebu_spi_50mhz_ac_timing_erratum(struct udevice *bus, uint mode)
  106. {
  107. struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
  108. struct kwspi_registers *reg = plat->spireg;
  109. u32 data;
  110. /*
  111. * Erratum description: (Erratum NO. FE-9144572) The device
  112. * SPI interface supports frequencies of up to 50 MHz.
  113. * However, due to this erratum, when the device core clock is
  114. * 250 MHz and the SPI interfaces is configured for 50MHz SPI
  115. * clock and CPOL=CPHA=1 there might occur data corruption on
  116. * reads from the SPI device.
  117. * Erratum Workaround:
  118. * Work in one of the following configurations:
  119. * 1. Set CPOL=CPHA=0 in "SPI Interface Configuration
  120. * Register".
  121. * 2. Set TMISO_SAMPLE value to 0x2 in "SPI Timing Parameters 1
  122. * Register" before setting the interface.
  123. */
  124. data = readl(&reg->timing1);
  125. data &= ~KW_SPI_TMISO_SAMPLE_MASK;
  126. if (CONFIG_SYS_TCLK == 250000000 &&
  127. mode & SPI_CPOL &&
  128. mode & SPI_CPHA)
  129. data |= KW_SPI_TMISO_SAMPLE_2;
  130. else
  131. data |= KW_SPI_TMISO_SAMPLE_1;
  132. writel(data, &reg->timing1);
  133. }
  134. static int mvebu_spi_set_mode(struct udevice *bus, uint mode)
  135. {
  136. struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
  137. struct kwspi_registers *reg = plat->spireg;
  138. u32 data = readl(&reg->cfg);
  139. data &= ~(KWSPI_CPHA | KWSPI_CPOL | KWSPI_RXLSBF | KWSPI_TXLSBF);
  140. if (mode & SPI_CPHA)
  141. data |= KWSPI_CPHA;
  142. if (mode & SPI_CPOL)
  143. data |= KWSPI_CPOL;
  144. if (mode & SPI_LSB_FIRST)
  145. data |= (KWSPI_RXLSBF | KWSPI_TXLSBF);
  146. writel(data, &reg->cfg);
  147. if (plat->is_errata_50mhz_ac)
  148. mvebu_spi_50mhz_ac_timing_erratum(bus, mode);
  149. return 0;
  150. }
  151. static int mvebu_spi_xfer(struct udevice *dev, unsigned int bitlen,
  152. const void *dout, void *din, unsigned long flags)
  153. {
  154. struct udevice *bus = dev->parent;
  155. struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
  156. return _spi_xfer(plat->spireg, bitlen, dout, din, flags);
  157. }
  158. __attribute__((weak)) int mvebu_board_spi_claim_bus(struct udevice *dev)
  159. {
  160. return 0;
  161. }
  162. static int mvebu_spi_claim_bus(struct udevice *dev)
  163. {
  164. struct udevice *bus = dev->parent;
  165. struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
  166. /* Configure the chip-select in the CTRL register */
  167. clrsetbits_le32(&plat->spireg->ctrl,
  168. KWSPI_CS_MASK << KWSPI_CS_SHIFT,
  169. spi_chip_select(dev) << KWSPI_CS_SHIFT);
  170. return mvebu_board_spi_claim_bus(dev);
  171. }
  172. __attribute__((weak)) int mvebu_board_spi_release_bus(struct udevice *dev)
  173. {
  174. return 0;
  175. }
  176. static int mvebu_spi_release_bus(struct udevice *dev)
  177. {
  178. return mvebu_board_spi_release_bus(dev);
  179. }
  180. static int mvebu_spi_probe(struct udevice *bus)
  181. {
  182. struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
  183. struct kwspi_registers *reg = plat->spireg;
  184. writel(KWSPI_SMEMRDY, &reg->ctrl);
  185. writel(KWSPI_SMEMRDIRQ, &reg->irq_cause);
  186. writel(KWSPI_IRQMASK, &reg->irq_mask);
  187. return 0;
  188. }
  189. static int mvebu_spi_ofdata_to_platdata(struct udevice *bus)
  190. {
  191. struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
  192. const struct mvebu_spi_dev *drvdata =
  193. (struct mvebu_spi_dev *)dev_get_driver_data(bus);
  194. plat->spireg = dev_read_addr_ptr(bus);
  195. plat->is_errata_50mhz_ac = drvdata->is_errata_50mhz_ac;
  196. return 0;
  197. }
  198. static const struct dm_spi_ops mvebu_spi_ops = {
  199. .claim_bus = mvebu_spi_claim_bus,
  200. .release_bus = mvebu_spi_release_bus,
  201. .xfer = mvebu_spi_xfer,
  202. .set_speed = mvebu_spi_set_speed,
  203. .set_mode = mvebu_spi_set_mode,
  204. /*
  205. * cs_info is not needed, since we require all chip selects to be
  206. * in the device tree explicitly
  207. */
  208. };
  209. static const struct mvebu_spi_dev armada_spi_dev_data = {
  210. .is_errata_50mhz_ac = false,
  211. };
  212. static const struct mvebu_spi_dev armada_xp_spi_dev_data = {
  213. .is_errata_50mhz_ac = false,
  214. };
  215. static const struct mvebu_spi_dev armada_375_spi_dev_data = {
  216. .is_errata_50mhz_ac = false,
  217. };
  218. static const struct mvebu_spi_dev armada_380_spi_dev_data = {
  219. .is_errata_50mhz_ac = true,
  220. };
  221. static const struct udevice_id mvebu_spi_ids[] = {
  222. {
  223. .compatible = "marvell,orion-spi",
  224. .data = (ulong)&armada_spi_dev_data,
  225. },
  226. {
  227. .compatible = "marvell,armada-375-spi",
  228. .data = (ulong)&armada_375_spi_dev_data
  229. },
  230. {
  231. .compatible = "marvell,armada-380-spi",
  232. .data = (ulong)&armada_380_spi_dev_data
  233. },
  234. {
  235. .compatible = "marvell,armada-xp-spi",
  236. .data = (ulong)&armada_xp_spi_dev_data
  237. },
  238. { }
  239. };
  240. U_BOOT_DRIVER(mvebu_spi) = {
  241. .name = "mvebu_spi",
  242. .id = UCLASS_SPI,
  243. .of_match = mvebu_spi_ids,
  244. .ops = &mvebu_spi_ops,
  245. .ofdata_to_platdata = mvebu_spi_ofdata_to_platdata,
  246. .platdata_auto_alloc_size = sizeof(struct mvebu_spi_platdata),
  247. .priv_auto_alloc_size = sizeof(struct mvebu_spi_priv),
  248. .probe = mvebu_spi_probe,
  249. };