ich.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2011-12 The Chromium OS Authors.
  4. *
  5. * This file is derived from the flashrom project.
  6. */
  7. #define LOG_CATEGORY UCLASS_SPI
  8. #include <common.h>
  9. #include <bootstage.h>
  10. #include <div64.h>
  11. #include <dm.h>
  12. #include <dt-structs.h>
  13. #include <errno.h>
  14. #include <log.h>
  15. #include <malloc.h>
  16. #include <pch.h>
  17. #include <pci.h>
  18. #include <pci_ids.h>
  19. #include <spi.h>
  20. #include <spi_flash.h>
  21. #include <spi-mem.h>
  22. #include <spl.h>
  23. #include <asm/fast_spi.h>
  24. #include <asm/io.h>
  25. #include <dm/uclass-internal.h>
  26. #include <asm/mtrr.h>
  27. #include <linux/bitops.h>
  28. #include <linux/delay.h>
  29. #include <linux/sizes.h>
  30. #include "ich.h"
  31. #ifdef DEBUG_TRACE
  32. #define debug_trace(fmt, args...) debug(fmt, ##args)
  33. #else
  34. #define debug_trace(x, args...)
  35. #endif
  36. struct ich_spi_platdata {
  37. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  38. struct dtd_intel_fast_spi dtplat;
  39. #endif
  40. enum ich_version ich_version; /* Controller version, 7 or 9 */
  41. bool lockdown; /* lock down controller settings? */
  42. ulong mmio_base; /* Base of MMIO registers */
  43. pci_dev_t bdf; /* PCI address used by of-platdata */
  44. bool hwseq; /* Use hardware sequencing (not s/w) */
  45. };
  46. static u8 ich_readb(struct ich_spi_priv *priv, int reg)
  47. {
  48. u8 value = readb(priv->base + reg);
  49. debug_trace("read %2.2x from %4.4x\n", value, reg);
  50. return value;
  51. }
  52. static u16 ich_readw(struct ich_spi_priv *priv, int reg)
  53. {
  54. u16 value = readw(priv->base + reg);
  55. debug_trace("read %4.4x from %4.4x\n", value, reg);
  56. return value;
  57. }
  58. static u32 ich_readl(struct ich_spi_priv *priv, int reg)
  59. {
  60. u32 value = readl(priv->base + reg);
  61. debug_trace("read %8.8x from %4.4x\n", value, reg);
  62. return value;
  63. }
  64. static void ich_writeb(struct ich_spi_priv *priv, u8 value, int reg)
  65. {
  66. writeb(value, priv->base + reg);
  67. debug_trace("wrote %2.2x to %4.4x\n", value, reg);
  68. }
  69. static void ich_writew(struct ich_spi_priv *priv, u16 value, int reg)
  70. {
  71. writew(value, priv->base + reg);
  72. debug_trace("wrote %4.4x to %4.4x\n", value, reg);
  73. }
  74. static void ich_writel(struct ich_spi_priv *priv, u32 value, int reg)
  75. {
  76. writel(value, priv->base + reg);
  77. debug_trace("wrote %8.8x to %4.4x\n", value, reg);
  78. }
  79. static void write_reg(struct ich_spi_priv *priv, const void *value,
  80. int dest_reg, uint32_t size)
  81. {
  82. memcpy_toio(priv->base + dest_reg, value, size);
  83. }
  84. static void read_reg(struct ich_spi_priv *priv, int src_reg, void *value,
  85. uint32_t size)
  86. {
  87. memcpy_fromio(value, priv->base + src_reg, size);
  88. }
  89. static void ich_set_bbar(struct ich_spi_priv *ctlr, uint32_t minaddr)
  90. {
  91. const uint32_t bbar_mask = 0x00ffff00;
  92. uint32_t ichspi_bbar;
  93. if (ctlr->bbar) {
  94. minaddr &= bbar_mask;
  95. ichspi_bbar = ich_readl(ctlr, ctlr->bbar) & ~bbar_mask;
  96. ichspi_bbar |= minaddr;
  97. ich_writel(ctlr, ichspi_bbar, ctlr->bbar);
  98. }
  99. }
  100. /* @return 1 if the SPI flash supports the 33MHz speed */
  101. static bool ich9_can_do_33mhz(struct udevice *dev)
  102. {
  103. struct ich_spi_priv *priv = dev_get_priv(dev);
  104. u32 fdod, speed;
  105. if (!CONFIG_IS_ENABLED(PCI))
  106. return false;
  107. /* Observe SPI Descriptor Component Section 0 */
  108. dm_pci_write_config32(priv->pch, 0xb0, 0x1000);
  109. /* Extract the Write/Erase SPI Frequency from descriptor */
  110. dm_pci_read_config32(priv->pch, 0xb4, &fdod);
  111. /* Bits 23:21 have the fast read clock frequency, 0=20MHz, 1=33MHz */
  112. speed = (fdod >> 21) & 7;
  113. return speed == 1;
  114. }
  115. static void spi_lock_down(struct ich_spi_platdata *plat, void *sbase)
  116. {
  117. if (plat->ich_version == ICHV_7) {
  118. struct ich7_spi_regs *ich7_spi = sbase;
  119. setbits_le16(&ich7_spi->spis, SPIS_LOCK);
  120. } else if (plat->ich_version == ICHV_9) {
  121. struct ich9_spi_regs *ich9_spi = sbase;
  122. setbits_le16(&ich9_spi->hsfs, HSFS_FLOCKDN);
  123. }
  124. }
  125. static bool spi_lock_status(struct ich_spi_platdata *plat, void *sbase)
  126. {
  127. int lock = 0;
  128. if (plat->ich_version == ICHV_7) {
  129. struct ich7_spi_regs *ich7_spi = sbase;
  130. lock = readw(&ich7_spi->spis) & SPIS_LOCK;
  131. } else if (plat->ich_version == ICHV_9) {
  132. struct ich9_spi_regs *ich9_spi = sbase;
  133. lock = readw(&ich9_spi->hsfs) & HSFS_FLOCKDN;
  134. }
  135. return lock != 0;
  136. }
  137. static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans,
  138. bool lock)
  139. {
  140. uint16_t optypes;
  141. uint8_t opmenu[ctlr->menubytes];
  142. if (!lock) {
  143. /* The lock is off, so just use index 0. */
  144. ich_writeb(ctlr, trans->opcode, ctlr->opmenu);
  145. optypes = ich_readw(ctlr, ctlr->optype);
  146. optypes = (optypes & 0xfffc) | (trans->type & 0x3);
  147. ich_writew(ctlr, optypes, ctlr->optype);
  148. return 0;
  149. } else {
  150. /* The lock is on. See if what we need is on the menu. */
  151. uint8_t optype;
  152. uint16_t opcode_index;
  153. /* Write Enable is handled as atomic prefix */
  154. if (trans->opcode == SPI_OPCODE_WREN)
  155. return 0;
  156. read_reg(ctlr, ctlr->opmenu, opmenu, sizeof(opmenu));
  157. for (opcode_index = 0; opcode_index < ctlr->menubytes;
  158. opcode_index++) {
  159. if (opmenu[opcode_index] == trans->opcode)
  160. break;
  161. }
  162. if (opcode_index == ctlr->menubytes) {
  163. debug("ICH SPI: Opcode %x not found\n", trans->opcode);
  164. return -EINVAL;
  165. }
  166. optypes = ich_readw(ctlr, ctlr->optype);
  167. optype = (optypes >> (opcode_index * 2)) & 0x3;
  168. if (optype != trans->type) {
  169. debug("ICH SPI: Transaction doesn't fit type %d\n",
  170. optype);
  171. return -ENOSPC;
  172. }
  173. return opcode_index;
  174. }
  175. }
  176. /*
  177. * Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set
  178. * below is true) or 0. In case the wait was for the bit(s) to set - write
  179. * those bits back, which would cause resetting them.
  180. *
  181. * Return the last read status value on success or -1 on failure.
  182. */
  183. static int ich_status_poll(struct ich_spi_priv *ctlr, u16 bitmask,
  184. int wait_til_set)
  185. {
  186. int timeout = 600000; /* This will result in 6s */
  187. u16 status = 0;
  188. while (timeout--) {
  189. status = ich_readw(ctlr, ctlr->status);
  190. if (wait_til_set ^ ((status & bitmask) == 0)) {
  191. if (wait_til_set) {
  192. ich_writew(ctlr, status & bitmask,
  193. ctlr->status);
  194. }
  195. return status;
  196. }
  197. udelay(10);
  198. }
  199. debug("ICH SPI: SCIP timeout, read %x, expected %x, wts %x %x\n",
  200. status, bitmask, wait_til_set, status & bitmask);
  201. return -ETIMEDOUT;
  202. }
  203. static void ich_spi_config_opcode(struct udevice *dev)
  204. {
  205. struct ich_spi_priv *ctlr = dev_get_priv(dev);
  206. /*
  207. * PREOP, OPTYPE, OPMENU1/OPMENU2 registers can be locked down
  208. * to prevent accidental or intentional writes. Before they get
  209. * locked down, these registers should be initialized properly.
  210. */
  211. ich_writew(ctlr, SPI_OPPREFIX, ctlr->preop);
  212. ich_writew(ctlr, SPI_OPTYPE, ctlr->optype);
  213. ich_writel(ctlr, SPI_OPMENU_LOWER, ctlr->opmenu);
  214. ich_writel(ctlr, SPI_OPMENU_UPPER, ctlr->opmenu + sizeof(u32));
  215. }
  216. static int ich_spi_exec_op_swseq(struct spi_slave *slave,
  217. const struct spi_mem_op *op)
  218. {
  219. struct udevice *bus = dev_get_parent(slave->dev);
  220. struct ich_spi_platdata *plat = dev_get_platdata(bus);
  221. struct ich_spi_priv *ctlr = dev_get_priv(bus);
  222. uint16_t control;
  223. int16_t opcode_index;
  224. int with_address;
  225. int status;
  226. struct spi_trans *trans = &ctlr->trans;
  227. bool lock = spi_lock_status(plat, ctlr->base);
  228. int ret = 0;
  229. trans->in = NULL;
  230. trans->out = NULL;
  231. trans->type = 0xFF;
  232. if (op->data.nbytes) {
  233. if (op->data.dir == SPI_MEM_DATA_IN) {
  234. trans->in = op->data.buf.in;
  235. trans->bytesin = op->data.nbytes;
  236. } else {
  237. trans->out = op->data.buf.out;
  238. trans->bytesout = op->data.nbytes;
  239. }
  240. }
  241. if (trans->opcode != op->cmd.opcode)
  242. trans->opcode = op->cmd.opcode;
  243. if (lock && trans->opcode == SPI_OPCODE_WRDIS)
  244. return 0;
  245. if (trans->opcode == SPI_OPCODE_WREN) {
  246. /*
  247. * Treat Write Enable as Atomic Pre-Op if possible
  248. * in order to prevent the Management Engine from
  249. * issuing a transaction between WREN and DATA.
  250. */
  251. if (!lock)
  252. ich_writew(ctlr, trans->opcode, ctlr->preop);
  253. return 0;
  254. }
  255. ret = ich_status_poll(ctlr, SPIS_SCIP, 0);
  256. if (ret < 0)
  257. return ret;
  258. if (plat->ich_version == ICHV_7)
  259. ich_writew(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
  260. else
  261. ich_writeb(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
  262. /* Try to guess spi transaction type */
  263. if (op->data.dir == SPI_MEM_DATA_OUT) {
  264. if (op->addr.nbytes)
  265. trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS;
  266. else
  267. trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS;
  268. } else {
  269. if (op->addr.nbytes)
  270. trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
  271. else
  272. trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS;
  273. }
  274. /* Special erase case handling */
  275. if (op->addr.nbytes && !op->data.buswidth)
  276. trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS;
  277. opcode_index = spi_setup_opcode(ctlr, trans, lock);
  278. if (opcode_index < 0)
  279. return -EINVAL;
  280. if (op->addr.nbytes) {
  281. trans->offset = op->addr.val;
  282. with_address = 1;
  283. }
  284. if (ctlr->speed && ctlr->max_speed >= 33000000) {
  285. int byte;
  286. byte = ich_readb(ctlr, ctlr->speed);
  287. if (ctlr->cur_speed >= 33000000)
  288. byte |= SSFC_SCF_33MHZ;
  289. else
  290. byte &= ~SSFC_SCF_33MHZ;
  291. ich_writeb(ctlr, byte, ctlr->speed);
  292. }
  293. /* Preset control fields */
  294. control = SPIC_SCGO | ((opcode_index & 0x07) << 4);
  295. /* Issue atomic preop cycle if needed */
  296. if (ich_readw(ctlr, ctlr->preop))
  297. control |= SPIC_ACS;
  298. if (!trans->bytesout && !trans->bytesin) {
  299. /* SPI addresses are 24 bit only */
  300. if (with_address) {
  301. ich_writel(ctlr, trans->offset & 0x00FFFFFF,
  302. ctlr->addr);
  303. }
  304. /*
  305. * This is a 'no data' command (like Write Enable), its
  306. * bitesout size was 1, decremented to zero while executing
  307. * spi_setup_opcode() above. Tell the chip to send the
  308. * command.
  309. */
  310. ich_writew(ctlr, control, ctlr->control);
  311. /* wait for the result */
  312. status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1);
  313. if (status < 0)
  314. return status;
  315. if (status & SPIS_FCERR) {
  316. debug("ICH SPI: Command transaction error\n");
  317. return -EIO;
  318. }
  319. return 0;
  320. }
  321. while (trans->bytesout || trans->bytesin) {
  322. uint32_t data_length;
  323. /* SPI addresses are 24 bit only */
  324. ich_writel(ctlr, trans->offset & 0x00FFFFFF, ctlr->addr);
  325. if (trans->bytesout)
  326. data_length = min(trans->bytesout, ctlr->databytes);
  327. else
  328. data_length = min(trans->bytesin, ctlr->databytes);
  329. /* Program data into FDATA0 to N */
  330. if (trans->bytesout) {
  331. write_reg(ctlr, trans->out, ctlr->data, data_length);
  332. trans->bytesout -= data_length;
  333. }
  334. /* Add proper control fields' values */
  335. control &= ~((ctlr->databytes - 1) << 8);
  336. control |= SPIC_DS;
  337. control |= (data_length - 1) << 8;
  338. /* write it */
  339. ich_writew(ctlr, control, ctlr->control);
  340. /* Wait for Cycle Done Status or Flash Cycle Error */
  341. status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1);
  342. if (status < 0)
  343. return status;
  344. if (status & SPIS_FCERR) {
  345. debug("ICH SPI: Data transaction error %x\n", status);
  346. return -EIO;
  347. }
  348. if (trans->bytesin) {
  349. read_reg(ctlr, ctlr->data, trans->in, data_length);
  350. trans->bytesin -= data_length;
  351. }
  352. }
  353. /* Clear atomic preop now that xfer is done */
  354. if (!lock)
  355. ich_writew(ctlr, 0, ctlr->preop);
  356. return 0;
  357. }
  358. /*
  359. * Ensure read/write xfer len is not greater than SPIBAR_FDATA_FIFO_SIZE and
  360. * that the operation does not cross page boundary.
  361. */
  362. static uint get_xfer_len(u32 offset, int len, int page_size)
  363. {
  364. uint xfer_len = min(len, SPIBAR_FDATA_FIFO_SIZE);
  365. uint bytes_left = ALIGN(offset, page_size) - offset;
  366. if (bytes_left)
  367. xfer_len = min(xfer_len, bytes_left);
  368. return xfer_len;
  369. }
  370. /* Fill FDATAn FIFO in preparation for a write transaction */
  371. static void fill_xfer_fifo(struct fast_spi_regs *regs, const void *data,
  372. uint len)
  373. {
  374. memcpy(regs->fdata, data, len);
  375. }
  376. /* Drain FDATAn FIFO after a read transaction populates data */
  377. static void drain_xfer_fifo(struct fast_spi_regs *regs, void *dest, uint len)
  378. {
  379. memcpy(dest, regs->fdata, len);
  380. }
  381. /* Fire up a transfer using the hardware sequencer */
  382. static void start_hwseq_xfer(struct fast_spi_regs *regs, uint hsfsts_cycle,
  383. uint offset, uint len)
  384. {
  385. /* Make sure all W1C status bits get cleared */
  386. u32 hsfsts;
  387. hsfsts = readl(&regs->hsfsts_ctl);
  388. hsfsts &= ~(HSFSTS_FCYCLE_MASK | HSFSTS_FDBC_MASK);
  389. hsfsts |= HSFSTS_AEL | HSFSTS_FCERR | HSFSTS_FDONE;
  390. /* Set up transaction parameters */
  391. hsfsts |= hsfsts_cycle << HSFSTS_FCYCLE_SHIFT;
  392. hsfsts |= ((len - 1) << HSFSTS_FDBC_SHIFT) & HSFSTS_FDBC_MASK;
  393. hsfsts |= HSFSTS_FGO;
  394. writel(offset, &regs->faddr);
  395. writel(hsfsts, &regs->hsfsts_ctl);
  396. }
  397. static int wait_for_hwseq_xfer(struct fast_spi_regs *regs, uint offset)
  398. {
  399. ulong start;
  400. u32 hsfsts;
  401. start = get_timer(0);
  402. do {
  403. hsfsts = readl(&regs->hsfsts_ctl);
  404. if (hsfsts & HSFSTS_FCERR) {
  405. debug("SPI transaction error at offset %x HSFSTS = %08x\n",
  406. offset, hsfsts);
  407. return -EIO;
  408. }
  409. if (hsfsts & HSFSTS_AEL)
  410. return -EPERM;
  411. if (hsfsts & HSFSTS_FDONE)
  412. return 0;
  413. } while (get_timer(start) < SPIBAR_HWSEQ_XFER_TIMEOUT_MS);
  414. debug("SPI transaction timeout at offset %x HSFSTS = %08x, timer %d\n",
  415. offset, hsfsts, (uint)get_timer(start));
  416. return -ETIMEDOUT;
  417. }
  418. /**
  419. * exec_sync_hwseq_xfer() - Execute flash transfer by hardware sequencing
  420. *
  421. * This waits until complete or timeout
  422. *
  423. * @regs: SPI registers
  424. * @hsfsts_cycle: Cycle type (enum hsfsts_cycle_t)
  425. * @offset: Offset to access
  426. * @len: Number of bytes to transfer (can be 0)
  427. * @return 0 if OK, -EIO on flash-cycle error (FCERR), -EPERM on access error
  428. * (AEL), -ETIMEDOUT on timeout
  429. */
  430. static int exec_sync_hwseq_xfer(struct fast_spi_regs *regs, uint hsfsts_cycle,
  431. uint offset, uint len)
  432. {
  433. start_hwseq_xfer(regs, hsfsts_cycle, offset, len);
  434. return wait_for_hwseq_xfer(regs, offset);
  435. }
  436. static int ich_spi_exec_op_hwseq(struct spi_slave *slave,
  437. const struct spi_mem_op *op)
  438. {
  439. struct spi_flash *flash = dev_get_uclass_priv(slave->dev);
  440. struct udevice *bus = dev_get_parent(slave->dev);
  441. struct ich_spi_priv *priv = dev_get_priv(bus);
  442. struct fast_spi_regs *regs = priv->base;
  443. uint page_size;
  444. uint offset;
  445. int cycle;
  446. uint len;
  447. bool out;
  448. int ret;
  449. u8 *buf;
  450. offset = op->addr.val;
  451. len = op->data.nbytes;
  452. switch (op->cmd.opcode) {
  453. case SPINOR_OP_RDID:
  454. cycle = HSFSTS_CYCLE_RDID;
  455. break;
  456. case SPINOR_OP_READ_FAST:
  457. cycle = HSFSTS_CYCLE_READ;
  458. break;
  459. case SPINOR_OP_PP:
  460. cycle = HSFSTS_CYCLE_WRITE;
  461. break;
  462. case SPINOR_OP_WREN:
  463. /* Nothing needs to be done */
  464. return 0;
  465. case SPINOR_OP_WRSR:
  466. cycle = HSFSTS_CYCLE_WR_STATUS;
  467. break;
  468. case SPINOR_OP_RDSR:
  469. cycle = HSFSTS_CYCLE_RD_STATUS;
  470. break;
  471. case SPINOR_OP_WRDI:
  472. return 0; /* ignore */
  473. case SPINOR_OP_BE_4K:
  474. cycle = HSFSTS_CYCLE_4K_ERASE;
  475. ret = exec_sync_hwseq_xfer(regs, cycle, offset, 0);
  476. return ret;
  477. default:
  478. debug("Unknown cycle %x\n", op->cmd.opcode);
  479. return -EINVAL;
  480. };
  481. out = op->data.dir == SPI_MEM_DATA_OUT;
  482. buf = out ? (u8 *)op->data.buf.out : op->data.buf.in;
  483. page_size = flash->page_size ? : 256;
  484. while (len) {
  485. uint xfer_len = get_xfer_len(offset, len, page_size);
  486. if (out)
  487. fill_xfer_fifo(regs, buf, xfer_len);
  488. ret = exec_sync_hwseq_xfer(regs, cycle, offset, xfer_len);
  489. if (ret)
  490. return ret;
  491. if (!out)
  492. drain_xfer_fifo(regs, buf, xfer_len);
  493. offset += xfer_len;
  494. buf += xfer_len;
  495. len -= xfer_len;
  496. }
  497. return 0;
  498. }
  499. static int ich_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op)
  500. {
  501. struct udevice *bus = dev_get_parent(slave->dev);
  502. struct ich_spi_platdata *plat = dev_get_platdata(bus);
  503. int ret;
  504. bootstage_start(BOOTSTAGE_ID_ACCUM_SPI, "fast_spi");
  505. if (plat->hwseq)
  506. ret = ich_spi_exec_op_hwseq(slave, op);
  507. else
  508. ret = ich_spi_exec_op_swseq(slave, op);
  509. bootstage_accum(BOOTSTAGE_ID_ACCUM_SPI);
  510. return ret;
  511. }
  512. #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  513. /**
  514. * ich_spi_get_basics() - Get basic information about the ICH device
  515. *
  516. * This works without probing any devices if requested.
  517. *
  518. * @bus: SPI controller to use
  519. * @can_probe: true if this function is allowed to probe the PCH
  520. * @pchp: Returns a pointer to the pch, or NULL if not found
  521. * @ich_versionp: Returns ICH version detected on success
  522. * @mmio_basep: Returns the address of the SPI registers on success
  523. * @return 0 if OK, -EPROTOTYPE if the PCH could not be found, -EAGAIN if
  524. * the function cannot success without probing, possible another error if
  525. * pch_get_spi_base() fails
  526. */
  527. static int ich_spi_get_basics(struct udevice *bus, bool can_probe,
  528. struct udevice **pchp,
  529. enum ich_version *ich_versionp, ulong *mmio_basep)
  530. {
  531. struct udevice *pch = NULL;
  532. int ret = 0;
  533. /* Find a PCH if there is one */
  534. if (can_probe) {
  535. pch = dev_get_parent(bus);
  536. if (device_get_uclass_id(pch) != UCLASS_PCH) {
  537. uclass_first_device(UCLASS_PCH, &pch);
  538. if (!pch)
  539. return log_msg_ret("uclass", -EPROTOTYPE);
  540. }
  541. }
  542. *ich_versionp = dev_get_driver_data(bus);
  543. if (*ich_versionp == ICHV_APL)
  544. *mmio_basep = dm_pci_read_bar32(bus, 0);
  545. else if (pch)
  546. ret = pch_get_spi_base(pch, mmio_basep);
  547. else
  548. return -EAGAIN;
  549. *pchp = pch;
  550. return ret;
  551. }
  552. #endif
  553. /**
  554. * ich_get_mmap_bus() - Handle the get_mmap() method for a bus
  555. *
  556. * There are several cases to consider:
  557. * 1. Using of-platdata, in which case we have the BDF and can access the
  558. * registers by reading the BAR
  559. * 2. Not using of-platdata, but still with a SPI controller that is on its own
  560. * PCI PDF. In this case we read the BDF from the parent platdata and again get
  561. * the registers by reading the BAR
  562. * 3. Using a SPI controller that is a child of the PCH, in which case we try
  563. * to find the registers by asking the PCH. This only works if the PCH has
  564. * been probed (which it will be if the bus is probed since parents are
  565. * probed before children), since the PCH may not have a PCI address until
  566. * its parent (the PCI bus itself) has been probed. If you are using this
  567. * method then you should make sure the SPI bus is probed.
  568. *
  569. * The first two cases are useful in early init. The last one is more useful
  570. * afterwards.
  571. */
  572. static int ich_get_mmap_bus(struct udevice *bus, ulong *map_basep,
  573. uint *map_sizep, uint *offsetp)
  574. {
  575. pci_dev_t spi_bdf;
  576. #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  577. if (device_is_on_pci_bus(bus)) {
  578. struct pci_child_platdata *pplat;
  579. pplat = dev_get_parent_platdata(bus);
  580. spi_bdf = pplat->devfn;
  581. } else {
  582. enum ich_version ich_version;
  583. struct fast_spi_regs *regs;
  584. struct udevice *pch;
  585. ulong mmio_base;
  586. int ret;
  587. ret = ich_spi_get_basics(bus, device_active(bus), &pch,
  588. &ich_version, &mmio_base);
  589. if (ret)
  590. return log_msg_ret("basics", ret);
  591. regs = (struct fast_spi_regs *)mmio_base;
  592. return fast_spi_get_bios_mmap_regs(regs, map_basep, map_sizep,
  593. offsetp);
  594. }
  595. #else
  596. struct ich_spi_platdata *plat = dev_get_platdata(bus);
  597. /*
  598. * We cannot rely on plat->bdf being set up yet since this method can
  599. * be called before the device is probed. Use the of-platdata directly
  600. * instead.
  601. */
  602. spi_bdf = pci_ofplat_get_devfn(plat->dtplat.reg[0]);
  603. #endif
  604. return fast_spi_get_bios_mmap(spi_bdf, map_basep, map_sizep, offsetp);
  605. }
  606. static int ich_get_mmap(struct udevice *dev, ulong *map_basep, uint *map_sizep,
  607. uint *offsetp)
  608. {
  609. struct udevice *bus = dev_get_parent(dev);
  610. return ich_get_mmap_bus(bus, map_basep, map_sizep, offsetp);
  611. }
  612. static int ich_spi_adjust_size(struct spi_slave *slave, struct spi_mem_op *op)
  613. {
  614. unsigned int page_offset;
  615. int addr = op->addr.val;
  616. unsigned int byte_count = op->data.nbytes;
  617. if (hweight32(ICH_BOUNDARY) == 1) {
  618. page_offset = addr & (ICH_BOUNDARY - 1);
  619. } else {
  620. u64 aux = addr;
  621. page_offset = do_div(aux, ICH_BOUNDARY);
  622. }
  623. if (op->data.dir == SPI_MEM_DATA_IN) {
  624. if (slave->max_read_size) {
  625. op->data.nbytes = min(ICH_BOUNDARY - page_offset,
  626. slave->max_read_size);
  627. }
  628. } else if (slave->max_write_size) {
  629. op->data.nbytes = min(ICH_BOUNDARY - page_offset,
  630. slave->max_write_size);
  631. }
  632. op->data.nbytes = min(op->data.nbytes, byte_count);
  633. return 0;
  634. }
  635. static int ich_protect_lockdown(struct udevice *dev)
  636. {
  637. struct ich_spi_platdata *plat = dev_get_platdata(dev);
  638. struct ich_spi_priv *priv = dev_get_priv(dev);
  639. int ret = -ENOSYS;
  640. /* Disable the BIOS write protect so write commands are allowed */
  641. if (priv->pch)
  642. ret = pch_set_spi_protect(priv->pch, false);
  643. if (ret == -ENOSYS) {
  644. u8 bios_cntl;
  645. bios_cntl = ich_readb(priv, priv->bcr);
  646. bios_cntl &= ~BIT(5); /* clear Enable InSMM_STS (EISS) */
  647. bios_cntl |= 1; /* Write Protect Disable (WPD) */
  648. ich_writeb(priv, bios_cntl, priv->bcr);
  649. } else if (ret) {
  650. debug("%s: Failed to disable write-protect: err=%d\n",
  651. __func__, ret);
  652. return ret;
  653. }
  654. /* Lock down SPI controller settings if required */
  655. if (plat->lockdown) {
  656. ich_spi_config_opcode(dev);
  657. spi_lock_down(plat, priv->base);
  658. }
  659. return 0;
  660. }
  661. static int ich_init_controller(struct udevice *dev,
  662. struct ich_spi_platdata *plat,
  663. struct ich_spi_priv *ctlr)
  664. {
  665. if (spl_phase() == PHASE_TPL) {
  666. struct ich_spi_platdata *plat = dev_get_platdata(dev);
  667. int ret;
  668. ret = fast_spi_early_init(plat->bdf, plat->mmio_base);
  669. if (ret)
  670. return ret;
  671. }
  672. ctlr->base = (void *)plat->mmio_base;
  673. if (plat->ich_version == ICHV_7) {
  674. struct ich7_spi_regs *ich7_spi = ctlr->base;
  675. ctlr->opmenu = offsetof(struct ich7_spi_regs, opmenu);
  676. ctlr->menubytes = sizeof(ich7_spi->opmenu);
  677. ctlr->optype = offsetof(struct ich7_spi_regs, optype);
  678. ctlr->addr = offsetof(struct ich7_spi_regs, spia);
  679. ctlr->data = offsetof(struct ich7_spi_regs, spid);
  680. ctlr->databytes = sizeof(ich7_spi->spid);
  681. ctlr->status = offsetof(struct ich7_spi_regs, spis);
  682. ctlr->control = offsetof(struct ich7_spi_regs, spic);
  683. ctlr->bbar = offsetof(struct ich7_spi_regs, bbar);
  684. ctlr->preop = offsetof(struct ich7_spi_regs, preop);
  685. } else if (plat->ich_version == ICHV_9) {
  686. struct ich9_spi_regs *ich9_spi = ctlr->base;
  687. ctlr->opmenu = offsetof(struct ich9_spi_regs, opmenu);
  688. ctlr->menubytes = sizeof(ich9_spi->opmenu);
  689. ctlr->optype = offsetof(struct ich9_spi_regs, optype);
  690. ctlr->addr = offsetof(struct ich9_spi_regs, faddr);
  691. ctlr->data = offsetof(struct ich9_spi_regs, fdata);
  692. ctlr->databytes = sizeof(ich9_spi->fdata);
  693. ctlr->status = offsetof(struct ich9_spi_regs, ssfs);
  694. ctlr->control = offsetof(struct ich9_spi_regs, ssfc);
  695. ctlr->speed = ctlr->control + 2;
  696. ctlr->bbar = offsetof(struct ich9_spi_regs, bbar);
  697. ctlr->preop = offsetof(struct ich9_spi_regs, preop);
  698. ctlr->bcr = offsetof(struct ich9_spi_regs, bcr);
  699. ctlr->pr = &ich9_spi->pr[0];
  700. } else if (plat->ich_version == ICHV_APL) {
  701. } else {
  702. debug("ICH SPI: Unrecognised ICH version %d\n",
  703. plat->ich_version);
  704. return -EINVAL;
  705. }
  706. /* Work out the maximum speed we can support */
  707. ctlr->max_speed = 20000000;
  708. if (plat->ich_version == ICHV_9 && ich9_can_do_33mhz(dev))
  709. ctlr->max_speed = 33000000;
  710. debug("ICH SPI: Version ID %d detected at %lx, speed %ld\n",
  711. plat->ich_version, plat->mmio_base, ctlr->max_speed);
  712. ich_set_bbar(ctlr, 0);
  713. return 0;
  714. }
  715. static int ich_cache_bios_region(struct udevice *dev)
  716. {
  717. ulong map_base;
  718. uint map_size;
  719. uint offset;
  720. ulong base;
  721. int ret;
  722. ret = ich_get_mmap_bus(dev, &map_base, &map_size, &offset);
  723. if (ret)
  724. return ret;
  725. /* Don't use WRBACK since we are not supposed to write to SPI flash */
  726. base = SZ_4G - map_size;
  727. mtrr_set_next_var(MTRR_TYPE_WRPROT, base, map_size);
  728. log_debug("BIOS cache base=%lx, size=%x\n", base, (uint)map_size);
  729. return 0;
  730. }
  731. static int ich_spi_probe(struct udevice *dev)
  732. {
  733. struct ich_spi_platdata *plat = dev_get_platdata(dev);
  734. struct ich_spi_priv *priv = dev_get_priv(dev);
  735. int ret;
  736. ret = ich_init_controller(dev, plat, priv);
  737. if (ret)
  738. return ret;
  739. if (spl_phase() == PHASE_TPL) {
  740. /* Cache the BIOS to speed things up */
  741. ret = ich_cache_bios_region(dev);
  742. if (ret)
  743. return ret;
  744. } else {
  745. ret = ich_protect_lockdown(dev);
  746. if (ret)
  747. return ret;
  748. }
  749. priv->cur_speed = priv->max_speed;
  750. return 0;
  751. }
  752. static int ich_spi_remove(struct udevice *bus)
  753. {
  754. /*
  755. * Configure SPI controller so that the Linux MTD driver can fully
  756. * access the SPI NOR chip
  757. */
  758. ich_spi_config_opcode(bus);
  759. return 0;
  760. }
  761. static int ich_spi_set_speed(struct udevice *bus, uint speed)
  762. {
  763. struct ich_spi_priv *priv = dev_get_priv(bus);
  764. priv->cur_speed = speed;
  765. return 0;
  766. }
  767. static int ich_spi_set_mode(struct udevice *bus, uint mode)
  768. {
  769. debug("%s: mode=%d\n", __func__, mode);
  770. return 0;
  771. }
  772. static int ich_spi_child_pre_probe(struct udevice *dev)
  773. {
  774. struct udevice *bus = dev_get_parent(dev);
  775. struct ich_spi_platdata *plat = dev_get_platdata(bus);
  776. struct ich_spi_priv *priv = dev_get_priv(bus);
  777. struct spi_slave *slave = dev_get_parent_priv(dev);
  778. /*
  779. * Yes this controller can only write a small number of bytes at
  780. * once! The limit is typically 64 bytes. For hardware sequencing a
  781. * a loop is used to get around this.
  782. */
  783. if (!plat->hwseq)
  784. slave->max_write_size = priv->databytes;
  785. /*
  786. * ICH 7 SPI controller only supports array read command
  787. * and byte program command for SST flash
  788. */
  789. if (plat->ich_version == ICHV_7)
  790. slave->mode = SPI_RX_SLOW | SPI_TX_BYTE;
  791. return 0;
  792. }
  793. static int ich_spi_ofdata_to_platdata(struct udevice *dev)
  794. {
  795. struct ich_spi_platdata *plat = dev_get_platdata(dev);
  796. #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  797. struct ich_spi_priv *priv = dev_get_priv(dev);
  798. int ret;
  799. ret = ich_spi_get_basics(dev, true, &priv->pch, &plat->ich_version,
  800. &plat->mmio_base);
  801. if (ret)
  802. return log_msg_ret("basics", ret);
  803. plat->lockdown = dev_read_bool(dev, "intel,spi-lock-down");
  804. /*
  805. * Use an int so that the property is present in of-platdata even
  806. * when false.
  807. */
  808. plat->hwseq = dev_read_u32_default(dev, "intel,hardware-seq", 0);
  809. #else
  810. plat->ich_version = ICHV_APL;
  811. plat->mmio_base = plat->dtplat.early_regs[0];
  812. plat->bdf = pci_ofplat_get_devfn(plat->dtplat.reg[0]);
  813. plat->hwseq = plat->dtplat.intel_hardware_seq;
  814. #endif
  815. debug("%s: mmio_base=%lx\n", __func__, plat->mmio_base);
  816. return 0;
  817. }
  818. static const struct spi_controller_mem_ops ich_controller_mem_ops = {
  819. .adjust_op_size = ich_spi_adjust_size,
  820. .supports_op = NULL,
  821. .exec_op = ich_spi_exec_op,
  822. };
  823. static const struct dm_spi_ops ich_spi_ops = {
  824. /* xfer is not supported */
  825. .set_speed = ich_spi_set_speed,
  826. .set_mode = ich_spi_set_mode,
  827. .mem_ops = &ich_controller_mem_ops,
  828. .get_mmap = ich_get_mmap,
  829. /*
  830. * cs_info is not needed, since we require all chip selects to be
  831. * in the device tree explicitly
  832. */
  833. };
  834. static const struct udevice_id ich_spi_ids[] = {
  835. { .compatible = "intel,ich7-spi", ICHV_7 },
  836. { .compatible = "intel,ich9-spi", ICHV_9 },
  837. { .compatible = "intel,fast-spi", ICHV_APL },
  838. { }
  839. };
  840. U_BOOT_DRIVER(intel_fast_spi) = {
  841. .name = "intel_fast_spi",
  842. .id = UCLASS_SPI,
  843. .of_match = ich_spi_ids,
  844. .ops = &ich_spi_ops,
  845. .ofdata_to_platdata = ich_spi_ofdata_to_platdata,
  846. .platdata_auto_alloc_size = sizeof(struct ich_spi_platdata),
  847. .priv_auto_alloc_size = sizeof(struct ich_spi_priv),
  848. .child_pre_probe = ich_spi_child_pre_probe,
  849. .probe = ich_spi_probe,
  850. .remove = ich_spi_remove,
  851. .flags = DM_FLAG_OS_PREPARE,
  852. };