fsl_qspi.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Freescale QuadSPI driver.
  4. *
  5. * Copyright (C) 2013 Freescale Semiconductor, Inc.
  6. * Copyright (C) 2018 Bootlin
  7. * Copyright (C) 2018 exceet electronics GmbH
  8. * Copyright (C) 2018 Kontron Electronics GmbH
  9. * Copyright 2019-2020 NXP
  10. *
  11. * This driver is a ported version of Linux Freescale QSPI driver taken from
  12. * v5.5-rc1 tag having following information.
  13. *
  14. * Transition to SPI MEM interface:
  15. * Authors:
  16. * Boris Brezillon <bbrezillon@kernel.org>
  17. * Frieder Schrempf <frieder.schrempf@kontron.de>
  18. * Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
  19. * Suresh Gupta <suresh.gupta@nxp.com>
  20. *
  21. * Based on the original fsl-quadspi.c spi-nor driver.
  22. * Transition to spi-mem in spi-fsl-qspi.c
  23. */
  24. #include <common.h>
  25. #include <dm.h>
  26. #include <dm/device_compat.h>
  27. #include <log.h>
  28. #include <spi.h>
  29. #include <spi-mem.h>
  30. #include <linux/bitops.h>
  31. #include <linux/delay.h>
  32. #include <linux/libfdt.h>
  33. #include <linux/sizes.h>
  34. #include <linux/iopoll.h>
  35. #include <linux/iopoll.h>
  36. #include <linux/sizes.h>
  37. #include <linux/err.h>
  38. #include <asm/io.h>
  39. DECLARE_GLOBAL_DATA_PTR;
  40. /*
  41. * The driver only uses one single LUT entry, that is updated on
  42. * each call of exec_op(). Index 0 is preset at boot with a basic
  43. * read operation, so let's use the last entry (15).
  44. */
  45. #define SEQID_LUT 15
  46. #define SEQID_LUT_AHB 14
  47. /* Registers used by the driver */
  48. #define QUADSPI_MCR 0x00
  49. #define QUADSPI_MCR_RESERVED_MASK GENMASK(19, 16)
  50. #define QUADSPI_MCR_MDIS_MASK BIT(14)
  51. #define QUADSPI_MCR_CLR_TXF_MASK BIT(11)
  52. #define QUADSPI_MCR_CLR_RXF_MASK BIT(10)
  53. #define QUADSPI_MCR_DDR_EN_MASK BIT(7)
  54. #define QUADSPI_MCR_END_CFG_MASK GENMASK(3, 2)
  55. #define QUADSPI_MCR_SWRSTHD_MASK BIT(1)
  56. #define QUADSPI_MCR_SWRSTSD_MASK BIT(0)
  57. #define QUADSPI_IPCR 0x08
  58. #define QUADSPI_IPCR_SEQID(x) ((x) << 24)
  59. #define QUADSPI_FLSHCR 0x0c
  60. #define QUADSPI_FLSHCR_TCSS_MASK GENMASK(3, 0)
  61. #define QUADSPI_FLSHCR_TCSH_MASK GENMASK(11, 8)
  62. #define QUADSPI_FLSHCR_TDH_MASK GENMASK(17, 16)
  63. #define QUADSPI_BUF3CR 0x1c
  64. #define QUADSPI_BUF3CR_ALLMST_MASK BIT(31)
  65. #define QUADSPI_BUF3CR_ADATSZ(x) ((x) << 8)
  66. #define QUADSPI_BUF3CR_ADATSZ_MASK GENMASK(15, 8)
  67. #define QUADSPI_BFGENCR 0x20
  68. #define QUADSPI_BFGENCR_SEQID(x) ((x) << 12)
  69. #define QUADSPI_BUF0IND 0x30
  70. #define QUADSPI_BUF1IND 0x34
  71. #define QUADSPI_BUF2IND 0x38
  72. #define QUADSPI_SFAR 0x100
  73. #define QUADSPI_SMPR 0x108
  74. #define QUADSPI_SMPR_DDRSMP_MASK GENMASK(18, 16)
  75. #define QUADSPI_SMPR_FSDLY_MASK BIT(6)
  76. #define QUADSPI_SMPR_FSPHS_MASK BIT(5)
  77. #define QUADSPI_SMPR_HSENA_MASK BIT(0)
  78. #define QUADSPI_RBCT 0x110
  79. #define QUADSPI_RBCT_WMRK_MASK GENMASK(4, 0)
  80. #define QUADSPI_RBCT_RXBRD_USEIPS BIT(8)
  81. #define QUADSPI_TBDR 0x154
  82. #define QUADSPI_SR 0x15c
  83. #define QUADSPI_SR_IP_ACC_MASK BIT(1)
  84. #define QUADSPI_SR_AHB_ACC_MASK BIT(2)
  85. #define QUADSPI_FR 0x160
  86. #define QUADSPI_FR_TFF_MASK BIT(0)
  87. #define QUADSPI_RSER 0x164
  88. #define QUADSPI_RSER_TFIE BIT(0)
  89. #define QUADSPI_SPTRCLR 0x16c
  90. #define QUADSPI_SPTRCLR_IPPTRC BIT(8)
  91. #define QUADSPI_SPTRCLR_BFPTRC BIT(0)
  92. #define QUADSPI_SFA1AD 0x180
  93. #define QUADSPI_SFA2AD 0x184
  94. #define QUADSPI_SFB1AD 0x188
  95. #define QUADSPI_SFB2AD 0x18c
  96. #define QUADSPI_RBDR(x) (0x200 + ((x) * 4))
  97. #define QUADSPI_LUTKEY 0x300
  98. #define QUADSPI_LUTKEY_VALUE 0x5AF05AF0
  99. #define QUADSPI_LCKCR 0x304
  100. #define QUADSPI_LCKER_LOCK BIT(0)
  101. #define QUADSPI_LCKER_UNLOCK BIT(1)
  102. #define QUADSPI_LUT_BASE 0x310
  103. #define QUADSPI_LUT_OFFSET (SEQID_LUT * 4 * 4)
  104. #define QUADSPI_LUT_REG(idx) \
  105. (QUADSPI_LUT_BASE + QUADSPI_LUT_OFFSET + (idx) * 4)
  106. #define QUADSPI_AHB_LUT_OFFSET (SEQID_LUT_AHB * 4 * 4)
  107. #define QUADSPI_AHB_LUT_REG(idx) \
  108. (QUADSPI_LUT_BASE + QUADSPI_AHB_LUT_OFFSET + (idx) * 4)
  109. /* Instruction set for the LUT register */
  110. #define LUT_STOP 0
  111. #define LUT_CMD 1
  112. #define LUT_ADDR 2
  113. #define LUT_DUMMY 3
  114. #define LUT_MODE 4
  115. #define LUT_MODE2 5
  116. #define LUT_MODE4 6
  117. #define LUT_FSL_READ 7
  118. #define LUT_FSL_WRITE 8
  119. #define LUT_JMP_ON_CS 9
  120. #define LUT_ADDR_DDR 10
  121. #define LUT_MODE_DDR 11
  122. #define LUT_MODE2_DDR 12
  123. #define LUT_MODE4_DDR 13
  124. #define LUT_FSL_READ_DDR 14
  125. #define LUT_FSL_WRITE_DDR 15
  126. #define LUT_DATA_LEARN 16
  127. /*
  128. * The PAD definitions for LUT register.
  129. *
  130. * The pad stands for the number of IO lines [0:3].
  131. * For example, the quad read needs four IO lines,
  132. * so you should use LUT_PAD(4).
  133. */
  134. #define LUT_PAD(x) (fls(x) - 1)
  135. /*
  136. * Macro for constructing the LUT entries with the following
  137. * register layout:
  138. *
  139. * ---------------------------------------------------
  140. * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
  141. * ---------------------------------------------------
  142. */
  143. #define LUT_DEF(idx, ins, pad, opr) \
  144. ((((ins) << 10) | ((pad) << 8) | (opr)) << (((idx) % 2) * 16))
  145. /* Controller needs driver to swap endianness */
  146. #define QUADSPI_QUIRK_SWAP_ENDIAN BIT(0)
  147. /* Controller needs 4x internal clock */
  148. #define QUADSPI_QUIRK_4X_INT_CLK BIT(1)
  149. /*
  150. * TKT253890, the controller needs the driver to fill the txfifo with
  151. * 16 bytes at least to trigger a data transfer, even though the extra
  152. * data won't be transferred.
  153. */
  154. #define QUADSPI_QUIRK_TKT253890 BIT(2)
  155. /* TKT245618, the controller cannot wake up from wait mode */
  156. #define QUADSPI_QUIRK_TKT245618 BIT(3)
  157. /*
  158. * Controller adds QSPI_AMBA_BASE (base address of the mapped memory)
  159. * internally. No need to add it when setting SFXXAD and SFAR registers
  160. */
  161. #define QUADSPI_QUIRK_BASE_INTERNAL BIT(4)
  162. /*
  163. * Controller uses TDH bits in register QUADSPI_FLSHCR.
  164. * They need to be set in accordance with the DDR/SDR mode.
  165. */
  166. #define QUADSPI_QUIRK_USE_TDH_SETTING BIT(5)
  167. /*
  168. * Controller only has Two CS on flash A, no flash B port
  169. */
  170. #define QUADSPI_QUIRK_SINGLE_BUS BIT(6)
  171. struct fsl_qspi_devtype_data {
  172. unsigned int rxfifo;
  173. unsigned int txfifo;
  174. unsigned int ahb_buf_size;
  175. unsigned int quirks;
  176. bool little_endian;
  177. };
  178. static const struct fsl_qspi_devtype_data vybrid_data = {
  179. .rxfifo = SZ_128,
  180. .txfifo = SZ_64,
  181. .ahb_buf_size = SZ_1K,
  182. .quirks = QUADSPI_QUIRK_SWAP_ENDIAN,
  183. .little_endian = true,
  184. };
  185. static const struct fsl_qspi_devtype_data imx6sx_data = {
  186. .rxfifo = SZ_128,
  187. .txfifo = SZ_512,
  188. .ahb_buf_size = SZ_1K,
  189. .quirks = QUADSPI_QUIRK_4X_INT_CLK | QUADSPI_QUIRK_TKT245618,
  190. .little_endian = true,
  191. };
  192. static const struct fsl_qspi_devtype_data imx7d_data = {
  193. .rxfifo = SZ_128,
  194. .txfifo = SZ_512,
  195. .ahb_buf_size = SZ_1K,
  196. .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK |
  197. QUADSPI_QUIRK_USE_TDH_SETTING,
  198. .little_endian = true,
  199. };
  200. static const struct fsl_qspi_devtype_data imx6ul_data = {
  201. .rxfifo = SZ_128,
  202. .txfifo = SZ_512,
  203. .ahb_buf_size = SZ_1K,
  204. .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK |
  205. QUADSPI_QUIRK_USE_TDH_SETTING,
  206. .little_endian = true,
  207. };
  208. static const struct fsl_qspi_devtype_data imx7ulp_data = {
  209. .rxfifo = SZ_64,
  210. .txfifo = SZ_64,
  211. .ahb_buf_size = SZ_128,
  212. .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK |
  213. QUADSPI_QUIRK_USE_TDH_SETTING | QUADSPI_QUIRK_SINGLE_BUS,
  214. .little_endian = true,
  215. };
  216. static const struct fsl_qspi_devtype_data ls1021a_data = {
  217. .rxfifo = SZ_128,
  218. .txfifo = SZ_64,
  219. .ahb_buf_size = SZ_1K,
  220. .quirks = 0,
  221. .little_endian = false,
  222. };
  223. static const struct fsl_qspi_devtype_data ls1088a_data = {
  224. .rxfifo = SZ_128,
  225. .txfifo = SZ_128,
  226. .ahb_buf_size = SZ_1K,
  227. .quirks = QUADSPI_QUIRK_TKT253890,
  228. .little_endian = true,
  229. };
  230. static const struct fsl_qspi_devtype_data ls2080a_data = {
  231. .rxfifo = SZ_128,
  232. .txfifo = SZ_64,
  233. .ahb_buf_size = SZ_1K,
  234. .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_BASE_INTERNAL,
  235. .little_endian = true,
  236. };
  237. struct fsl_qspi {
  238. struct udevice *dev;
  239. void __iomem *iobase;
  240. void __iomem *ahb_addr;
  241. u32 memmap_phy;
  242. u32 memmap_size;
  243. const struct fsl_qspi_devtype_data *devtype_data;
  244. int selected;
  245. };
  246. static inline int needs_swap_endian(struct fsl_qspi *q)
  247. {
  248. return q->devtype_data->quirks & QUADSPI_QUIRK_SWAP_ENDIAN;
  249. }
  250. static inline int needs_4x_clock(struct fsl_qspi *q)
  251. {
  252. return q->devtype_data->quirks & QUADSPI_QUIRK_4X_INT_CLK;
  253. }
  254. static inline int needs_fill_txfifo(struct fsl_qspi *q)
  255. {
  256. return q->devtype_data->quirks & QUADSPI_QUIRK_TKT253890;
  257. }
  258. static inline int needs_wakeup_wait_mode(struct fsl_qspi *q)
  259. {
  260. return q->devtype_data->quirks & QUADSPI_QUIRK_TKT245618;
  261. }
  262. static inline int needs_amba_base_offset(struct fsl_qspi *q)
  263. {
  264. return !(q->devtype_data->quirks & QUADSPI_QUIRK_BASE_INTERNAL);
  265. }
  266. static inline int needs_tdh_setting(struct fsl_qspi *q)
  267. {
  268. return q->devtype_data->quirks & QUADSPI_QUIRK_USE_TDH_SETTING;
  269. }
  270. static inline int needs_single_bus(struct fsl_qspi *q)
  271. {
  272. return q->devtype_data->quirks & QUADSPI_QUIRK_SINGLE_BUS;
  273. }
  274. /*
  275. * An IC bug makes it necessary to rearrange the 32-bit data.
  276. * Later chips, such as IMX6SLX, have fixed this bug.
  277. */
  278. static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a)
  279. {
  280. return needs_swap_endian(q) ? __swab32(a) : a;
  281. }
  282. /*
  283. * R/W functions for big- or little-endian registers:
  284. * The QSPI controller's endianness is independent of
  285. * the CPU core's endianness. So far, although the CPU
  286. * core is little-endian the QSPI controller can use
  287. * big-endian or little-endian.
  288. */
  289. static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr)
  290. {
  291. if (q->devtype_data->little_endian)
  292. out_le32(addr, val);
  293. else
  294. out_be32(addr, val);
  295. }
  296. static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr)
  297. {
  298. if (q->devtype_data->little_endian)
  299. return in_le32(addr);
  300. return in_be32(addr);
  301. }
  302. static int fsl_qspi_check_buswidth(struct fsl_qspi *q, u8 width)
  303. {
  304. switch (width) {
  305. case 1:
  306. case 2:
  307. case 4:
  308. return 0;
  309. }
  310. return -ENOTSUPP;
  311. }
  312. static bool fsl_qspi_supports_op(struct spi_slave *slave,
  313. const struct spi_mem_op *op)
  314. {
  315. struct fsl_qspi *q = dev_get_priv(slave->dev->parent);
  316. int ret;
  317. ret = fsl_qspi_check_buswidth(q, op->cmd.buswidth);
  318. if (op->addr.nbytes)
  319. ret |= fsl_qspi_check_buswidth(q, op->addr.buswidth);
  320. if (op->dummy.nbytes)
  321. ret |= fsl_qspi_check_buswidth(q, op->dummy.buswidth);
  322. if (op->data.nbytes)
  323. ret |= fsl_qspi_check_buswidth(q, op->data.buswidth);
  324. if (ret)
  325. return false;
  326. /*
  327. * The number of instructions needed for the op, needs
  328. * to fit into a single LUT entry.
  329. */
  330. if (op->addr.nbytes +
  331. (op->dummy.nbytes ? 1 : 0) +
  332. (op->data.nbytes ? 1 : 0) > 6)
  333. return false;
  334. /* Max 64 dummy clock cycles supported */
  335. if (op->dummy.nbytes &&
  336. (op->dummy.nbytes * 8 / op->dummy.buswidth > 64))
  337. return false;
  338. /* Max data length, check controller limits and alignment */
  339. if (op->data.dir == SPI_MEM_DATA_IN &&
  340. (op->data.nbytes > q->devtype_data->ahb_buf_size ||
  341. (op->data.nbytes > q->devtype_data->rxfifo - 4 &&
  342. !IS_ALIGNED(op->data.nbytes, 8))))
  343. return false;
  344. if (op->data.dir == SPI_MEM_DATA_OUT &&
  345. op->data.nbytes > q->devtype_data->txfifo)
  346. return false;
  347. return true;
  348. }
  349. static void fsl_qspi_prepare_lut(struct fsl_qspi *q,
  350. const struct spi_mem_op *op)
  351. {
  352. void __iomem *base = q->iobase;
  353. u32 lutval[4] = {};
  354. int lutidx = 1, i;
  355. lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth),
  356. op->cmd.opcode);
  357. if (IS_ENABLED(CONFIG_FSL_QSPI_AHB_FULL_MAP)) {
  358. if (op->addr.nbytes) {
  359. lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_ADDR,
  360. LUT_PAD(op->addr.buswidth),
  361. (op->addr.nbytes == 4) ? 0x20 : 0x18);
  362. lutidx++;
  363. }
  364. } else {
  365. /*
  366. * For some unknown reason, using LUT_ADDR doesn't work in some
  367. * cases (at least with only one byte long addresses), so
  368. * let's use LUT_MODE to write the address bytes one by one
  369. */
  370. for (i = 0; i < op->addr.nbytes; i++) {
  371. u8 addrbyte = op->addr.val >> (8 * (op->addr.nbytes - i - 1));
  372. lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_MODE,
  373. LUT_PAD(op->addr.buswidth),
  374. addrbyte);
  375. lutidx++;
  376. }
  377. }
  378. if (op->dummy.nbytes) {
  379. lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY,
  380. LUT_PAD(op->dummy.buswidth),
  381. op->dummy.nbytes * 8 /
  382. op->dummy.buswidth);
  383. lutidx++;
  384. }
  385. if (op->data.nbytes) {
  386. lutval[lutidx / 2] |= LUT_DEF(lutidx,
  387. op->data.dir == SPI_MEM_DATA_IN ?
  388. LUT_FSL_READ : LUT_FSL_WRITE,
  389. LUT_PAD(op->data.buswidth),
  390. 0);
  391. lutidx++;
  392. }
  393. lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0);
  394. /* unlock LUT */
  395. qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
  396. qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
  397. dev_dbg(q->dev, "CMD[%x] lutval[0:%x \t 1:%x \t 2:%x \t 3:%x]\n",
  398. op->cmd.opcode, lutval[0], lutval[1], lutval[2], lutval[3]);
  399. /* fill LUT */
  400. for (i = 0; i < ARRAY_SIZE(lutval); i++)
  401. qspi_writel(q, lutval[i], base + QUADSPI_LUT_REG(i));
  402. if (IS_ENABLED(CONFIG_FSL_QSPI_AHB_FULL_MAP)) {
  403. if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN &&
  404. op->addr.nbytes) {
  405. for (i = 0; i < ARRAY_SIZE(lutval); i++)
  406. qspi_writel(q, lutval[i], base + QUADSPI_AHB_LUT_REG(i));
  407. }
  408. }
  409. /* lock LUT */
  410. qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
  411. qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
  412. }
  413. /*
  414. * If we have changed the content of the flash by writing or erasing, or if we
  415. * read from flash with a different offset into the page buffer, we need to
  416. * invalidate the AHB buffer. If we do not do so, we may read out the wrong
  417. * data. The spec tells us reset the AHB domain and Serial Flash domain at
  418. * the same time.
  419. */
  420. static void fsl_qspi_invalidate(struct fsl_qspi *q)
  421. {
  422. u32 reg;
  423. reg = qspi_readl(q, q->iobase + QUADSPI_MCR);
  424. reg |= QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK;
  425. qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
  426. /*
  427. * The minimum delay : 1 AHB + 2 SFCK clocks.
  428. * Delay 1 us is enough.
  429. */
  430. udelay(1);
  431. reg &= ~(QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK);
  432. qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
  433. }
  434. static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_slave *slave)
  435. {
  436. struct dm_spi_slave_platdata *plat =
  437. dev_get_parent_platdata(slave->dev);
  438. if (q->selected == plat->cs)
  439. return;
  440. q->selected = plat->cs;
  441. fsl_qspi_invalidate(q);
  442. }
  443. static u32 fsl_qspi_memsize_per_cs(struct fsl_qspi *q)
  444. {
  445. if (IS_ENABLED(CONFIG_FSL_QSPI_AHB_FULL_MAP)) {
  446. if (needs_single_bus(q))
  447. return q->memmap_size / 2;
  448. else
  449. return q->memmap_size / 4;
  450. } else {
  451. return ALIGN(q->devtype_data->ahb_buf_size, 0x400);
  452. }
  453. }
  454. static void fsl_qspi_read_ahb(struct fsl_qspi *q, const struct spi_mem_op *op)
  455. {
  456. void __iomem *ahb_read_addr = q->ahb_addr;
  457. if (IS_ENABLED(CONFIG_FSL_QSPI_AHB_FULL_MAP)) {
  458. if (op->addr.nbytes)
  459. ahb_read_addr += op->addr.val;
  460. }
  461. memcpy_fromio(op->data.buf.in,
  462. ahb_read_addr + q->selected * fsl_qspi_memsize_per_cs(q),
  463. op->data.nbytes);
  464. }
  465. static void fsl_qspi_fill_txfifo(struct fsl_qspi *q,
  466. const struct spi_mem_op *op)
  467. {
  468. void __iomem *base = q->iobase;
  469. int i;
  470. u32 val;
  471. for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) {
  472. memcpy(&val, op->data.buf.out + i, 4);
  473. val = fsl_qspi_endian_xchg(q, val);
  474. qspi_writel(q, val, base + QUADSPI_TBDR);
  475. }
  476. if (i < op->data.nbytes) {
  477. memcpy(&val, op->data.buf.out + i, op->data.nbytes - i);
  478. val = fsl_qspi_endian_xchg(q, val);
  479. qspi_writel(q, val, base + QUADSPI_TBDR);
  480. }
  481. if (needs_fill_txfifo(q)) {
  482. for (i = op->data.nbytes; i < 16; i += 4)
  483. qspi_writel(q, 0, base + QUADSPI_TBDR);
  484. }
  485. }
  486. static void fsl_qspi_read_rxfifo(struct fsl_qspi *q,
  487. const struct spi_mem_op *op)
  488. {
  489. void __iomem *base = q->iobase;
  490. int i;
  491. u8 *buf = op->data.buf.in;
  492. u32 val;
  493. for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) {
  494. val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));
  495. val = fsl_qspi_endian_xchg(q, val);
  496. memcpy(buf + i, &val, 4);
  497. }
  498. if (i < op->data.nbytes) {
  499. val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));
  500. val = fsl_qspi_endian_xchg(q, val);
  501. memcpy(buf + i, &val, op->data.nbytes - i);
  502. }
  503. }
  504. static int fsl_qspi_readl_poll_tout(struct fsl_qspi *q, void __iomem *base,
  505. u32 mask, u32 delay_us, u32 timeout_us)
  506. {
  507. u32 reg;
  508. if (!q->devtype_data->little_endian)
  509. mask = (u32)cpu_to_be32(mask);
  510. return readl_poll_timeout(base, reg, !(reg & mask), timeout_us);
  511. }
  512. static int fsl_qspi_do_op(struct fsl_qspi *q, const struct spi_mem_op *op)
  513. {
  514. void __iomem *base = q->iobase;
  515. int err = 0;
  516. /*
  517. * Always start the sequence at the same index since we update
  518. * the LUT at each exec_op() call. And also specify the DATA
  519. * length, since it's has not been specified in the LUT.
  520. */
  521. qspi_writel(q, op->data.nbytes | QUADSPI_IPCR_SEQID(SEQID_LUT),
  522. base + QUADSPI_IPCR);
  523. /* wait for the controller being ready */
  524. err = fsl_qspi_readl_poll_tout(q, base + QUADSPI_SR,
  525. (QUADSPI_SR_IP_ACC_MASK |
  526. QUADSPI_SR_AHB_ACC_MASK),
  527. 10, 1000);
  528. if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN)
  529. fsl_qspi_read_rxfifo(q, op);
  530. return err;
  531. }
  532. static int fsl_qspi_exec_op(struct spi_slave *slave,
  533. const struct spi_mem_op *op)
  534. {
  535. struct fsl_qspi *q = dev_get_priv(slave->dev->parent);
  536. void __iomem *base = q->iobase;
  537. u32 addr_offset = 0;
  538. int err = 0;
  539. /* wait for the controller being ready */
  540. fsl_qspi_readl_poll_tout(q, base + QUADSPI_SR, (QUADSPI_SR_IP_ACC_MASK |
  541. QUADSPI_SR_AHB_ACC_MASK), 10, 1000);
  542. fsl_qspi_select_mem(q, slave);
  543. if (needs_amba_base_offset(q))
  544. addr_offset = q->memmap_phy;
  545. if (IS_ENABLED(CONFIG_FSL_QSPI_AHB_FULL_MAP)) {
  546. if (op->addr.nbytes)
  547. addr_offset += op->addr.val;
  548. }
  549. qspi_writel(q,
  550. q->selected * fsl_qspi_memsize_per_cs(q) + addr_offset,
  551. base + QUADSPI_SFAR);
  552. qspi_writel(q, qspi_readl(q, base + QUADSPI_MCR) |
  553. QUADSPI_MCR_CLR_RXF_MASK | QUADSPI_MCR_CLR_TXF_MASK,
  554. base + QUADSPI_MCR);
  555. qspi_writel(q, QUADSPI_SPTRCLR_BFPTRC | QUADSPI_SPTRCLR_IPPTRC,
  556. base + QUADSPI_SPTRCLR);
  557. fsl_qspi_prepare_lut(q, op);
  558. /*
  559. * If we have large chunks of data, we read them through the AHB bus
  560. * by accessing the mapped memory. In all other cases we use
  561. * IP commands to access the flash.
  562. */
  563. if (op->data.nbytes > (q->devtype_data->rxfifo - 4) &&
  564. op->data.dir == SPI_MEM_DATA_IN) {
  565. fsl_qspi_read_ahb(q, op);
  566. } else {
  567. qspi_writel(q, QUADSPI_RBCT_WMRK_MASK |
  568. QUADSPI_RBCT_RXBRD_USEIPS, base + QUADSPI_RBCT);
  569. if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
  570. fsl_qspi_fill_txfifo(q, op);
  571. err = fsl_qspi_do_op(q, op);
  572. }
  573. /* Invalidate the data in the AHB buffer. */
  574. fsl_qspi_invalidate(q);
  575. return err;
  576. }
  577. static int fsl_qspi_adjust_op_size(struct spi_slave *slave,
  578. struct spi_mem_op *op)
  579. {
  580. struct fsl_qspi *q = dev_get_priv(slave->dev->parent);
  581. if (op->data.dir == SPI_MEM_DATA_OUT) {
  582. if (op->data.nbytes > q->devtype_data->txfifo)
  583. op->data.nbytes = q->devtype_data->txfifo;
  584. } else {
  585. if (op->data.nbytes > q->devtype_data->ahb_buf_size)
  586. op->data.nbytes = q->devtype_data->ahb_buf_size;
  587. else if (op->data.nbytes > (q->devtype_data->rxfifo - 4))
  588. op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8);
  589. }
  590. return 0;
  591. }
  592. static int fsl_qspi_default_setup(struct fsl_qspi *q)
  593. {
  594. void __iomem *base = q->iobase;
  595. u32 reg, addr_offset = 0, memsize_cs;
  596. /* Reset the module */
  597. qspi_writel(q, QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK,
  598. base + QUADSPI_MCR);
  599. udelay(1);
  600. /* Disable the module */
  601. qspi_writel(q, QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,
  602. base + QUADSPI_MCR);
  603. /*
  604. * Previous boot stages (BootROM, bootloader) might have used DDR
  605. * mode and did not clear the TDH bits. As we currently use SDR mode
  606. * only, clear the TDH bits if necessary.
  607. */
  608. if (needs_tdh_setting(q))
  609. qspi_writel(q, qspi_readl(q, base + QUADSPI_FLSHCR) &
  610. ~QUADSPI_FLSHCR_TDH_MASK,
  611. base + QUADSPI_FLSHCR);
  612. reg = qspi_readl(q, base + QUADSPI_SMPR);
  613. qspi_writel(q, reg & ~(QUADSPI_SMPR_FSDLY_MASK
  614. | QUADSPI_SMPR_FSPHS_MASK
  615. | QUADSPI_SMPR_HSENA_MASK
  616. | QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR);
  617. /* We only use the buffer3 for AHB read */
  618. qspi_writel(q, 0, base + QUADSPI_BUF0IND);
  619. qspi_writel(q, 0, base + QUADSPI_BUF1IND);
  620. qspi_writel(q, 0, base + QUADSPI_BUF2IND);
  621. if (IS_ENABLED(CONFIG_FSL_QSPI_AHB_FULL_MAP))
  622. qspi_writel(q, QUADSPI_BFGENCR_SEQID(SEQID_LUT_AHB),
  623. q->iobase + QUADSPI_BFGENCR);
  624. else
  625. qspi_writel(q, QUADSPI_BFGENCR_SEQID(SEQID_LUT),
  626. q->iobase + QUADSPI_BFGENCR);
  627. qspi_writel(q, QUADSPI_RBCT_WMRK_MASK, base + QUADSPI_RBCT);
  628. qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
  629. QUADSPI_BUF3CR_ADATSZ(q->devtype_data->ahb_buf_size / 8),
  630. base + QUADSPI_BUF3CR);
  631. if (needs_amba_base_offset(q))
  632. addr_offset = q->memmap_phy;
  633. /*
  634. * In HW there can be a maximum of four chips on two buses with
  635. * two chip selects on each bus. We use four chip selects in SW
  636. * to differentiate between the four chips.
  637. * We use ahb_buf_size for each chip and set SFA1AD, SFA2AD, SFB1AD,
  638. * SFB2AD accordingly.
  639. */
  640. memsize_cs = fsl_qspi_memsize_per_cs(q);
  641. qspi_writel(q, memsize_cs + addr_offset,
  642. base + QUADSPI_SFA1AD);
  643. qspi_writel(q, memsize_cs * 2 + addr_offset,
  644. base + QUADSPI_SFA2AD);
  645. if (!needs_single_bus(q)) {
  646. qspi_writel(q, memsize_cs * 3 + addr_offset,
  647. base + QUADSPI_SFB1AD);
  648. qspi_writel(q, memsize_cs * 4 + addr_offset,
  649. base + QUADSPI_SFB2AD);
  650. }
  651. q->selected = -1;
  652. /* Enable the module */
  653. qspi_writel(q, QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,
  654. base + QUADSPI_MCR);
  655. return 0;
  656. }
  657. static const struct spi_controller_mem_ops fsl_qspi_mem_ops = {
  658. .adjust_op_size = fsl_qspi_adjust_op_size,
  659. .supports_op = fsl_qspi_supports_op,
  660. .exec_op = fsl_qspi_exec_op,
  661. };
  662. static int fsl_qspi_probe(struct udevice *bus)
  663. {
  664. struct dm_spi_bus *dm_bus = bus->uclass_priv;
  665. struct fsl_qspi *q = dev_get_priv(bus);
  666. const void *blob = gd->fdt_blob;
  667. int node = dev_of_offset(bus);
  668. struct fdt_resource res;
  669. int ret;
  670. q->dev = bus;
  671. q->devtype_data = (struct fsl_qspi_devtype_data *)
  672. dev_get_driver_data(bus);
  673. /* find the resources */
  674. ret = fdt_get_named_resource(blob, node, "reg", "reg-names", "QuadSPI",
  675. &res);
  676. if (ret) {
  677. dev_err(bus, "Can't get regs base addresses(ret = %d)!\n", ret);
  678. return -ENOMEM;
  679. }
  680. q->iobase = map_physmem(res.start, res.end - res.start, MAP_NOCACHE);
  681. ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
  682. "QuadSPI-memory", &res);
  683. if (ret) {
  684. dev_err(bus, "Can't get AMBA base addresses(ret = %d)!\n", ret);
  685. return -ENOMEM;
  686. }
  687. q->ahb_addr = map_physmem(res.start, res.end - res.start, MAP_NOCACHE);
  688. q->memmap_phy = res.start;
  689. q->memmap_size = res.end - res.start;
  690. dm_bus->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
  691. 66000000);
  692. fsl_qspi_default_setup(q);
  693. return 0;
  694. }
  695. static int fsl_qspi_xfer(struct udevice *dev, unsigned int bitlen,
  696. const void *dout, void *din, unsigned long flags)
  697. {
  698. return 0;
  699. }
  700. static int fsl_qspi_claim_bus(struct udevice *dev)
  701. {
  702. return 0;
  703. }
  704. static int fsl_qspi_release_bus(struct udevice *dev)
  705. {
  706. return 0;
  707. }
  708. static int fsl_qspi_set_speed(struct udevice *bus, uint speed)
  709. {
  710. return 0;
  711. }
  712. static int fsl_qspi_set_mode(struct udevice *bus, uint mode)
  713. {
  714. return 0;
  715. }
  716. static const struct dm_spi_ops fsl_qspi_ops = {
  717. .claim_bus = fsl_qspi_claim_bus,
  718. .release_bus = fsl_qspi_release_bus,
  719. .xfer = fsl_qspi_xfer,
  720. .set_speed = fsl_qspi_set_speed,
  721. .set_mode = fsl_qspi_set_mode,
  722. .mem_ops = &fsl_qspi_mem_ops,
  723. };
  724. static const struct udevice_id fsl_qspi_ids[] = {
  725. { .compatible = "fsl,vf610-qspi", .data = (ulong)&vybrid_data, },
  726. { .compatible = "fsl,imx6sx-qspi", .data = (ulong)&imx6sx_data, },
  727. { .compatible = "fsl,imx6ul-qspi", .data = (ulong)&imx6ul_data, },
  728. { .compatible = "fsl,imx7d-qspi", .data = (ulong)&imx7d_data, },
  729. { .compatible = "fsl,imx7ulp-qspi", .data = (ulong)&imx7ulp_data, },
  730. { .compatible = "fsl,ls1021a-qspi", .data = (ulong)&ls1021a_data, },
  731. { .compatible = "fsl,ls1088a-qspi", .data = (ulong)&ls1088a_data, },
  732. { .compatible = "fsl,ls2080a-qspi", .data = (ulong)&ls2080a_data, },
  733. { }
  734. };
  735. U_BOOT_DRIVER(fsl_qspi) = {
  736. .name = "fsl_qspi",
  737. .id = UCLASS_SPI,
  738. .of_match = fsl_qspi_ids,
  739. .ops = &fsl_qspi_ops,
  740. .priv_auto_alloc_size = sizeof(struct fsl_qspi),
  741. .probe = fsl_qspi_probe,
  742. };