designware_spi.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Designware master SPI core controller driver
  4. *
  5. * Copyright (C) 2014 Stefan Roese <sr@denx.de>
  6. * Copyright (C) 2020 Sean Anderson <seanga2@gmail.com>
  7. *
  8. * Very loosely based on the Linux driver:
  9. * drivers/spi/spi-dw.c, which is:
  10. * Copyright (c) 2009, Intel Corporation.
  11. */
  12. #define LOG_CATEGORY UCLASS_SPI
  13. #include <common.h>
  14. #include <clk.h>
  15. #include <dm.h>
  16. #include <dm/device_compat.h>
  17. #include <errno.h>
  18. #include <fdtdec.h>
  19. #include <log.h>
  20. #include <malloc.h>
  21. #include <reset.h>
  22. #include <spi.h>
  23. #include <spi-mem.h>
  24. #include <asm/io.h>
  25. #include <asm-generic/gpio.h>
  26. #include <linux/bitfield.h>
  27. #include <linux/bitops.h>
  28. #include <linux/compat.h>
  29. #include <linux/iopoll.h>
  30. #include <linux/sizes.h>
  31. /* Register offsets */
  32. #define DW_SPI_CTRLR0 0x00
  33. #define DW_SPI_CTRLR1 0x04
  34. #define DW_SPI_SSIENR 0x08
  35. #define DW_SPI_MWCR 0x0c
  36. #define DW_SPI_SER 0x10
  37. #define DW_SPI_BAUDR 0x14
  38. #define DW_SPI_TXFTLR 0x18
  39. #define DW_SPI_RXFTLR 0x1c
  40. #define DW_SPI_TXFLR 0x20
  41. #define DW_SPI_RXFLR 0x24
  42. #define DW_SPI_SR 0x28
  43. #define DW_SPI_IMR 0x2c
  44. #define DW_SPI_ISR 0x30
  45. #define DW_SPI_RISR 0x34
  46. #define DW_SPI_TXOICR 0x38
  47. #define DW_SPI_RXOICR 0x3c
  48. #define DW_SPI_RXUICR 0x40
  49. #define DW_SPI_MSTICR 0x44
  50. #define DW_SPI_ICR 0x48
  51. #define DW_SPI_DMACR 0x4c
  52. #define DW_SPI_DMATDLR 0x50
  53. #define DW_SPI_DMARDLR 0x54
  54. #define DW_SPI_IDR 0x58
  55. #define DW_SPI_VERSION 0x5c
  56. #define DW_SPI_DR 0x60
  57. /* Bit fields in CTRLR0 */
  58. /*
  59. * Only present when SSI_MAX_XFER_SIZE=16. This is the default, and the only
  60. * option before version 3.23a.
  61. */
  62. #define CTRLR0_DFS_MASK GENMASK(3, 0)
  63. #define CTRLR0_FRF_MASK GENMASK(5, 4)
  64. #define CTRLR0_FRF_SPI 0x0
  65. #define CTRLR0_FRF_SSP 0x1
  66. #define CTRLR0_FRF_MICROWIRE 0x2
  67. #define CTRLR0_FRF_RESV 0x3
  68. #define CTRLR0_MODE_MASK GENMASK(7, 6)
  69. #define CTRLR0_MODE_SCPH 0x1
  70. #define CTRLR0_MODE_SCPOL 0x2
  71. #define CTRLR0_TMOD_MASK GENMASK(9, 8)
  72. #define CTRLR0_TMOD_TR 0x0 /* xmit & recv */
  73. #define CTRLR0_TMOD_TO 0x1 /* xmit only */
  74. #define CTRLR0_TMOD_RO 0x2 /* recv only */
  75. #define CTRLR0_TMOD_EPROMREAD 0x3 /* eeprom read mode */
  76. #define CTRLR0_SLVOE_OFFSET 10
  77. #define CTRLR0_SRL_OFFSET 11
  78. #define CTRLR0_CFS_MASK GENMASK(15, 12)
  79. /* Only present when SSI_MAX_XFER_SIZE=32 */
  80. #define CTRLR0_DFS_32_MASK GENMASK(20, 16)
  81. /* The next field is only present on versions after 4.00a */
  82. #define CTRLR0_SPI_FRF_MASK GENMASK(22, 21)
  83. #define CTRLR0_SPI_FRF_BYTE 0x0
  84. #define CTRLR0_SPI_FRF_DUAL 0x1
  85. #define CTRLR0_SPI_FRF_QUAD 0x2
  86. /* Bit fields in CTRLR0 based on DWC_ssi_databook.pdf v1.01a */
  87. #define DWC_SSI_CTRLR0_DFS_MASK GENMASK(4, 0)
  88. #define DWC_SSI_CTRLR0_FRF_MASK GENMASK(7, 6)
  89. #define DWC_SSI_CTRLR0_MODE_MASK GENMASK(9, 8)
  90. #define DWC_SSI_CTRLR0_TMOD_MASK GENMASK(11, 10)
  91. #define DWC_SSI_CTRLR0_SRL_OFFSET 13
  92. #define DWC_SSI_CTRLR0_SPI_FRF_MASK GENMASK(23, 22)
  93. /* Bit fields in SR, 7 bits */
  94. #define SR_MASK GENMASK(6, 0) /* cover 7 bits */
  95. #define SR_BUSY BIT(0)
  96. #define SR_TF_NOT_FULL BIT(1)
  97. #define SR_TF_EMPT BIT(2)
  98. #define SR_RF_NOT_EMPT BIT(3)
  99. #define SR_RF_FULL BIT(4)
  100. #define SR_TX_ERR BIT(5)
  101. #define SR_DCOL BIT(6)
  102. #define RX_TIMEOUT 1000 /* timeout in ms */
  103. struct dw_spi_platdata {
  104. s32 frequency; /* Default clock frequency, -1 for none */
  105. void __iomem *regs;
  106. };
  107. struct dw_spi_priv {
  108. struct clk clk;
  109. struct reset_ctl_bulk resets;
  110. struct gpio_desc cs_gpio; /* External chip-select gpio */
  111. u32 (*update_cr0)(struct dw_spi_priv *priv);
  112. void __iomem *regs;
  113. unsigned long bus_clk_rate;
  114. unsigned int freq; /* Default frequency */
  115. unsigned int mode;
  116. const void *tx;
  117. const void *tx_end;
  118. void *rx;
  119. void *rx_end;
  120. u32 fifo_len; /* depth of the FIFO buffer */
  121. u32 max_xfer; /* Maximum transfer size (in bits) */
  122. int bits_per_word;
  123. int len;
  124. u8 cs; /* chip select pin */
  125. u8 tmode; /* TR/TO/RO/EEPROM */
  126. u8 type; /* SPI/SSP/MicroWire */
  127. };
  128. static inline u32 dw_read(struct dw_spi_priv *priv, u32 offset)
  129. {
  130. return __raw_readl(priv->regs + offset);
  131. }
  132. static inline void dw_write(struct dw_spi_priv *priv, u32 offset, u32 val)
  133. {
  134. __raw_writel(val, priv->regs + offset);
  135. }
  136. static u32 dw_spi_dw16_update_cr0(struct dw_spi_priv *priv)
  137. {
  138. return FIELD_PREP(CTRLR0_DFS_MASK, priv->bits_per_word - 1)
  139. | FIELD_PREP(CTRLR0_FRF_MASK, priv->type)
  140. | FIELD_PREP(CTRLR0_MODE_MASK, priv->mode)
  141. | FIELD_PREP(CTRLR0_TMOD_MASK, priv->tmode);
  142. }
  143. static u32 dw_spi_dw32_update_cr0(struct dw_spi_priv *priv)
  144. {
  145. return FIELD_PREP(CTRLR0_DFS_32_MASK, priv->bits_per_word - 1)
  146. | FIELD_PREP(CTRLR0_FRF_MASK, priv->type)
  147. | FIELD_PREP(CTRLR0_MODE_MASK, priv->mode)
  148. | FIELD_PREP(CTRLR0_TMOD_MASK, priv->tmode);
  149. }
  150. static u32 dw_spi_dwc_update_cr0(struct dw_spi_priv *priv)
  151. {
  152. return FIELD_PREP(DWC_SSI_CTRLR0_DFS_MASK, priv->bits_per_word - 1)
  153. | FIELD_PREP(DWC_SSI_CTRLR0_FRF_MASK, priv->type)
  154. | FIELD_PREP(DWC_SSI_CTRLR0_MODE_MASK, priv->mode)
  155. | FIELD_PREP(DWC_SSI_CTRLR0_TMOD_MASK, priv->tmode);
  156. }
  157. static int dw_spi_apb_init(struct udevice *bus, struct dw_spi_priv *priv)
  158. {
  159. /* If we read zeros from DFS, then we need to use DFS_32 instead */
  160. dw_write(priv, DW_SPI_SSIENR, 0);
  161. dw_write(priv, DW_SPI_CTRLR0, 0xffffffff);
  162. if (FIELD_GET(CTRLR0_DFS_MASK, dw_read(priv, DW_SPI_CTRLR0))) {
  163. priv->max_xfer = 16;
  164. priv->update_cr0 = dw_spi_dw16_update_cr0;
  165. } else {
  166. priv->max_xfer = 32;
  167. priv->update_cr0 = dw_spi_dw32_update_cr0;
  168. }
  169. return 0;
  170. }
  171. static int dw_spi_dwc_init(struct udevice *bus, struct dw_spi_priv *priv)
  172. {
  173. priv->max_xfer = 32;
  174. priv->update_cr0 = dw_spi_dwc_update_cr0;
  175. return 0;
  176. }
  177. static int request_gpio_cs(struct udevice *bus)
  178. {
  179. #if CONFIG_IS_ENABLED(DM_GPIO) && !defined(CONFIG_SPL_BUILD)
  180. struct dw_spi_priv *priv = dev_get_priv(bus);
  181. int ret;
  182. /* External chip select gpio line is optional */
  183. ret = gpio_request_by_name(bus, "cs-gpios", 0, &priv->cs_gpio,
  184. GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
  185. if (ret == -ENOENT)
  186. return 0;
  187. if (ret < 0) {
  188. dev_err(bus, "Couldn't request gpio! (error %d)\n", ret);
  189. return ret;
  190. }
  191. if (dm_gpio_is_valid(&priv->cs_gpio)) {
  192. dm_gpio_set_dir_flags(&priv->cs_gpio,
  193. GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
  194. }
  195. dev_dbg(bus, "Using external gpio for CS management\n");
  196. #endif
  197. return 0;
  198. }
  199. static int dw_spi_ofdata_to_platdata(struct udevice *bus)
  200. {
  201. struct dw_spi_platdata *plat = bus->platdata;
  202. plat->regs = dev_read_addr_ptr(bus);
  203. if (!plat->regs)
  204. return -EINVAL;
  205. /* Use 500KHz as a suitable default */
  206. plat->frequency = dev_read_u32_default(bus, "spi-max-frequency",
  207. 500000);
  208. if (dev_read_bool(bus, "spi-slave"))
  209. return -EINVAL;
  210. dev_info(bus, "max-frequency=%d\n", plat->frequency);
  211. return request_gpio_cs(bus);
  212. }
  213. /* Restart the controller, disable all interrupts, clean rx fifo */
  214. static void spi_hw_init(struct udevice *bus, struct dw_spi_priv *priv)
  215. {
  216. dw_write(priv, DW_SPI_SSIENR, 0);
  217. dw_write(priv, DW_SPI_IMR, 0xff);
  218. dw_write(priv, DW_SPI_SSIENR, 1);
  219. /*
  220. * Try to detect the FIFO depth if not set by interface driver,
  221. * the depth could be from 2 to 256 from HW spec
  222. */
  223. if (!priv->fifo_len) {
  224. u32 fifo;
  225. for (fifo = 1; fifo < 256; fifo++) {
  226. dw_write(priv, DW_SPI_TXFTLR, fifo);
  227. if (fifo != dw_read(priv, DW_SPI_TXFTLR))
  228. break;
  229. }
  230. priv->fifo_len = (fifo == 1) ? 0 : fifo;
  231. dw_write(priv, DW_SPI_TXFTLR, 0);
  232. }
  233. dev_dbg(bus, "fifo_len=%d\n", priv->fifo_len);
  234. }
  235. /*
  236. * We define dw_spi_get_clk function as 'weak' as some targets
  237. * (like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) don't use standard clock API
  238. * and implement dw_spi_get_clk their own way in their clock manager.
  239. */
  240. __weak int dw_spi_get_clk(struct udevice *bus, ulong *rate)
  241. {
  242. struct dw_spi_priv *priv = dev_get_priv(bus);
  243. int ret;
  244. ret = clk_get_by_index(bus, 0, &priv->clk);
  245. if (ret)
  246. return ret;
  247. ret = clk_enable(&priv->clk);
  248. if (ret && ret != -ENOSYS && ret != -ENOTSUPP)
  249. return ret;
  250. *rate = clk_get_rate(&priv->clk);
  251. if (!*rate)
  252. goto err_rate;
  253. dev_dbg(bus, "Got clock via device tree: %lu Hz\n", *rate);
  254. return 0;
  255. err_rate:
  256. clk_disable(&priv->clk);
  257. clk_free(&priv->clk);
  258. return -EINVAL;
  259. }
  260. static int dw_spi_reset(struct udevice *bus)
  261. {
  262. int ret;
  263. struct dw_spi_priv *priv = dev_get_priv(bus);
  264. ret = reset_get_bulk(bus, &priv->resets);
  265. if (ret) {
  266. /*
  267. * Return 0 if error due to !CONFIG_DM_RESET and reset
  268. * DT property is not present.
  269. */
  270. if (ret == -ENOENT || ret == -ENOTSUPP)
  271. return 0;
  272. dev_warn(bus, "Couldn't find/assert reset device (error %d)\n",
  273. ret);
  274. return ret;
  275. }
  276. ret = reset_deassert_bulk(&priv->resets);
  277. if (ret) {
  278. reset_release_bulk(&priv->resets);
  279. dev_err(bus, "Failed to de-assert reset for SPI (error %d)\n",
  280. ret);
  281. return ret;
  282. }
  283. return 0;
  284. }
  285. typedef int (*dw_spi_init_t)(struct udevice *bus, struct dw_spi_priv *priv);
  286. static int dw_spi_probe(struct udevice *bus)
  287. {
  288. dw_spi_init_t init = (dw_spi_init_t)dev_get_driver_data(bus);
  289. struct dw_spi_platdata *plat = dev_get_platdata(bus);
  290. struct dw_spi_priv *priv = dev_get_priv(bus);
  291. int ret;
  292. u32 version;
  293. priv->regs = plat->regs;
  294. priv->freq = plat->frequency;
  295. ret = dw_spi_get_clk(bus, &priv->bus_clk_rate);
  296. if (ret)
  297. return ret;
  298. ret = dw_spi_reset(bus);
  299. if (ret)
  300. return ret;
  301. if (!init)
  302. return -EINVAL;
  303. ret = init(bus, priv);
  304. if (ret)
  305. return ret;
  306. version = dw_read(priv, DW_SPI_VERSION);
  307. dev_dbg(bus, "ssi_version_id=%c.%c%c%c ssi_max_xfer_size=%u\n",
  308. version >> 24, version >> 16, version >> 8, version,
  309. priv->max_xfer);
  310. /* Currently only bits_per_word == 8 supported */
  311. priv->bits_per_word = 8;
  312. priv->tmode = 0; /* Tx & Rx */
  313. /* Basic HW init */
  314. spi_hw_init(bus, priv);
  315. return 0;
  316. }
  317. /* Return the max entries we can fill into tx fifo */
  318. static inline u32 tx_max(struct dw_spi_priv *priv)
  319. {
  320. u32 tx_left, tx_room, rxtx_gap;
  321. tx_left = (priv->tx_end - priv->tx) / (priv->bits_per_word >> 3);
  322. tx_room = priv->fifo_len - dw_read(priv, DW_SPI_TXFLR);
  323. /*
  324. * Another concern is about the tx/rx mismatch, we
  325. * thought about using (priv->fifo_len - rxflr - txflr) as
  326. * one maximum value for tx, but it doesn't cover the
  327. * data which is out of tx/rx fifo and inside the
  328. * shift registers. So a control from sw point of
  329. * view is taken.
  330. */
  331. rxtx_gap = ((priv->rx_end - priv->rx) - (priv->tx_end - priv->tx)) /
  332. (priv->bits_per_word >> 3);
  333. return min3(tx_left, tx_room, (u32)(priv->fifo_len - rxtx_gap));
  334. }
  335. /* Return the max entries we should read out of rx fifo */
  336. static inline u32 rx_max(struct dw_spi_priv *priv)
  337. {
  338. u32 rx_left = (priv->rx_end - priv->rx) / (priv->bits_per_word >> 3);
  339. return min_t(u32, rx_left, dw_read(priv, DW_SPI_RXFLR));
  340. }
  341. static void dw_writer(struct dw_spi_priv *priv)
  342. {
  343. u32 max = tx_max(priv);
  344. u32 txw = 0xFFFFFFFF;
  345. while (max--) {
  346. /* Set the tx word if the transfer's original "tx" is not null */
  347. if (priv->tx_end - priv->len) {
  348. if (priv->bits_per_word == 8)
  349. txw = *(u8 *)(priv->tx);
  350. else
  351. txw = *(u16 *)(priv->tx);
  352. }
  353. dw_write(priv, DW_SPI_DR, txw);
  354. log_content("tx=0x%02x\n", txw);
  355. priv->tx += priv->bits_per_word >> 3;
  356. }
  357. }
  358. static void dw_reader(struct dw_spi_priv *priv)
  359. {
  360. u32 max = rx_max(priv);
  361. u16 rxw;
  362. while (max--) {
  363. rxw = dw_read(priv, DW_SPI_DR);
  364. log_content("rx=0x%02x\n", rxw);
  365. /* Care about rx if the transfer's original "rx" is not null */
  366. if (priv->rx_end - priv->len) {
  367. if (priv->bits_per_word == 8)
  368. *(u8 *)(priv->rx) = rxw;
  369. else
  370. *(u16 *)(priv->rx) = rxw;
  371. }
  372. priv->rx += priv->bits_per_word >> 3;
  373. }
  374. }
  375. static int poll_transfer(struct dw_spi_priv *priv)
  376. {
  377. do {
  378. dw_writer(priv);
  379. dw_reader(priv);
  380. } while (priv->rx_end > priv->rx);
  381. return 0;
  382. }
  383. /*
  384. * We define external_cs_manage function as 'weak' as some targets
  385. * (like MSCC Ocelot) don't control the external CS pin using a GPIO
  386. * controller. These SoCs use specific registers to control by
  387. * software the SPI pins (and especially the CS).
  388. */
  389. __weak void external_cs_manage(struct udevice *dev, bool on)
  390. {
  391. #if CONFIG_IS_ENABLED(DM_GPIO) && !defined(CONFIG_SPL_BUILD)
  392. struct dw_spi_priv *priv = dev_get_priv(dev->parent);
  393. if (!dm_gpio_is_valid(&priv->cs_gpio))
  394. return;
  395. dm_gpio_set_value(&priv->cs_gpio, on ? 1 : 0);
  396. #endif
  397. }
  398. static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen,
  399. const void *dout, void *din, unsigned long flags)
  400. {
  401. struct udevice *bus = dev->parent;
  402. struct dw_spi_priv *priv = dev_get_priv(bus);
  403. const u8 *tx = dout;
  404. u8 *rx = din;
  405. int ret = 0;
  406. u32 cr0 = 0;
  407. u32 val;
  408. u32 cs;
  409. /* spi core configured to do 8 bit transfers */
  410. if (bitlen % 8) {
  411. dev_err(dev, "Non byte aligned SPI transfer.\n");
  412. return -1;
  413. }
  414. /* Start the transaction if necessary. */
  415. if (flags & SPI_XFER_BEGIN)
  416. external_cs_manage(dev, false);
  417. if (rx && tx)
  418. priv->tmode = CTRLR0_TMOD_TR;
  419. else if (rx)
  420. priv->tmode = CTRLR0_TMOD_RO;
  421. else
  422. /*
  423. * In transmit only mode (CTRL0_TMOD_TO) input FIFO never gets
  424. * any data which breaks our logic in poll_transfer() above.
  425. */
  426. priv->tmode = CTRLR0_TMOD_TR;
  427. cr0 = priv->update_cr0(priv);
  428. priv->len = bitlen >> 3;
  429. priv->tx = (void *)tx;
  430. priv->tx_end = priv->tx + priv->len;
  431. priv->rx = rx;
  432. priv->rx_end = priv->rx + priv->len;
  433. /* Disable controller before writing control registers */
  434. dw_write(priv, DW_SPI_SSIENR, 0);
  435. dev_dbg(dev, "cr0=%08x rx=%p tx=%p len=%d [bytes]\n", cr0, rx, tx,
  436. priv->len);
  437. /* Reprogram cr0 only if changed */
  438. if (dw_read(priv, DW_SPI_CTRLR0) != cr0)
  439. dw_write(priv, DW_SPI_CTRLR0, cr0);
  440. /*
  441. * Configure the desired SS (slave select 0...3) in the controller
  442. * The DW SPI controller will activate and deactivate this CS
  443. * automatically. So no cs_activate() etc is needed in this driver.
  444. */
  445. cs = spi_chip_select(dev);
  446. dw_write(priv, DW_SPI_SER, 1 << cs);
  447. /* Enable controller after writing control registers */
  448. dw_write(priv, DW_SPI_SSIENR, 1);
  449. /* Start transfer in a polling loop */
  450. ret = poll_transfer(priv);
  451. /*
  452. * Wait for current transmit operation to complete.
  453. * Otherwise if some data still exists in Tx FIFO it can be
  454. * silently flushed, i.e. dropped on disabling of the controller,
  455. * which happens when writing 0 to DW_SPI_SSIENR which happens
  456. * in the beginning of new transfer.
  457. */
  458. if (readl_poll_timeout(priv->regs + DW_SPI_SR, val,
  459. (val & SR_TF_EMPT) && !(val & SR_BUSY),
  460. RX_TIMEOUT * 1000)) {
  461. ret = -ETIMEDOUT;
  462. }
  463. /* Stop the transaction if necessary */
  464. if (flags & SPI_XFER_END)
  465. external_cs_manage(dev, true);
  466. return ret;
  467. }
  468. /*
  469. * This function is necessary for reading SPI flash with the native CS
  470. * c.f. https://lkml.org/lkml/2015/12/23/132
  471. */
  472. static int dw_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op)
  473. {
  474. bool read = op->data.dir == SPI_MEM_DATA_IN;
  475. int pos, i, ret = 0;
  476. struct udevice *bus = slave->dev->parent;
  477. struct dw_spi_priv *priv = dev_get_priv(bus);
  478. u8 op_len = sizeof(op->cmd.opcode) + op->addr.nbytes + op->dummy.nbytes;
  479. u8 op_buf[op_len];
  480. u32 cr0;
  481. if (read)
  482. priv->tmode = CTRLR0_TMOD_EPROMREAD;
  483. else
  484. priv->tmode = CTRLR0_TMOD_TO;
  485. cr0 = priv->update_cr0(priv);
  486. dev_dbg(bus, "cr0=%08x buf=%p len=%u [bytes]\n", cr0, op->data.buf.in,
  487. op->data.nbytes);
  488. dw_write(priv, DW_SPI_SSIENR, 0);
  489. dw_write(priv, DW_SPI_CTRLR0, cr0);
  490. if (read)
  491. dw_write(priv, DW_SPI_CTRLR1, op->data.nbytes - 1);
  492. dw_write(priv, DW_SPI_SSIENR, 1);
  493. /* From spi_mem_exec_op */
  494. pos = 0;
  495. op_buf[pos++] = op->cmd.opcode;
  496. if (op->addr.nbytes) {
  497. for (i = 0; i < op->addr.nbytes; i++)
  498. op_buf[pos + i] = op->addr.val >>
  499. (8 * (op->addr.nbytes - i - 1));
  500. pos += op->addr.nbytes;
  501. }
  502. if (op->dummy.nbytes)
  503. memset(op_buf + pos, 0xff, op->dummy.nbytes);
  504. external_cs_manage(slave->dev, false);
  505. priv->tx = &op_buf;
  506. priv->tx_end = priv->tx + op_len;
  507. priv->rx = NULL;
  508. priv->rx_end = NULL;
  509. while (priv->tx != priv->tx_end)
  510. dw_writer(priv);
  511. /*
  512. * XXX: The following are tight loops! Enabling debug messages may cause
  513. * them to fail because we are not reading/writing the fifo fast enough.
  514. */
  515. if (read) {
  516. priv->rx = op->data.buf.in;
  517. priv->rx_end = priv->rx + op->data.nbytes;
  518. dw_write(priv, DW_SPI_SER, 1 << spi_chip_select(slave->dev));
  519. while (priv->rx != priv->rx_end)
  520. dw_reader(priv);
  521. } else {
  522. u32 val;
  523. priv->tx = op->data.buf.out;
  524. priv->tx_end = priv->tx + op->data.nbytes;
  525. /* Fill up the write fifo before starting the transfer */
  526. dw_writer(priv);
  527. dw_write(priv, DW_SPI_SER, 1 << spi_chip_select(slave->dev));
  528. while (priv->tx != priv->tx_end)
  529. dw_writer(priv);
  530. if (readl_poll_timeout(priv->regs + DW_SPI_SR, val,
  531. (val & SR_TF_EMPT) && !(val & SR_BUSY),
  532. RX_TIMEOUT * 1000)) {
  533. ret = -ETIMEDOUT;
  534. }
  535. }
  536. dw_write(priv, DW_SPI_SER, 0);
  537. external_cs_manage(slave->dev, true);
  538. dev_dbg(bus, "%u bytes xfered\n", op->data.nbytes);
  539. return ret;
  540. }
  541. /* The size of ctrl1 limits data transfers to 64K */
  542. static int dw_spi_adjust_op_size(struct spi_slave *slave, struct spi_mem_op *op)
  543. {
  544. op->data.nbytes = min(op->data.nbytes, (unsigned int)SZ_64K);
  545. return 0;
  546. }
  547. static const struct spi_controller_mem_ops dw_spi_mem_ops = {
  548. .exec_op = dw_spi_exec_op,
  549. .adjust_op_size = dw_spi_adjust_op_size,
  550. };
  551. static int dw_spi_set_speed(struct udevice *bus, uint speed)
  552. {
  553. struct dw_spi_platdata *plat = dev_get_platdata(bus);
  554. struct dw_spi_priv *priv = dev_get_priv(bus);
  555. u16 clk_div;
  556. if (speed > plat->frequency)
  557. speed = plat->frequency;
  558. /* Disable controller before writing control registers */
  559. dw_write(priv, DW_SPI_SSIENR, 0);
  560. /* clk_div doesn't support odd number */
  561. clk_div = priv->bus_clk_rate / speed;
  562. clk_div = (clk_div + 1) & 0xfffe;
  563. dw_write(priv, DW_SPI_BAUDR, clk_div);
  564. /* Enable controller after writing control registers */
  565. dw_write(priv, DW_SPI_SSIENR, 1);
  566. priv->freq = speed;
  567. dev_dbg(bus, "speed=%d clk_div=%d\n", priv->freq, clk_div);
  568. return 0;
  569. }
  570. static int dw_spi_set_mode(struct udevice *bus, uint mode)
  571. {
  572. struct dw_spi_priv *priv = dev_get_priv(bus);
  573. /*
  574. * Can't set mode yet. Since this depends on if rx, tx, or
  575. * rx & tx is requested. So we have to defer this to the
  576. * real transfer function.
  577. */
  578. priv->mode = mode;
  579. dev_dbg(bus, "mode=%d\n", priv->mode);
  580. return 0;
  581. }
  582. static int dw_spi_remove(struct udevice *bus)
  583. {
  584. struct dw_spi_priv *priv = dev_get_priv(bus);
  585. int ret;
  586. ret = reset_release_bulk(&priv->resets);
  587. if (ret)
  588. return ret;
  589. #if CONFIG_IS_ENABLED(CLK)
  590. ret = clk_disable(&priv->clk);
  591. if (ret)
  592. return ret;
  593. ret = clk_free(&priv->clk);
  594. if (ret)
  595. return ret;
  596. #endif
  597. return 0;
  598. }
  599. static const struct dm_spi_ops dw_spi_ops = {
  600. .xfer = dw_spi_xfer,
  601. .mem_ops = &dw_spi_mem_ops,
  602. .set_speed = dw_spi_set_speed,
  603. .set_mode = dw_spi_set_mode,
  604. /*
  605. * cs_info is not needed, since we require all chip selects to be
  606. * in the device tree explicitly
  607. */
  608. };
  609. static const struct udevice_id dw_spi_ids[] = {
  610. /* Generic compatible strings */
  611. { .compatible = "snps,dw-apb-ssi", .data = (ulong)dw_spi_apb_init },
  612. { .compatible = "snps,dw-apb-ssi-3.20a", .data = (ulong)dw_spi_apb_init },
  613. { .compatible = "snps,dw-apb-ssi-3.22a", .data = (ulong)dw_spi_apb_init },
  614. /* First version with SSI_MAX_XFER_SIZE */
  615. { .compatible = "snps,dw-apb-ssi-3.23a", .data = (ulong)dw_spi_apb_init },
  616. /* First version with Dual/Quad SPI; unused by this driver */
  617. { .compatible = "snps,dw-apb-ssi-4.00a", .data = (ulong)dw_spi_apb_init },
  618. { .compatible = "snps,dw-apb-ssi-4.01", .data = (ulong)dw_spi_apb_init },
  619. { .compatible = "snps,dwc-ssi-1.01a", .data = (ulong)dw_spi_dwc_init },
  620. /* Compatible strings for specific SoCs */
  621. /*
  622. * Both the Cyclone V and Arria V share a device tree and have the same
  623. * version of this device. This compatible string is used for those
  624. * devices, and is not used for sofpgas in general.
  625. */
  626. { .compatible = "altr,socfpga-spi", .data = (ulong)dw_spi_apb_init },
  627. { .compatible = "altr,socfpga-arria10-spi", .data = (ulong)dw_spi_apb_init },
  628. { .compatible = "canaan,kendryte-k210-spi", .data = (ulong)dw_spi_apb_init },
  629. { .compatible = "canaan,kendryte-k210-ssi", .data = (ulong)dw_spi_dwc_init },
  630. { .compatible = "intel,stratix10-spi", .data = (ulong)dw_spi_apb_init },
  631. { .compatible = "intel,agilex-spi", .data = (ulong)dw_spi_apb_init },
  632. { .compatible = "mscc,ocelot-spi", .data = (ulong)dw_spi_apb_init },
  633. { .compatible = "mscc,jaguar2-spi", .data = (ulong)dw_spi_apb_init },
  634. { .compatible = "snps,axs10x-spi", .data = (ulong)dw_spi_apb_init },
  635. { .compatible = "snps,hsdk-spi", .data = (ulong)dw_spi_apb_init },
  636. { }
  637. };
  638. U_BOOT_DRIVER(dw_spi) = {
  639. .name = "dw_spi",
  640. .id = UCLASS_SPI,
  641. .of_match = dw_spi_ids,
  642. .ops = &dw_spi_ops,
  643. .ofdata_to_platdata = dw_spi_ofdata_to_platdata,
  644. .platdata_auto_alloc_size = sizeof(struct dw_spi_platdata),
  645. .priv_auto_alloc_size = sizeof(struct dw_spi_priv),
  646. .probe = dw_spi_probe,
  647. .remove = dw_spi_remove,
  648. };