davinci_spi.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
  4. *
  5. * Driver for SPI controller on DaVinci. Based on atmel_spi.c
  6. * by Atmel Corporation
  7. *
  8. * Copyright (C) 2007 Atmel Corporation
  9. */
  10. #include <common.h>
  11. #include <log.h>
  12. #include <spi.h>
  13. #include <malloc.h>
  14. #include <asm/io.h>
  15. #include <asm/arch/hardware.h>
  16. #include <dm.h>
  17. #include <dm/platform_data/spi_davinci.h>
  18. #include <linux/bitops.h>
  19. #include <linux/delay.h>
  20. /* SPIGCR0 */
  21. #define SPIGCR0_SPIENA_MASK 0x1
  22. #define SPIGCR0_SPIRST_MASK 0x0
  23. /* SPIGCR0 */
  24. #define SPIGCR1_CLKMOD_MASK BIT(1)
  25. #define SPIGCR1_MASTER_MASK BIT(0)
  26. #define SPIGCR1_SPIENA_MASK BIT(24)
  27. /* SPIPC0 */
  28. #define SPIPC0_DIFUN_MASK BIT(11) /* SIMO */
  29. #define SPIPC0_DOFUN_MASK BIT(10) /* SOMI */
  30. #define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */
  31. #define SPIPC0_EN0FUN_MASK BIT(0)
  32. /* SPIFMT0 */
  33. #define SPIFMT_SHIFTDIR_SHIFT 20
  34. #define SPIFMT_POLARITY_SHIFT 17
  35. #define SPIFMT_PHASE_SHIFT 16
  36. #define SPIFMT_PRESCALE_SHIFT 8
  37. /* SPIDAT1 */
  38. #define SPIDAT1_CSHOLD_SHIFT 28
  39. #define SPIDAT1_CSNR_SHIFT 16
  40. /* SPIDELAY */
  41. #define SPI_C2TDELAY_SHIFT 24
  42. #define SPI_T2CDELAY_SHIFT 16
  43. /* SPIBUF */
  44. #define SPIBUF_RXEMPTY_MASK BIT(31)
  45. #define SPIBUF_TXFULL_MASK BIT(29)
  46. /* SPIDEF */
  47. #define SPIDEF_CSDEF0_MASK BIT(0)
  48. DECLARE_GLOBAL_DATA_PTR;
  49. /* davinci spi register set */
  50. struct davinci_spi_regs {
  51. dv_reg gcr0; /* 0x00 */
  52. dv_reg gcr1; /* 0x04 */
  53. dv_reg int0; /* 0x08 */
  54. dv_reg lvl; /* 0x0c */
  55. dv_reg flg; /* 0x10 */
  56. dv_reg pc0; /* 0x14 */
  57. dv_reg pc1; /* 0x18 */
  58. dv_reg pc2; /* 0x1c */
  59. dv_reg pc3; /* 0x20 */
  60. dv_reg pc4; /* 0x24 */
  61. dv_reg pc5; /* 0x28 */
  62. dv_reg rsvd[3];
  63. dv_reg dat0; /* 0x38 */
  64. dv_reg dat1; /* 0x3c */
  65. dv_reg buf; /* 0x40 */
  66. dv_reg emu; /* 0x44 */
  67. dv_reg delay; /* 0x48 */
  68. dv_reg def; /* 0x4c */
  69. dv_reg fmt0; /* 0x50 */
  70. dv_reg fmt1; /* 0x54 */
  71. dv_reg fmt2; /* 0x58 */
  72. dv_reg fmt3; /* 0x5c */
  73. dv_reg intvec0; /* 0x60 */
  74. dv_reg intvec1; /* 0x64 */
  75. };
  76. /* davinci spi slave */
  77. struct davinci_spi_slave {
  78. struct davinci_spi_regs *regs;
  79. unsigned int freq; /* current SPI bus frequency */
  80. unsigned int mode; /* current SPI mode used */
  81. u8 num_cs; /* total no. of CS available */
  82. u8 cur_cs; /* CS of current slave */
  83. bool half_duplex; /* true, if master is half-duplex only */
  84. };
  85. /*
  86. * This functions needs to act like a macro to avoid pipeline reloads in the
  87. * loops below. Use always_inline. This gains us about 160KiB/s and the bloat
  88. * appears to be zero bytes (da830).
  89. */
  90. __attribute__((always_inline))
  91. static inline u32 davinci_spi_xfer_data(struct davinci_spi_slave *ds, u32 data)
  92. {
  93. u32 buf_reg_val;
  94. /* send out data */
  95. writel(data, &ds->regs->dat1);
  96. /* wait for the data to clock in/out */
  97. while ((buf_reg_val = readl(&ds->regs->buf)) & SPIBUF_RXEMPTY_MASK)
  98. ;
  99. return buf_reg_val;
  100. }
  101. static int davinci_spi_read(struct davinci_spi_slave *ds, unsigned int len,
  102. u8 *rxp, unsigned long flags)
  103. {
  104. unsigned int data1_reg_val;
  105. /* enable CS hold, CS[n] and clear the data bits */
  106. data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) |
  107. (ds->cur_cs << SPIDAT1_CSNR_SHIFT));
  108. /* wait till TXFULL is deasserted */
  109. while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK)
  110. ;
  111. /* preload the TX buffer to avoid clock starvation */
  112. writel(data1_reg_val, &ds->regs->dat1);
  113. /* keep reading 1 byte until only 1 byte left */
  114. while ((len--) > 1)
  115. *rxp++ = davinci_spi_xfer_data(ds, data1_reg_val);
  116. /* clear CS hold when we reach the end */
  117. if (flags & SPI_XFER_END)
  118. data1_reg_val &= ~(1 << SPIDAT1_CSHOLD_SHIFT);
  119. /* read the last byte */
  120. *rxp = davinci_spi_xfer_data(ds, data1_reg_val);
  121. return 0;
  122. }
  123. static int davinci_spi_write(struct davinci_spi_slave *ds, unsigned int len,
  124. const u8 *txp, unsigned long flags)
  125. {
  126. unsigned int data1_reg_val;
  127. /* enable CS hold and clear the data bits */
  128. data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) |
  129. (ds->cur_cs << SPIDAT1_CSNR_SHIFT));
  130. /* wait till TXFULL is deasserted */
  131. while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK)
  132. ;
  133. /* preload the TX buffer to avoid clock starvation */
  134. if (len > 2) {
  135. writel(data1_reg_val | *txp++, &ds->regs->dat1);
  136. len--;
  137. }
  138. /* keep writing 1 byte until only 1 byte left */
  139. while ((len--) > 1)
  140. davinci_spi_xfer_data(ds, data1_reg_val | *txp++);
  141. /* clear CS hold when we reach the end */
  142. if (flags & SPI_XFER_END)
  143. data1_reg_val &= ~(1 << SPIDAT1_CSHOLD_SHIFT);
  144. /* write the last byte */
  145. davinci_spi_xfer_data(ds, data1_reg_val | *txp);
  146. return 0;
  147. }
  148. static int davinci_spi_read_write(struct davinci_spi_slave *ds, unsigned
  149. int len, u8 *rxp, const u8 *txp,
  150. unsigned long flags)
  151. {
  152. unsigned int data1_reg_val;
  153. /* enable CS hold and clear the data bits */
  154. data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) |
  155. (ds->cur_cs << SPIDAT1_CSNR_SHIFT));
  156. /* wait till TXFULL is deasserted */
  157. while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK)
  158. ;
  159. /* keep reading and writing 1 byte until only 1 byte left */
  160. while ((len--) > 1)
  161. *rxp++ = davinci_spi_xfer_data(ds, data1_reg_val | *txp++);
  162. /* clear CS hold when we reach the end */
  163. if (flags & SPI_XFER_END)
  164. data1_reg_val &= ~(1 << SPIDAT1_CSHOLD_SHIFT);
  165. /* read and write the last byte */
  166. *rxp = davinci_spi_xfer_data(ds, data1_reg_val | *txp);
  167. return 0;
  168. }
  169. static int __davinci_spi_claim_bus(struct davinci_spi_slave *ds, int cs)
  170. {
  171. unsigned int mode = 0, scalar;
  172. /* Enable the SPI hardware */
  173. writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
  174. udelay(1000);
  175. writel(SPIGCR0_SPIENA_MASK, &ds->regs->gcr0);
  176. /* Set master mode, powered up and not activated */
  177. writel(SPIGCR1_MASTER_MASK | SPIGCR1_CLKMOD_MASK, &ds->regs->gcr1);
  178. /* CS, CLK, SIMO and SOMI are functional pins */
  179. writel(((1 << cs) | SPIPC0_CLKFUN_MASK |
  180. SPIPC0_DOFUN_MASK | SPIPC0_DIFUN_MASK), &ds->regs->pc0);
  181. /* setup format */
  182. scalar = ((CONFIG_SYS_SPI_CLK / ds->freq) - 1) & 0xFF;
  183. /*
  184. * Use following format:
  185. * character length = 8,
  186. * MSB shifted out first
  187. */
  188. if (ds->mode & SPI_CPOL)
  189. mode |= SPI_CPOL;
  190. if (!(ds->mode & SPI_CPHA))
  191. mode |= SPI_CPHA;
  192. writel(8 | (scalar << SPIFMT_PRESCALE_SHIFT) |
  193. (mode << SPIFMT_PHASE_SHIFT), &ds->regs->fmt0);
  194. /*
  195. * Including a minor delay. No science here. Should be good even with
  196. * no delay
  197. */
  198. writel((50 << SPI_C2TDELAY_SHIFT) |
  199. (50 << SPI_T2CDELAY_SHIFT), &ds->regs->delay);
  200. /* default chip select register */
  201. writel(SPIDEF_CSDEF0_MASK, &ds->regs->def);
  202. /* no interrupts */
  203. writel(0, &ds->regs->int0);
  204. writel(0, &ds->regs->lvl);
  205. /* enable SPI */
  206. writel((readl(&ds->regs->gcr1) | SPIGCR1_SPIENA_MASK), &ds->regs->gcr1);
  207. return 0;
  208. }
  209. static int __davinci_spi_release_bus(struct davinci_spi_slave *ds)
  210. {
  211. /* Disable the SPI hardware */
  212. writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
  213. return 0;
  214. }
  215. static int __davinci_spi_xfer(struct davinci_spi_slave *ds,
  216. unsigned int bitlen, const void *dout, void *din,
  217. unsigned long flags)
  218. {
  219. unsigned int len;
  220. if (bitlen == 0)
  221. /* Finish any previously submitted transfers */
  222. goto out;
  223. /*
  224. * It's not clear how non-8-bit-aligned transfers are supposed to be
  225. * represented as a stream of bytes...this is a limitation of
  226. * the current SPI interface - here we terminate on receiving such a
  227. * transfer request.
  228. */
  229. if (bitlen % 8) {
  230. /* Errors always terminate an ongoing transfer */
  231. flags |= SPI_XFER_END;
  232. goto out;
  233. }
  234. len = bitlen / 8;
  235. if (!dout)
  236. return davinci_spi_read(ds, len, din, flags);
  237. if (!din)
  238. return davinci_spi_write(ds, len, dout, flags);
  239. if (!ds->half_duplex)
  240. return davinci_spi_read_write(ds, len, din, dout, flags);
  241. printf("SPI full duplex not supported\n");
  242. flags |= SPI_XFER_END;
  243. out:
  244. if (flags & SPI_XFER_END) {
  245. u8 dummy = 0;
  246. davinci_spi_write(ds, 1, &dummy, flags);
  247. }
  248. return 0;
  249. }
  250. static int davinci_spi_set_speed(struct udevice *bus, uint max_hz)
  251. {
  252. struct davinci_spi_slave *ds = dev_get_priv(bus);
  253. debug("%s speed %u\n", __func__, max_hz);
  254. if (max_hz > CONFIG_SYS_SPI_CLK / 2)
  255. return -EINVAL;
  256. ds->freq = max_hz;
  257. return 0;
  258. }
  259. static int davinci_spi_set_mode(struct udevice *bus, uint mode)
  260. {
  261. struct davinci_spi_slave *ds = dev_get_priv(bus);
  262. debug("%s mode %u\n", __func__, mode);
  263. ds->mode = mode;
  264. return 0;
  265. }
  266. static int davinci_spi_claim_bus(struct udevice *dev)
  267. {
  268. struct dm_spi_slave_platdata *slave_plat =
  269. dev_get_parent_platdata(dev);
  270. struct udevice *bus = dev->parent;
  271. struct davinci_spi_slave *ds = dev_get_priv(bus);
  272. if (slave_plat->cs >= ds->num_cs) {
  273. printf("Invalid SPI chipselect\n");
  274. return -EINVAL;
  275. }
  276. ds->half_duplex = slave_plat->mode & SPI_PREAMBLE;
  277. return __davinci_spi_claim_bus(ds, slave_plat->cs);
  278. }
  279. static int davinci_spi_release_bus(struct udevice *dev)
  280. {
  281. struct davinci_spi_slave *ds = dev_get_priv(dev->parent);
  282. return __davinci_spi_release_bus(ds);
  283. }
  284. static int davinci_spi_xfer(struct udevice *dev, unsigned int bitlen,
  285. const void *dout, void *din,
  286. unsigned long flags)
  287. {
  288. struct dm_spi_slave_platdata *slave =
  289. dev_get_parent_platdata(dev);
  290. struct udevice *bus = dev->parent;
  291. struct davinci_spi_slave *ds = dev_get_priv(bus);
  292. if (slave->cs >= ds->num_cs) {
  293. printf("Invalid SPI chipselect\n");
  294. return -EINVAL;
  295. }
  296. ds->cur_cs = slave->cs;
  297. return __davinci_spi_xfer(ds, bitlen, dout, din, flags);
  298. }
  299. static const struct dm_spi_ops davinci_spi_ops = {
  300. .claim_bus = davinci_spi_claim_bus,
  301. .release_bus = davinci_spi_release_bus,
  302. .xfer = davinci_spi_xfer,
  303. .set_speed = davinci_spi_set_speed,
  304. .set_mode = davinci_spi_set_mode,
  305. };
  306. static int davinci_spi_probe(struct udevice *bus)
  307. {
  308. struct davinci_spi_slave *ds = dev_get_priv(bus);
  309. struct davinci_spi_platdata *plat = bus->platdata;
  310. ds->regs = plat->regs;
  311. ds->num_cs = plat->num_cs;
  312. return 0;
  313. }
  314. #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
  315. static int davinci_ofdata_to_platadata(struct udevice *bus)
  316. {
  317. struct davinci_spi_platdata *plat = bus->platdata;
  318. fdt_addr_t addr;
  319. addr = dev_read_addr(bus);
  320. if (addr == FDT_ADDR_T_NONE)
  321. return -EINVAL;
  322. plat->regs = (struct davinci_spi_regs *)addr;
  323. plat->num_cs = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus), "num-cs", 4);
  324. return 0;
  325. }
  326. static const struct udevice_id davinci_spi_ids[] = {
  327. { .compatible = "ti,keystone-spi" },
  328. { .compatible = "ti,dm6441-spi" },
  329. { .compatible = "ti,da830-spi" },
  330. { }
  331. };
  332. #endif
  333. U_BOOT_DRIVER(davinci_spi) = {
  334. .name = "davinci_spi",
  335. .id = UCLASS_SPI,
  336. #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
  337. .of_match = davinci_spi_ids,
  338. .ofdata_to_platdata = davinci_ofdata_to_platadata,
  339. .platdata_auto_alloc_size = sizeof(struct davinci_spi_platdata),
  340. #endif
  341. .probe = davinci_spi_probe,
  342. .ops = &davinci_spi_ops,
  343. .priv_auto_alloc_size = sizeof(struct davinci_spi_slave),
  344. };