cf_spi.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. *
  4. * (C) Copyright 2000-2003
  5. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  6. *
  7. * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
  8. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  9. *
  10. * Support for DM and DT, non-DM code removed.
  11. * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
  12. *
  13. * TODO: fsl_dspi.c should work as a driver for the DSPI module.
  14. */
  15. #include <common.h>
  16. #include <dm.h>
  17. #include <log.h>
  18. #include <dm/platform_data/spi_coldfire.h>
  19. #include <spi.h>
  20. #include <malloc.h>
  21. #include <asm/coldfire/dspi.h>
  22. #include <asm/io.h>
  23. struct coldfire_spi_priv {
  24. struct dspi *regs;
  25. uint baudrate;
  26. int mode;
  27. int charbit;
  28. };
  29. DECLARE_GLOBAL_DATA_PTR;
  30. #ifndef CONFIG_SPI_IDLE_VAL
  31. #if defined(CONFIG_SPI_MMC)
  32. #define CONFIG_SPI_IDLE_VAL 0xFFFF
  33. #else
  34. #define CONFIG_SPI_IDLE_VAL 0x0
  35. #endif
  36. #endif
  37. /*
  38. * DSPI specific mode
  39. *
  40. * bit 31 - 28: Transfer size 3 to 16 bits
  41. * 27 - 26: PCS to SCK delay prescaler
  42. * 25 - 24: After SCK delay prescaler
  43. * 23 - 22: Delay after transfer prescaler
  44. * 21 : Allow overwrite for bit 31-22 and bit 20-8
  45. * 20 : Double baud rate
  46. * 19 - 16: PCS to SCK delay scaler
  47. * 15 - 12: After SCK delay scaler
  48. * 11 - 8: Delay after transfer scaler
  49. * 7 - 0: SPI_CPHA, SPI_CPOL, SPI_LSB_FIRST
  50. */
  51. #define SPI_MODE_MOD 0x00200000
  52. #define SPI_MODE_DBLRATE 0x00100000
  53. #define SPI_MODE_XFER_SZ_MASK 0xf0000000
  54. #define SPI_MODE_DLY_PRE_MASK 0x0fc00000
  55. #define SPI_MODE_DLY_SCA_MASK 0x000fff00
  56. #define MCF_FRM_SZ_16BIT DSPI_CTAR_TRSZ(0xf)
  57. #define MCF_DSPI_SPEED_BESTMATCH 0x7FFFFFFF
  58. #define MCF_DSPI_MAX_CTAR_REGS 8
  59. /* Default values */
  60. #define MCF_DSPI_DEFAULT_SCK_FREQ 10000000
  61. #define MCF_DSPI_DEFAULT_MAX_CS 4
  62. #define MCF_DSPI_DEFAULT_MODE 0
  63. #define MCF_DSPI_DEFAULT_CTAR (DSPI_CTAR_TRSZ(7) | \
  64. DSPI_CTAR_PCSSCK_1CLK | \
  65. DSPI_CTAR_PASC(0) | \
  66. DSPI_CTAR_PDT(0) | \
  67. DSPI_CTAR_CSSCK(0) | \
  68. DSPI_CTAR_ASC(0) | \
  69. DSPI_CTAR_DT(1) | \
  70. DSPI_CTAR_BR(6))
  71. #define MCF_CTAR_MODE_MASK (MCF_FRM_SZ_16BIT | \
  72. DSPI_CTAR_PCSSCK(3) | \
  73. DSPI_CTAR_PASC_7CLK | \
  74. DSPI_CTAR_PDT(3) | \
  75. DSPI_CTAR_CSSCK(0x0f) | \
  76. DSPI_CTAR_ASC(0x0f) | \
  77. DSPI_CTAR_DT(0x0f))
  78. #define setup_ctrl(ctrl, cs) ((ctrl & 0xFF000000) | ((1 << cs) << 16))
  79. static inline void cfspi_tx(struct coldfire_spi_priv *cfspi,
  80. u32 ctrl, u16 data)
  81. {
  82. /*
  83. * Need to check fifo level here
  84. */
  85. while ((readl(&cfspi->regs->sr) & 0x0000F000) >= 0x4000)
  86. ;
  87. writel(ctrl | data, &cfspi->regs->tfr);
  88. }
  89. static inline u16 cfspi_rx(struct coldfire_spi_priv *cfspi)
  90. {
  91. while ((readl(&cfspi->regs->sr) & 0x000000F0) == 0)
  92. ;
  93. return readw(&cfspi->regs->rfr);
  94. }
  95. static int coldfire_spi_claim_bus(struct udevice *dev)
  96. {
  97. struct udevice *bus = dev->parent;
  98. struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
  99. struct dspi *dspi = cfspi->regs;
  100. struct dm_spi_slave_platdata *slave_plat =
  101. dev_get_parent_platdata(dev);
  102. if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
  103. return -1;
  104. /* Clear FIFO and resume transfer */
  105. clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
  106. dspi_chip_select(slave_plat->cs);
  107. return 0;
  108. }
  109. static int coldfire_spi_release_bus(struct udevice *dev)
  110. {
  111. struct udevice *bus = dev->parent;
  112. struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
  113. struct dspi *dspi = cfspi->regs;
  114. struct dm_spi_slave_platdata *slave_plat =
  115. dev_get_parent_platdata(dev);
  116. /* Clear FIFO */
  117. clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
  118. dspi_chip_unselect(slave_plat->cs);
  119. return 0;
  120. }
  121. static int coldfire_spi_xfer(struct udevice *dev, unsigned int bitlen,
  122. const void *dout, void *din,
  123. unsigned long flags)
  124. {
  125. struct udevice *bus = dev_get_parent(dev);
  126. struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
  127. struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
  128. u16 *spi_rd16 = NULL, *spi_wr16 = NULL;
  129. u8 *spi_rd = NULL, *spi_wr = NULL;
  130. static u32 ctrl;
  131. uint len = bitlen >> 3;
  132. if (cfspi->charbit == 16) {
  133. bitlen >>= 1;
  134. spi_wr16 = (u16 *)dout;
  135. spi_rd16 = (u16 *)din;
  136. } else {
  137. spi_wr = (u8 *)dout;
  138. spi_rd = (u8 *)din;
  139. }
  140. if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN)
  141. ctrl |= DSPI_TFR_CONT;
  142. ctrl = setup_ctrl(ctrl, slave_plat->cs);
  143. if (len > 1) {
  144. int tmp_len = len - 1;
  145. while (tmp_len--) {
  146. if (dout) {
  147. if (cfspi->charbit == 16)
  148. cfspi_tx(cfspi, ctrl, *spi_wr16++);
  149. else
  150. cfspi_tx(cfspi, ctrl, *spi_wr++);
  151. cfspi_rx(cfspi);
  152. }
  153. if (din) {
  154. cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
  155. if (cfspi->charbit == 16)
  156. *spi_rd16++ = cfspi_rx(cfspi);
  157. else
  158. *spi_rd++ = cfspi_rx(cfspi);
  159. }
  160. }
  161. len = 1; /* remaining byte */
  162. }
  163. if (flags & SPI_XFER_END)
  164. ctrl &= ~DSPI_TFR_CONT;
  165. if (len) {
  166. if (dout) {
  167. if (cfspi->charbit == 16)
  168. cfspi_tx(cfspi, ctrl, *spi_wr16);
  169. else
  170. cfspi_tx(cfspi, ctrl, *spi_wr);
  171. cfspi_rx(cfspi);
  172. }
  173. if (din) {
  174. cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
  175. if (cfspi->charbit == 16)
  176. *spi_rd16 = cfspi_rx(cfspi);
  177. else
  178. *spi_rd = cfspi_rx(cfspi);
  179. }
  180. } else {
  181. /* dummy read */
  182. cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
  183. cfspi_rx(cfspi);
  184. }
  185. return 0;
  186. }
  187. static int coldfire_spi_set_speed(struct udevice *bus, uint max_hz)
  188. {
  189. struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
  190. struct dspi *dspi = cfspi->regs;
  191. int prescaler[] = { 2, 3, 5, 7 };
  192. int scaler[] = {
  193. 2, 4, 6, 8,
  194. 16, 32, 64, 128,
  195. 256, 512, 1024, 2048,
  196. 4096, 8192, 16384, 32768
  197. };
  198. int i, j, pbrcnt, brcnt, diff, tmp, dbr = 0;
  199. int best_i, best_j, bestmatch = MCF_DSPI_SPEED_BESTMATCH, baud_speed;
  200. u32 bus_setup;
  201. cfspi->baudrate = max_hz;
  202. /* Read current setup */
  203. bus_setup = readl(&dspi->ctar[bus->seq]);
  204. tmp = (prescaler[3] * scaler[15]);
  205. /* Maximum and minimum baudrate it can handle */
  206. if ((cfspi->baudrate > (gd->bus_clk >> 1)) ||
  207. (cfspi->baudrate < (gd->bus_clk / tmp))) {
  208. printf("Exceed baudrate limitation: Max %d - Min %d\n",
  209. (int)(gd->bus_clk >> 1), (int)(gd->bus_clk / tmp));
  210. return -1;
  211. }
  212. /* Activate Double Baud when it exceed 1/4 the bus clk */
  213. if ((bus_setup & DSPI_CTAR_DBR) ||
  214. (cfspi->baudrate > (gd->bus_clk / (prescaler[0] * scaler[0])))) {
  215. bus_setup |= DSPI_CTAR_DBR;
  216. dbr = 1;
  217. }
  218. /* Overwrite default value set in platform configuration file */
  219. if (cfspi->mode & SPI_MODE_MOD) {
  220. /*
  221. * Check to see if it is enabled by default in platform
  222. * config, or manual setting passed by mode parameter
  223. */
  224. if (cfspi->mode & SPI_MODE_DBLRATE) {
  225. bus_setup |= DSPI_CTAR_DBR;
  226. dbr = 1;
  227. }
  228. }
  229. pbrcnt = sizeof(prescaler) / sizeof(int);
  230. brcnt = sizeof(scaler) / sizeof(int);
  231. /* baudrate calculation - to closer value, may not be exact match */
  232. for (best_i = 0, best_j = 0, i = 0; i < pbrcnt; i++) {
  233. baud_speed = gd->bus_clk / prescaler[i];
  234. for (j = 0; j < brcnt; j++) {
  235. tmp = (baud_speed / scaler[j]) * (1 + dbr);
  236. if (tmp > cfspi->baudrate)
  237. diff = tmp - cfspi->baudrate;
  238. else
  239. diff = cfspi->baudrate - tmp;
  240. if (diff < bestmatch) {
  241. bestmatch = diff;
  242. best_i = i;
  243. best_j = j;
  244. }
  245. }
  246. }
  247. bus_setup &= ~(DSPI_CTAR_PBR(0x03) | DSPI_CTAR_BR(0x0f));
  248. bus_setup |= (DSPI_CTAR_PBR(best_i) | DSPI_CTAR_BR(best_j));
  249. writel(bus_setup, &dspi->ctar[bus->seq]);
  250. return 0;
  251. }
  252. static int coldfire_spi_set_mode(struct udevice *bus, uint mode)
  253. {
  254. struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
  255. struct dspi *dspi = cfspi->regs;
  256. u32 bus_setup = 0;
  257. cfspi->mode = mode;
  258. if (cfspi->mode & SPI_CPOL)
  259. bus_setup |= DSPI_CTAR_CPOL;
  260. if (cfspi->mode & SPI_CPHA)
  261. bus_setup |= DSPI_CTAR_CPHA;
  262. if (cfspi->mode & SPI_LSB_FIRST)
  263. bus_setup |= DSPI_CTAR_LSBFE;
  264. /* Overwrite default value set in platform configuration file */
  265. if (cfspi->mode & SPI_MODE_MOD) {
  266. if ((cfspi->mode & SPI_MODE_XFER_SZ_MASK) == 0)
  267. bus_setup |=
  268. readl(&dspi->ctar[bus->seq]) & MCF_FRM_SZ_16BIT;
  269. else
  270. bus_setup |=
  271. ((cfspi->mode & SPI_MODE_XFER_SZ_MASK) >> 1);
  272. /* PSCSCK, PASC, PDT */
  273. bus_setup |= (cfspi->mode & SPI_MODE_DLY_PRE_MASK) >> 4;
  274. /* CSSCK, ASC, DT */
  275. bus_setup |= (cfspi->mode & SPI_MODE_DLY_SCA_MASK) >> 4;
  276. } else {
  277. bus_setup |=
  278. (readl(&dspi->ctar[bus->seq]) & MCF_CTAR_MODE_MASK);
  279. }
  280. cfspi->charbit =
  281. ((readl(&dspi->ctar[bus->seq]) & MCF_FRM_SZ_16BIT) ==
  282. MCF_FRM_SZ_16BIT) ? 16 : 8;
  283. setbits_be32(&dspi->ctar[bus->seq], bus_setup);
  284. return 0;
  285. }
  286. static int coldfire_spi_probe(struct udevice *bus)
  287. {
  288. struct coldfire_spi_platdata *plat = dev_get_platdata(bus);
  289. struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
  290. struct dspi *dspi = cfspi->regs;
  291. int i;
  292. cfspi->regs = (struct dspi *)plat->regs_addr;
  293. cfspi->baudrate = plat->speed_hz;
  294. cfspi->mode = plat->mode;
  295. for (i = 0; i < MCF_DSPI_MAX_CTAR_REGS; i++) {
  296. unsigned int ctar = 0;
  297. if (plat->ctar[i][0] == 0)
  298. break;
  299. ctar = DSPI_CTAR_TRSZ(plat->ctar[i][0]) |
  300. DSPI_CTAR_PCSSCK(plat->ctar[i][1]) |
  301. DSPI_CTAR_PASC(plat->ctar[i][2]) |
  302. DSPI_CTAR_PDT(plat->ctar[i][3]) |
  303. DSPI_CTAR_CSSCK(plat->ctar[i][4]) |
  304. DSPI_CTAR_ASC(plat->ctar[i][5]) |
  305. DSPI_CTAR_DT(plat->ctar[i][6]) |
  306. DSPI_CTAR_BR(plat->ctar[i][7]);
  307. writel(ctar, &cfspi->regs->ctar[i]);
  308. }
  309. /* Default CTARs */
  310. for (i = 0; i < MCF_DSPI_MAX_CTAR_REGS; i++)
  311. writel(MCF_DSPI_DEFAULT_CTAR, &dspi->ctar[i]);
  312. dspi->mcr = DSPI_MCR_MSTR | DSPI_MCR_CSIS7 | DSPI_MCR_CSIS6 |
  313. DSPI_MCR_CSIS5 | DSPI_MCR_CSIS4 | DSPI_MCR_CSIS3 |
  314. DSPI_MCR_CSIS2 | DSPI_MCR_CSIS1 | DSPI_MCR_CSIS0 |
  315. DSPI_MCR_CRXF | DSPI_MCR_CTXF;
  316. return 0;
  317. }
  318. #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
  319. static int coldfire_dspi_ofdata_to_platdata(struct udevice *bus)
  320. {
  321. fdt_addr_t addr;
  322. struct coldfire_spi_platdata *plat = bus->platdata;
  323. const void *blob = gd->fdt_blob;
  324. int node = dev_of_offset(bus);
  325. int *ctar, len;
  326. addr = dev_read_addr(bus);
  327. if (addr == FDT_ADDR_T_NONE)
  328. return -ENOMEM;
  329. plat->regs_addr = addr;
  330. plat->num_cs = fdtdec_get_int(blob, node, "num-cs",
  331. MCF_DSPI_DEFAULT_MAX_CS);
  332. plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
  333. MCF_DSPI_DEFAULT_SCK_FREQ);
  334. plat->mode = fdtdec_get_int(blob, node, "spi-mode",
  335. MCF_DSPI_DEFAULT_MODE);
  336. memset(plat->ctar, 0, sizeof(plat->ctar));
  337. ctar = (int *)fdt_getprop(blob, node, "ctar-params", &len);
  338. if (ctar && len) {
  339. int i, q, ctar_regs;
  340. ctar_regs = len / sizeof(unsigned int) / MAX_CTAR_FIELDS;
  341. if (ctar_regs > MAX_CTAR_REGS)
  342. ctar_regs = MAX_CTAR_REGS;
  343. for (i = 0; i < ctar_regs; i++) {
  344. for (q = 0; q < MAX_CTAR_FIELDS; q++)
  345. plat->ctar[i][q] = *ctar++;
  346. }
  347. }
  348. debug("DSPI: regs=%pa, max-frequency=%d, num-cs=%d, mode=%d\n",
  349. (void *)plat->regs_addr,
  350. plat->speed_hz, plat->num_cs, plat->mode);
  351. return 0;
  352. }
  353. static const struct udevice_id coldfire_spi_ids[] = {
  354. { .compatible = "fsl,mcf-dspi" },
  355. { }
  356. };
  357. #endif
  358. static const struct dm_spi_ops coldfire_spi_ops = {
  359. .claim_bus = coldfire_spi_claim_bus,
  360. .release_bus = coldfire_spi_release_bus,
  361. .xfer = coldfire_spi_xfer,
  362. .set_speed = coldfire_spi_set_speed,
  363. .set_mode = coldfire_spi_set_mode,
  364. };
  365. U_BOOT_DRIVER(coldfire_spi) = {
  366. .name = "spi_coldfire",
  367. .id = UCLASS_SPI,
  368. #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
  369. .of_match = coldfire_spi_ids,
  370. .ofdata_to_platdata = coldfire_dspi_ofdata_to_platdata,
  371. .platdata_auto_alloc_size = sizeof(struct coldfire_spi_platdata),
  372. #endif
  373. .probe = coldfire_spi_probe,
  374. .ops = &coldfire_spi_ops,
  375. .priv_auto_alloc_size = sizeof(struct coldfire_spi_priv),
  376. };