cadence_qspi_apb.c 23 KB

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  1. /*
  2. * Copyright (C) 2012 Altera Corporation <www.altera.com>
  3. * All rights reserved.
  4. *
  5. * Redistribution and use in source and binary forms, with or without
  6. * modification, are permitted provided that the following conditions are met:
  7. * - Redistributions of source code must retain the above copyright
  8. * notice, this list of conditions and the following disclaimer.
  9. * - Redistributions in binary form must reproduce the above copyright
  10. * notice, this list of conditions and the following disclaimer in the
  11. * documentation and/or other materials provided with the distribution.
  12. * - Neither the name of the Altera Corporation nor the
  13. * names of its contributors may be used to endorse or promote products
  14. * derived from this software without specific prior written permission.
  15. *
  16. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19. * ARE DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
  20. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  25. * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26. */
  27. #include <common.h>
  28. #include <log.h>
  29. #include <asm/io.h>
  30. #include <dma.h>
  31. #include <linux/bitops.h>
  32. #include <linux/delay.h>
  33. #include <linux/errno.h>
  34. #include <wait_bit.h>
  35. #include <spi.h>
  36. #include <spi-mem.h>
  37. #include <malloc.h>
  38. #include "cadence_qspi.h"
  39. #define CQSPI_REG_POLL_US 1 /* 1us */
  40. #define CQSPI_REG_RETRY 10000
  41. #define CQSPI_POLL_IDLE_RETRY 3
  42. /* Transfer mode */
  43. #define CQSPI_INST_TYPE_SINGLE 0
  44. #define CQSPI_INST_TYPE_DUAL 1
  45. #define CQSPI_INST_TYPE_QUAD 2
  46. #define CQSPI_INST_TYPE_OCTAL 3
  47. #define CQSPI_STIG_DATA_LEN_MAX 8
  48. #define CQSPI_DUMMY_CLKS_PER_BYTE 8
  49. #define CQSPI_DUMMY_BYTES_MAX 4
  50. /****************************************************************************
  51. * Controller's configuration and status register (offset from QSPI_BASE)
  52. ****************************************************************************/
  53. #define CQSPI_REG_CONFIG 0x00
  54. #define CQSPI_REG_CONFIG_ENABLE BIT(0)
  55. #define CQSPI_REG_CONFIG_CLK_POL BIT(1)
  56. #define CQSPI_REG_CONFIG_CLK_PHA BIT(2)
  57. #define CQSPI_REG_CONFIG_DIRECT BIT(7)
  58. #define CQSPI_REG_CONFIG_DECODE BIT(9)
  59. #define CQSPI_REG_CONFIG_XIP_IMM BIT(18)
  60. #define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10
  61. #define CQSPI_REG_CONFIG_BAUD_LSB 19
  62. #define CQSPI_REG_CONFIG_IDLE_LSB 31
  63. #define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF
  64. #define CQSPI_REG_CONFIG_BAUD_MASK 0xF
  65. #define CQSPI_REG_RD_INSTR 0x04
  66. #define CQSPI_REG_RD_INSTR_OPCODE_LSB 0
  67. #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8
  68. #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12
  69. #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16
  70. #define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20
  71. #define CQSPI_REG_RD_INSTR_DUMMY_LSB 24
  72. #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3
  73. #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3
  74. #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3
  75. #define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F
  76. #define CQSPI_REG_WR_INSTR 0x08
  77. #define CQSPI_REG_WR_INSTR_OPCODE_LSB 0
  78. #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB 16
  79. #define CQSPI_REG_DELAY 0x0C
  80. #define CQSPI_REG_DELAY_TSLCH_LSB 0
  81. #define CQSPI_REG_DELAY_TCHSH_LSB 8
  82. #define CQSPI_REG_DELAY_TSD2D_LSB 16
  83. #define CQSPI_REG_DELAY_TSHSL_LSB 24
  84. #define CQSPI_REG_DELAY_TSLCH_MASK 0xFF
  85. #define CQSPI_REG_DELAY_TCHSH_MASK 0xFF
  86. #define CQSPI_REG_DELAY_TSD2D_MASK 0xFF
  87. #define CQSPI_REG_DELAY_TSHSL_MASK 0xFF
  88. #define CQSPI_REG_RD_DATA_CAPTURE 0x10
  89. #define CQSPI_REG_RD_DATA_CAPTURE_BYPASS BIT(0)
  90. #define CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB 1
  91. #define CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK 0xF
  92. #define CQSPI_REG_SIZE 0x14
  93. #define CQSPI_REG_SIZE_ADDRESS_LSB 0
  94. #define CQSPI_REG_SIZE_PAGE_LSB 4
  95. #define CQSPI_REG_SIZE_BLOCK_LSB 16
  96. #define CQSPI_REG_SIZE_ADDRESS_MASK 0xF
  97. #define CQSPI_REG_SIZE_PAGE_MASK 0xFFF
  98. #define CQSPI_REG_SIZE_BLOCK_MASK 0x3F
  99. #define CQSPI_REG_SRAMPARTITION 0x18
  100. #define CQSPI_REG_INDIRECTTRIGGER 0x1C
  101. #define CQSPI_REG_REMAP 0x24
  102. #define CQSPI_REG_MODE_BIT 0x28
  103. #define CQSPI_REG_SDRAMLEVEL 0x2C
  104. #define CQSPI_REG_SDRAMLEVEL_RD_LSB 0
  105. #define CQSPI_REG_SDRAMLEVEL_WR_LSB 16
  106. #define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF
  107. #define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF
  108. #define CQSPI_REG_IRQSTATUS 0x40
  109. #define CQSPI_REG_IRQMASK 0x44
  110. #define CQSPI_REG_INDIRECTRD 0x60
  111. #define CQSPI_REG_INDIRECTRD_START BIT(0)
  112. #define CQSPI_REG_INDIRECTRD_CANCEL BIT(1)
  113. #define CQSPI_REG_INDIRECTRD_INPROGRESS BIT(2)
  114. #define CQSPI_REG_INDIRECTRD_DONE BIT(5)
  115. #define CQSPI_REG_INDIRECTRDWATERMARK 0x64
  116. #define CQSPI_REG_INDIRECTRDSTARTADDR 0x68
  117. #define CQSPI_REG_INDIRECTRDBYTES 0x6C
  118. #define CQSPI_REG_CMDCTRL 0x90
  119. #define CQSPI_REG_CMDCTRL_EXECUTE BIT(0)
  120. #define CQSPI_REG_CMDCTRL_INPROGRESS BIT(1)
  121. #define CQSPI_REG_CMDCTRL_DUMMY_LSB 7
  122. #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12
  123. #define CQSPI_REG_CMDCTRL_WR_EN_LSB 15
  124. #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16
  125. #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19
  126. #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20
  127. #define CQSPI_REG_CMDCTRL_RD_EN_LSB 23
  128. #define CQSPI_REG_CMDCTRL_OPCODE_LSB 24
  129. #define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F
  130. #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7
  131. #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3
  132. #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7
  133. #define CQSPI_REG_CMDCTRL_OPCODE_MASK 0xFF
  134. #define CQSPI_REG_INDIRECTWR 0x70
  135. #define CQSPI_REG_INDIRECTWR_START BIT(0)
  136. #define CQSPI_REG_INDIRECTWR_CANCEL BIT(1)
  137. #define CQSPI_REG_INDIRECTWR_INPROGRESS BIT(2)
  138. #define CQSPI_REG_INDIRECTWR_DONE BIT(5)
  139. #define CQSPI_REG_INDIRECTWRWATERMARK 0x74
  140. #define CQSPI_REG_INDIRECTWRSTARTADDR 0x78
  141. #define CQSPI_REG_INDIRECTWRBYTES 0x7C
  142. #define CQSPI_REG_CMDADDRESS 0x94
  143. #define CQSPI_REG_CMDREADDATALOWER 0xA0
  144. #define CQSPI_REG_CMDREADDATAUPPER 0xA4
  145. #define CQSPI_REG_CMDWRITEDATALOWER 0xA8
  146. #define CQSPI_REG_CMDWRITEDATAUPPER 0xAC
  147. #define CQSPI_REG_IS_IDLE(base) \
  148. ((readl(base + CQSPI_REG_CONFIG) >> \
  149. CQSPI_REG_CONFIG_IDLE_LSB) & 0x1)
  150. #define CQSPI_GET_RD_SRAM_LEVEL(reg_base) \
  151. (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \
  152. CQSPI_REG_SDRAMLEVEL_RD_LSB) & CQSPI_REG_SDRAMLEVEL_RD_MASK)
  153. #define CQSPI_GET_WR_SRAM_LEVEL(reg_base) \
  154. (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \
  155. CQSPI_REG_SDRAMLEVEL_WR_LSB) & CQSPI_REG_SDRAMLEVEL_WR_MASK)
  156. void cadence_qspi_apb_controller_enable(void *reg_base)
  157. {
  158. unsigned int reg;
  159. reg = readl(reg_base + CQSPI_REG_CONFIG);
  160. reg |= CQSPI_REG_CONFIG_ENABLE;
  161. writel(reg, reg_base + CQSPI_REG_CONFIG);
  162. }
  163. void cadence_qspi_apb_controller_disable(void *reg_base)
  164. {
  165. unsigned int reg;
  166. reg = readl(reg_base + CQSPI_REG_CONFIG);
  167. reg &= ~CQSPI_REG_CONFIG_ENABLE;
  168. writel(reg, reg_base + CQSPI_REG_CONFIG);
  169. }
  170. void cadence_qspi_apb_dac_mode_enable(void *reg_base)
  171. {
  172. unsigned int reg;
  173. reg = readl(reg_base + CQSPI_REG_CONFIG);
  174. reg |= CQSPI_REG_CONFIG_DIRECT;
  175. writel(reg, reg_base + CQSPI_REG_CONFIG);
  176. }
  177. /* Return 1 if idle, otherwise return 0 (busy). */
  178. static unsigned int cadence_qspi_wait_idle(void *reg_base)
  179. {
  180. unsigned int start, count = 0;
  181. /* timeout in unit of ms */
  182. unsigned int timeout = 5000;
  183. start = get_timer(0);
  184. for ( ; get_timer(start) < timeout ; ) {
  185. if (CQSPI_REG_IS_IDLE(reg_base))
  186. count++;
  187. else
  188. count = 0;
  189. /*
  190. * Ensure the QSPI controller is in true idle state after
  191. * reading back the same idle status consecutively
  192. */
  193. if (count >= CQSPI_POLL_IDLE_RETRY)
  194. return 1;
  195. }
  196. /* Timeout, still in busy mode. */
  197. printf("QSPI: QSPI is still busy after poll for %d times.\n",
  198. CQSPI_REG_RETRY);
  199. return 0;
  200. }
  201. void cadence_qspi_apb_readdata_capture(void *reg_base,
  202. unsigned int bypass, unsigned int delay)
  203. {
  204. unsigned int reg;
  205. cadence_qspi_apb_controller_disable(reg_base);
  206. reg = readl(reg_base + CQSPI_REG_RD_DATA_CAPTURE);
  207. if (bypass)
  208. reg |= CQSPI_REG_RD_DATA_CAPTURE_BYPASS;
  209. else
  210. reg &= ~CQSPI_REG_RD_DATA_CAPTURE_BYPASS;
  211. reg &= ~(CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK
  212. << CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB);
  213. reg |= (delay & CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK)
  214. << CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB;
  215. writel(reg, reg_base + CQSPI_REG_RD_DATA_CAPTURE);
  216. cadence_qspi_apb_controller_enable(reg_base);
  217. }
  218. void cadence_qspi_apb_config_baudrate_div(void *reg_base,
  219. unsigned int ref_clk_hz, unsigned int sclk_hz)
  220. {
  221. unsigned int reg;
  222. unsigned int div;
  223. cadence_qspi_apb_controller_disable(reg_base);
  224. reg = readl(reg_base + CQSPI_REG_CONFIG);
  225. reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
  226. /*
  227. * The baud_div field in the config reg is 4 bits, and the ref clock is
  228. * divided by 2 * (baud_div + 1). Round up the divider to ensure the
  229. * SPI clock rate is less than or equal to the requested clock rate.
  230. */
  231. div = DIV_ROUND_UP(ref_clk_hz, sclk_hz * 2) - 1;
  232. /* ensure the baud rate doesn't exceed the max value */
  233. if (div > CQSPI_REG_CONFIG_BAUD_MASK)
  234. div = CQSPI_REG_CONFIG_BAUD_MASK;
  235. debug("%s: ref_clk %dHz sclk %dHz Div 0x%x, actual %dHz\n", __func__,
  236. ref_clk_hz, sclk_hz, div, ref_clk_hz / (2 * (div + 1)));
  237. reg |= (div << CQSPI_REG_CONFIG_BAUD_LSB);
  238. writel(reg, reg_base + CQSPI_REG_CONFIG);
  239. cadence_qspi_apb_controller_enable(reg_base);
  240. }
  241. void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode)
  242. {
  243. unsigned int reg;
  244. cadence_qspi_apb_controller_disable(reg_base);
  245. reg = readl(reg_base + CQSPI_REG_CONFIG);
  246. reg &= ~(CQSPI_REG_CONFIG_CLK_POL | CQSPI_REG_CONFIG_CLK_PHA);
  247. if (mode & SPI_CPOL)
  248. reg |= CQSPI_REG_CONFIG_CLK_POL;
  249. if (mode & SPI_CPHA)
  250. reg |= CQSPI_REG_CONFIG_CLK_PHA;
  251. writel(reg, reg_base + CQSPI_REG_CONFIG);
  252. cadence_qspi_apb_controller_enable(reg_base);
  253. }
  254. void cadence_qspi_apb_chipselect(void *reg_base,
  255. unsigned int chip_select, unsigned int decoder_enable)
  256. {
  257. unsigned int reg;
  258. cadence_qspi_apb_controller_disable(reg_base);
  259. debug("%s : chipselect %d decode %d\n", __func__, chip_select,
  260. decoder_enable);
  261. reg = readl(reg_base + CQSPI_REG_CONFIG);
  262. /* docoder */
  263. if (decoder_enable) {
  264. reg |= CQSPI_REG_CONFIG_DECODE;
  265. } else {
  266. reg &= ~CQSPI_REG_CONFIG_DECODE;
  267. /* Convert CS if without decoder.
  268. * CS0 to 4b'1110
  269. * CS1 to 4b'1101
  270. * CS2 to 4b'1011
  271. * CS3 to 4b'0111
  272. */
  273. chip_select = 0xF & ~(1 << chip_select);
  274. }
  275. reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
  276. << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
  277. reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
  278. << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
  279. writel(reg, reg_base + CQSPI_REG_CONFIG);
  280. cadence_qspi_apb_controller_enable(reg_base);
  281. }
  282. void cadence_qspi_apb_delay(void *reg_base,
  283. unsigned int ref_clk, unsigned int sclk_hz,
  284. unsigned int tshsl_ns, unsigned int tsd2d_ns,
  285. unsigned int tchsh_ns, unsigned int tslch_ns)
  286. {
  287. unsigned int ref_clk_ns;
  288. unsigned int sclk_ns;
  289. unsigned int tshsl, tchsh, tslch, tsd2d;
  290. unsigned int reg;
  291. cadence_qspi_apb_controller_disable(reg_base);
  292. /* Convert to ns. */
  293. ref_clk_ns = DIV_ROUND_UP(1000000000, ref_clk);
  294. /* Convert to ns. */
  295. sclk_ns = DIV_ROUND_UP(1000000000, sclk_hz);
  296. /* The controller adds additional delay to that programmed in the reg */
  297. if (tshsl_ns >= sclk_ns + ref_clk_ns)
  298. tshsl_ns -= sclk_ns + ref_clk_ns;
  299. if (tchsh_ns >= sclk_ns + 3 * ref_clk_ns)
  300. tchsh_ns -= sclk_ns + 3 * ref_clk_ns;
  301. tshsl = DIV_ROUND_UP(tshsl_ns, ref_clk_ns);
  302. tchsh = DIV_ROUND_UP(tchsh_ns, ref_clk_ns);
  303. tslch = DIV_ROUND_UP(tslch_ns, ref_clk_ns);
  304. tsd2d = DIV_ROUND_UP(tsd2d_ns, ref_clk_ns);
  305. reg = ((tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
  306. << CQSPI_REG_DELAY_TSHSL_LSB);
  307. reg |= ((tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
  308. << CQSPI_REG_DELAY_TCHSH_LSB);
  309. reg |= ((tslch & CQSPI_REG_DELAY_TSLCH_MASK)
  310. << CQSPI_REG_DELAY_TSLCH_LSB);
  311. reg |= ((tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
  312. << CQSPI_REG_DELAY_TSD2D_LSB);
  313. writel(reg, reg_base + CQSPI_REG_DELAY);
  314. cadence_qspi_apb_controller_enable(reg_base);
  315. }
  316. void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat)
  317. {
  318. unsigned reg;
  319. cadence_qspi_apb_controller_disable(plat->regbase);
  320. /* Configure the device size and address bytes */
  321. reg = readl(plat->regbase + CQSPI_REG_SIZE);
  322. /* Clear the previous value */
  323. reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB);
  324. reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB);
  325. reg |= (plat->page_size << CQSPI_REG_SIZE_PAGE_LSB);
  326. reg |= (plat->block_size << CQSPI_REG_SIZE_BLOCK_LSB);
  327. writel(reg, plat->regbase + CQSPI_REG_SIZE);
  328. /* Configure the remap address register, no remap */
  329. writel(0, plat->regbase + CQSPI_REG_REMAP);
  330. /* Indirect mode configurations */
  331. writel(plat->fifo_depth / 2, plat->regbase + CQSPI_REG_SRAMPARTITION);
  332. /* Disable all interrupts */
  333. writel(0, plat->regbase + CQSPI_REG_IRQMASK);
  334. cadence_qspi_apb_controller_enable(plat->regbase);
  335. }
  336. static int cadence_qspi_apb_exec_flash_cmd(void *reg_base,
  337. unsigned int reg)
  338. {
  339. unsigned int retry = CQSPI_REG_RETRY;
  340. /* Write the CMDCTRL without start execution. */
  341. writel(reg, reg_base + CQSPI_REG_CMDCTRL);
  342. /* Start execute */
  343. reg |= CQSPI_REG_CMDCTRL_EXECUTE;
  344. writel(reg, reg_base + CQSPI_REG_CMDCTRL);
  345. while (retry--) {
  346. reg = readl(reg_base + CQSPI_REG_CMDCTRL);
  347. if ((reg & CQSPI_REG_CMDCTRL_INPROGRESS) == 0)
  348. break;
  349. udelay(1);
  350. }
  351. if (!retry) {
  352. printf("QSPI: flash command execution timeout\n");
  353. return -EIO;
  354. }
  355. /* Polling QSPI idle status. */
  356. if (!cadence_qspi_wait_idle(reg_base))
  357. return -EIO;
  358. return 0;
  359. }
  360. /* For command RDID, RDSR. */
  361. int cadence_qspi_apb_command_read(void *reg_base, const struct spi_mem_op *op)
  362. {
  363. unsigned int reg;
  364. unsigned int read_len;
  365. int status;
  366. unsigned int rxlen = op->data.nbytes;
  367. void *rxbuf = op->data.buf.in;
  368. if (rxlen > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) {
  369. printf("QSPI: Invalid input arguments rxlen %u\n", rxlen);
  370. return -EINVAL;
  371. }
  372. reg = op->cmd.opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
  373. reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
  374. /* 0 means 1 byte. */
  375. reg |= (((rxlen - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
  376. << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
  377. status = cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
  378. if (status != 0)
  379. return status;
  380. reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
  381. /* Put the read value into rx_buf */
  382. read_len = (rxlen > 4) ? 4 : rxlen;
  383. memcpy(rxbuf, &reg, read_len);
  384. rxbuf += read_len;
  385. if (rxlen > 4) {
  386. reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
  387. read_len = rxlen - read_len;
  388. memcpy(rxbuf, &reg, read_len);
  389. }
  390. return 0;
  391. }
  392. /* For commands: WRSR, WREN, WRDI, CHIP_ERASE, BE, etc. */
  393. int cadence_qspi_apb_command_write(void *reg_base, const struct spi_mem_op *op)
  394. {
  395. unsigned int reg = 0;
  396. unsigned int wr_data;
  397. unsigned int wr_len;
  398. unsigned int txlen = op->data.nbytes;
  399. const void *txbuf = op->data.buf.out;
  400. u32 addr;
  401. /* Reorder address to SPI bus order if only transferring address */
  402. if (!txlen) {
  403. addr = cpu_to_be32(op->addr.val);
  404. if (op->addr.nbytes == 3)
  405. addr >>= 8;
  406. txbuf = &addr;
  407. txlen = op->addr.nbytes;
  408. }
  409. if (txlen > CQSPI_STIG_DATA_LEN_MAX) {
  410. printf("QSPI: Invalid input arguments txlen %u\n", txlen);
  411. return -EINVAL;
  412. }
  413. reg |= op->cmd.opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
  414. if (txlen) {
  415. /* writing data = yes */
  416. reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
  417. reg |= ((txlen - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
  418. << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
  419. wr_len = txlen > 4 ? 4 : txlen;
  420. memcpy(&wr_data, txbuf, wr_len);
  421. writel(wr_data, reg_base +
  422. CQSPI_REG_CMDWRITEDATALOWER);
  423. if (txlen > 4) {
  424. txbuf += wr_len;
  425. wr_len = txlen - wr_len;
  426. memcpy(&wr_data, txbuf, wr_len);
  427. writel(wr_data, reg_base +
  428. CQSPI_REG_CMDWRITEDATAUPPER);
  429. }
  430. }
  431. /* Execute the command */
  432. return cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
  433. }
  434. /* Opcode + Address (3/4 bytes) + dummy bytes (0-4 bytes) */
  435. int cadence_qspi_apb_read_setup(struct cadence_spi_platdata *plat,
  436. const struct spi_mem_op *op)
  437. {
  438. unsigned int reg;
  439. unsigned int rd_reg;
  440. unsigned int dummy_clk;
  441. unsigned int dummy_bytes = op->dummy.nbytes;
  442. /* Setup the indirect trigger address */
  443. writel(plat->trigger_address,
  444. plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
  445. /* Configure the opcode */
  446. rd_reg = op->cmd.opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
  447. if (op->data.buswidth == 8)
  448. /* Instruction and address at DQ0, data at DQ0-7. */
  449. rd_reg |= CQSPI_INST_TYPE_OCTAL << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
  450. else if (op->data.buswidth == 4)
  451. /* Instruction and address at DQ0, data at DQ0-3. */
  452. rd_reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
  453. writel(op->addr.val, plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
  454. if (dummy_bytes) {
  455. if (dummy_bytes > CQSPI_DUMMY_BYTES_MAX)
  456. dummy_bytes = CQSPI_DUMMY_BYTES_MAX;
  457. /* Convert to clock cycles. */
  458. dummy_clk = dummy_bytes * CQSPI_DUMMY_CLKS_PER_BYTE;
  459. if (dummy_clk)
  460. rd_reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
  461. << CQSPI_REG_RD_INSTR_DUMMY_LSB;
  462. }
  463. writel(rd_reg, plat->regbase + CQSPI_REG_RD_INSTR);
  464. /* set device size */
  465. reg = readl(plat->regbase + CQSPI_REG_SIZE);
  466. reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
  467. reg |= (op->addr.nbytes - 1);
  468. writel(reg, plat->regbase + CQSPI_REG_SIZE);
  469. return 0;
  470. }
  471. static u32 cadence_qspi_get_rd_sram_level(struct cadence_spi_platdata *plat)
  472. {
  473. u32 reg = readl(plat->regbase + CQSPI_REG_SDRAMLEVEL);
  474. reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
  475. return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
  476. }
  477. static int cadence_qspi_wait_for_data(struct cadence_spi_platdata *plat)
  478. {
  479. unsigned int timeout = 10000;
  480. u32 reg;
  481. while (timeout--) {
  482. reg = cadence_qspi_get_rd_sram_level(plat);
  483. if (reg)
  484. return reg;
  485. udelay(1);
  486. }
  487. return -ETIMEDOUT;
  488. }
  489. static int
  490. cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
  491. unsigned int n_rx, u8 *rxbuf)
  492. {
  493. unsigned int remaining = n_rx;
  494. unsigned int bytes_to_read = 0;
  495. int ret;
  496. writel(n_rx, plat->regbase + CQSPI_REG_INDIRECTRDBYTES);
  497. /* Start the indirect read transfer */
  498. writel(CQSPI_REG_INDIRECTRD_START,
  499. plat->regbase + CQSPI_REG_INDIRECTRD);
  500. while (remaining > 0) {
  501. ret = cadence_qspi_wait_for_data(plat);
  502. if (ret < 0) {
  503. printf("Indirect write timed out (%i)\n", ret);
  504. goto failrd;
  505. }
  506. bytes_to_read = ret;
  507. while (bytes_to_read != 0) {
  508. bytes_to_read *= plat->fifo_width;
  509. bytes_to_read = bytes_to_read > remaining ?
  510. remaining : bytes_to_read;
  511. /*
  512. * Handle non-4-byte aligned access to avoid
  513. * data abort.
  514. */
  515. if (((uintptr_t)rxbuf % 4) || (bytes_to_read % 4))
  516. readsb(plat->ahbbase, rxbuf, bytes_to_read);
  517. else
  518. readsl(plat->ahbbase, rxbuf,
  519. bytes_to_read >> 2);
  520. rxbuf += bytes_to_read;
  521. remaining -= bytes_to_read;
  522. bytes_to_read = cadence_qspi_get_rd_sram_level(plat);
  523. }
  524. }
  525. /* Check indirect done status */
  526. ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTRD,
  527. CQSPI_REG_INDIRECTRD_DONE, 1, 10, 0);
  528. if (ret) {
  529. printf("Indirect read completion error (%i)\n", ret);
  530. goto failrd;
  531. }
  532. /* Clear indirect completion status */
  533. writel(CQSPI_REG_INDIRECTRD_DONE,
  534. plat->regbase + CQSPI_REG_INDIRECTRD);
  535. return 0;
  536. failrd:
  537. /* Cancel the indirect read */
  538. writel(CQSPI_REG_INDIRECTRD_CANCEL,
  539. plat->regbase + CQSPI_REG_INDIRECTRD);
  540. return ret;
  541. }
  542. int cadence_qspi_apb_read_execute(struct cadence_spi_platdata *plat,
  543. const struct spi_mem_op *op)
  544. {
  545. u64 from = op->addr.val;
  546. void *buf = op->data.buf.in;
  547. size_t len = op->data.nbytes;
  548. if (plat->use_dac_mode && (from + len < plat->ahbsize)) {
  549. if (len < 256 ||
  550. dma_memcpy(buf, plat->ahbbase + from, len) < 0) {
  551. memcpy_fromio(buf, plat->ahbbase + from, len);
  552. }
  553. if (!cadence_qspi_wait_idle(plat->regbase))
  554. return -EIO;
  555. return 0;
  556. }
  557. return cadence_qspi_apb_indirect_read_execute(plat, len, buf);
  558. }
  559. /* Opcode + Address (3/4 bytes) */
  560. int cadence_qspi_apb_write_setup(struct cadence_spi_platdata *plat,
  561. const struct spi_mem_op *op)
  562. {
  563. unsigned int reg;
  564. /* Setup the indirect trigger address */
  565. writel(plat->trigger_address,
  566. plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
  567. /* Configure the opcode */
  568. reg = op->cmd.opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
  569. writel(reg, plat->regbase + CQSPI_REG_WR_INSTR);
  570. writel(op->addr.val, plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);
  571. reg = readl(plat->regbase + CQSPI_REG_SIZE);
  572. reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
  573. reg |= (op->addr.nbytes - 1);
  574. writel(reg, plat->regbase + CQSPI_REG_SIZE);
  575. return 0;
  576. }
  577. static int
  578. cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
  579. unsigned int n_tx, const u8 *txbuf)
  580. {
  581. unsigned int page_size = plat->page_size;
  582. unsigned int remaining = n_tx;
  583. const u8 *bb_txbuf = txbuf;
  584. void *bounce_buf = NULL;
  585. unsigned int write_bytes;
  586. int ret;
  587. /*
  588. * Use bounce buffer for non 32 bit aligned txbuf to avoid data
  589. * aborts
  590. */
  591. if ((uintptr_t)txbuf % 4) {
  592. bounce_buf = malloc(n_tx);
  593. if (!bounce_buf)
  594. return -ENOMEM;
  595. memcpy(bounce_buf, txbuf, n_tx);
  596. bb_txbuf = bounce_buf;
  597. }
  598. /* Configure the indirect read transfer bytes */
  599. writel(n_tx, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);
  600. /* Start the indirect write transfer */
  601. writel(CQSPI_REG_INDIRECTWR_START,
  602. plat->regbase + CQSPI_REG_INDIRECTWR);
  603. while (remaining > 0) {
  604. write_bytes = remaining > page_size ? page_size : remaining;
  605. writesl(plat->ahbbase, bb_txbuf, write_bytes >> 2);
  606. if (write_bytes % 4)
  607. writesb(plat->ahbbase,
  608. bb_txbuf + rounddown(write_bytes, 4),
  609. write_bytes % 4);
  610. ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_SDRAMLEVEL,
  611. CQSPI_REG_SDRAMLEVEL_WR_MASK <<
  612. CQSPI_REG_SDRAMLEVEL_WR_LSB, 0, 10, 0);
  613. if (ret) {
  614. printf("Indirect write timed out (%i)\n", ret);
  615. goto failwr;
  616. }
  617. bb_txbuf += write_bytes;
  618. remaining -= write_bytes;
  619. }
  620. /* Check indirect done status */
  621. ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTWR,
  622. CQSPI_REG_INDIRECTWR_DONE, 1, 10, 0);
  623. if (ret) {
  624. printf("Indirect write completion error (%i)\n", ret);
  625. goto failwr;
  626. }
  627. /* Clear indirect completion status */
  628. writel(CQSPI_REG_INDIRECTWR_DONE,
  629. plat->regbase + CQSPI_REG_INDIRECTWR);
  630. if (bounce_buf)
  631. free(bounce_buf);
  632. return 0;
  633. failwr:
  634. /* Cancel the indirect write */
  635. writel(CQSPI_REG_INDIRECTWR_CANCEL,
  636. plat->regbase + CQSPI_REG_INDIRECTWR);
  637. if (bounce_buf)
  638. free(bounce_buf);
  639. return ret;
  640. }
  641. int cadence_qspi_apb_write_execute(struct cadence_spi_platdata *plat,
  642. const struct spi_mem_op *op)
  643. {
  644. u32 to = op->addr.val;
  645. const void *buf = op->data.buf.out;
  646. size_t len = op->data.nbytes;
  647. if (plat->use_dac_mode && (to + len < plat->ahbsize)) {
  648. memcpy_toio(plat->ahbbase + to, buf, len);
  649. if (!cadence_qspi_wait_idle(plat->regbase))
  650. return -EIO;
  651. return 0;
  652. }
  653. return cadence_qspi_apb_indirect_write_execute(plat, len, buf);
  654. }
  655. void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy)
  656. {
  657. unsigned int reg;
  658. /* enter XiP mode immediately and enable direct mode */
  659. reg = readl(reg_base + CQSPI_REG_CONFIG);
  660. reg |= CQSPI_REG_CONFIG_ENABLE;
  661. reg |= CQSPI_REG_CONFIG_DIRECT;
  662. reg |= CQSPI_REG_CONFIG_XIP_IMM;
  663. writel(reg, reg_base + CQSPI_REG_CONFIG);
  664. /* keep the XiP mode */
  665. writel(xip_dummy, reg_base + CQSPI_REG_MODE_BIT);
  666. /* Enable mode bit at devrd */
  667. reg = readl(reg_base + CQSPI_REG_RD_INSTR);
  668. reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
  669. writel(reg, reg_base + CQSPI_REG_RD_INSTR);
  670. }