ca_sflash.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Driver for Cortina SPI-FLASH Controller
  4. *
  5. * Copyright (C) 2020 Cortina Access Inc. All Rights Reserved.
  6. *
  7. * Author: PengPeng Chen <pengpeng.chen@cortina-access.com>
  8. */
  9. #include <common.h>
  10. #include <malloc.h>
  11. #include <clk.h>
  12. #include <dm.h>
  13. #include <errno.h>
  14. #include <fdtdec.h>
  15. #include <linux/compat.h>
  16. #include <linux/io.h>
  17. #include <linux/iopoll.h>
  18. #include <linux/ioport.h>
  19. #include <linux/sizes.h>
  20. #include <spi.h>
  21. #include <spi-mem.h>
  22. #include <reset.h>
  23. DECLARE_GLOBAL_DATA_PTR;
  24. struct ca_sflash_regs {
  25. u32 idr; /* 0x00:Flash word ID Register */
  26. u32 tc; /* 0x04:Flash Timeout Counter Register */
  27. u32 sr; /* 0x08:Flash Status Register */
  28. u32 tr; /* 0x0C:Flash Type Register */
  29. u32 asr; /* 0x10:Flash ACCESS START/BUSY Register */
  30. u32 isr; /* 0x14:Flash Interrupt Status Register */
  31. u32 imr; /* 0x18:Flash Interrupt Mask Register */
  32. u32 fcr; /* 0x1C:NAND Flash FIFO Control Register */
  33. u32 ffsr; /* 0x20:Flash FIFO Status Register */
  34. u32 ffar; /* 0x24:Flash FIFO ADDRESS Register */
  35. u32 ffmar; /* 0x28:Flash FIFO MATCHING ADDRESS Register */
  36. u32 ffdr; /* 0x2C:Flash FIFO Data Register */
  37. u32 ar; /* 0x30:Serial Flash Access Register */
  38. u32 ear; /* 0x34:Serial Flash Extend Access Register */
  39. u32 adr; /* 0x38:Serial Flash ADdress Register */
  40. u32 dr; /* 0x3C:Serial Flash Data Register */
  41. u32 tmr; /* 0x40:Serial Flash Timing Register */
  42. };
  43. /*
  44. * FLASH_TYPE
  45. */
  46. #define CA_FLASH_TR_PIN BIT(15)
  47. #define CA_FLASH_TR_TYPE_MSK GENMASK(14, 12)
  48. #define CA_FLASH_TR_TYPE(tp) (((tp) << 12) & CA_FLASH_TR_TYPE_MSK)
  49. #define CA_FLASH_TR_WIDTH BIT(11)
  50. #define CA_FLASH_TR_SIZE_MSK GENMASK(10, 9)
  51. #define CA_FLASH_TR_SIZE(sz) (((sz) << 9) & CA_FLASH_TR_SIZE_MSK)
  52. /*
  53. * FLASH_FLASH_ACCESS_START
  54. */
  55. #define CA_FLASH_ASR_IND_START_EN BIT(1)
  56. #define CA_FLASH_ASR_DMA_START_EN BIT(3)
  57. #define CA_FLASH_ASR_WR_ACCESS_EN BIT(9)
  58. /*
  59. * FLASH_FLASH_INTERRUPT
  60. */
  61. #define CA_FLASH_ISR_REG_IRQ BIT(1)
  62. #define CA_FLASH_ISR_FIFO_IRQ BIT(2)
  63. /*
  64. * FLASH_SF_ACCESS
  65. */
  66. #define CA_SF_AR_OP_MSK GENMASK(7, 0)
  67. #define CA_SF_AR_OP(op) ((op) << 0 & CA_SF_AR_OP_MSK)
  68. #define CA_SF_AR_ACCODE_MSK GENMASK(11, 8)
  69. #define CA_SF_AR_ACCODE(ac) (((ac) << 8) & CA_SF_AR_ACCODE_MSK)
  70. #define CA_SF_AR_FORCE_TERM BIT(12)
  71. #define CA_SF_AR_FORCE_BURST BIT(13)
  72. #define CA_SF_AR_AUTO_MODE_EN BIT(15)
  73. #define CA_SF_AR_CHIP_EN_ALT BIT(16)
  74. #define CA_SF_AR_HI_SPEED_RD BIT(17)
  75. #define CA_SF_AR_MIO_INF_DC BIT(24)
  76. #define CA_SF_AR_MIO_INF_AC BIT(25)
  77. #define CA_SF_AR_MIO_INF_CC BIT(26)
  78. #define CA_SF_AR_DDR_MSK GENMASK(29, 28)
  79. #define CA_SF_AR_DDR(ddr) (((ddr) << 28) & CA_SF_AR_DDR_MSK)
  80. #define CA_SF_AR_MIO_INF_MSK GENMASK(31, 30)
  81. #define CA_SF_AR_MIO_INF(io) (((io) << 30) & CA_SF_AR_MIO_INF_MSK)
  82. /*
  83. * FLASH_SF_EXT_ACCESS
  84. */
  85. #define CA_SF_EAR_OP_MSK GENMASK(7, 0)
  86. #define CA_SF_EAR_OP(op) (((op) << 0) & CA_SF_EAR_OP_MSK)
  87. #define CA_SF_EAR_DATA_CNT_MSK GENMASK(20, 8)
  88. #define CA_SF_EAR_DATA_CNT(cnt) (((cnt) << 8) & CA_SF_EAR_DATA_CNT_MSK)
  89. #define CA_SF_EAR_DATA_CNT_MAX (4096)
  90. #define CA_SF_EAR_ADDR_CNT_MSK GENMASK(23, 21)
  91. #define CA_SF_EAR_ADDR_CNT(cnt) (((cnt) << 21) & CA_SF_EAR_ADDR_CNT_MSK)
  92. #define CA_SF_EAR_ADDR_CNT_MAX (5)
  93. #define CA_SF_EAR_DUMY_CNT_MSK GENMASK(29, 24)
  94. #define CA_SF_EAR_DUMY_CNT(cnt) (((cnt) << 24) & CA_SF_EAR_DUMY_CNT_MSK)
  95. #define CA_SF_EAR_DUMY_CNT_MAX (32)
  96. #define CA_SF_EAR_DRD_CMD_EN BIT(31)
  97. /*
  98. * FLASH_SF_ADDRESS
  99. */
  100. #define CA_SF_ADR_REG_MSK GENMASK(31, 0)
  101. #define CA_SF_ADR_REG(addr) (((addr) << 0) & CA_SF_ADR_REG_MSK)
  102. /*
  103. * FLASH_SF_DATA
  104. */
  105. #define CA_SF_DR_REG_MSK GENMASK(31, 0)
  106. #define CA_SF_DR_REG(addr) (((addr) << 0) & CA_SF_DR_REG_MSK)
  107. /*
  108. * FLASH_SF_TIMING
  109. */
  110. #define CA_SF_TMR_IDLE_MSK GENMASK(7, 0)
  111. #define CA_SF_TMR_IDLE(idle) (((idle) << 0) & CA_SF_TMR_IDLE_MSK)
  112. #define CA_SF_TMR_HOLD_MSK GENMASK(15, 8)
  113. #define CA_SF_TMR_HOLD(hold) (((hold) << 8) & CA_SF_TMR_HOLD_MSK)
  114. #define CA_SF_TMR_SETUP_MSK GENMASK(23, 16)
  115. #define CA_SF_TMR_SETUP(setup) (((setup) << 16) & CA_SF_TMR_SETUP_MSK)
  116. #define CA_SF_TMR_CLK_MSK GENMASK(26, 24)
  117. #define CA_SF_TMR_CLK(clk) (((clk) << 24) & CA_SF_TMR_CLK_MSK)
  118. #define CA_SFLASH_IND_WRITE 0
  119. #define CA_SFLASH_IND_READ 1
  120. #define CA_SFLASH_MEM_MAP 3
  121. #define CA_SFLASH_FIFO_TIMEOUT_US 30000
  122. #define CA_SFLASH_BUSY_TIMEOUT_US 40000
  123. #define CA_SF_AC_OP 0x00
  124. #define CA_SF_AC_OP_1_DATA 0x01
  125. #define CA_SF_AC_OP_2_DATA 0x02
  126. #define CA_SF_AC_OP_3_DATA 0x03
  127. #define CA_SF_AC_OP_4_DATA 0x04
  128. #define CA_SF_AC_OP_3_ADDR 0x05
  129. #define CA_SF_AC_OP_4_ADDR (CA_SF_AC_OP_3_ADDR)
  130. #define CA_SF_AC_OP_3_ADDR_1_DATA 0x06
  131. #define CA_SF_AC_OP_4_ADDR_1_DATA (CA_SF_AC_OP_3_ADDR_1_DATA << 2)
  132. #define CA_SF_AC_OP_3_ADDR_2_DATA 0x07
  133. #define CA_SF_AC_OP_4_ADDR_2_DATA (CA_SF_AC_OP_3_ADDR_2_DATA << 2)
  134. #define CA_SF_AC_OP_3_ADDR_3_DATA 0x08
  135. #define CA_SF_AC_OP_4_ADDR_3_DATA (CA_SF_AC_OP_3_ADDR_3_DATA << 2)
  136. #define CA_SF_AC_OP_3_ADDR_4_DATA 0x09
  137. #define CA_SF_AC_OP_4_ADDR_4_DATA (CA_SF_AC_OP_3_ADDR_4_DATA << 2)
  138. #define CA_SF_AC_OP_3_ADDR_X_1_DATA 0x0A
  139. #define CA_SF_AC_OP_4_ADDR_X_1_DATA (CA_SF_AC_OP_3_ADDR_X_1_DATA << 2)
  140. #define CA_SF_AC_OP_3_ADDR_X_2_DATA 0x0B
  141. #define CA_SF_AC_OP_4_ADDR_X_2_DATA (CA_SF_AC_OP_3_ADDR_X_2_DATA << 2)
  142. #define CA_SF_AC_OP_3_ADDR_X_3_DATA 0x0C
  143. #define CA_SF_AC_OP_4_ADDR_X_3_DATA (CA_SF_AC_OP_3_ADDR_X_3_DATA << 2)
  144. #define CA_SF_AC_OP_3_ADDR_X_4_DATA 0x0D
  145. #define CA_SF_AC_OP_4_ADDR_X_4_DATA (CA_SF_AC_OP_3_ADDR_X_4_DATA << 2)
  146. #define CA_SF_AC_OP_3_ADDR_4X_1_DATA 0x0E
  147. #define CA_SF_AC_OP_4_ADDR_4X_1_DATA (CA_SF_AC_OP_3_ADDR_4X_1_DATA << 2)
  148. #define CA_SF_AC_OP_EXTEND 0x0F
  149. #define CA_SF_ACCESS_MIO_SINGLE 0
  150. #define CA_SF_ACCESS_MIO_DUAL 1
  151. #define CA_SF_ACCESS_MIO_QUARD 2
  152. enum access_type {
  153. RD_ACCESS,
  154. WR_ACCESS,
  155. };
  156. struct ca_sflash_priv {
  157. struct ca_sflash_regs *regs;
  158. u8 rx_width;
  159. u8 tx_width;
  160. };
  161. /*
  162. * This function doesn't do anything except help with debugging
  163. */
  164. static int ca_sflash_claim_bus(struct udevice *dev)
  165. {
  166. debug("%s:\n", __func__);
  167. return 0;
  168. }
  169. static int ca_sflash_release_bus(struct udevice *dev)
  170. {
  171. debug("%s:\n", __func__);
  172. return 0;
  173. }
  174. static int ca_sflash_set_speed(struct udevice *dev, uint speed)
  175. {
  176. debug("%s:\n", __func__);
  177. return 0;
  178. }
  179. static int ca_sflash_set_mode(struct udevice *dev, uint mode)
  180. {
  181. struct ca_sflash_priv *priv = dev_get_priv(dev);
  182. if (mode & SPI_RX_QUAD)
  183. priv->rx_width = 4;
  184. else if (mode & SPI_RX_DUAL)
  185. priv->rx_width = 2;
  186. else
  187. priv->rx_width = 1;
  188. if (mode & SPI_TX_QUAD)
  189. priv->tx_width = 4;
  190. else if (mode & SPI_TX_DUAL)
  191. priv->tx_width = 2;
  192. else
  193. priv->tx_width = 1;
  194. debug("%s: mode=%d, rx_width=%d, tx_width=%d\n",
  195. __func__, mode, priv->rx_width, priv->tx_width);
  196. return 0;
  197. }
  198. static int _ca_sflash_wait_for_not_busy(struct ca_sflash_priv *priv)
  199. {
  200. u32 asr;
  201. if (readl_poll_timeout(&priv->regs->asr, asr,
  202. !(asr & CA_FLASH_ASR_IND_START_EN),
  203. CA_SFLASH_BUSY_TIMEOUT_US)) {
  204. pr_err("busy timeout (stat:%#x)\n", asr);
  205. return -1;
  206. }
  207. return 0;
  208. }
  209. static int _ca_sflash_wait_cmd(struct ca_sflash_priv *priv,
  210. enum access_type type)
  211. {
  212. if (type == WR_ACCESS) {
  213. /* Enable write access and start the sflash indirect access */
  214. clrsetbits_le32(&priv->regs->asr, GENMASK(31, 0),
  215. CA_FLASH_ASR_WR_ACCESS_EN
  216. | CA_FLASH_ASR_IND_START_EN);
  217. } else if (type == RD_ACCESS) {
  218. /* Start the sflash indirect access */
  219. clrsetbits_le32(&priv->regs->asr, GENMASK(31, 0),
  220. CA_FLASH_ASR_IND_START_EN);
  221. } else {
  222. printf("%s: !error access type.\n", __func__);
  223. return -1;
  224. }
  225. /* Wait til the action(rd/wr) completed */
  226. return _ca_sflash_wait_for_not_busy(priv);
  227. }
  228. static int _ca_sflash_read(struct ca_sflash_priv *priv,
  229. u8 *buf, unsigned int data_len)
  230. {
  231. u32 reg_data;
  232. int len;
  233. len = data_len;
  234. while (len >= 4) {
  235. if (_ca_sflash_wait_cmd(priv, RD_ACCESS))
  236. return -1;
  237. reg_data = readl(&priv->regs->dr);
  238. *buf++ = reg_data & 0xFF;
  239. *buf++ = (reg_data >> 8) & 0xFF;
  240. *buf++ = (reg_data >> 16) & 0xFF;
  241. *buf++ = (reg_data >> 24) & 0xFF;
  242. len -= 4;
  243. debug("%s: reg_data=%#08x\n",
  244. __func__, reg_data);
  245. }
  246. if (len > 0) {
  247. if (_ca_sflash_wait_cmd(priv, RD_ACCESS))
  248. return -1;
  249. reg_data = readl(&priv->regs->dr);
  250. debug("%s: reg_data=%#08x\n",
  251. __func__, reg_data);
  252. }
  253. switch (len) {
  254. case 3:
  255. *buf++ = reg_data & 0xFF;
  256. *buf++ = (reg_data >> 8) & 0xFF;
  257. *buf++ = (reg_data >> 16) & 0xFF;
  258. break;
  259. case 2:
  260. *buf++ = reg_data & 0xFF;
  261. *buf++ = (reg_data >> 8) & 0xFF;
  262. break;
  263. case 1:
  264. *buf++ = reg_data & 0xFF;
  265. break;
  266. case 0:
  267. break;
  268. default:
  269. printf("%s: error data_length %d!\n", __func__, len);
  270. }
  271. return 0;
  272. }
  273. static int _ca_sflash_mio_set(struct ca_sflash_priv *priv,
  274. u8 width)
  275. {
  276. if (width == 4) {
  277. setbits_le32(&priv->regs->ar,
  278. CA_SF_AR_MIO_INF_DC
  279. | CA_SF_AR_MIO_INF(CA_SF_ACCESS_MIO_QUARD)
  280. | CA_SF_AR_FORCE_BURST);
  281. } else if (width == 2) {
  282. setbits_le32(&priv->regs->ar,
  283. CA_SF_AR_MIO_INF_DC
  284. | CA_SF_AR_MIO_INF(CA_SF_ACCESS_MIO_DUAL)
  285. | CA_SF_AR_FORCE_BURST);
  286. } else if (width == 1) {
  287. setbits_le32(&priv->regs->ar,
  288. CA_SF_AR_MIO_INF(CA_SF_ACCESS_MIO_SINGLE)
  289. | CA_SF_AR_FORCE_BURST);
  290. } else {
  291. printf("%s: error rx/tx width %d!\n", __func__, width);
  292. return -1;
  293. }
  294. return 0;
  295. }
  296. static int _ca_sflash_write(struct ca_sflash_priv *priv,
  297. u8 *buf, unsigned int data_len)
  298. {
  299. u32 reg_data;
  300. int len;
  301. len = data_len;
  302. while (len > 0) {
  303. reg_data = buf[0]
  304. | (buf[1] << 8)
  305. | (buf[2] << 16)
  306. | (buf[3] << 24);
  307. debug("%s: reg_data=%#08x\n",
  308. __func__, reg_data);
  309. /* Fill data */
  310. clrsetbits_le32(&priv->regs->dr, GENMASK(31, 0), reg_data);
  311. if (_ca_sflash_wait_cmd(priv, WR_ACCESS))
  312. return -1;
  313. len -= 4;
  314. buf += 4;
  315. }
  316. return 0;
  317. }
  318. static int _ca_sflash_access_data(struct ca_sflash_priv *priv,
  319. struct spi_mem_op *op)
  320. {
  321. int total_cnt;
  322. unsigned int len;
  323. unsigned int data_cnt = op->data.nbytes;
  324. u64 addr_offset = op->addr.val;
  325. u8 addr_cnt = op->addr.nbytes;
  326. u8 *data_buf = NULL;
  327. u8 *buf = NULL;
  328. if (op->data.dir == SPI_MEM_DATA_IN)
  329. data_buf = (u8 *)op->data.buf.in;
  330. else
  331. data_buf = (u8 *)op->data.buf.out;
  332. if (data_cnt > CA_SF_EAR_DATA_CNT_MAX)
  333. buf = malloc(CA_SF_EAR_DATA_CNT_MAX);
  334. else
  335. buf = malloc(data_cnt);
  336. total_cnt = data_cnt;
  337. while (total_cnt > 0) {
  338. /* Fill address */
  339. if (addr_cnt > 0)
  340. clrsetbits_le32(&priv->regs->adr,
  341. GENMASK(31, 0), (u32)addr_offset);
  342. if (total_cnt > CA_SF_EAR_DATA_CNT_MAX) {
  343. len = CA_SF_EAR_DATA_CNT_MAX;
  344. addr_offset += CA_SF_EAR_DATA_CNT_MAX;
  345. /* Clear start bit before next bulk read */
  346. clrbits_le32(&priv->regs->asr, GENMASK(31, 0));
  347. } else {
  348. len = total_cnt;
  349. }
  350. memset(buf, 0, len);
  351. if (op->data.dir == SPI_MEM_DATA_IN) {
  352. if (_ca_sflash_read(priv, buf, len))
  353. break;
  354. memcpy(data_buf, buf, len);
  355. } else {
  356. memcpy(buf, data_buf, len);
  357. if (_ca_sflash_write(priv, buf, len))
  358. break;
  359. }
  360. total_cnt -= len;
  361. data_buf += len;
  362. }
  363. if (buf)
  364. free(buf);
  365. return total_cnt > 0 ? -1 : 0;
  366. }
  367. static int _ca_sflash_issue_cmd(struct ca_sflash_priv *priv,
  368. struct spi_mem_op *op, u8 opcode)
  369. {
  370. u8 dummy_cnt = op->dummy.nbytes;
  371. u8 addr_cnt = op->addr.nbytes;
  372. u8 mio_width;
  373. unsigned int data_cnt = op->data.nbytes;
  374. u64 addr_offset = op->addr.val;
  375. /* Set the access register */
  376. clrsetbits_le32(&priv->regs->ar,
  377. GENMASK(31, 0), CA_SF_AR_ACCODE(opcode));
  378. if (opcode == CA_SF_AC_OP_EXTEND) { /* read_data, write_data */
  379. if (data_cnt > 6) {
  380. if (op->data.dir == SPI_MEM_DATA_IN)
  381. mio_width = priv->rx_width;
  382. else
  383. mio_width = priv->tx_width;
  384. if (_ca_sflash_mio_set(priv, mio_width))
  385. return -1;
  386. }
  387. debug("%s: FLASH ACCESS reg=%#08x\n",
  388. __func__, readl(&priv->regs->ar));
  389. /* Use command in extend_access register */
  390. clrsetbits_le32(&priv->regs->ear,
  391. GENMASK(31, 0), CA_SF_EAR_OP(op->cmd.opcode)
  392. | CA_SF_EAR_DUMY_CNT(dummy_cnt * 8 - 1)
  393. | CA_SF_EAR_ADDR_CNT(addr_cnt - 1)
  394. | CA_SF_EAR_DATA_CNT(4 - 1)
  395. | CA_SF_EAR_DRD_CMD_EN);
  396. debug("%s: FLASH EXT ACCESS reg=%#08x\n",
  397. __func__, readl(&priv->regs->ear));
  398. if (_ca_sflash_access_data(priv, op))
  399. return -1;
  400. } else { /* reset_op, wr_enable, wr_disable */
  401. setbits_le32(&priv->regs->ar,
  402. CA_SF_AR_OP(op->cmd.opcode));
  403. debug("%s: FLASH ACCESS reg=%#08x\n",
  404. __func__, readl(&priv->regs->ar));
  405. if (opcode == CA_SF_AC_OP_4_ADDR) { /* erase_op */
  406. /* Configure address length */
  407. if (addr_cnt > 3) /* 4 Bytes address */
  408. setbits_le32(&priv->regs->tr,
  409. CA_FLASH_TR_SIZE(2));
  410. else /* 3 Bytes address */
  411. clrbits_le32(&priv->regs->tr,
  412. CA_FLASH_TR_SIZE_MSK);
  413. /* Fill address */
  414. if (addr_cnt > 0)
  415. clrsetbits_le32(&priv->regs->adr,
  416. GENMASK(31, 0),
  417. (u32)addr_offset);
  418. }
  419. if (_ca_sflash_wait_cmd(priv, RD_ACCESS))
  420. return -1;
  421. }
  422. /* elapse 10us before issuing any other command */
  423. udelay(10);
  424. return 0;
  425. }
  426. static int ca_sflash_exec_op(struct spi_slave *slave,
  427. const struct spi_mem_op *op)
  428. {
  429. struct ca_sflash_priv *priv = dev_get_priv(slave->dev->parent);
  430. u8 opcode;
  431. debug("%s: cmd:%#02x addr.val:%#llx addr.len:%#x data.len:%#x data.dir:%#x\n",
  432. __func__, op->cmd.opcode, op->addr.val,
  433. op->addr.nbytes, op->data.nbytes, op->data.dir);
  434. if (op->data.nbytes == 0 && op->addr.nbytes == 0) {
  435. opcode = CA_SF_AC_OP;
  436. } else if (op->data.nbytes == 0 && op->addr.nbytes > 0) {
  437. opcode = CA_SF_AC_OP_4_ADDR;
  438. } else if (op->data.nbytes > 0) {
  439. opcode = CA_SF_AC_OP_EXTEND;
  440. } else {
  441. printf("%s: can't support cmd.opcode:(%#02x) type currently!\n",
  442. __func__, op->cmd.opcode);
  443. return -1;
  444. }
  445. return _ca_sflash_issue_cmd(priv, (struct spi_mem_op *)op, opcode);
  446. }
  447. static void ca_sflash_init(struct ca_sflash_priv *priv)
  448. {
  449. /* Set FLASH_TYPE as serial flash, value: 0x0400*/
  450. clrsetbits_le32(&priv->regs->tr,
  451. GENMASK(31, 0), CA_FLASH_TR_SIZE(2));
  452. debug("%s: FLASH_TYPE reg=%#x\n",
  453. __func__, readl(&priv->regs->tr));
  454. /* Minimize flash timing, value: 0x07010101 */
  455. clrsetbits_le32(&priv->regs->tmr,
  456. GENMASK(31, 0),
  457. CA_SF_TMR_CLK(0x07)
  458. | CA_SF_TMR_SETUP(0x01)
  459. | CA_SF_TMR_HOLD(0x01)
  460. | CA_SF_TMR_IDLE(0x01));
  461. debug("%s: FLASH_TIMING reg=%#x\n",
  462. __func__, readl(&priv->regs->tmr));
  463. }
  464. static int ca_sflash_probe(struct udevice *dev)
  465. {
  466. struct ca_sflash_priv *priv = dev_get_priv(dev);
  467. struct resource res;
  468. int ret;
  469. /* Map the registers */
  470. ret = dev_read_resource_byname(dev, "sflash-regs", &res);
  471. if (ret) {
  472. dev_err(dev, "can't get regs base addresses(ret = %d)!\n", ret);
  473. return ret;
  474. }
  475. priv->regs = devm_ioremap(dev, res.start, resource_size(&res));
  476. if (IS_ERR(priv->regs))
  477. return PTR_ERR(priv->regs);
  478. ca_sflash_init(priv);
  479. printf("SFLASH: Controller probed ready\n");
  480. return 0;
  481. }
  482. static const struct spi_controller_mem_ops ca_sflash_mem_ops = {
  483. .exec_op = ca_sflash_exec_op,
  484. };
  485. static const struct dm_spi_ops ca_sflash_ops = {
  486. .claim_bus = ca_sflash_claim_bus,
  487. .release_bus = ca_sflash_release_bus,
  488. .set_speed = ca_sflash_set_speed,
  489. .set_mode = ca_sflash_set_mode,
  490. .mem_ops = &ca_sflash_mem_ops,
  491. };
  492. static const struct udevice_id ca_sflash_ids[] = {
  493. {.compatible = "cortina,ca-sflash"},
  494. {}
  495. };
  496. U_BOOT_DRIVER(ca_sflash) = {
  497. .name = "ca_sflash",
  498. .id = UCLASS_SPI,
  499. .of_match = ca_sflash_ids,
  500. .ops = &ca_sflash_ops,
  501. .priv_auto_alloc_size = sizeof(struct ca_sflash_priv),
  502. .probe = ca_sflash_probe,
  503. };