bcm63xx_spi.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
  4. *
  5. * Derived from linux/drivers/spi/spi-bcm63xx.c:
  6. * Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org>
  7. * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
  8. */
  9. #include <common.h>
  10. #include <clk.h>
  11. #include <dm.h>
  12. #include <log.h>
  13. #include <malloc.h>
  14. #include <spi.h>
  15. #include <reset.h>
  16. #include <wait_bit.h>
  17. #include <asm/io.h>
  18. /* BCM6348 SPI core */
  19. #define SPI_6348_CLK 0x06
  20. #define SPI_6348_CMD 0x00
  21. #define SPI_6348_CTL 0x40
  22. #define SPI_6348_CTL_SHIFT 6
  23. #define SPI_6348_FILL 0x07
  24. #define SPI_6348_IR_MASK 0x04
  25. #define SPI_6348_IR_STAT 0x02
  26. #define SPI_6348_RX 0x80
  27. #define SPI_6348_RX_SIZE 0x3f
  28. #define SPI_6348_TX 0x41
  29. #define SPI_6348_TX_SIZE 0x3f
  30. /* BCM6358 SPI core */
  31. #define SPI_6358_CLK 0x706
  32. #define SPI_6358_CMD 0x700
  33. #define SPI_6358_CTL 0x000
  34. #define SPI_6358_CTL_SHIFT 14
  35. #define SPI_6358_FILL 0x707
  36. #define SPI_6358_IR_MASK 0x702
  37. #define SPI_6358_IR_STAT 0x704
  38. #define SPI_6358_RX 0x400
  39. #define SPI_6358_RX_SIZE 0x220
  40. #define SPI_6358_TX 0x002
  41. #define SPI_6358_TX_SIZE 0x21e
  42. /* SPI Clock register */
  43. #define SPI_CLK_SHIFT 0
  44. #define SPI_CLK_20MHZ (0 << SPI_CLK_SHIFT)
  45. #define SPI_CLK_0_391MHZ (1 << SPI_CLK_SHIFT)
  46. #define SPI_CLK_0_781MHZ (2 << SPI_CLK_SHIFT)
  47. #define SPI_CLK_1_563MHZ (3 << SPI_CLK_SHIFT)
  48. #define SPI_CLK_3_125MHZ (4 << SPI_CLK_SHIFT)
  49. #define SPI_CLK_6_250MHZ (5 << SPI_CLK_SHIFT)
  50. #define SPI_CLK_12_50MHZ (6 << SPI_CLK_SHIFT)
  51. #define SPI_CLK_25MHZ (7 << SPI_CLK_SHIFT)
  52. #define SPI_CLK_MASK (7 << SPI_CLK_SHIFT)
  53. #define SPI_CLK_SSOFF_SHIFT 3
  54. #define SPI_CLK_SSOFF_2 (2 << SPI_CLK_SSOFF_SHIFT)
  55. #define SPI_CLK_SSOFF_MASK (7 << SPI_CLK_SSOFF_SHIFT)
  56. #define SPI_CLK_BSWAP_SHIFT 7
  57. #define SPI_CLK_BSWAP_MASK (1 << SPI_CLK_BSWAP_SHIFT)
  58. /* SPI Command register */
  59. #define SPI_CMD_OP_SHIFT 0
  60. #define SPI_CMD_OP_START (0x3 << SPI_CMD_OP_SHIFT)
  61. #define SPI_CMD_SLAVE_SHIFT 4
  62. #define SPI_CMD_SLAVE_MASK (0xf << SPI_CMD_SLAVE_SHIFT)
  63. #define SPI_CMD_PREPEND_SHIFT 8
  64. #define SPI_CMD_PREPEND_BYTES 0xf
  65. #define SPI_CMD_3WIRE_SHIFT 12
  66. #define SPI_CMD_3WIRE_MASK (1 << SPI_CMD_3WIRE_SHIFT)
  67. /* SPI Control register */
  68. #define SPI_CTL_TYPE_FD_RW 0
  69. #define SPI_CTL_TYPE_HD_W 1
  70. #define SPI_CTL_TYPE_HD_R 2
  71. /* SPI Interrupt registers */
  72. #define SPI_IR_DONE_SHIFT 0
  73. #define SPI_IR_DONE_MASK (1 << SPI_IR_DONE_SHIFT)
  74. #define SPI_IR_RXOVER_SHIFT 1
  75. #define SPI_IR_RXOVER_MASK (1 << SPI_IR_RXOVER_SHIFT)
  76. #define SPI_IR_TXUNDER_SHIFT 2
  77. #define SPI_IR_TXUNDER_MASK (1 << SPI_IR_TXUNDER_SHIFT)
  78. #define SPI_IR_TXOVER_SHIFT 3
  79. #define SPI_IR_TXOVER_MASK (1 << SPI_IR_TXOVER_SHIFT)
  80. #define SPI_IR_RXUNDER_SHIFT 4
  81. #define SPI_IR_RXUNDER_MASK (1 << SPI_IR_RXUNDER_SHIFT)
  82. #define SPI_IR_CLEAR_MASK (SPI_IR_DONE_MASK |\
  83. SPI_IR_RXOVER_MASK |\
  84. SPI_IR_TXUNDER_MASK |\
  85. SPI_IR_TXOVER_MASK |\
  86. SPI_IR_RXUNDER_MASK)
  87. enum bcm63xx_regs_spi {
  88. SPI_CLK,
  89. SPI_CMD,
  90. SPI_CTL,
  91. SPI_CTL_SHIFT,
  92. SPI_FILL,
  93. SPI_IR_MASK,
  94. SPI_IR_STAT,
  95. SPI_RX,
  96. SPI_RX_SIZE,
  97. SPI_TX,
  98. SPI_TX_SIZE,
  99. };
  100. struct bcm63xx_spi_priv {
  101. const unsigned long *regs;
  102. void __iomem *base;
  103. size_t tx_bytes;
  104. uint8_t num_cs;
  105. };
  106. #define SPI_CLK_CNT 8
  107. static const unsigned bcm63xx_spi_freq_table[SPI_CLK_CNT][2] = {
  108. { 25000000, SPI_CLK_25MHZ },
  109. { 20000000, SPI_CLK_20MHZ },
  110. { 12500000, SPI_CLK_12_50MHZ },
  111. { 6250000, SPI_CLK_6_250MHZ },
  112. { 3125000, SPI_CLK_3_125MHZ },
  113. { 1563000, SPI_CLK_1_563MHZ },
  114. { 781000, SPI_CLK_0_781MHZ },
  115. { 391000, SPI_CLK_0_391MHZ }
  116. };
  117. static int bcm63xx_spi_cs_info(struct udevice *bus, uint cs,
  118. struct spi_cs_info *info)
  119. {
  120. struct bcm63xx_spi_priv *priv = dev_get_priv(bus);
  121. if (cs >= priv->num_cs) {
  122. printf("no cs %u\n", cs);
  123. return -EINVAL;
  124. }
  125. return 0;
  126. }
  127. static int bcm63xx_spi_set_mode(struct udevice *bus, uint mode)
  128. {
  129. struct bcm63xx_spi_priv *priv = dev_get_priv(bus);
  130. const unsigned long *regs = priv->regs;
  131. if (mode & SPI_LSB_FIRST)
  132. setbits_8(priv->base + regs[SPI_CLK], SPI_CLK_BSWAP_MASK);
  133. else
  134. clrbits_8(priv->base + regs[SPI_CLK], SPI_CLK_BSWAP_MASK);
  135. return 0;
  136. }
  137. static int bcm63xx_spi_set_speed(struct udevice *bus, uint speed)
  138. {
  139. struct bcm63xx_spi_priv *priv = dev_get_priv(bus);
  140. const unsigned long *regs = priv->regs;
  141. uint8_t clk_cfg;
  142. int i;
  143. /* default to lowest clock configuration */
  144. clk_cfg = SPI_CLK_0_391MHZ;
  145. /* find the closest clock configuration */
  146. for (i = 0; i < SPI_CLK_CNT; i++) {
  147. if (speed >= bcm63xx_spi_freq_table[i][0]) {
  148. clk_cfg = bcm63xx_spi_freq_table[i][1];
  149. break;
  150. }
  151. }
  152. /* write clock configuration */
  153. clrsetbits_8(priv->base + regs[SPI_CLK],
  154. SPI_CLK_SSOFF_MASK | SPI_CLK_MASK,
  155. clk_cfg | SPI_CLK_SSOFF_2);
  156. return 0;
  157. }
  158. /*
  159. * BCM63xx SPI driver doesn't allow keeping CS active between transfers since
  160. * they are HW controlled.
  161. * However, it provides a mechanism to prepend write transfers prior to read
  162. * transfers (with a maximum prepend of 15 bytes), which is usually enough for
  163. * SPI-connected flashes since reading requires prepending a write transfer of
  164. * 5 bytes.
  165. *
  166. * This implementation takes advantage of the prepend mechanism and combines
  167. * multiple transfers into a single one where possible (single/multiple write
  168. * transfer(s) followed by a final read/write transfer).
  169. * However, it's not possible to buffer reads, which means that read transfers
  170. * should always be done as the final ones.
  171. * On the other hand, take into account that combining write transfers into
  172. * a single one is just buffering and doesn't require prepend mechanism.
  173. */
  174. static int bcm63xx_spi_xfer(struct udevice *dev, unsigned int bitlen,
  175. const void *dout, void *din, unsigned long flags)
  176. {
  177. struct bcm63xx_spi_priv *priv = dev_get_priv(dev->parent);
  178. const unsigned long *regs = priv->regs;
  179. size_t data_bytes = bitlen / 8;
  180. if (flags & SPI_XFER_BEGIN) {
  181. /* clear prepends */
  182. priv->tx_bytes = 0;
  183. /* initialize hardware */
  184. writeb_be(0, priv->base + regs[SPI_IR_MASK]);
  185. }
  186. if (din) {
  187. /* buffering reads not possible since cs is hw controlled */
  188. if (!(flags & SPI_XFER_END)) {
  189. printf("unable to buffer reads\n");
  190. return -EINVAL;
  191. }
  192. /* check rx size */
  193. if (data_bytes > regs[SPI_RX_SIZE]) {
  194. printf("max rx bytes exceeded\n");
  195. return -EMSGSIZE;
  196. }
  197. }
  198. if (dout) {
  199. /* check tx size */
  200. if (priv->tx_bytes + data_bytes > regs[SPI_TX_SIZE]) {
  201. printf("max tx bytes exceeded\n");
  202. return -EMSGSIZE;
  203. }
  204. /* copy tx data */
  205. memcpy_toio(priv->base + regs[SPI_TX] + priv->tx_bytes,
  206. dout, data_bytes);
  207. priv->tx_bytes += data_bytes;
  208. }
  209. if (flags & SPI_XFER_END) {
  210. struct dm_spi_slave_platdata *plat =
  211. dev_get_parent_platdata(dev);
  212. uint16_t val, cmd;
  213. int ret;
  214. /* determine control config */
  215. if (dout && !din) {
  216. /* buffered write transfers */
  217. val = priv->tx_bytes;
  218. val |= (SPI_CTL_TYPE_HD_W << regs[SPI_CTL_SHIFT]);
  219. priv->tx_bytes = 0;
  220. } else {
  221. if (dout && din && (flags & SPI_XFER_ONCE)) {
  222. /* full duplex read/write */
  223. val = data_bytes;
  224. val |= (SPI_CTL_TYPE_FD_RW <<
  225. regs[SPI_CTL_SHIFT]);
  226. priv->tx_bytes = 0;
  227. } else {
  228. /* prepended write transfer */
  229. val = data_bytes;
  230. val |= (SPI_CTL_TYPE_HD_R <<
  231. regs[SPI_CTL_SHIFT]);
  232. if (priv->tx_bytes > SPI_CMD_PREPEND_BYTES) {
  233. printf("max prepend bytes exceeded\n");
  234. return -EMSGSIZE;
  235. }
  236. }
  237. }
  238. if (regs[SPI_CTL_SHIFT] >= 8)
  239. writew_be(val, priv->base + regs[SPI_CTL]);
  240. else
  241. writeb_be(val, priv->base + regs[SPI_CTL]);
  242. /* clear interrupts */
  243. writeb_be(SPI_IR_CLEAR_MASK, priv->base + regs[SPI_IR_STAT]);
  244. /* issue the transfer */
  245. cmd = SPI_CMD_OP_START;
  246. cmd |= (plat->cs << SPI_CMD_SLAVE_SHIFT) & SPI_CMD_SLAVE_MASK;
  247. cmd |= (priv->tx_bytes << SPI_CMD_PREPEND_SHIFT);
  248. if (plat->mode & SPI_3WIRE)
  249. cmd |= SPI_CMD_3WIRE_MASK;
  250. writew_be(cmd, priv->base + regs[SPI_CMD]);
  251. /* enable interrupts */
  252. writeb_be(SPI_IR_DONE_MASK, priv->base + regs[SPI_IR_MASK]);
  253. ret = wait_for_bit_8(priv->base + regs[SPI_IR_STAT],
  254. SPI_IR_DONE_MASK, true, 1000, false);
  255. if (ret) {
  256. printf("interrupt timeout\n");
  257. return ret;
  258. }
  259. /* copy rx data */
  260. if (din)
  261. memcpy_fromio(din, priv->base + regs[SPI_RX],
  262. data_bytes);
  263. }
  264. return 0;
  265. }
  266. static const struct dm_spi_ops bcm63xx_spi_ops = {
  267. .cs_info = bcm63xx_spi_cs_info,
  268. .set_mode = bcm63xx_spi_set_mode,
  269. .set_speed = bcm63xx_spi_set_speed,
  270. .xfer = bcm63xx_spi_xfer,
  271. };
  272. static const unsigned long bcm6348_spi_regs[] = {
  273. [SPI_CLK] = SPI_6348_CLK,
  274. [SPI_CMD] = SPI_6348_CMD,
  275. [SPI_CTL] = SPI_6348_CTL,
  276. [SPI_CTL_SHIFT] = SPI_6348_CTL_SHIFT,
  277. [SPI_FILL] = SPI_6348_FILL,
  278. [SPI_IR_MASK] = SPI_6348_IR_MASK,
  279. [SPI_IR_STAT] = SPI_6348_IR_STAT,
  280. [SPI_RX] = SPI_6348_RX,
  281. [SPI_RX_SIZE] = SPI_6348_RX_SIZE,
  282. [SPI_TX] = SPI_6348_TX,
  283. [SPI_TX_SIZE] = SPI_6348_TX_SIZE,
  284. };
  285. static const unsigned long bcm6358_spi_regs[] = {
  286. [SPI_CLK] = SPI_6358_CLK,
  287. [SPI_CMD] = SPI_6358_CMD,
  288. [SPI_CTL] = SPI_6358_CTL,
  289. [SPI_CTL_SHIFT] = SPI_6358_CTL_SHIFT,
  290. [SPI_FILL] = SPI_6358_FILL,
  291. [SPI_IR_MASK] = SPI_6358_IR_MASK,
  292. [SPI_IR_STAT] = SPI_6358_IR_STAT,
  293. [SPI_RX] = SPI_6358_RX,
  294. [SPI_RX_SIZE] = SPI_6358_RX_SIZE,
  295. [SPI_TX] = SPI_6358_TX,
  296. [SPI_TX_SIZE] = SPI_6358_TX_SIZE,
  297. };
  298. static const struct udevice_id bcm63xx_spi_ids[] = {
  299. {
  300. .compatible = "brcm,bcm6348-spi",
  301. .data = (ulong)&bcm6348_spi_regs,
  302. }, {
  303. .compatible = "brcm,bcm6358-spi",
  304. .data = (ulong)&bcm6358_spi_regs,
  305. }, { /* sentinel */ }
  306. };
  307. static int bcm63xx_spi_child_pre_probe(struct udevice *dev)
  308. {
  309. struct bcm63xx_spi_priv *priv = dev_get_priv(dev->parent);
  310. const unsigned long *regs = priv->regs;
  311. struct spi_slave *slave = dev_get_parent_priv(dev);
  312. struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
  313. /* check cs */
  314. if (plat->cs >= priv->num_cs) {
  315. printf("no cs %u\n", plat->cs);
  316. return -ENODEV;
  317. }
  318. /* max read/write sizes */
  319. slave->max_read_size = regs[SPI_RX_SIZE];
  320. slave->max_write_size = regs[SPI_TX_SIZE];
  321. return 0;
  322. }
  323. static int bcm63xx_spi_probe(struct udevice *dev)
  324. {
  325. struct bcm63xx_spi_priv *priv = dev_get_priv(dev);
  326. const unsigned long *regs =
  327. (const unsigned long *)dev_get_driver_data(dev);
  328. struct reset_ctl rst_ctl;
  329. struct clk clk;
  330. int ret;
  331. priv->base = dev_remap_addr(dev);
  332. if (!priv->base)
  333. return -EINVAL;
  334. priv->regs = regs;
  335. priv->num_cs = dev_read_u32_default(dev, "num-cs", 8);
  336. /* enable clock */
  337. ret = clk_get_by_index(dev, 0, &clk);
  338. if (ret < 0)
  339. return ret;
  340. ret = clk_enable(&clk);
  341. if (ret < 0)
  342. return ret;
  343. ret = clk_free(&clk);
  344. if (ret < 0)
  345. return ret;
  346. /* perform reset */
  347. ret = reset_get_by_index(dev, 0, &rst_ctl);
  348. if (ret < 0)
  349. return ret;
  350. ret = reset_deassert(&rst_ctl);
  351. if (ret < 0)
  352. return ret;
  353. ret = reset_free(&rst_ctl);
  354. if (ret < 0)
  355. return ret;
  356. /* initialize hardware */
  357. writeb_be(0, priv->base + regs[SPI_IR_MASK]);
  358. /* set fill register */
  359. writeb_be(0xff, priv->base + regs[SPI_FILL]);
  360. return 0;
  361. }
  362. U_BOOT_DRIVER(bcm63xx_spi) = {
  363. .name = "bcm63xx_spi",
  364. .id = UCLASS_SPI,
  365. .of_match = bcm63xx_spi_ids,
  366. .ops = &bcm63xx_spi_ops,
  367. .priv_auto_alloc_size = sizeof(struct bcm63xx_spi_priv),
  368. .child_pre_probe = bcm63xx_spi_child_pre_probe,
  369. .probe = bcm63xx_spi_probe,
  370. };