atmel-quadspi.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Driver for Atmel QSPI Controller
  4. *
  5. * Copyright (C) 2015 Atmel Corporation
  6. * Copyright (C) 2018 Cryptera A/S
  7. *
  8. * Author: Cyrille Pitchen <cyrille.pitchen@atmel.com>
  9. * Author: Piotr Bugalski <bugalski.piotr@gmail.com>
  10. */
  11. #include <malloc.h>
  12. #include <asm/io.h>
  13. #include <clk.h>
  14. #include <common.h>
  15. #include <dm.h>
  16. #include <errno.h>
  17. #include <fdtdec.h>
  18. #include <dm/device_compat.h>
  19. #include <linux/bitops.h>
  20. #include <linux/err.h>
  21. #include <linux/io.h>
  22. #include <linux/iopoll.h>
  23. #include <linux/ioport.h>
  24. #include <mach/clk.h>
  25. #include <spi.h>
  26. #include <spi-mem.h>
  27. /* QSPI register offsets */
  28. #define QSPI_CR 0x0000 /* Control Register */
  29. #define QSPI_MR 0x0004 /* Mode Register */
  30. #define QSPI_RD 0x0008 /* Receive Data Register */
  31. #define QSPI_TD 0x000c /* Transmit Data Register */
  32. #define QSPI_SR 0x0010 /* Status Register */
  33. #define QSPI_IER 0x0014 /* Interrupt Enable Register */
  34. #define QSPI_IDR 0x0018 /* Interrupt Disable Register */
  35. #define QSPI_IMR 0x001c /* Interrupt Mask Register */
  36. #define QSPI_SCR 0x0020 /* Serial Clock Register */
  37. #define QSPI_IAR 0x0030 /* Instruction Address Register */
  38. #define QSPI_ICR 0x0034 /* Instruction Code Register */
  39. #define QSPI_WICR 0x0034 /* Write Instruction Code Register */
  40. #define QSPI_IFR 0x0038 /* Instruction Frame Register */
  41. #define QSPI_RICR 0x003C /* Read Instruction Code Register */
  42. #define QSPI_SMR 0x0040 /* Scrambling Mode Register */
  43. #define QSPI_SKR 0x0044 /* Scrambling Key Register */
  44. #define QSPI_WPMR 0x00E4 /* Write Protection Mode Register */
  45. #define QSPI_WPSR 0x00E8 /* Write Protection Status Register */
  46. #define QSPI_VERSION 0x00FC /* Version Register */
  47. /* Bitfields in QSPI_CR (Control Register) */
  48. #define QSPI_CR_QSPIEN BIT(0)
  49. #define QSPI_CR_QSPIDIS BIT(1)
  50. #define QSPI_CR_SWRST BIT(7)
  51. #define QSPI_CR_LASTXFER BIT(24)
  52. /* Bitfields in QSPI_MR (Mode Register) */
  53. #define QSPI_MR_SMM BIT(0)
  54. #define QSPI_MR_LLB BIT(1)
  55. #define QSPI_MR_WDRBT BIT(2)
  56. #define QSPI_MR_SMRM BIT(3)
  57. #define QSPI_MR_CSMODE_MASK GENMASK(5, 4)
  58. #define QSPI_MR_CSMODE_NOT_RELOADED (0 << 4)
  59. #define QSPI_MR_CSMODE_LASTXFER (1 << 4)
  60. #define QSPI_MR_CSMODE_SYSTEMATICALLY (2 << 4)
  61. #define QSPI_MR_NBBITS_MASK GENMASK(11, 8)
  62. #define QSPI_MR_NBBITS(n) ((((n) - 8) << 8) & QSPI_MR_NBBITS_MASK)
  63. #define QSPI_MR_DLYBCT_MASK GENMASK(23, 16)
  64. #define QSPI_MR_DLYBCT(n) (((n) << 16) & QSPI_MR_DLYBCT_MASK)
  65. #define QSPI_MR_DLYCS_MASK GENMASK(31, 24)
  66. #define QSPI_MR_DLYCS(n) (((n) << 24) & QSPI_MR_DLYCS_MASK)
  67. /* Bitfields in QSPI_SR/QSPI_IER/QSPI_IDR/QSPI_IMR */
  68. #define QSPI_SR_RDRF BIT(0)
  69. #define QSPI_SR_TDRE BIT(1)
  70. #define QSPI_SR_TXEMPTY BIT(2)
  71. #define QSPI_SR_OVRES BIT(3)
  72. #define QSPI_SR_CSR BIT(8)
  73. #define QSPI_SR_CSS BIT(9)
  74. #define QSPI_SR_INSTRE BIT(10)
  75. #define QSPI_SR_QSPIENS BIT(24)
  76. #define QSPI_SR_CMD_COMPLETED (QSPI_SR_INSTRE | QSPI_SR_CSR)
  77. /* Bitfields in QSPI_SCR (Serial Clock Register) */
  78. #define QSPI_SCR_CPOL BIT(0)
  79. #define QSPI_SCR_CPHA BIT(1)
  80. #define QSPI_SCR_SCBR_MASK GENMASK(15, 8)
  81. #define QSPI_SCR_SCBR(n) (((n) << 8) & QSPI_SCR_SCBR_MASK)
  82. #define QSPI_SCR_DLYBS_MASK GENMASK(23, 16)
  83. #define QSPI_SCR_DLYBS(n) (((n) << 16) & QSPI_SCR_DLYBS_MASK)
  84. /* Bitfields in QSPI_ICR (Read/Write Instruction Code Register) */
  85. #define QSPI_ICR_INST_MASK GENMASK(7, 0)
  86. #define QSPI_ICR_INST(inst) (((inst) << 0) & QSPI_ICR_INST_MASK)
  87. #define QSPI_ICR_OPT_MASK GENMASK(23, 16)
  88. #define QSPI_ICR_OPT(opt) (((opt) << 16) & QSPI_ICR_OPT_MASK)
  89. /* Bitfields in QSPI_IFR (Instruction Frame Register) */
  90. #define QSPI_IFR_WIDTH_MASK GENMASK(2, 0)
  91. #define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (0 << 0)
  92. #define QSPI_IFR_WIDTH_DUAL_OUTPUT (1 << 0)
  93. #define QSPI_IFR_WIDTH_QUAD_OUTPUT (2 << 0)
  94. #define QSPI_IFR_WIDTH_DUAL_IO (3 << 0)
  95. #define QSPI_IFR_WIDTH_QUAD_IO (4 << 0)
  96. #define QSPI_IFR_WIDTH_DUAL_CMD (5 << 0)
  97. #define QSPI_IFR_WIDTH_QUAD_CMD (6 << 0)
  98. #define QSPI_IFR_INSTEN BIT(4)
  99. #define QSPI_IFR_ADDREN BIT(5)
  100. #define QSPI_IFR_OPTEN BIT(6)
  101. #define QSPI_IFR_DATAEN BIT(7)
  102. #define QSPI_IFR_OPTL_MASK GENMASK(9, 8)
  103. #define QSPI_IFR_OPTL_1BIT (0 << 8)
  104. #define QSPI_IFR_OPTL_2BIT (1 << 8)
  105. #define QSPI_IFR_OPTL_4BIT (2 << 8)
  106. #define QSPI_IFR_OPTL_8BIT (3 << 8)
  107. #define QSPI_IFR_ADDRL BIT(10)
  108. #define QSPI_IFR_TFRTYP_MEM BIT(12)
  109. #define QSPI_IFR_SAMA5D2_WRITE_TRSFR BIT(13)
  110. #define QSPI_IFR_CRM BIT(14)
  111. #define QSPI_IFR_NBDUM_MASK GENMASK(20, 16)
  112. #define QSPI_IFR_NBDUM(n) (((n) << 16) & QSPI_IFR_NBDUM_MASK)
  113. #define QSPI_IFR_APBTFRTYP_READ BIT(24) /* Defined in SAM9X60 */
  114. /* Bitfields in QSPI_SMR (Scrambling Mode Register) */
  115. #define QSPI_SMR_SCREN BIT(0)
  116. #define QSPI_SMR_RVDIS BIT(1)
  117. /* Bitfields in QSPI_WPMR (Write Protection Mode Register) */
  118. #define QSPI_WPMR_WPEN BIT(0)
  119. #define QSPI_WPMR_WPKEY_MASK GENMASK(31, 8)
  120. #define QSPI_WPMR_WPKEY(wpkey) (((wpkey) << 8) & QSPI_WPMR_WPKEY_MASK)
  121. /* Bitfields in QSPI_WPSR (Write Protection Status Register) */
  122. #define QSPI_WPSR_WPVS BIT(0)
  123. #define QSPI_WPSR_WPVSRC_MASK GENMASK(15, 8)
  124. #define QSPI_WPSR_WPVSRC(src) (((src) << 8) & QSPI_WPSR_WPVSRC)
  125. struct atmel_qspi_caps {
  126. bool has_qspick;
  127. bool has_ricr;
  128. };
  129. struct atmel_qspi {
  130. void __iomem *regs;
  131. void __iomem *mem;
  132. resource_size_t mmap_size;
  133. const struct atmel_qspi_caps *caps;
  134. struct udevice *dev;
  135. ulong bus_clk_rate;
  136. u32 mr;
  137. };
  138. struct atmel_qspi_mode {
  139. u8 cmd_buswidth;
  140. u8 addr_buswidth;
  141. u8 data_buswidth;
  142. u32 config;
  143. };
  144. static const struct atmel_qspi_mode atmel_qspi_modes[] = {
  145. { 1, 1, 1, QSPI_IFR_WIDTH_SINGLE_BIT_SPI },
  146. { 1, 1, 2, QSPI_IFR_WIDTH_DUAL_OUTPUT },
  147. { 1, 1, 4, QSPI_IFR_WIDTH_QUAD_OUTPUT },
  148. { 1, 2, 2, QSPI_IFR_WIDTH_DUAL_IO },
  149. { 1, 4, 4, QSPI_IFR_WIDTH_QUAD_IO },
  150. { 2, 2, 2, QSPI_IFR_WIDTH_DUAL_CMD },
  151. { 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD },
  152. };
  153. #ifdef VERBOSE_DEBUG
  154. static const char *atmel_qspi_reg_name(u32 offset, char *tmp, size_t sz)
  155. {
  156. switch (offset) {
  157. case QSPI_CR:
  158. return "CR";
  159. case QSPI_MR:
  160. return "MR";
  161. case QSPI_RD:
  162. return "MR";
  163. case QSPI_TD:
  164. return "TD";
  165. case QSPI_SR:
  166. return "SR";
  167. case QSPI_IER:
  168. return "IER";
  169. case QSPI_IDR:
  170. return "IDR";
  171. case QSPI_IMR:
  172. return "IMR";
  173. case QSPI_SCR:
  174. return "SCR";
  175. case QSPI_IAR:
  176. return "IAR";
  177. case QSPI_ICR:
  178. return "ICR/WICR";
  179. case QSPI_IFR:
  180. return "IFR";
  181. case QSPI_RICR:
  182. return "RICR";
  183. case QSPI_SMR:
  184. return "SMR";
  185. case QSPI_SKR:
  186. return "SKR";
  187. case QSPI_WPMR:
  188. return "WPMR";
  189. case QSPI_WPSR:
  190. return "WPSR";
  191. case QSPI_VERSION:
  192. return "VERSION";
  193. default:
  194. snprintf(tmp, sz, "0x%02x", offset);
  195. break;
  196. }
  197. return tmp;
  198. }
  199. #endif /* VERBOSE_DEBUG */
  200. static u32 atmel_qspi_read(struct atmel_qspi *aq, u32 offset)
  201. {
  202. u32 value = readl(aq->regs + offset);
  203. #ifdef VERBOSE_DEBUG
  204. char tmp[16];
  205. dev_vdbg(aq->dev, "read 0x%08x from %s\n", value,
  206. atmel_qspi_reg_name(offset, tmp, sizeof(tmp)));
  207. #endif /* VERBOSE_DEBUG */
  208. return value;
  209. }
  210. static void atmel_qspi_write(u32 value, struct atmel_qspi *aq, u32 offset)
  211. {
  212. #ifdef VERBOSE_DEBUG
  213. char tmp[16];
  214. dev_vdbg(aq->dev, "write 0x%08x into %s\n", value,
  215. atmel_qspi_reg_name(offset, tmp, sizeof(tmp)));
  216. #endif /* VERBOSE_DEBUG */
  217. writel(value, aq->regs + offset);
  218. }
  219. static inline bool atmel_qspi_is_compatible(const struct spi_mem_op *op,
  220. const struct atmel_qspi_mode *mode)
  221. {
  222. if (op->cmd.buswidth != mode->cmd_buswidth)
  223. return false;
  224. if (op->addr.nbytes && op->addr.buswidth != mode->addr_buswidth)
  225. return false;
  226. if (op->data.nbytes && op->data.buswidth != mode->data_buswidth)
  227. return false;
  228. return true;
  229. }
  230. static int atmel_qspi_find_mode(const struct spi_mem_op *op)
  231. {
  232. u32 i;
  233. for (i = 0; i < ARRAY_SIZE(atmel_qspi_modes); i++)
  234. if (atmel_qspi_is_compatible(op, &atmel_qspi_modes[i]))
  235. return i;
  236. return -ENOTSUPP;
  237. }
  238. static bool atmel_qspi_supports_op(struct spi_slave *slave,
  239. const struct spi_mem_op *op)
  240. {
  241. if (atmel_qspi_find_mode(op) < 0)
  242. return false;
  243. /* special case not supported by hardware */
  244. if (op->addr.nbytes == 2 && op->cmd.buswidth != op->addr.buswidth &&
  245. op->dummy.nbytes == 0)
  246. return false;
  247. return true;
  248. }
  249. static int atmel_qspi_set_cfg(struct atmel_qspi *aq,
  250. const struct spi_mem_op *op, u32 *offset)
  251. {
  252. u32 iar, icr, ifr;
  253. u32 dummy_cycles = 0;
  254. int mode;
  255. iar = 0;
  256. icr = QSPI_ICR_INST(op->cmd.opcode);
  257. ifr = QSPI_IFR_INSTEN;
  258. mode = atmel_qspi_find_mode(op);
  259. if (mode < 0)
  260. return mode;
  261. ifr |= atmel_qspi_modes[mode].config;
  262. if (op->dummy.buswidth && op->dummy.nbytes)
  263. dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth;
  264. /*
  265. * The controller allows 24 and 32-bit addressing while NAND-flash
  266. * requires 16-bit long. Handling 8-bit long addresses is done using
  267. * the option field. For the 16-bit addresses, the workaround depends
  268. * of the number of requested dummy bits. If there are 8 or more dummy
  269. * cycles, the address is shifted and sent with the first dummy byte.
  270. * Otherwise opcode is disabled and the first byte of the address
  271. * contains the command opcode (works only if the opcode and address
  272. * use the same buswidth). The limitation is when the 16-bit address is
  273. * used without enough dummy cycles and the opcode is using a different
  274. * buswidth than the address.
  275. */
  276. if (op->addr.buswidth) {
  277. switch (op->addr.nbytes) {
  278. case 0:
  279. break;
  280. case 1:
  281. ifr |= QSPI_IFR_OPTEN | QSPI_IFR_OPTL_8BIT;
  282. icr |= QSPI_ICR_OPT(op->addr.val & 0xff);
  283. break;
  284. case 2:
  285. if (dummy_cycles < 8 / op->addr.buswidth) {
  286. ifr &= ~QSPI_IFR_INSTEN;
  287. ifr |= QSPI_IFR_ADDREN;
  288. iar = (op->cmd.opcode << 16) |
  289. (op->addr.val & 0xffff);
  290. } else {
  291. ifr |= QSPI_IFR_ADDREN;
  292. iar = (op->addr.val << 8) & 0xffffff;
  293. dummy_cycles -= 8 / op->addr.buswidth;
  294. }
  295. break;
  296. case 3:
  297. ifr |= QSPI_IFR_ADDREN;
  298. iar = op->addr.val & 0xffffff;
  299. break;
  300. case 4:
  301. ifr |= QSPI_IFR_ADDREN | QSPI_IFR_ADDRL;
  302. iar = op->addr.val & 0x7ffffff;
  303. break;
  304. default:
  305. return -ENOTSUPP;
  306. }
  307. }
  308. /* offset of the data access in the QSPI memory space */
  309. *offset = iar;
  310. /* Set number of dummy cycles */
  311. if (dummy_cycles)
  312. ifr |= QSPI_IFR_NBDUM(dummy_cycles);
  313. /* Set data enable */
  314. if (op->data.nbytes)
  315. ifr |= QSPI_IFR_DATAEN;
  316. /*
  317. * If the QSPI controller is set in regular SPI mode, set it in
  318. * Serial Memory Mode (SMM).
  319. */
  320. if (aq->mr != QSPI_MR_SMM) {
  321. atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR);
  322. aq->mr = QSPI_MR_SMM;
  323. }
  324. /* Clear pending interrupts */
  325. (void)atmel_qspi_read(aq, QSPI_SR);
  326. if (aq->caps->has_ricr) {
  327. if (!op->addr.nbytes && op->data.dir == SPI_MEM_DATA_IN)
  328. ifr |= QSPI_IFR_APBTFRTYP_READ;
  329. /* Set QSPI Instruction Frame registers */
  330. atmel_qspi_write(iar, aq, QSPI_IAR);
  331. if (op->data.dir == SPI_MEM_DATA_IN)
  332. atmel_qspi_write(icr, aq, QSPI_RICR);
  333. else
  334. atmel_qspi_write(icr, aq, QSPI_WICR);
  335. atmel_qspi_write(ifr, aq, QSPI_IFR);
  336. } else {
  337. if (op->data.dir == SPI_MEM_DATA_OUT)
  338. ifr |= QSPI_IFR_SAMA5D2_WRITE_TRSFR;
  339. /* Set QSPI Instruction Frame registers */
  340. atmel_qspi_write(iar, aq, QSPI_IAR);
  341. atmel_qspi_write(icr, aq, QSPI_ICR);
  342. atmel_qspi_write(ifr, aq, QSPI_IFR);
  343. }
  344. return 0;
  345. }
  346. static int atmel_qspi_exec_op(struct spi_slave *slave,
  347. const struct spi_mem_op *op)
  348. {
  349. struct atmel_qspi *aq = dev_get_priv(slave->dev->parent);
  350. u32 sr, imr, offset;
  351. int err;
  352. /*
  353. * Check if the address exceeds the MMIO window size. An improvement
  354. * would be to add support for regular SPI mode and fall back to it
  355. * when the flash memories overrun the controller's memory space.
  356. */
  357. if (op->addr.val + op->data.nbytes > aq->mmap_size)
  358. return -ENOTSUPP;
  359. err = atmel_qspi_set_cfg(aq, op, &offset);
  360. if (err)
  361. return err;
  362. /* Skip to the final steps if there is no data */
  363. if (op->data.nbytes) {
  364. /* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */
  365. (void)atmel_qspi_read(aq, QSPI_IFR);
  366. /* Send/Receive data */
  367. if (op->data.dir == SPI_MEM_DATA_IN)
  368. memcpy_fromio(op->data.buf.in, aq->mem + offset,
  369. op->data.nbytes);
  370. else
  371. memcpy_toio(aq->mem + offset, op->data.buf.out,
  372. op->data.nbytes);
  373. /* Release the chip-select */
  374. atmel_qspi_write(QSPI_CR_LASTXFER, aq, QSPI_CR);
  375. }
  376. /* Poll INSTruction End and Chip Select Rise flags. */
  377. imr = QSPI_SR_INSTRE | QSPI_SR_CSR;
  378. return readl_poll_timeout(aq->regs + QSPI_SR, sr, (sr & imr) == imr,
  379. 1000000);
  380. }
  381. static int atmel_qspi_set_speed(struct udevice *bus, uint hz)
  382. {
  383. struct atmel_qspi *aq = dev_get_priv(bus);
  384. u32 scr, scbr, mask, new_value;
  385. /* Compute the QSPI baudrate */
  386. scbr = DIV_ROUND_UP(aq->bus_clk_rate, hz);
  387. if (scbr > 0)
  388. scbr--;
  389. new_value = QSPI_SCR_SCBR(scbr);
  390. mask = QSPI_SCR_SCBR_MASK;
  391. scr = atmel_qspi_read(aq, QSPI_SCR);
  392. if ((scr & mask) == new_value)
  393. return 0;
  394. scr = (scr & ~mask) | new_value;
  395. atmel_qspi_write(scr, aq, QSPI_SCR);
  396. return 0;
  397. }
  398. static int atmel_qspi_set_mode(struct udevice *bus, uint mode)
  399. {
  400. struct atmel_qspi *aq = dev_get_priv(bus);
  401. u32 scr, mask, new_value = 0;
  402. if (mode & SPI_CPOL)
  403. new_value = QSPI_SCR_CPOL;
  404. if (mode & SPI_CPHA)
  405. new_value = QSPI_SCR_CPHA;
  406. mask = QSPI_SCR_CPOL | QSPI_SCR_CPHA;
  407. scr = atmel_qspi_read(aq, QSPI_SCR);
  408. if ((scr & mask) == new_value)
  409. return 0;
  410. scr = (scr & ~mask) | new_value;
  411. atmel_qspi_write(scr, aq, QSPI_SCR);
  412. return 0;
  413. }
  414. static int atmel_qspi_enable_clk(struct udevice *dev)
  415. {
  416. struct atmel_qspi *aq = dev_get_priv(dev);
  417. struct clk pclk, qspick;
  418. int ret;
  419. ret = clk_get_by_name(dev, "pclk", &pclk);
  420. if (ret)
  421. ret = clk_get_by_index(dev, 0, &pclk);
  422. if (ret) {
  423. dev_err(dev, "Missing QSPI peripheral clock\n");
  424. return ret;
  425. }
  426. ret = clk_enable(&pclk);
  427. if (ret) {
  428. dev_err(dev, "Failed to enable QSPI peripheral clock\n");
  429. goto free_pclk;
  430. }
  431. if (aq->caps->has_qspick) {
  432. /* Get the QSPI system clock */
  433. ret = clk_get_by_name(dev, "qspick", &qspick);
  434. if (ret) {
  435. dev_err(dev, "Missing QSPI peripheral clock\n");
  436. goto free_pclk;
  437. }
  438. ret = clk_enable(&qspick);
  439. if (ret)
  440. dev_err(dev, "Failed to enable QSPI system clock\n");
  441. clk_free(&qspick);
  442. }
  443. aq->bus_clk_rate = clk_get_rate(&pclk);
  444. if (!aq->bus_clk_rate)
  445. ret = -EINVAL;
  446. free_pclk:
  447. clk_free(&pclk);
  448. return ret;
  449. }
  450. static void atmel_qspi_init(struct atmel_qspi *aq)
  451. {
  452. /* Reset the QSPI controller */
  453. atmel_qspi_write(QSPI_CR_SWRST, aq, QSPI_CR);
  454. /* Set the QSPI controller by default in Serial Memory Mode */
  455. atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR);
  456. aq->mr = QSPI_MR_SMM;
  457. /* Enable the QSPI controller */
  458. atmel_qspi_write(QSPI_CR_QSPIEN, aq, QSPI_CR);
  459. }
  460. static int atmel_qspi_probe(struct udevice *dev)
  461. {
  462. struct atmel_qspi *aq = dev_get_priv(dev);
  463. struct resource res;
  464. int ret;
  465. aq->caps = (struct atmel_qspi_caps *)dev_get_driver_data(dev);
  466. if (!aq->caps) {
  467. dev_err(dev, "Could not retrieve QSPI caps\n");
  468. return -EINVAL;
  469. };
  470. /* Map the registers */
  471. ret = dev_read_resource_byname(dev, "qspi_base", &res);
  472. if (ret) {
  473. dev_err(dev, "missing registers\n");
  474. return ret;
  475. }
  476. aq->regs = devm_ioremap(dev, res.start, resource_size(&res));
  477. if (IS_ERR(aq->regs))
  478. return PTR_ERR(aq->regs);
  479. /* Map the AHB memory */
  480. ret = dev_read_resource_byname(dev, "qspi_mmap", &res);
  481. if (ret) {
  482. dev_err(dev, "missing AHB memory\n");
  483. return ret;
  484. }
  485. aq->mem = devm_ioremap(dev, res.start, resource_size(&res));
  486. if (IS_ERR(aq->mem))
  487. return PTR_ERR(aq->mem);
  488. aq->mmap_size = resource_size(&res);
  489. ret = atmel_qspi_enable_clk(dev);
  490. if (ret)
  491. return ret;
  492. aq->dev = dev;
  493. atmel_qspi_init(aq);
  494. return 0;
  495. }
  496. static const struct spi_controller_mem_ops atmel_qspi_mem_ops = {
  497. .supports_op = atmel_qspi_supports_op,
  498. .exec_op = atmel_qspi_exec_op,
  499. };
  500. static const struct dm_spi_ops atmel_qspi_ops = {
  501. .set_speed = atmel_qspi_set_speed,
  502. .set_mode = atmel_qspi_set_mode,
  503. .mem_ops = &atmel_qspi_mem_ops,
  504. };
  505. static const struct atmel_qspi_caps atmel_sama5d2_qspi_caps = {};
  506. static const struct atmel_qspi_caps atmel_sam9x60_qspi_caps = {
  507. .has_qspick = true,
  508. .has_ricr = true,
  509. };
  510. static const struct udevice_id atmel_qspi_ids[] = {
  511. {
  512. .compatible = "atmel,sama5d2-qspi",
  513. .data = (ulong)&atmel_sama5d2_qspi_caps,
  514. },
  515. {
  516. .compatible = "microchip,sam9x60-qspi",
  517. .data = (ulong)&atmel_sam9x60_qspi_caps,
  518. },
  519. { /* sentinel */ }
  520. };
  521. U_BOOT_DRIVER(atmel_qspi) = {
  522. .name = "atmel_qspi",
  523. .id = UCLASS_SPI,
  524. .of_match = atmel_qspi_ids,
  525. .ops = &atmel_qspi_ops,
  526. .priv_auto_alloc_size = sizeof(struct atmel_qspi),
  527. .probe = atmel_qspi_probe,
  528. };