wm8994_registers.h 9.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2012 Samsung Electronics
  4. */
  5. #ifndef __WM8994_REGISTERS_H__
  6. #define __WM8994_REGISTERS_H__
  7. /*
  8. * Register values.
  9. */
  10. #define WM8994_SOFTWARE_RESET 0x00
  11. #define WM8994_POWER_MANAGEMENT_1 0x01
  12. #define WM8994_POWER_MANAGEMENT_2 0x02
  13. #define WM8994_POWER_MANAGEMENT_4 0x04
  14. #define WM8994_POWER_MANAGEMENT_5 0x05
  15. #define WM8994_LEFT_OUTPUT_VOLUME 0x1C
  16. #define WM8994_RIGHT_OUTPUT_VOLUME 0x1D
  17. #define WM8994_OUTPUT_MIXER_1 0x2D
  18. #define WM8994_OUTPUT_MIXER_2 0x2E
  19. #define WM8994_CHARGE_PUMP_1 0x4C
  20. #define WM8994_DC_SERVO_1 0x54
  21. #define WM8994_ANALOGUE_HP_1 0x60
  22. #define WM8994_CHIP_REVISION 0x100
  23. #define WM8994_AIF1_CLOCKING_1 0x200
  24. #define WM8994_AIF1_CLOCKING_2 0x201
  25. #define WM8994_AIF2_CLOCKING_1 0x204
  26. #define WM8994_CLOCKING_1 0x208
  27. #define WM8994_CLOCKING_2 0x209
  28. #define WM8994_AIF1_RATE 0x210
  29. #define WM8994_AIF2_RATE 0x211
  30. #define WM8994_RATE_STATUS 0x212
  31. #define WM8994_AIF1_CONTROL_1 0x300
  32. #define WM8994_AIF1_CONTROL_2 0x301
  33. #define WM8994_AIF1_MASTER_SLAVE 0x302
  34. #define WM8994_AIF1_BCLK 0x303
  35. #define WM8994_AIF2_CONTROL_1 0x310
  36. #define WM8994_AIF2_CONTROL_2 0x311
  37. #define WM8994_AIF2_MASTER_SLAVE 0x312
  38. #define WM8994_AIF2_BCLK 0x313
  39. #define WM8994_AIF1_DAC_FILTERS_1 0x420
  40. #define WM8994_AIF2_DAC_LEFT_VOLUME 0x502
  41. #define WM8994_AIF2_DAC_RIGHT_VOLUME 0x503
  42. #define WM8994_AIF2_DAC_FILTERS_1 0x520
  43. #define WM8994_DAC1_LEFT_MIXER_ROUTING 0x601
  44. #define WM8994_DAC1_RIGHT_MIXER_ROUTING 0x602
  45. #define WM8994_DAC1_LEFT_VOLUME 0x610
  46. #define WM8994_DAC1_RIGHT_VOLUME 0x611
  47. #define WM8994_GPIO_1 0x700
  48. #define WM8994_GPIO_3 0x702
  49. #define WM8994_GPIO_4 0x703
  50. #define WM8994_GPIO_5 0x704
  51. /*
  52. * Field Definitions.
  53. */
  54. /*
  55. * R0 (0x00) - Software Reset
  56. */
  57. /* SW_RESET */
  58. #define WM8994_SW_RESET 1
  59. /*
  60. * R1 (0x01) - Power Management (1)
  61. */
  62. /* HPOUT1L_ENA */
  63. #define WM8994_HPOUT1L_ENA 0x0200
  64. /* HPOUT1L_ENA */
  65. #define WM8994_HPOUT1L_ENA_MASK 0x0200
  66. /* HPOUT1R_ENA */
  67. #define WM8994_HPOUT1R_ENA 0x0100
  68. /* HPOUT1R_ENA */
  69. #define WM8994_HPOUT1R_ENA_MASK 0x0100
  70. /* VMID_SEL - [2:1] */
  71. #define WM8994_VMID_SEL_MASK 0x0006
  72. /* BIAS_ENA */
  73. #define WM8994_BIAS_ENA 0x0001
  74. /* BIAS_ENA */
  75. #define WM8994_BIAS_ENA_MASK 0x0001
  76. /*
  77. * R2 (0x02) - Power Management (2)
  78. */
  79. /* OPCLK_ENA */
  80. #define WM8994_OPCLK_ENA 0x0800
  81. #define WM8994_TSHUT_ENA 0x4000
  82. #define WM8994_MIXINL_ENA 0x0200
  83. #define WM8994_MIXINR_ENA 0x0100
  84. #define WM8994_IN2L_ENA 0x0080
  85. #define WM8994_IN2R_ENA 0x0020
  86. /*
  87. * R5 (0x04) - Power Management (4)
  88. */
  89. #define WM8994_ADCL_ENA 0x0001
  90. #define WM8994_ADCR_ENA 0x0002
  91. #define WM8994_AIF1ADC1R_ENA 0x0100
  92. #define WM8994_AIF1ADC1L_ENA 0x0200
  93. /*
  94. * R5 (0x05) - Power Management (5)
  95. */
  96. /* AIF2DACL_ENA */
  97. #define WM8994_AIF2DACL_ENA 0x2000
  98. #define WM8994_AIF2DACL_ENA_MASK 0x2000
  99. /* AIF2DACR_ENA */
  100. #define WM8994_AIF2DACR_ENA 0x1000
  101. #define WM8994_AIF2DACR_ENA_MASK 0x1000
  102. /* AIF1DACL_ENA */
  103. #define WM8994_AIF1DACL_ENA 0x0200
  104. #define WM8994_AIF1DACL_ENA_MASK 0x0200
  105. /* AIF1DACR_ENA */
  106. #define WM8994_AIF1DACR_ENA 0x0100
  107. #define WM8994_AIF1DACR_ENA_MASK 0x0100
  108. /* DAC1L_ENA */
  109. #define WM8994_DAC1L_ENA 0x0002
  110. #define WM8994_DAC1L_ENA_MASK 0x0002
  111. /* DAC1R_ENA */
  112. #define WM8994_DAC1R_ENA 0x0001
  113. #define WM8994_DAC1R_ENA_MASK 0x0001
  114. /*
  115. * R45 (0x2D) - Output Mixer (1)
  116. */
  117. /* DAC1L_TO_HPOUT1L */
  118. #define WM8994_DAC1L_TO_HPOUT1L 0x0100
  119. #define WM8994_DAC1L_TO_HPOUT1L_MASK 0x0100
  120. /*
  121. * R46 (0x2E) - Output Mixer (2)
  122. */
  123. /* DAC1R_TO_HPOUT1R */
  124. #define WM8994_DAC1R_TO_HPOUT1R 0x0100
  125. #define WM8994_DAC1R_TO_HPOUT1R_MASK 0x0100
  126. /*
  127. * R76 (0x4C) - Charge Pump (1)
  128. */
  129. /* CP_ENA */
  130. #define WM8994_CP_ENA 0x8000
  131. #define WM8994_CP_ENA_MASK 0x8000
  132. /*
  133. * R84 (0x54) - DC Servo (1)
  134. */
  135. /* DCS_ENA_CHAN_1 */
  136. #define WM8994_DCS_ENA_CHAN_1 0x0002
  137. #define WM8994_DCS_ENA_CHAN_1_MASK 0x0002
  138. /* DCS_ENA_CHAN_0 */
  139. #define WM8994_DCS_ENA_CHAN_0 0x0001
  140. #define WM8994_DCS_ENA_CHAN_0_MASK 0x0001
  141. /*
  142. * R96 (0x60) - Analogue HP (1)
  143. */
  144. /* HPOUT1L_RMV_SHORT */
  145. #define WM8994_HPOUT1L_RMV_SHORT 0x0080
  146. #define WM8994_HPOUT1L_RMV_SHORT_MASK 0x0080
  147. /* HPOUT1L_OUTP */
  148. #define WM8994_HPOUT1L_OUTP 0x0040
  149. #define WM8994_HPOUT1L_OUTP_MASK 0x0040
  150. /* HPOUT1L_DLY */
  151. #define WM8994_HPOUT1L_DLY 0x0020
  152. #define WM8994_HPOUT1L_DLY_MASK 0x0020
  153. /* HPOUT1R_RMV_SHORT */
  154. #define WM8994_HPOUT1R_RMV_SHORT 0x0008
  155. #define WM8994_HPOUT1R_RMV_SHORT_MASK 0x0008
  156. /* HPOUT1R_OUTP */
  157. #define WM8994_HPOUT1R_OUTP 0x0004
  158. #define WM8994_HPOUT1R_OUTP_MASK 0x0004
  159. /* HPOUT1R_DLY */
  160. #define WM8994_HPOUT1R_DLY 0x0002
  161. #define WM8994_HPOUT1R_DLY_MASK 0x0002
  162. /*
  163. * R512 (0x200) - AIF1 Clocking (1)
  164. */
  165. /* AIF1CLK_SRC - [4:3] */
  166. #define WM8994_AIF1CLK_SRC_MASK 0x0018
  167. /* AIF1CLK_DIV */
  168. #define WM8994_AIF1CLK_DIV 0x0002
  169. /* AIF1CLK_ENA */
  170. #define WM8994_AIF1CLK_ENA 0x0001
  171. #define WM8994_AIF1CLK_ENA_MASK 0x0001
  172. /*
  173. * R517 (0x205) - AIF2 Clocking (2)
  174. */
  175. /* AIF2DAC_DIV - [5:3] */
  176. #define WM8994_AIF2DAC_DIV_MASK 0x0038
  177. /*
  178. * R520 (0x208) - Clocking (1)
  179. */
  180. /* AIF1DSPCLK_ENA */
  181. #define WM8994_AIF1DSPCLK_ENA 0x0008
  182. #define WM8994_AIF1DSPCLK_ENA_MASK 0x0008
  183. /* AIF2DSPCLK_ENA */
  184. #define WM8994_AIF2DSPCLK_ENA 0x0004
  185. #define WM8994_AIF2DSPCLK_ENA_MASK 0x0004
  186. /* SYSDSPCLK_ENA */
  187. #define WM8994_SYSDSPCLK_ENA 0x0002
  188. #define WM8994_SYSDSPCLK_ENA_MASK 0x0002
  189. /* SYSCLK_SRC */
  190. #define WM8994_SYSCLK_SRC 0x0001
  191. /*
  192. * R521 (0x209) - Clocking (2)
  193. */
  194. /* OPCLK_DIV - [2:0] */
  195. #define WM8994_OPCLK_DIV_MASK 0x0007
  196. /*
  197. * R528 (0x210) - AIF1 Rate
  198. */
  199. /* AIF1_SR - [7:4] */
  200. #define WM8994_AIF1_SR_MASK 0x00F0
  201. #define WM8994_AIF1_SR_SHIFT 4
  202. /* AIF1CLK_RATE - [3:0] */
  203. #define WM8994_AIF1CLK_RATE_MASK 0x000F
  204. /*
  205. * R768 (0x300) - AIF1 Control (1)
  206. */
  207. /* AIF1_BCLK_INV */
  208. #define WM8994_AIF1_BCLK_INV 0x0100
  209. /* AIF1_LRCLK_INV */
  210. #define WM8994_AIF1_LRCLK_INV 0x0080
  211. #define WM8994_AIF1_LRCLK_INV_MASK 0x0080
  212. /* AIF1_WL - [6:5] */
  213. #define WM8994_AIF1_WL_MASK 0x0060
  214. /* AIF1_FMT - [4:3] */
  215. #define WM8994_AIF1_FMT_MASK 0x0018
  216. /*
  217. * R769 (0x301) - AIF1 Control (2)
  218. */
  219. /* AIF1_MONO */
  220. #define WM8994_AIF1_MONO 0x0100
  221. /*
  222. * R770 (0x302) - AIF1 Master/Slave
  223. */
  224. /* AIF1_MSTR */
  225. #define WM8994_AIF1_MSTR 0x4000
  226. #define WM8994_AIF1_MSTR_MASK 0x4000
  227. /*
  228. * R771 (0x303) - AIF1 BCLK
  229. */
  230. /* AIF1_BCLK_DIV - [8:4] */
  231. #define WM8994_AIF1_BCLK_DIV_MASK 0x01F0
  232. #define WM8994_AIF1_BCLK_DIV_SHIFT 4
  233. /*
  234. * R1282 (0x502) - AIF2 DAC Left Volume
  235. */
  236. /* AIF2DAC_VU */
  237. #define WM8994_AIF2DAC_VU 0x0100
  238. #define WM8994_AIF2DAC_VU_MASK 0x0100
  239. /* AIF2DACL_VOL - [7:0] */
  240. #define WM8994_AIF2DACL_VOL_MASK 0x00FF
  241. /*
  242. * R1283 (0x503) - AIF2 DAC Right Volume
  243. */
  244. /* AIF2DACR_VOL - [7:0] */
  245. #define WM8994_AIF2DACR_VOL_MASK 0x00FF
  246. /*
  247. * R1312 (0x520) - AIF2 DAC Filters (1)
  248. */
  249. /* AIF2DAC_MUTE */
  250. #define WM8994_AIF2DAC_MUTE_MASK 0x0200
  251. /*
  252. * R1537 (0x601) - DAC1 Left Mixer Routing
  253. */
  254. /* AIF2DACL_TO_DAC1L */
  255. #define WM8994_AIF2DACL_TO_DAC1L 0x0004
  256. #define WM8994_AIF2DACL_TO_DAC1L_MASK 0x0004
  257. /* AIF1DAC1L_TO_DAC1L */
  258. #define WM8994_AIF1DAC1L_TO_DAC1L 0x0001
  259. /*
  260. * R1538 (0x602) - DAC1 Right Mixer Routing
  261. */
  262. /* AIF2DACR_TO_DAC1R */
  263. #define WM8994_AIF2DACR_TO_DAC1R 0x0004
  264. #define WM8994_AIF2DACR_TO_DAC1R_MASK 0x0004
  265. /* AIF1DAC1R_TO_DAC1R */
  266. #define WM8994_AIF1DAC1R_TO_DAC1R 0x0001
  267. /*
  268. * R1552 (0x610) - DAC1 Left Volume
  269. */
  270. /* DAC1L_MUTE */
  271. #define WM8994_DAC1L_MUTE_MASK 0x0200
  272. /* DAC1_VU */
  273. #define WM8994_DAC1_VU 0x0100
  274. #define WM8994_DAC1_VU_MASK 0x0100
  275. /* DAC1L_VOL - [7:0] */
  276. #define WM8994_DAC1L_VOL_MASK 0x00FF
  277. /*
  278. * R1553 (0x611) - DAC1 Right Volume
  279. */
  280. /* DAC1R_MUTE */
  281. #define WM8994_DAC1R_MUTE_MASK 0x0200
  282. /* DAC1R_VOL - [7:0] */
  283. #define WM8994_DAC1R_VOL_MASK 0x00FF
  284. /*
  285. * GPIO
  286. */
  287. /* OUTPUT PIN */
  288. #define WM8994_GPIO_DIR_OUTPUT 0x8000
  289. /* GPIO PIN MASK */
  290. #define WM8994_GPIO_DIR_MASK 0xFFE0
  291. /* I2S CLK */
  292. #define WM8994_GPIO_FUNCTION_I2S_CLK 0x0001
  293. #define WM8994_GPIO_INPUT_DEBOUNCE 0x0100
  294. /* GPn FN */
  295. #define WM8994_GPIO_FUNCTION_MASK 0x001F
  296. #endif