rt5677.h 50 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * rt5677.h -- RealTek ALC5677 ALSA SoC Audio driver
  4. *
  5. * Copyright 2013 Realtek Semiconductor Corp.
  6. * Author: Oder Chiou <oder_chiou@realtek.com>
  7. *
  8. * Based on the file by the same name in Chromium OS dc
  9. */
  10. #ifndef __DRIVERS_SOUND_RT5677_H__
  11. #define __DRIVERS_SOUND_RT5677_H__
  12. /*
  13. * RT5677 Registers Definition
  14. */
  15. /* Info */
  16. #define RT5677_RESET 0x00
  17. #define RT5677_VENDOR_ID 0xfd
  18. #define RT5677_VENDOR_ID1 0xfe
  19. #define RT5677_VENDOR_ID2 0xff
  20. #define RT5677_REG_CNT (RT5677_VENDOR_ID2 + 1)
  21. #define RT5677_PR_REG_CNT 255
  22. /* I/O - Output */
  23. #define RT5677_LOUT1 0x01
  24. /* I/O - Input */
  25. #define RT5677_IN1 0x03
  26. #define RT5677_MICBIAS 0x04
  27. /* I/O - SLIMBus */
  28. #define RT5677_SLIMBUS_PARAM 0x07
  29. #define RT5677_SLIMBUS_RX 0x08
  30. #define RT5677_SLIMBUS_CTRL 0x09
  31. /* I/O */
  32. #define RT5677_SIDETONE_CTRL 0x13
  33. /* I/O - ADC/DAC */
  34. #define RT5677_ANA_DAC1_2_3_SRC 0x15
  35. #define RT5677_IF_DSP_DAC3_4_MIXER 0x16
  36. #define RT5677_DAC4_DIG_VOL 0x17
  37. #define RT5677_DAC3_DIG_VOL 0x18
  38. #define RT5677_DAC1_DIG_VOL 0x19
  39. #define RT5677_DAC2_DIG_VOL 0x1a
  40. #define RT5677_IF_DSP_DAC2_MIXER 0x1b
  41. #define RT5677_STO1_ADC_DIG_VOL 0x1c
  42. #define RT5677_MONO_ADC_DIG_VOL 0x1d
  43. #define RT5677_STO1_2_ADC_BST 0x1e
  44. #define RT5677_STO2_ADC_DIG_VOL 0x1f
  45. /* Mixer - D-D */
  46. #define RT5677_ADC_BST_CTRL2 0x20
  47. #define RT5677_STO3_4_ADC_BST 0x21
  48. #define RT5677_STO3_ADC_DIG_VOL 0x22
  49. #define RT5677_STO4_ADC_DIG_VOL 0x23
  50. #define RT5677_STO4_ADC_MIXER 0x24
  51. #define RT5677_STO3_ADC_MIXER 0x25
  52. #define RT5677_STO2_ADC_MIXER 0x26
  53. #define RT5677_STO1_ADC_MIXER 0x27
  54. #define RT5677_MONO_ADC_MIXER 0x28
  55. #define RT5677_ADC_IF_DSP_DAC1_MIXER 0x29
  56. #define RT5677_STO1_DAC_MIXER 0x2a
  57. #define RT5677_MONO_DAC_MIXER 0x2b
  58. #define RT5677_DD1_MIXER 0x2c
  59. #define RT5677_DD2_MIXER 0x2d
  60. #define RT5677_IF3_DATA 0x2f
  61. #define RT5677_IF4_DATA 0x30
  62. /* Mixer - PDM */
  63. #define RT5677_PDM_OUT_CTRL 0x31
  64. #define RT5677_PDM_DATA_CTRL1 0x32
  65. #define RT5677_PDM_DATA_CTRL2 0x33
  66. #define RT5677_PDM1_DATA_CTRL2 0x34
  67. #define RT5677_PDM1_DATA_CTRL3 0x35
  68. #define RT5677_PDM1_DATA_CTRL4 0x36
  69. #define RT5677_PDM2_DATA_CTRL2 0x37
  70. #define RT5677_PDM2_DATA_CTRL3 0x38
  71. #define RT5677_PDM2_DATA_CTRL4 0x39
  72. /* TDM */
  73. #define RT5677_TDM1_CTRL1 0x3b
  74. #define RT5677_TDM1_CTRL2 0x3c
  75. #define RT5677_TDM1_CTRL3 0x3d
  76. #define RT5677_TDM1_CTRL4 0x3e
  77. #define RT5677_TDM1_CTRL5 0x3f
  78. #define RT5677_TDM2_CTRL1 0x40
  79. #define RT5677_TDM2_CTRL2 0x41
  80. #define RT5677_TDM2_CTRL3 0x42
  81. #define RT5677_TDM2_CTRL4 0x43
  82. #define RT5677_TDM2_CTRL5 0x44
  83. /* I2C_MASTER_CTRL */
  84. #define RT5677_I2C_MASTER_CTRL1 0x47
  85. #define RT5677_I2C_MASTER_CTRL2 0x48
  86. #define RT5677_I2C_MASTER_CTRL3 0x49
  87. #define RT5677_I2C_MASTER_CTRL4 0x4a
  88. #define RT5677_I2C_MASTER_CTRL5 0x4b
  89. #define RT5677_I2C_MASTER_CTRL6 0x4c
  90. #define RT5677_I2C_MASTER_CTRL7 0x4d
  91. #define RT5677_I2C_MASTER_CTRL8 0x4e
  92. /* DMIC */
  93. #define RT5677_DMIC_CTRL1 0x50
  94. #define RT5677_DMIC_CTRL2 0x51
  95. /* Haptic Generator */
  96. #define RT5677_HAP_GENE_CTRL1 0x56
  97. #define RT5677_HAP_GENE_CTRL2 0x57
  98. #define RT5677_HAP_GENE_CTRL3 0x58
  99. #define RT5677_HAP_GENE_CTRL4 0x59
  100. #define RT5677_HAP_GENE_CTRL5 0x5a
  101. #define RT5677_HAP_GENE_CTRL6 0x5b
  102. #define RT5677_HAP_GENE_CTRL7 0x5c
  103. #define RT5677_HAP_GENE_CTRL8 0x5d
  104. #define RT5677_HAP_GENE_CTRL9 0x5e
  105. #define RT5677_HAP_GENE_CTRL10 0x5f
  106. /* Power */
  107. #define RT5677_PWR_DIG1 0x61
  108. #define RT5677_PWR_DIG2 0x62
  109. #define RT5677_PWR_ANLG1 0x63
  110. #define RT5677_PWR_ANLG2 0x64
  111. #define RT5677_PWR_DSP1 0x65
  112. #define RT5677_PWR_DSP_ST 0x66
  113. #define RT5677_PWR_DSP2 0x67
  114. #define RT5677_ADC_DAC_HPF_CTRL1 0x68
  115. /* Private Register Control */
  116. #define RT5677_PRIV_INDEX 0x6a
  117. #define RT5677_PRIV_DATA 0x6c
  118. /* Format - ADC/DAC */
  119. #define RT5677_I2S4_SDP 0x6f
  120. #define RT5677_I2S1_SDP 0x70
  121. #define RT5677_I2S2_SDP 0x71
  122. #define RT5677_I2S3_SDP 0x72
  123. #define RT5677_CLK_TREE_CTRL1 0x73
  124. #define RT5677_CLK_TREE_CTRL2 0x74
  125. #define RT5677_CLK_TREE_CTRL3 0x75
  126. /* Function - Analog */
  127. #define RT5677_PLL1_CTRL1 0x7a
  128. #define RT5677_PLL1_CTRL2 0x7b
  129. #define RT5677_PLL2_CTRL1 0x7c
  130. #define RT5677_PLL2_CTRL2 0x7d
  131. #define RT5677_GLB_CLK1 0x80
  132. #define RT5677_GLB_CLK2 0x81
  133. #define RT5677_ASRC_1 0x83
  134. #define RT5677_ASRC_2 0x84
  135. #define RT5677_ASRC_3 0x85
  136. #define RT5677_ASRC_4 0x86
  137. #define RT5677_ASRC_5 0x87
  138. #define RT5677_ASRC_6 0x88
  139. #define RT5677_ASRC_7 0x89
  140. #define RT5677_ASRC_8 0x8a
  141. #define RT5677_ASRC_9 0x8b
  142. #define RT5677_ASRC_10 0x8c
  143. #define RT5677_ASRC_11 0x8d
  144. #define RT5677_ASRC_12 0x8e
  145. #define RT5677_ASRC_13 0x8f
  146. #define RT5677_ASRC_14 0x90
  147. #define RT5677_ASRC_15 0x91
  148. #define RT5677_ASRC_16 0x92
  149. #define RT5677_ASRC_17 0x93
  150. #define RT5677_ASRC_18 0x94
  151. #define RT5677_ASRC_19 0x95
  152. #define RT5677_ASRC_20 0x97
  153. #define RT5677_ASRC_21 0x98
  154. #define RT5677_ASRC_22 0x99
  155. #define RT5677_ASRC_23 0x9a
  156. #define RT5677_VAD_CTRL1 0x9c
  157. #define RT5677_VAD_CTRL2 0x9d
  158. #define RT5677_VAD_CTRL3 0x9e
  159. #define RT5677_VAD_CTRL4 0x9f
  160. #define RT5677_VAD_CTRL5 0xa0
  161. /* Function - Digital */
  162. #define RT5677_DSP_INB_CTRL1 0xa3
  163. #define RT5677_DSP_INB_CTRL2 0xa4
  164. #define RT5677_DSP_IN_OUTB_CTRL 0xa5
  165. #define RT5677_DSP_OUTB0_1_DIG_VOL 0xa6
  166. #define RT5677_DSP_OUTB2_3_DIG_VOL 0xa7
  167. #define RT5677_DSP_OUTB4_5_DIG_VOL 0xa8
  168. #define RT5677_DSP_OUTB6_7_DIG_VOL 0xa9
  169. #define RT5677_ADC_EQ_CTRL1 0xae
  170. #define RT5677_ADC_EQ_CTRL2 0xaf
  171. #define RT5677_EQ_CTRL1 0xb0
  172. #define RT5677_EQ_CTRL2 0xb1
  173. #define RT5677_EQ_CTRL3 0xb2
  174. #define RT5677_SOFT_VOL_ZERO_CROSS1 0xb3
  175. #define RT5677_JD_CTRL1 0xb5
  176. #define RT5677_JD_CTRL2 0xb6
  177. #define RT5677_JD_CTRL3 0xb8
  178. #define RT5677_IRQ_CTRL1 0xbd
  179. #define RT5677_IRQ_CTRL2 0xbe
  180. #define RT5677_GPIO_ST 0xbf
  181. #define RT5677_GPIO_CTRL1 0xc0
  182. #define RT5677_GPIO_CTRL2 0xc1
  183. #define RT5677_GPIO_CTRL3 0xc2
  184. #define RT5677_STO1_ADC_HI_FILTER1 0xc5
  185. #define RT5677_STO1_ADC_HI_FILTER2 0xc6
  186. #define RT5677_MONO_ADC_HI_FILTER1 0xc7
  187. #define RT5677_MONO_ADC_HI_FILTER2 0xc8
  188. #define RT5677_STO2_ADC_HI_FILTER1 0xc9
  189. #define RT5677_STO2_ADC_HI_FILTER2 0xca
  190. #define RT5677_STO3_ADC_HI_FILTER1 0xcb
  191. #define RT5677_STO3_ADC_HI_FILTER2 0xcc
  192. #define RT5677_STO4_ADC_HI_FILTER1 0xcd
  193. #define RT5677_STO4_ADC_HI_FILTER2 0xce
  194. #define RT5677_MB_DRC_CTRL1 0xd0
  195. #define RT5677_DRC1_CTRL1 0xd2
  196. #define RT5677_DRC1_CTRL2 0xd3
  197. #define RT5677_DRC1_CTRL3 0xd4
  198. #define RT5677_DRC1_CTRL4 0xd5
  199. #define RT5677_DRC1_CTRL5 0xd6
  200. #define RT5677_DRC1_CTRL6 0xd7
  201. #define RT5677_DRC2_CTRL1 0xd8
  202. #define RT5677_DRC2_CTRL2 0xd9
  203. #define RT5677_DRC2_CTRL3 0xda
  204. #define RT5677_DRC2_CTRL4 0xdb
  205. #define RT5677_DRC2_CTRL5 0xdc
  206. #define RT5677_DRC2_CTRL6 0xdd
  207. #define RT5677_DRC1_HL_CTRL1 0xde
  208. #define RT5677_DRC1_HL_CTRL2 0xdf
  209. #define RT5677_DRC2_HL_CTRL1 0xe0
  210. #define RT5677_DRC2_HL_CTRL2 0xe1
  211. #define RT5677_DSP_INB1_SRC_CTRL1 0xe3
  212. #define RT5677_DSP_INB1_SRC_CTRL2 0xe4
  213. #define RT5677_DSP_INB1_SRC_CTRL3 0xe5
  214. #define RT5677_DSP_INB1_SRC_CTRL4 0xe6
  215. #define RT5677_DSP_INB2_SRC_CTRL1 0xe7
  216. #define RT5677_DSP_INB2_SRC_CTRL2 0xe8
  217. #define RT5677_DSP_INB2_SRC_CTRL3 0xe9
  218. #define RT5677_DSP_INB2_SRC_CTRL4 0xea
  219. #define RT5677_DSP_INB3_SRC_CTRL1 0xeb
  220. #define RT5677_DSP_INB3_SRC_CTRL2 0xec
  221. #define RT5677_DSP_INB3_SRC_CTRL3 0xed
  222. #define RT5677_DSP_INB3_SRC_CTRL4 0xee
  223. #define RT5677_DSP_OUTB1_SRC_CTRL1 0xef
  224. #define RT5677_DSP_OUTB1_SRC_CTRL2 0xf0
  225. #define RT5677_DSP_OUTB1_SRC_CTRL3 0xf1
  226. #define RT5677_DSP_OUTB1_SRC_CTRL4 0xf2
  227. #define RT5677_DSP_OUTB2_SRC_CTRL1 0xf3
  228. #define RT5677_DSP_OUTB2_SRC_CTRL2 0xf4
  229. #define RT5677_DSP_OUTB2_SRC_CTRL3 0xf5
  230. #define RT5677_DSP_OUTB2_SRC_CTRL4 0xf6
  231. /* Virtual DSP Mixer Control */
  232. #define RT5677_DSP_OUTB_0123_MIXER_CTRL 0xf7
  233. #define RT5677_DSP_OUTB_45_MIXER_CTRL 0xf8
  234. #define RT5677_DSP_OUTB_67_MIXER_CTRL 0xf9
  235. /* General Control */
  236. #define RT5677_DIG_MISC 0xfa
  237. #define RT5677_GEN_CTRL1 0xfb
  238. #define RT5677_GEN_CTRL2 0xfc
  239. /* DSP Mode I2C Control*/
  240. #define RT5677_DSP_I2C_OP_CODE 0x00
  241. #define RT5677_DSP_I2C_ADDR_LSB 0x01
  242. #define RT5677_DSP_I2C_ADDR_MSB 0x02
  243. #define RT5677_DSP_I2C_DATA_LSB 0x03
  244. #define RT5677_DSP_I2C_DATA_MSB 0x04
  245. /* Index of Codec Private Register definition */
  246. #define RT5677_PR_DRC1_CTRL_1 0x01
  247. #define RT5677_PR_DRC1_CTRL_2 0x02
  248. #define RT5677_PR_DRC1_CTRL_3 0x03
  249. #define RT5677_PR_DRC1_CTRL_4 0x04
  250. #define RT5677_PR_DRC1_CTRL_5 0x05
  251. #define RT5677_PR_DRC1_CTRL_6 0x06
  252. #define RT5677_PR_DRC1_CTRL_7 0x07
  253. #define RT5677_PR_DRC2_CTRL_1 0x08
  254. #define RT5677_PR_DRC2_CTRL_2 0x09
  255. #define RT5677_PR_DRC2_CTRL_3 0x0a
  256. #define RT5677_PR_DRC2_CTRL_4 0x0b
  257. #define RT5677_PR_DRC2_CTRL_5 0x0c
  258. #define RT5677_PR_DRC2_CTRL_6 0x0d
  259. #define RT5677_PR_DRC2_CTRL_7 0x0e
  260. #define RT5677_BIAS_CUR1 0x10
  261. #define RT5677_BIAS_CUR2 0x12
  262. #define RT5677_BIAS_CUR3 0x13
  263. #define RT5677_BIAS_CUR4 0x14
  264. #define RT5677_BIAS_CUR5 0x15
  265. #define RT5677_VREF_LOUT_CTRL 0x17
  266. #define RT5677_DIG_VOL_CTRL1 0x1a
  267. #define RT5677_DIG_VOL_CTRL2 0x1b
  268. #define RT5677_ANA_ADC_GAIN_CTRL 0x1e
  269. #define RT5677_VAD_SRAM_TEST1 0x20
  270. #define RT5677_VAD_SRAM_TEST2 0x21
  271. #define RT5677_VAD_SRAM_TEST3 0x22
  272. #define RT5677_VAD_SRAM_TEST4 0x23
  273. #define RT5677_PAD_DRV_CTRL 0x26
  274. #define RT5677_DIG_IN_PIN_ST_CTRL1 0x29
  275. #define RT5677_DIG_IN_PIN_ST_CTRL2 0x2a
  276. #define RT5677_DIG_IN_PIN_ST_CTRL3 0x2b
  277. #define RT5677_PLL1_INT 0x38
  278. #define RT5677_PLL2_INT 0x39
  279. #define RT5677_TEST_CTRL1 0x3a
  280. #define RT5677_TEST_CTRL2 0x3b
  281. #define RT5677_TEST_CTRL3 0x3c
  282. #define RT5677_CHOP_DAC_ADC 0x3d
  283. #define RT5677_SOFT_DEPOP_DAC_CLK_CTRL 0x3e
  284. #define RT5677_CROSS_OVER_FILTER1 0x90
  285. #define RT5677_CROSS_OVER_FILTER2 0x91
  286. #define RT5677_CROSS_OVER_FILTER3 0x92
  287. #define RT5677_CROSS_OVER_FILTER4 0x93
  288. #define RT5677_CROSS_OVER_FILTER5 0x94
  289. #define RT5677_CROSS_OVER_FILTER6 0x95
  290. #define RT5677_CROSS_OVER_FILTER7 0x96
  291. #define RT5677_CROSS_OVER_FILTER8 0x97
  292. #define RT5677_CROSS_OVER_FILTER9 0x98
  293. #define RT5677_CROSS_OVER_FILTER10 0x99
  294. /* global definition */
  295. #define RT5677_L_MUTE (0x1 << 15)
  296. #define RT5677_L_MUTE_SFT 15
  297. #define RT5677_VOL_L_MUTE (0x1 << 14)
  298. #define RT5677_VOL_L_SFT 14
  299. #define RT5677_R_MUTE (0x1 << 7)
  300. #define RT5677_R_MUTE_SFT 7
  301. #define RT5677_VOL_R_MUTE (0x1 << 6)
  302. #define RT5677_VOL_R_SFT 6
  303. #define RT5677_L_VOL_MASK (0x3f << 8)
  304. #define RT5677_L_VOL_SFT 8
  305. #define RT5677_R_VOL_MASK (0x3f)
  306. #define RT5677_R_VOL_SFT 0
  307. /* LOUT1 Control (0x01) */
  308. #define RT5677_LOUT1_L_MUTE (0x1 << 15)
  309. #define RT5677_LOUT1_L_MUTE_SFT (15)
  310. #define RT5677_LOUT1_L_DF (0x1 << 14)
  311. #define RT5677_LOUT1_L_DF_SFT (14)
  312. #define RT5677_LOUT2_L_MUTE (0x1 << 13)
  313. #define RT5677_LOUT2_L_MUTE_SFT (13)
  314. #define RT5677_LOUT2_L_DF (0x1 << 12)
  315. #define RT5677_LOUT2_L_DF_SFT (12)
  316. #define RT5677_LOUT3_L_MUTE (0x1 << 11)
  317. #define RT5677_LOUT3_L_MUTE_SFT (11)
  318. #define RT5677_LOUT3_L_DF (0x1 << 10)
  319. #define RT5677_LOUT3_L_DF_SFT (10)
  320. #define RT5677_LOUT1_ENH_DRV (0x1 << 9)
  321. #define RT5677_LOUT1_ENH_DRV_SFT (9)
  322. #define RT5677_LOUT2_ENH_DRV (0x1 << 8)
  323. #define RT5677_LOUT2_ENH_DRV_SFT (8)
  324. #define RT5677_LOUT3_ENH_DRV (0x1 << 7)
  325. #define RT5677_LOUT3_ENH_DRV_SFT (7)
  326. /* IN1 Control (0x03) */
  327. #define RT5677_BST_MASK1 (0xf << 12)
  328. #define RT5677_BST_SFT1 12
  329. #define RT5677_BST_MASK2 (0xf << 8)
  330. #define RT5677_BST_SFT2 8
  331. #define RT5677_IN_DF1 (0x1 << 7)
  332. #define RT5677_IN_DF1_SFT 7
  333. #define RT5677_IN_DF2 (0x1 << 6)
  334. #define RT5677_IN_DF2_SFT 6
  335. /* Micbias Control (0x04) */
  336. #define RT5677_MICBIAS1_OUTVOLT_MASK (0x1 << 15)
  337. #define RT5677_MICBIAS1_OUTVOLT_SFT (15)
  338. #define RT5677_MICBIAS1_OUTVOLT_2_7V (0x0 << 15)
  339. #define RT5677_MICBIAS1_OUTVOLT_2_25V (0x1 << 15)
  340. #define RT5677_MICBIAS1_CTRL_VDD_MASK (0x1 << 14)
  341. #define RT5677_MICBIAS1_CTRL_VDD_SFT (14)
  342. #define RT5677_MICBIAS1_CTRL_VDD_1_8V (0x0 << 14)
  343. #define RT5677_MICBIAS1_CTRL_VDD_3_3V (0x1 << 14)
  344. #define RT5677_MICBIAS1_OVCD_MASK (0x1 << 11)
  345. #define RT5677_MICBIAS1_OVCD_SHIFT (11)
  346. #define RT5677_MICBIAS1_OVCD_DIS (0x0 << 11)
  347. #define RT5677_MICBIAS1_OVCD_EN (0x1 << 11)
  348. #define RT5677_MICBIAS1_OVTH_MASK (0x3 << 9)
  349. #define RT5677_MICBIAS1_OVTH_SFT 9
  350. #define RT5677_MICBIAS1_OVTH_640UA (0x0 << 9)
  351. #define RT5677_MICBIAS1_OVTH_1280UA (0x1 << 9)
  352. #define RT5677_MICBIAS1_OVTH_1920UA (0x2 << 9)
  353. /* SLIMbus Parameter (0x07) */
  354. /* SLIMbus Rx (0x08) */
  355. #define RT5677_SLB_ADC4_MASK (0x3 << 6)
  356. #define RT5677_SLB_ADC4_SFT 6
  357. #define RT5677_SLB_ADC3_MASK (0x3 << 4)
  358. #define RT5677_SLB_ADC3_SFT 4
  359. #define RT5677_SLB_ADC2_MASK (0x3 << 2)
  360. #define RT5677_SLB_ADC2_SFT 2
  361. #define RT5677_SLB_ADC1_MASK (0x3 << 0)
  362. #define RT5677_SLB_ADC1_SFT 0
  363. /* SLIMBus control (0x09) */
  364. /* Sidetone Control (0x13) */
  365. #define RT5677_ST_HPF_SEL_MASK (0x7 << 13)
  366. #define RT5677_ST_HPF_SEL_SFT 13
  367. #define RT5677_ST_HPF_PATH (0x1 << 12)
  368. #define RT5677_ST_HPF_PATH_SFT 12
  369. #define RT5677_ST_SEL_MASK (0x7 << 9)
  370. #define RT5677_ST_SEL_SFT 9
  371. #define RT5677_ST_EN (0x1 << 6)
  372. #define RT5677_ST_EN_SFT 6
  373. /* Analog DAC1/2/3 Source Control (0x15) */
  374. #define RT5677_ANA_DAC3_SRC_SEL_MASK (0x3 << 4)
  375. #define RT5677_ANA_DAC3_SRC_SEL_SFT 4
  376. #define RT5677_ANA_DAC1_2_SRC_SEL_MASK (0x3 << 0)
  377. #define RT5677_ANA_DAC1_2_SRC_SEL_SFT 0
  378. /* IF/DSP to DAC3/4 Mixer Control (0x16) */
  379. #define RT5677_M_DAC4_L_VOL (0x1 << 15)
  380. #define RT5677_M_DAC4_L_VOL_SFT 15
  381. #define RT5677_SEL_DAC4_L_SRC_MASK (0x7 << 12)
  382. #define RT5677_SEL_DAC4_L_SRC_SFT 12
  383. #define RT5677_M_DAC4_R_VOL (0x1 << 11)
  384. #define RT5677_M_DAC4_R_VOL_SFT 11
  385. #define RT5677_SEL_DAC4_R_SRC_MASK (0x7 << 8)
  386. #define RT5677_SEL_DAC4_R_SRC_SFT 8
  387. #define RT5677_M_DAC3_L_VOL (0x1 << 7)
  388. #define RT5677_M_DAC3_L_VOL_SFT 7
  389. #define RT5677_SEL_DAC3_L_SRC_MASK (0x7 << 4)
  390. #define RT5677_SEL_DAC3_L_SRC_SFT 4
  391. #define RT5677_M_DAC3_R_VOL (0x1 << 3)
  392. #define RT5677_M_DAC3_R_VOL_SFT 3
  393. #define RT5677_SEL_DAC3_R_SRC_MASK (0x7 << 0)
  394. #define RT5677_SEL_DAC3_R_SRC_SFT 0
  395. /* DAC4 Digital Volume (0x17) */
  396. #define RT5677_DAC4_L_VOL_MASK (0xff << 8)
  397. #define RT5677_DAC4_L_VOL_SFT 8
  398. #define RT5677_DAC4_R_VOL_MASK (0xff)
  399. #define RT5677_DAC4_R_VOL_SFT 0
  400. /* DAC3 Digital Volume (0x18) */
  401. #define RT5677_DAC3_L_VOL_MASK (0xff << 8)
  402. #define RT5677_DAC3_L_VOL_SFT 8
  403. #define RT5677_DAC3_R_VOL_MASK (0xff)
  404. #define RT5677_DAC3_R_VOL_SFT 0
  405. /* DAC3 Digital Volume (0x19) */
  406. #define RT5677_DAC1_L_VOL_MASK (0xff << 8)
  407. #define RT5677_DAC1_L_VOL_SFT 8
  408. #define RT5677_DAC1_R_VOL_MASK (0xff)
  409. #define RT5677_DAC1_R_VOL_SFT 0
  410. /* DAC2 Digital Volume (0x1a) */
  411. #define RT5677_DAC2_L_VOL_MASK (0xff << 8)
  412. #define RT5677_DAC2_L_VOL_SFT 8
  413. #define RT5677_DAC2_R_VOL_MASK (0xff)
  414. #define RT5677_DAC2_R_VOL_SFT 0
  415. /* IF/DSP to DAC2 Mixer Control (0x1b) */
  416. #define RT5677_M_DAC2_L_VOL (0x1 << 7)
  417. #define RT5677_M_DAC2_L_VOL_SFT 7
  418. #define RT5677_SEL_DAC2_L_SRC_MASK (0x7 << 4)
  419. #define RT5677_SEL_DAC2_L_SRC_SFT 4
  420. #define RT5677_M_DAC2_R_VOL (0x1 << 3)
  421. #define RT5677_M_DAC2_R_VOL_SFT 3
  422. #define RT5677_SEL_DAC2_R_SRC_MASK (0x7 << 0)
  423. #define RT5677_SEL_DAC2_R_SRC_SFT 0
  424. /* Stereo1 ADC Digital Volume Control (0x1c) */
  425. #define RT5677_STO1_ADC_L_VOL_MASK (0x7f << 8)
  426. #define RT5677_STO1_ADC_L_VOL_SFT 8
  427. #define RT5677_STO1_ADC_R_VOL_MASK (0x7f)
  428. #define RT5677_STO1_ADC_R_VOL_SFT 0
  429. /* Mono ADC Digital Volume Control (0x1d) */
  430. #define RT5677_MONO_ADC_L_VOL_MASK (0x7f << 8)
  431. #define RT5677_MONO_ADC_L_VOL_SFT 8
  432. #define RT5677_MONO_ADC_R_VOL_MASK (0x7f)
  433. #define RT5677_MONO_ADC_R_VOL_SFT 0
  434. /* Stereo 1/2 ADC Boost Gain Control (0x1e) */
  435. #define RT5677_STO1_ADC_L_BST_MASK (0x3 << 14)
  436. #define RT5677_STO1_ADC_L_BST_SFT 14
  437. #define RT5677_STO1_ADC_R_BST_MASK (0x3 << 12)
  438. #define RT5677_STO1_ADC_R_BST_SFT 12
  439. #define RT5677_STO1_ADC_COMP_MASK (0x3 << 10)
  440. #define RT5677_STO1_ADC_COMP_SFT 10
  441. #define RT5677_STO2_ADC_L_BST_MASK (0x3 << 8)
  442. #define RT5677_STO2_ADC_L_BST_SFT 8
  443. #define RT5677_STO2_ADC_R_BST_MASK (0x3 << 6)
  444. #define RT5677_STO2_ADC_R_BST_SFT 6
  445. #define RT5677_STO2_ADC_COMP_MASK (0x3 << 4)
  446. #define RT5677_STO2_ADC_COMP_SFT 4
  447. /* Stereo2 ADC Digital Volume Control (0x1f) */
  448. #define RT5677_STO2_ADC_L_VOL_MASK (0x7f << 8)
  449. #define RT5677_STO2_ADC_L_VOL_SFT 8
  450. #define RT5677_STO2_ADC_R_VOL_MASK (0x7f)
  451. #define RT5677_STO2_ADC_R_VOL_SFT 0
  452. /* ADC Boost Gain Control 2 (0x20) */
  453. #define RT5677_MONO_ADC_L_BST_MASK (0x3 << 14)
  454. #define RT5677_MONO_ADC_L_BST_SFT 14
  455. #define RT5677_MONO_ADC_R_BST_MASK (0x3 << 12)
  456. #define RT5677_MONO_ADC_R_BST_SFT 12
  457. #define RT5677_MONO_ADC_COMP_MASK (0x3 << 10)
  458. #define RT5677_MONO_ADC_COMP_SFT 10
  459. /* Stereo 3/4 ADC Boost Gain Control (0x21) */
  460. #define RT5677_STO3_ADC_L_BST_MASK (0x3 << 14)
  461. #define RT5677_STO3_ADC_L_BST_SFT 14
  462. #define RT5677_STO3_ADC_R_BST_MASK (0x3 << 12)
  463. #define RT5677_STO3_ADC_R_BST_SFT 12
  464. #define RT5677_STO3_ADC_COMP_MASK (0x3 << 10)
  465. #define RT5677_STO3_ADC_COMP_SFT 10
  466. #define RT5677_STO4_ADC_L_BST_MASK (0x3 << 8)
  467. #define RT5677_STO4_ADC_L_BST_SFT 8
  468. #define RT5677_STO4_ADC_R_BST_MASK (0x3 << 6)
  469. #define RT5677_STO4_ADC_R_BST_SFT 6
  470. #define RT5677_STO4_ADC_COMP_MASK (0x3 << 4)
  471. #define RT5677_STO4_ADC_COMP_SFT 4
  472. /* Stereo3 ADC Digital Volume Control (0x22) */
  473. #define RT5677_STO3_ADC_L_VOL_MASK (0x7f << 8)
  474. #define RT5677_STO3_ADC_L_VOL_SFT 8
  475. #define RT5677_STO3_ADC_R_VOL_MASK (0x7f)
  476. #define RT5677_STO3_ADC_R_VOL_SFT 0
  477. /* Stereo4 ADC Digital Volume Control (0x23) */
  478. #define RT5677_STO4_ADC_L_VOL_MASK (0x7f << 8)
  479. #define RT5677_STO4_ADC_L_VOL_SFT 8
  480. #define RT5677_STO4_ADC_R_VOL_MASK (0x7f)
  481. #define RT5677_STO4_ADC_R_VOL_SFT 0
  482. /* Stereo4 ADC Mixer control (0x24) */
  483. #define RT5677_M_STO4_ADC_L2 (0x1 << 15)
  484. #define RT5677_M_STO4_ADC_L2_SFT 15
  485. #define RT5677_M_STO4_ADC_L1 (0x1 << 14)
  486. #define RT5677_M_STO4_ADC_L1_SFT 14
  487. #define RT5677_SEL_STO4_ADC1_MASK (0x3 << 12)
  488. #define RT5677_SEL_STO4_ADC1_SFT 12
  489. #define RT5677_SEL_STO4_ADC2_MASK (0x3 << 10)
  490. #define RT5677_SEL_STO4_ADC2_SFT 10
  491. #define RT5677_SEL_STO4_DMIC_MASK (0x3 << 8)
  492. #define RT5677_SEL_STO4_DMIC_SFT 8
  493. #define RT5677_M_STO4_ADC_R1 (0x1 << 7)
  494. #define RT5677_M_STO4_ADC_R1_SFT 7
  495. #define RT5677_M_STO4_ADC_R2 (0x1 << 6)
  496. #define RT5677_M_STO4_ADC_R2_SFT 6
  497. /* Stereo3 ADC Mixer control (0x25) */
  498. #define RT5677_M_STO3_ADC_L2 (0x1 << 15)
  499. #define RT5677_M_STO3_ADC_L2_SFT 15
  500. #define RT5677_M_STO3_ADC_L1 (0x1 << 14)
  501. #define RT5677_M_STO3_ADC_L1_SFT 14
  502. #define RT5677_SEL_STO3_ADC1_MASK (0x3 << 12)
  503. #define RT5677_SEL_STO3_ADC1_SFT 12
  504. #define RT5677_SEL_STO3_ADC2_MASK (0x3 << 10)
  505. #define RT5677_SEL_STO3_ADC2_SFT 10
  506. #define RT5677_SEL_STO3_DMIC_MASK (0x3 << 8)
  507. #define RT5677_SEL_STO3_DMIC_SFT 8
  508. #define RT5677_M_STO3_ADC_R1 (0x1 << 7)
  509. #define RT5677_M_STO3_ADC_R1_SFT 7
  510. #define RT5677_M_STO3_ADC_R2 (0x1 << 6)
  511. #define RT5677_M_STO3_ADC_R2_SFT 6
  512. /* Stereo2 ADC Mixer Control (0x26) */
  513. #define RT5677_M_STO2_ADC_L2 (0x1 << 15)
  514. #define RT5677_M_STO2_ADC_L2_SFT 15
  515. #define RT5677_M_STO2_ADC_L1 (0x1 << 14)
  516. #define RT5677_M_STO2_ADC_L1_SFT 14
  517. #define RT5677_SEL_STO2_ADC1_MASK (0x3 << 12)
  518. #define RT5677_SEL_STO2_ADC1_SFT 12
  519. #define RT5677_SEL_STO2_ADC2_MASK (0x3 << 10)
  520. #define RT5677_SEL_STO2_ADC2_SFT 10
  521. #define RT5677_SEL_STO2_DMIC_MASK (0x3 << 8)
  522. #define RT5677_SEL_STO2_DMIC_SFT 8
  523. #define RT5677_M_STO2_ADC_R1 (0x1 << 7)
  524. #define RT5677_M_STO2_ADC_R1_SFT 7
  525. #define RT5677_M_STO2_ADC_R2 (0x1 << 6)
  526. #define RT5677_M_STO2_ADC_R2_SFT 6
  527. #define RT5677_SEL_STO2_LR_MIX_MASK (0x1 << 0)
  528. #define RT5677_SEL_STO2_LR_MIX_SFT 0
  529. #define RT5677_SEL_STO2_LR_MIX_L (0x0 << 0)
  530. #define RT5677_SEL_STO2_LR_MIX_LR (0x1 << 0)
  531. /* Stereo1 ADC Mixer control (0x27) */
  532. #define RT5677_M_STO1_ADC_L2 (0x1 << 15)
  533. #define RT5677_M_STO1_ADC_L2_SFT 15
  534. #define RT5677_M_STO1_ADC_L1 (0x1 << 14)
  535. #define RT5677_M_STO1_ADC_L1_SFT 14
  536. #define RT5677_SEL_STO1_ADC1_MASK (0x3 << 12)
  537. #define RT5677_SEL_STO1_ADC1_SFT 12
  538. #define RT5677_SEL_STO1_ADC2_MASK (0x3 << 10)
  539. #define RT5677_SEL_STO1_ADC2_SFT 10
  540. #define RT5677_SEL_STO1_DMIC_MASK (0x3 << 8)
  541. #define RT5677_SEL_STO1_DMIC_SFT 8
  542. #define RT5677_M_STO1_ADC_R1 (0x1 << 7)
  543. #define RT5677_M_STO1_ADC_R1_SFT 7
  544. #define RT5677_M_STO1_ADC_R2 (0x1 << 6)
  545. #define RT5677_M_STO1_ADC_R2_SFT 6
  546. /* Mono ADC Mixer control (0x28) */
  547. #define RT5677_M_MONO_ADC_L2 (0x1 << 15)
  548. #define RT5677_M_MONO_ADC_L2_SFT 15
  549. #define RT5677_M_MONO_ADC_L1 (0x1 << 14)
  550. #define RT5677_M_MONO_ADC_L1_SFT 14
  551. #define RT5677_SEL_MONO_ADC_L1_MASK (0x3 << 12)
  552. #define RT5677_SEL_MONO_ADC_L1_SFT 12
  553. #define RT5677_SEL_MONO_ADC_L2_MASK (0x3 << 10)
  554. #define RT5677_SEL_MONO_ADC_L2_SFT 10
  555. #define RT5677_SEL_MONO_DMIC_L_MASK (0x3 << 8)
  556. #define RT5677_SEL_MONO_DMIC_L_SFT 8
  557. #define RT5677_M_MONO_ADC_R1 (0x1 << 7)
  558. #define RT5677_M_MONO_ADC_R1_SFT 7
  559. #define RT5677_M_MONO_ADC_R2 (0x1 << 6)
  560. #define RT5677_M_MONO_ADC_R2_SFT 6
  561. #define RT5677_SEL_MONO_ADC_R1_MASK (0x3 << 4)
  562. #define RT5677_SEL_MONO_ADC_R1_SFT 4
  563. #define RT5677_SEL_MONO_ADC_R2_MASK (0x3 << 2)
  564. #define RT5677_SEL_MONO_ADC_R2_SFT 2
  565. #define RT5677_SEL_MONO_DMIC_R_MASK (0x3 << 0)
  566. #define RT5677_SEL_MONO_DMIC_R_SFT 0
  567. /* ADC/IF/DSP to DAC1 Mixer control (0x29) */
  568. #define RT5677_M_ADDA_MIXER1_L (0x1 << 15)
  569. #define RT5677_M_ADDA_MIXER1_L_SFT 15
  570. #define RT5677_M_DAC1_L (0x1 << 14)
  571. #define RT5677_M_DAC1_L_SFT 14
  572. #define RT5677_DAC1_L_SEL_MASK (0x7 << 8)
  573. #define RT5677_DAC1_L_SEL_SFT 8
  574. #define RT5677_M_ADDA_MIXER1_R (0x1 << 7)
  575. #define RT5677_M_ADDA_MIXER1_R_SFT 7
  576. #define RT5677_M_DAC1_R (0x1 << 6)
  577. #define RT5677_M_DAC1_R_SFT 6
  578. #define RT5677_ADDA1_SEL_MASK (0x3 << 0)
  579. #define RT5677_ADDA1_SEL_SFT 0
  580. /* Stereo1 DAC Mixer L/R Control (0x2a) */
  581. #define RT5677_M_ST_DAC1_L (0x1 << 15)
  582. #define RT5677_M_ST_DAC1_L_SFT 15
  583. #define RT5677_M_DAC1_L_STO_L (0x1 << 13)
  584. #define RT5677_M_DAC1_L_STO_L_SFT 13
  585. #define RT5677_DAC1_L_STO_L_VOL_MASK (0x1 << 12)
  586. #define RT5677_DAC1_L_STO_L_VOL_SFT 12
  587. #define RT5677_M_DAC2_L_STO_L (0x1 << 11)
  588. #define RT5677_M_DAC2_L_STO_L_SFT 11
  589. #define RT5677_DAC2_L_STO_L_VOL_MASK (0x1 << 10)
  590. #define RT5677_DAC2_L_STO_L_VOL_SFT 10
  591. #define RT5677_M_DAC1_R_STO_L (0x1 << 9)
  592. #define RT5677_M_DAC1_R_STO_L_SFT 9
  593. #define RT5677_DAC1_R_STO_L_VOL_MASK (0x1 << 8)
  594. #define RT5677_DAC1_R_STO_L_VOL_SFT 8
  595. #define RT5677_M_ST_DAC1_R (0x1 << 7)
  596. #define RT5677_M_ST_DAC1_R_SFT 7
  597. #define RT5677_M_DAC1_R_STO_R (0x1 << 5)
  598. #define RT5677_M_DAC1_R_STO_R_SFT 5
  599. #define RT5677_DAC1_R_STO_R_VOL_MASK (0x1 << 4)
  600. #define RT5677_DAC1_R_STO_R_VOL_SFT 4
  601. #define RT5677_M_DAC2_R_STO_R (0x1 << 3)
  602. #define RT5677_M_DAC2_R_STO_R_SFT 3
  603. #define RT5677_DAC2_R_STO_R_VOL_MASK (0x1 << 2)
  604. #define RT5677_DAC2_R_STO_R_VOL_SFT 2
  605. #define RT5677_M_DAC1_L_STO_R (0x1 << 1)
  606. #define RT5677_M_DAC1_L_STO_R_SFT 1
  607. #define RT5677_DAC1_L_STO_R_VOL_MASK (0x1 << 0)
  608. #define RT5677_DAC1_L_STO_R_VOL_SFT 0
  609. /* Mono DAC Mixer L/R Control (0x2b) */
  610. #define RT5677_M_ST_DAC2_L (0x1 << 15)
  611. #define RT5677_M_ST_DAC2_L_SFT 15
  612. #define RT5677_M_DAC2_L_MONO_L (0x1 << 13)
  613. #define RT5677_M_DAC2_L_MONO_L_SFT 13
  614. #define RT5677_DAC2_L_MONO_L_VOL_MASK (0x1 << 12)
  615. #define RT5677_DAC2_L_MONO_L_VOL_SFT 12
  616. #define RT5677_M_DAC2_R_MONO_L (0x1 << 11)
  617. #define RT5677_M_DAC2_R_MONO_L_SFT 11
  618. #define RT5677_DAC2_R_MONO_L_VOL_MASK (0x1 << 10)
  619. #define RT5677_DAC2_R_MONO_L_VOL_SFT 10
  620. #define RT5677_M_DAC1_L_MONO_L (0x1 << 9)
  621. #define RT5677_M_DAC1_L_MONO_L_SFT 9
  622. #define RT5677_DAC1_L_MONO_L_VOL_MASK (0x1 << 8)
  623. #define RT5677_DAC1_L_MONO_L_VOL_SFT 8
  624. #define RT5677_M_ST_DAC2_R (0x1 << 7)
  625. #define RT5677_M_ST_DAC2_R_SFT 7
  626. #define RT5677_M_DAC2_R_MONO_R (0x1 << 5)
  627. #define RT5677_M_DAC2_R_MONO_R_SFT 5
  628. #define RT5677_DAC2_R_MONO_R_VOL_MASK (0x1 << 4)
  629. #define RT5677_DAC2_R_MONO_R_VOL_SFT 4
  630. #define RT5677_M_DAC1_R_MONO_R (0x1 << 3)
  631. #define RT5677_M_DAC1_R_MONO_R_SFT 3
  632. #define RT5677_DAC1_R_MONO_R_VOL_MASK (0x1 << 2)
  633. #define RT5677_DAC1_R_MONO_R_VOL_SFT 2
  634. #define RT5677_M_DAC2_L_MONO_R (0x1 << 1)
  635. #define RT5677_M_DAC2_L_MONO_R_SFT 1
  636. #define RT5677_DAC2_L_MONO_R_VOL_MASK (0x1 << 0)
  637. #define RT5677_DAC2_L_MONO_R_VOL_SFT 0
  638. /* DD Mixer 1 Control (0x2c) */
  639. #define RT5677_M_STO_L_DD1_L (0x1 << 15)
  640. #define RT5677_M_STO_L_DD1_L_SFT 15
  641. #define RT5677_STO_L_DD1_L_VOL_MASK (0x1 << 14)
  642. #define RT5677_STO_L_DD1_L_VOL_SFT 14
  643. #define RT5677_M_MONO_L_DD1_L (0x1 << 13)
  644. #define RT5677_M_MONO_L_DD1_L_SFT 13
  645. #define RT5677_MONO_L_DD1_L_VOL_MASK (0x1 << 12)
  646. #define RT5677_MONO_L_DD1_L_VOL_SFT 12
  647. #define RT5677_M_DAC3_L_DD1_L (0x1 << 11)
  648. #define RT5677_M_DAC3_L_DD1_L_SFT 11
  649. #define RT5677_DAC3_L_DD1_L_VOL_MASK (0x1 << 10)
  650. #define RT5677_DAC3_L_DD1_L_VOL_SFT 10
  651. #define RT5677_M_DAC3_R_DD1_L (0x1 << 9)
  652. #define RT5677_M_DAC3_R_DD1_L_SFT 9
  653. #define RT5677_DAC3_R_DD1_L_VOL_MASK (0x1 << 8)
  654. #define RT5677_DAC3_R_DD1_L_VOL_SFT 8
  655. #define RT5677_M_STO_R_DD1_R (0x1 << 7)
  656. #define RT5677_M_STO_R_DD1_R_SFT 7
  657. #define RT5677_STO_R_DD1_R_VOL_MASK (0x1 << 6)
  658. #define RT5677_STO_R_DD1_R_VOL_SFT 6
  659. #define RT5677_M_MONO_R_DD1_R (0x1 << 5)
  660. #define RT5677_M_MONO_R_DD1_R_SFT 5
  661. #define RT5677_MONO_R_DD1_R_VOL_MASK (0x1 << 4)
  662. #define RT5677_MONO_R_DD1_R_VOL_SFT 4
  663. #define RT5677_M_DAC3_R_DD1_R (0x1 << 3)
  664. #define RT5677_M_DAC3_R_DD1_R_SFT 3
  665. #define RT5677_DAC3_R_DD1_R_VOL_MASK (0x1 << 2)
  666. #define RT5677_DAC3_R_DD1_R_VOL_SFT 2
  667. #define RT5677_M_DAC3_L_DD1_R (0x1 << 1)
  668. #define RT5677_M_DAC3_L_DD1_R_SFT 1
  669. #define RT5677_DAC3_L_DD1_R_VOL_MASK (0x1 << 0)
  670. #define RT5677_DAC3_L_DD1_R_VOL_SFT 0
  671. /* DD Mixer 2 Control (0x2d) */
  672. #define RT5677_M_STO_L_DD2_L (0x1 << 15)
  673. #define RT5677_M_STO_L_DD2_L_SFT 15
  674. #define RT5677_STO_L_DD2_L_VOL_MASK (0x1 << 14)
  675. #define RT5677_STO_L_DD2_L_VOL_SFT 14
  676. #define RT5677_M_MONO_L_DD2_L (0x1 << 13)
  677. #define RT5677_M_MONO_L_DD2_L_SFT 13
  678. #define RT5677_MONO_L_DD2_L_VOL_MASK (0x1 << 12)
  679. #define RT5677_MONO_L_DD2_L_VOL_SFT 12
  680. #define RT5677_M_DAC4_L_DD2_L (0x1 << 11)
  681. #define RT5677_M_DAC4_L_DD2_L_SFT 11
  682. #define RT5677_DAC4_L_DD2_L_VOL_MASK (0x1 << 10)
  683. #define RT5677_DAC4_L_DD2_L_VOL_SFT 10
  684. #define RT5677_M_DAC4_R_DD2_L (0x1 << 9)
  685. #define RT5677_M_DAC4_R_DD2_L_SFT 9
  686. #define RT5677_DAC4_R_DD2_L_VOL_MASK (0x1 << 8)
  687. #define RT5677_DAC4_R_DD2_L_VOL_SFT 8
  688. #define RT5677_M_STO_R_DD2_R (0x1 << 7)
  689. #define RT5677_M_STO_R_DD2_R_SFT 7
  690. #define RT5677_STO_R_DD2_R_VOL_MASK (0x1 << 6)
  691. #define RT5677_STO_R_DD2_R_VOL_SFT 6
  692. #define RT5677_M_MONO_R_DD2_R (0x1 << 5)
  693. #define RT5677_M_MONO_R_DD2_R_SFT 5
  694. #define RT5677_MONO_R_DD2_R_VOL_MASK (0x1 << 4)
  695. #define RT5677_MONO_R_DD2_R_VOL_SFT 4
  696. #define RT5677_M_DAC4_R_DD2_R (0x1 << 3)
  697. #define RT5677_M_DAC4_R_DD2_R_SFT 3
  698. #define RT5677_DAC4_R_DD2_R_VOL_MASK (0x1 << 2)
  699. #define RT5677_DAC4_R_DD2_R_VOL_SFT 2
  700. #define RT5677_M_DAC4_L_DD2_R (0x1 << 1)
  701. #define RT5677_M_DAC4_L_DD2_R_SFT 1
  702. #define RT5677_DAC4_L_DD2_R_VOL_MASK (0x1 << 0)
  703. #define RT5677_DAC4_L_DD2_R_VOL_SFT 0
  704. /* IF3 data control (0x2f) */
  705. #define RT5677_IF3_DAC_SEL_MASK (0x3 << 6)
  706. #define RT5677_IF3_DAC_SEL_SFT 6
  707. #define RT5677_IF3_ADC_SEL_MASK (0x3 << 4)
  708. #define RT5677_IF3_ADC_SEL_SFT 4
  709. #define RT5677_IF3_ADC_IN_MASK (0xf << 0)
  710. #define RT5677_IF3_ADC_IN_SFT 0
  711. /* IF4 data control (0x30) */
  712. #define RT5677_IF4_ADC_IN_MASK (0xf << 4)
  713. #define RT5677_IF4_ADC_IN_SFT 4
  714. #define RT5677_IF4_DAC_SEL_MASK (0x3 << 2)
  715. #define RT5677_IF4_DAC_SEL_SFT 2
  716. #define RT5677_IF4_ADC_SEL_MASK (0x3 << 0)
  717. #define RT5677_IF4_ADC_SEL_SFT 0
  718. /* PDM Output Control (0x31) */
  719. #define RT5677_M_PDM1_L (0x1 << 15)
  720. #define RT5677_M_PDM1_L_SFT 15
  721. #define RT5677_SEL_PDM1_L_MASK (0x3 << 12)
  722. #define RT5677_SEL_PDM1_L_SFT 12
  723. #define RT5677_M_PDM1_R (0x1 << 11)
  724. #define RT5677_M_PDM1_R_SFT 11
  725. #define RT5677_SEL_PDM1_R_MASK (0x3 << 8)
  726. #define RT5677_SEL_PDM1_R_SFT 8
  727. #define RT5677_M_PDM2_L (0x1 << 7)
  728. #define RT5677_M_PDM2_L_SFT 7
  729. #define RT5677_SEL_PDM2_L_MASK (0x3 << 4)
  730. #define RT5677_SEL_PDM2_L_SFT 4
  731. #define RT5677_M_PDM2_R (0x1 << 3)
  732. #define RT5677_M_PDM2_R_SFT 3
  733. #define RT5677_SEL_PDM2_R_MASK (0x3 << 0)
  734. #define RT5677_SEL_PDM2_R_SFT 0
  735. /* PDM I2C / Data Control 1 (0x32) */
  736. #define RT5677_PDM2_PW_DOWN (0x1 << 7)
  737. #define RT5677_PDM1_PW_DOWN (0x1 << 6)
  738. #define RT5677_PDM2_BUSY (0x1 << 5)
  739. #define RT5677_PDM1_BUSY (0x1 << 4)
  740. #define RT5677_PDM_PATTERN (0x1 << 3)
  741. #define RT5677_PDM_GAIN (0x1 << 2)
  742. #define RT5677_PDM_DIV_MASK (0x3 << 0)
  743. /* PDM I2C / Data Control 2 (0x33) */
  744. #define RT5677_PDM1_I2C_ID (0xf << 12)
  745. #define RT5677_PDM1_EXE (0x1 << 11)
  746. #define RT5677_PDM1_I2C_CMD (0x1 << 10)
  747. #define RT5677_PDM1_I2C_EXE (0x1 << 9)
  748. #define RT5677_PDM1_I2C_BUSY (0x1 << 8)
  749. #define RT5677_PDM2_I2C_ID (0xf << 4)
  750. #define RT5677_PDM2_EXE (0x1 << 3)
  751. #define RT5677_PDM2_I2C_CMD (0x1 << 2)
  752. #define RT5677_PDM2_I2C_EXE (0x1 << 1)
  753. #define RT5677_PDM2_I2C_BUSY (0x1 << 0)
  754. /* MX3C TDM1 control 1 (0x3c) */
  755. #define RT5677_IF1_ADC4_MASK (0x3 << 10)
  756. #define RT5677_IF1_ADC4_SFT 10
  757. #define RT5677_IF1_ADC3_MASK (0x3 << 8)
  758. #define RT5677_IF1_ADC3_SFT 8
  759. #define RT5677_IF1_ADC2_MASK (0x3 << 6)
  760. #define RT5677_IF1_ADC2_SFT 6
  761. #define RT5677_IF1_ADC1_MASK (0x3 << 4)
  762. #define RT5677_IF1_ADC1_SFT 4
  763. /* MX41 TDM2 control 1 (0x41) */
  764. #define RT5677_IF2_ADC4_MASK (0x3 << 10)
  765. #define RT5677_IF2_ADC4_SFT 10
  766. #define RT5677_IF2_ADC3_MASK (0x3 << 8)
  767. #define RT5677_IF2_ADC3_SFT 8
  768. #define RT5677_IF2_ADC2_MASK (0x3 << 6)
  769. #define RT5677_IF2_ADC2_SFT 6
  770. #define RT5677_IF2_ADC1_MASK (0x3 << 4)
  771. #define RT5677_IF2_ADC1_SFT 4
  772. /* Digital Microphone Control 1 (0x50) */
  773. #define RT5677_DMIC_1_EN_MASK (0x1 << 15)
  774. #define RT5677_DMIC_1_EN_SFT 15
  775. #define RT5677_DMIC_1_DIS (0x0 << 15)
  776. #define RT5677_DMIC_1_EN (0x1 << 15)
  777. #define RT5677_DMIC_2_EN_MASK (0x1 << 14)
  778. #define RT5677_DMIC_2_EN_SFT 14
  779. #define RT5677_DMIC_2_DIS (0x0 << 14)
  780. #define RT5677_DMIC_2_EN (0x1 << 14)
  781. #define RT5677_DMIC_L_STO1_LH_MASK (0x1 << 13)
  782. #define RT5677_DMIC_L_STO1_LH_SFT 13
  783. #define RT5677_DMIC_L_STO1_LH_FALLING (0x0 << 13)
  784. #define RT5677_DMIC_L_STO1_LH_RISING (0x1 << 13)
  785. #define RT5677_DMIC_R_STO1_LH_MASK (0x1 << 12)
  786. #define RT5677_DMIC_R_STO1_LH_SFT 12
  787. #define RT5677_DMIC_R_STO1_LH_FALLING (0x0 << 12)
  788. #define RT5677_DMIC_R_STO1_LH_RISING (0x1 << 12)
  789. #define RT5677_DMIC_L_STO3_LH_MASK (0x1 << 11)
  790. #define RT5677_DMIC_L_STO3_LH_SFT 11
  791. #define RT5677_DMIC_L_STO3_LH_FALLING (0x0 << 11)
  792. #define RT5677_DMIC_L_STO3_LH_RISING (0x1 << 11)
  793. #define RT5677_DMIC_R_STO3_LH_MASK (0x1 << 10)
  794. #define RT5677_DMIC_R_STO3_LH_SFT 10
  795. #define RT5677_DMIC_R_STO3_LH_FALLING (0x0 << 10)
  796. #define RT5677_DMIC_R_STO3_LH_RISING (0x1 << 10)
  797. #define RT5677_DMIC_L_STO2_LH_MASK (0x1 << 9)
  798. #define RT5677_DMIC_L_STO2_LH_SFT 9
  799. #define RT5677_DMIC_L_STO2_LH_FALLING (0x0 << 9)
  800. #define RT5677_DMIC_L_STO2_LH_RISING (0x1 << 9)
  801. #define RT5677_DMIC_R_STO2_LH_MASK (0x1 << 8)
  802. #define RT5677_DMIC_R_STO2_LH_SFT 8
  803. #define RT5677_DMIC_R_STO2_LH_FALLING (0x0 << 8)
  804. #define RT5677_DMIC_R_STO2_LH_RISING (0x1 << 8)
  805. #define RT5677_DMIC_CLK_MASK (0x7 << 5)
  806. #define RT5677_DMIC_CLK_SFT 5
  807. #define RT5677_DMIC_3_EN_MASK (0x1 << 4)
  808. #define RT5677_DMIC_3_EN_SFT 4
  809. #define RT5677_DMIC_3_DIS (0x0 << 4)
  810. #define RT5677_DMIC_3_EN (0x1 << 4)
  811. #define RT5677_DMIC_R_MONO_LH_MASK (0x1 << 2)
  812. #define RT5677_DMIC_R_MONO_LH_SFT 2
  813. #define RT5677_DMIC_R_MONO_LH_FALLING (0x0 << 2)
  814. #define RT5677_DMIC_R_MONO_LH_RISING (0x1 << 2)
  815. #define RT5677_DMIC_L_STO4_LH_MASK (0x1 << 1)
  816. #define RT5677_DMIC_L_STO4_LH_SFT 1
  817. #define RT5677_DMIC_L_STO4_LH_FALLING (0x0 << 1)
  818. #define RT5677_DMIC_L_STO4_LH_RISING (0x1 << 1)
  819. #define RT5677_DMIC_R_STO4_LH_MASK (0x1 << 0)
  820. #define RT5677_DMIC_R_STO4_LH_SFT 0
  821. #define RT5677_DMIC_R_STO4_LH_FALLING (0x0 << 0)
  822. #define RT5677_DMIC_R_STO4_LH_RISING (0x1 << 0)
  823. /* Digital Microphone Control 2 (0x51) */
  824. #define RT5677_DMIC_4_EN_MASK (0x1 << 15)
  825. #define RT5677_DMIC_4_EN_SFT 15
  826. #define RT5677_DMIC_4_DIS (0x0 << 15)
  827. #define RT5677_DMIC_4_EN (0x1 << 15)
  828. #define RT5677_DMIC_4L_LH_MASK (0x1 << 7)
  829. #define RT5677_DMIC_4L_LH_SFT 7
  830. #define RT5677_DMIC_4L_LH_FALLING (0x0 << 7)
  831. #define RT5677_DMIC_4L_LH_RISING (0x1 << 7)
  832. #define RT5677_DMIC_4R_LH_MASK (0x1 << 6)
  833. #define RT5677_DMIC_4R_LH_SFT 6
  834. #define RT5677_DMIC_4R_LH_FALLING (0x0 << 6)
  835. #define RT5677_DMIC_4R_LH_RISING (0x1 << 6)
  836. #define RT5677_DMIC_3L_LH_MASK (0x1 << 5)
  837. #define RT5677_DMIC_3L_LH_SFT 5
  838. #define RT5677_DMIC_3L_LH_FALLING (0x0 << 5)
  839. #define RT5677_DMIC_3L_LH_RISING (0x1 << 5)
  840. #define RT5677_DMIC_3R_LH_MASK (0x1 << 4)
  841. #define RT5677_DMIC_3R_LH_SFT 4
  842. #define RT5677_DMIC_3R_LH_FALLING (0x0 << 4)
  843. #define RT5677_DMIC_3R_LH_RISING (0x1 << 4)
  844. #define RT5677_DMIC_2L_LH_MASK (0x1 << 3)
  845. #define RT5677_DMIC_2L_LH_SFT 3
  846. #define RT5677_DMIC_2L_LH_FALLING (0x0 << 3)
  847. #define RT5677_DMIC_2L_LH_RISING (0x1 << 3)
  848. #define RT5677_DMIC_2R_LH_MASK (0x1 << 2)
  849. #define RT5677_DMIC_2R_LH_SFT 2
  850. #define RT5677_DMIC_2R_LH_FALLING (0x0 << 2)
  851. #define RT5677_DMIC_2R_LH_RISING (0x1 << 2)
  852. #define RT5677_DMIC_1L_LH_MASK (0x1 << 1)
  853. #define RT5677_DMIC_1L_LH_SFT 1
  854. #define RT5677_DMIC_1L_LH_FALLING (0x0 << 1)
  855. #define RT5677_DMIC_1L_LH_RISING (0x1 << 1)
  856. #define RT5677_DMIC_1R_LH_MASK (0x1 << 0)
  857. #define RT5677_DMIC_1R_LH_SFT 0
  858. #define RT5677_DMIC_1R_LH_FALLING (0x0 << 0)
  859. #define RT5677_DMIC_1R_LH_RISING (0x1 << 0)
  860. /* Power Management for Digital 1 (0x61) */
  861. #define RT5677_PWR_I2S1 (0x1 << 15)
  862. #define RT5677_PWR_I2S1_BIT 15
  863. #define RT5677_PWR_I2S2 (0x1 << 14)
  864. #define RT5677_PWR_I2S2_BIT 14
  865. #define RT5677_PWR_I2S3 (0x1 << 13)
  866. #define RT5677_PWR_I2S3_BIT 13
  867. #define RT5677_PWR_DAC1 (0x1 << 12)
  868. #define RT5677_PWR_DAC1_BIT 12
  869. #define RT5677_PWR_DAC2 (0x1 << 11)
  870. #define RT5677_PWR_DAC2_BIT 11
  871. #define RT5677_PWR_I2S4 (0x1 << 10)
  872. #define RT5677_PWR_I2S4_BIT 10
  873. #define RT5677_PWR_SLB (0x1 << 9)
  874. #define RT5677_PWR_SLB_BIT 9
  875. #define RT5677_PWR_DAC3 (0x1 << 7)
  876. #define RT5677_PWR_DAC3_BIT 7
  877. #define RT5677_PWR_ADCFED2 (0x1 << 4)
  878. #define RT5677_PWR_ADCFED2_BIT 4
  879. #define RT5677_PWR_ADCFED1 (0x1 << 3)
  880. #define RT5677_PWR_ADCFED1_BIT 3
  881. #define RT5677_PWR_ADC_L (0x1 << 2)
  882. #define RT5677_PWR_ADC_L_BIT 2
  883. #define RT5677_PWR_ADC_R (0x1 << 1)
  884. #define RT5677_PWR_ADC_R_BIT 1
  885. #define RT5677_PWR_I2C_MASTER (0x1 << 0)
  886. #define RT5677_PWR_I2C_MASTER_BIT 0
  887. /* Power Management for Digital 2 (0x62) */
  888. #define RT5677_PWR_ADC_S1F (0x1 << 15)
  889. #define RT5677_PWR_ADC_S1F_BIT 15
  890. #define RT5677_PWR_ADC_MF_L (0x1 << 14)
  891. #define RT5677_PWR_ADC_MF_L_BIT 14
  892. #define RT5677_PWR_ADC_MF_R (0x1 << 13)
  893. #define RT5677_PWR_ADC_MF_R_BIT 13
  894. #define RT5677_PWR_DAC_S1F (0x1 << 12)
  895. #define RT5677_PWR_DAC_S1F_BIT 12
  896. #define RT5677_PWR_DAC_M2F_L (0x1 << 11)
  897. #define RT5677_PWR_DAC_M2F_L_BIT 11
  898. #define RT5677_PWR_DAC_M2F_R (0x1 << 10)
  899. #define RT5677_PWR_DAC_M2F_R_BIT 10
  900. #define RT5677_PWR_DAC_M3F_L (0x1 << 9)
  901. #define RT5677_PWR_DAC_M3F_L_BIT 9
  902. #define RT5677_PWR_DAC_M3F_R (0x1 << 8)
  903. #define RT5677_PWR_DAC_M3F_R_BIT 8
  904. #define RT5677_PWR_DAC_M4F_L (0x1 << 7)
  905. #define RT5677_PWR_DAC_M4F_L_BIT 7
  906. #define RT5677_PWR_DAC_M4F_R (0x1 << 6)
  907. #define RT5677_PWR_DAC_M4F_R_BIT 6
  908. #define RT5677_PWR_ADC_S2F (0x1 << 5)
  909. #define RT5677_PWR_ADC_S2F_BIT 5
  910. #define RT5677_PWR_ADC_S3F (0x1 << 4)
  911. #define RT5677_PWR_ADC_S3F_BIT 4
  912. #define RT5677_PWR_ADC_S4F (0x1 << 3)
  913. #define RT5677_PWR_ADC_S4F_BIT 3
  914. #define RT5677_PWR_PDM1 (0x1 << 2)
  915. #define RT5677_PWR_PDM1_BIT 2
  916. #define RT5677_PWR_PDM2 (0x1 << 1)
  917. #define RT5677_PWR_PDM2_BIT 1
  918. /* Power Management for Analog 1 (0x63) */
  919. #define RT5677_PWR_VREF1 (0x1 << 15)
  920. #define RT5677_PWR_VREF1_BIT 15
  921. #define RT5677_PWR_FV1 (0x1 << 14)
  922. #define RT5677_PWR_FV1_BIT 14
  923. #define RT5677_PWR_MB (0x1 << 13)
  924. #define RT5677_PWR_MB_BIT 13
  925. #define RT5677_PWR_LO1 (0x1 << 12)
  926. #define RT5677_PWR_LO1_BIT 12
  927. #define RT5677_PWR_BG (0x1 << 11)
  928. #define RT5677_PWR_BG_BIT 11
  929. #define RT5677_PWR_LO2 (0x1 << 10)
  930. #define RT5677_PWR_LO2_BIT 10
  931. #define RT5677_PWR_LO3 (0x1 << 9)
  932. #define RT5677_PWR_LO3_BIT 9
  933. #define RT5677_PWR_VREF2 (0x1 << 8)
  934. #define RT5677_PWR_VREF2_BIT 8
  935. #define RT5677_PWR_FV2 (0x1 << 7)
  936. #define RT5677_PWR_FV2_BIT 7
  937. #define RT5677_LDO2_SEL_MASK (0x7 << 4)
  938. #define RT5677_LDO2_SEL_SFT 4
  939. #define RT5677_LDO1_SEL_MASK (0x7 << 0)
  940. #define RT5677_LDO1_SEL_SFT 0
  941. /* Power Management for Analog 2 (0x64) */
  942. #define RT5677_PWR_BST1 (0x1 << 15)
  943. #define RT5677_PWR_BST1_BIT 15
  944. #define RT5677_PWR_BST2 (0x1 << 14)
  945. #define RT5677_PWR_BST2_BIT 14
  946. #define RT5677_PWR_CLK_MB1 (0x1 << 13)
  947. #define RT5677_PWR_CLK_MB1_BIT 13
  948. #define RT5677_PWR_SLIM (0x1 << 12)
  949. #define RT5677_PWR_SLIM_BIT 12
  950. #define RT5677_PWR_MB1 (0x1 << 11)
  951. #define RT5677_PWR_MB1_BIT 11
  952. #define RT5677_PWR_PP_MB1 (0x1 << 10)
  953. #define RT5677_PWR_PP_MB1_BIT 10
  954. #define RT5677_PWR_PLL1 (0x1 << 9)
  955. #define RT5677_PWR_PLL1_BIT 9
  956. #define RT5677_PWR_PLL2 (0x1 << 8)
  957. #define RT5677_PWR_PLL2_BIT 8
  958. #define RT5677_PWR_CORE (0x1 << 7)
  959. #define RT5677_PWR_CORE_BIT 7
  960. #define RT5677_PWR_CLK_MB (0x1 << 6)
  961. #define RT5677_PWR_CLK_MB_BIT 6
  962. #define RT5677_PWR_BST1_P (0x1 << 5)
  963. #define RT5677_PWR_BST1_P_BIT 5
  964. #define RT5677_PWR_BST2_P (0x1 << 4)
  965. #define RT5677_PWR_BST2_P_BIT 4
  966. #define RT5677_PWR_IPTV (0x1 << 3)
  967. #define RT5677_PWR_IPTV_BIT 3
  968. #define RT5677_PWR_25M_CLK (0x1 << 1)
  969. #define RT5677_PWR_25M_CLK_BIT 1
  970. #define RT5677_PWR_LDO1 (0x1 << 0)
  971. #define RT5677_PWR_LDO1_BIT 0
  972. /* Power Management for DSP (0x65) */
  973. #define RT5677_PWR_SR7 (0x1 << 10)
  974. #define RT5677_PWR_SR7_BIT 10
  975. #define RT5677_PWR_SR6 (0x1 << 9)
  976. #define RT5677_PWR_SR6_BIT 9
  977. #define RT5677_PWR_SR5 (0x1 << 8)
  978. #define RT5677_PWR_SR5_BIT 8
  979. #define RT5677_PWR_SR4 (0x1 << 7)
  980. #define RT5677_PWR_SR4_BIT 7
  981. #define RT5677_PWR_SR3 (0x1 << 6)
  982. #define RT5677_PWR_SR3_BIT 6
  983. #define RT5677_PWR_SR2 (0x1 << 5)
  984. #define RT5677_PWR_SR2_BIT 5
  985. #define RT5677_PWR_SR1 (0x1 << 4)
  986. #define RT5677_PWR_SR1_BIT 4
  987. #define RT5677_PWR_SR0 (0x1 << 3)
  988. #define RT5677_PWR_SR0_BIT 3
  989. #define RT5677_PWR_MLT (0x1 << 2)
  990. #define RT5677_PWR_MLT_BIT 2
  991. #define RT5677_PWR_DSP (0x1 << 1)
  992. #define RT5677_PWR_DSP_BIT 1
  993. #define RT5677_PWR_DSP_CPU (0x1 << 0)
  994. #define RT5677_PWR_DSP_CPU_BIT 0
  995. /* Power Status for DSP (0x66) */
  996. #define RT5677_PWR_SR7_RDY (0x1 << 9)
  997. #define RT5677_PWR_SR7_RDY_BIT 9
  998. #define RT5677_PWR_SR6_RDY (0x1 << 8)
  999. #define RT5677_PWR_SR6_RDY_BIT 8
  1000. #define RT5677_PWR_SR5_RDY (0x1 << 7)
  1001. #define RT5677_PWR_SR5_RDY_BIT 7
  1002. #define RT5677_PWR_SR4_RDY (0x1 << 6)
  1003. #define RT5677_PWR_SR4_RDY_BIT 6
  1004. #define RT5677_PWR_SR3_RDY (0x1 << 5)
  1005. #define RT5677_PWR_SR3_RDY_BIT 5
  1006. #define RT5677_PWR_SR2_RDY (0x1 << 4)
  1007. #define RT5677_PWR_SR2_RDY_BIT 4
  1008. #define RT5677_PWR_SR1_RDY (0x1 << 3)
  1009. #define RT5677_PWR_SR1_RDY_BIT 3
  1010. #define RT5677_PWR_SR0_RDY (0x1 << 2)
  1011. #define RT5677_PWR_SR0_RDY_BIT 2
  1012. #define RT5677_PWR_MLT_RDY (0x1 << 1)
  1013. #define RT5677_PWR_MLT_RDY_BIT 1
  1014. #define RT5677_PWR_DSP_RDY (0x1 << 0)
  1015. #define RT5677_PWR_DSP_RDY_BIT 0
  1016. /* Power Management for DSP (0x67) */
  1017. #define RT5677_PWR_SLIM_ISO (0x1 << 11)
  1018. #define RT5677_PWR_SLIM_ISO_BIT 11
  1019. #define RT5677_PWR_CORE_ISO (0x1 << 10)
  1020. #define RT5677_PWR_CORE_ISO_BIT 10
  1021. #define RT5677_PWR_DSP_ISO (0x1 << 9)
  1022. #define RT5677_PWR_DSP_ISO_BIT 9
  1023. #define RT5677_PWR_SR7_ISO (0x1 << 8)
  1024. #define RT5677_PWR_SR7_ISO_BIT 8
  1025. #define RT5677_PWR_SR6_ISO (0x1 << 7)
  1026. #define RT5677_PWR_SR6_ISO_BIT 7
  1027. #define RT5677_PWR_SR5_ISO (0x1 << 6)
  1028. #define RT5677_PWR_SR5_ISO_BIT 6
  1029. #define RT5677_PWR_SR4_ISO (0x1 << 5)
  1030. #define RT5677_PWR_SR4_ISO_BIT 5
  1031. #define RT5677_PWR_SR3_ISO (0x1 << 4)
  1032. #define RT5677_PWR_SR3_ISO_BIT 4
  1033. #define RT5677_PWR_SR2_ISO (0x1 << 3)
  1034. #define RT5677_PWR_SR2_ISO_BIT 3
  1035. #define RT5677_PWR_SR1_ISO (0x1 << 2)
  1036. #define RT5677_PWR_SR1_ISO_BIT 2
  1037. #define RT5677_PWR_SR0_ISO (0x1 << 1)
  1038. #define RT5677_PWR_SR0_ISO_BIT 1
  1039. #define RT5677_PWR_MLT_ISO (0x1 << 0)
  1040. #define RT5677_PWR_MLT_ISO_BIT 0
  1041. /* I2S1/2/3/4 Audio Serial Data Port Control (0x6f 0x70 0x71 0x72) */
  1042. #define RT5677_I2S_MS_MASK (0x1 << 15)
  1043. #define RT5677_I2S_MS_SFT 15
  1044. #define RT5677_I2S_MS_M (0x0 << 15)
  1045. #define RT5677_I2S_MS_S (0x1 << 15)
  1046. #define RT5677_I2S_O_CP_MASK (0x3 << 10)
  1047. #define RT5677_I2S_O_CP_SFT 10
  1048. #define RT5677_I2S_O_CP_OFF (0x0 << 10)
  1049. #define RT5677_I2S_O_CP_U_LAW (0x1 << 10)
  1050. #define RT5677_I2S_O_CP_A_LAW (0x2 << 10)
  1051. #define RT5677_I2S_I_CP_MASK (0x3 << 8)
  1052. #define RT5677_I2S_I_CP_SFT 8
  1053. #define RT5677_I2S_I_CP_OFF (0x0 << 8)
  1054. #define RT5677_I2S_I_CP_U_LAW (0x1 << 8)
  1055. #define RT5677_I2S_I_CP_A_LAW (0x2 << 8)
  1056. #define RT5677_I2S_BP_MASK (0x1 << 7)
  1057. #define RT5677_I2S_BP_SFT 7
  1058. #define RT5677_I2S_BP_NOR (0x0 << 7)
  1059. #define RT5677_I2S_BP_INV (0x1 << 7)
  1060. #define RT5677_I2S_DL_MASK (0x3 << 2)
  1061. #define RT5677_I2S_DL_SFT 2
  1062. #define RT5677_I2S_DL_16 (0x0 << 2)
  1063. #define RT5677_I2S_DL_20 (0x1 << 2)
  1064. #define RT5677_I2S_DL_24 (0x2 << 2)
  1065. #define RT5677_I2S_DL_8 (0x3 << 2)
  1066. #define RT5677_I2S_DF_MASK (0x3 << 0)
  1067. #define RT5677_I2S_DF_SFT 0
  1068. #define RT5677_I2S_DF_I2S (0x0 << 0)
  1069. #define RT5677_I2S_DF_LEFT (0x1 << 0)
  1070. #define RT5677_I2S_DF_PCM_A (0x2 << 0)
  1071. #define RT5677_I2S_DF_PCM_B (0x3 << 0)
  1072. /* Clock Tree Control 1 (0x73) */
  1073. #define RT5677_I2S_PD1_MASK (0x7 << 12)
  1074. #define RT5677_I2S_PD1_SFT 12
  1075. #define RT5677_I2S_PD1_1 (0x0 << 12)
  1076. #define RT5677_I2S_PD1_2 (0x1 << 12)
  1077. #define RT5677_I2S_PD1_3 (0x2 << 12)
  1078. #define RT5677_I2S_PD1_4 (0x3 << 12)
  1079. #define RT5677_I2S_PD1_6 (0x4 << 12)
  1080. #define RT5677_I2S_PD1_8 (0x5 << 12)
  1081. #define RT5677_I2S_PD1_12 (0x6 << 12)
  1082. #define RT5677_I2S_PD1_16 (0x7 << 12)
  1083. #define RT5677_I2S_BCLK_MS2_MASK (0x1 << 11)
  1084. #define RT5677_I2S_BCLK_MS2_SFT 11
  1085. #define RT5677_I2S_BCLK_MS2_32 (0x0 << 11)
  1086. #define RT5677_I2S_BCLK_MS2_64 (0x1 << 11)
  1087. #define RT5677_I2S_PD2_MASK (0x7 << 8)
  1088. #define RT5677_I2S_PD2_SFT 8
  1089. #define RT5677_I2S_PD2_1 (0x0 << 8)
  1090. #define RT5677_I2S_PD2_2 (0x1 << 8)
  1091. #define RT5677_I2S_PD2_3 (0x2 << 8)
  1092. #define RT5677_I2S_PD2_4 (0x3 << 8)
  1093. #define RT5677_I2S_PD2_6 (0x4 << 8)
  1094. #define RT5677_I2S_PD2_8 (0x5 << 8)
  1095. #define RT5677_I2S_PD2_12 (0x6 << 8)
  1096. #define RT5677_I2S_PD2_16 (0x7 << 8)
  1097. #define RT5677_I2S_BCLK_MS3_MASK (0x1 << 7)
  1098. #define RT5677_I2S_BCLK_MS3_SFT 7
  1099. #define RT5677_I2S_BCLK_MS3_32 (0x0 << 7)
  1100. #define RT5677_I2S_BCLK_MS3_64 (0x1 << 7)
  1101. #define RT5677_I2S_PD3_MASK (0x7 << 4)
  1102. #define RT5677_I2S_PD3_SFT 4
  1103. #define RT5677_I2S_PD3_1 (0x0 << 4)
  1104. #define RT5677_I2S_PD3_2 (0x1 << 4)
  1105. #define RT5677_I2S_PD3_3 (0x2 << 4)
  1106. #define RT5677_I2S_PD3_4 (0x3 << 4)
  1107. #define RT5677_I2S_PD3_6 (0x4 << 4)
  1108. #define RT5677_I2S_PD3_8 (0x5 << 4)
  1109. #define RT5677_I2S_PD3_12 (0x6 << 4)
  1110. #define RT5677_I2S_PD3_16 (0x7 << 4)
  1111. #define RT5677_I2S_BCLK_MS4_MASK (0x1 << 3)
  1112. #define RT5677_I2S_BCLK_MS4_SFT 3
  1113. #define RT5677_I2S_BCLK_MS4_32 (0x0 << 3)
  1114. #define RT5677_I2S_BCLK_MS4_64 (0x1 << 3)
  1115. #define RT5677_I2S_PD4_MASK (0x7 << 0)
  1116. #define RT5677_I2S_PD4_SFT 0
  1117. #define RT5677_I2S_PD4_1 (0x0 << 0)
  1118. #define RT5677_I2S_PD4_2 (0x1 << 0)
  1119. #define RT5677_I2S_PD4_3 (0x2 << 0)
  1120. #define RT5677_I2S_PD4_4 (0x3 << 0)
  1121. #define RT5677_I2S_PD4_6 (0x4 << 0)
  1122. #define RT5677_I2S_PD4_8 (0x5 << 0)
  1123. #define RT5677_I2S_PD4_12 (0x6 << 0)
  1124. #define RT5677_I2S_PD4_16 (0x7 << 0)
  1125. /* Clock Tree Control 2 (0x74) */
  1126. #define RT5677_I2S_PD5_MASK (0x7 << 12)
  1127. #define RT5677_I2S_PD5_SFT 12
  1128. #define RT5677_I2S_PD5_1 (0x0 << 12)
  1129. #define RT5677_I2S_PD5_2 (0x1 << 12)
  1130. #define RT5677_I2S_PD5_3 (0x2 << 12)
  1131. #define RT5677_I2S_PD5_4 (0x3 << 12)
  1132. #define RT5677_I2S_PD5_6 (0x4 << 12)
  1133. #define RT5677_I2S_PD5_8 (0x5 << 12)
  1134. #define RT5677_I2S_PD5_12 (0x6 << 12)
  1135. #define RT5677_I2S_PD5_16 (0x7 << 12)
  1136. #define RT5677_I2S_PD6_MASK (0x7 << 8)
  1137. #define RT5677_I2S_PD6_SFT 8
  1138. #define RT5677_I2S_PD6_1 (0x0 << 8)
  1139. #define RT5677_I2S_PD6_2 (0x1 << 8)
  1140. #define RT5677_I2S_PD6_3 (0x2 << 8)
  1141. #define RT5677_I2S_PD6_4 (0x3 << 8)
  1142. #define RT5677_I2S_PD6_6 (0x4 << 8)
  1143. #define RT5677_I2S_PD6_8 (0x5 << 8)
  1144. #define RT5677_I2S_PD6_12 (0x6 << 8)
  1145. #define RT5677_I2S_PD6_16 (0x7 << 8)
  1146. #define RT5677_I2S_PD7_MASK (0x7 << 4)
  1147. #define RT5677_I2S_PD7_SFT 4
  1148. #define RT5677_I2S_PD7_1 (0x0 << 4)
  1149. #define RT5677_I2S_PD7_2 (0x1 << 4)
  1150. #define RT5677_I2S_PD7_3 (0x2 << 4)
  1151. #define RT5677_I2S_PD7_4 (0x3 << 4)
  1152. #define RT5677_I2S_PD7_6 (0x4 << 4)
  1153. #define RT5677_I2S_PD7_8 (0x5 << 4)
  1154. #define RT5677_I2S_PD7_12 (0x6 << 4)
  1155. #define RT5677_I2S_PD7_16 (0x7 << 4)
  1156. #define RT5677_I2S_PD8_MASK (0x7 << 0)
  1157. #define RT5677_I2S_PD8_SFT 0
  1158. #define RT5677_I2S_PD8_1 (0x0 << 0)
  1159. #define RT5677_I2S_PD8_2 (0x1 << 0)
  1160. #define RT5677_I2S_PD8_3 (0x2 << 0)
  1161. #define RT5677_I2S_PD8_4 (0x3 << 0)
  1162. #define RT5677_I2S_PD8_6 (0x4 << 0)
  1163. #define RT5677_I2S_PD8_8 (0x5 << 0)
  1164. #define RT5677_I2S_PD8_12 (0x6 << 0)
  1165. #define RT5677_I2S_PD8_16 (0x7 << 0)
  1166. /* Clock Tree Control 3 (0x75) */
  1167. #define RT5677_DSP_ASRC_O_MASK (0x3 << 6)
  1168. #define RT5677_DSP_ASRC_O_SFT 6
  1169. #define RT5677_DSP_ASRC_O_1_0 (0x0 << 6)
  1170. #define RT5677_DSP_ASRC_O_1_5 (0x1 << 6)
  1171. #define RT5677_DSP_ASRC_O_2_0 (0x2 << 6)
  1172. #define RT5677_DSP_ASRC_O_3_0 (0x3 << 6)
  1173. #define RT5677_DSP_ASRC_I_MASK (0x3 << 4)
  1174. #define RT5677_DSP_ASRC_I_SFT 4
  1175. #define RT5677_DSP_ASRC_I_1_0 (0x0 << 4)
  1176. #define RT5677_DSP_ASRC_I_1_5 (0x1 << 4)
  1177. #define RT5677_DSP_ASRC_I_2_0 (0x2 << 4)
  1178. #define RT5677_DSP_ASRC_I_3_0 (0x3 << 4)
  1179. #define RT5677_DSP_BUS_PD_MASK (0x7 << 0)
  1180. #define RT5677_DSP_BUS_PD_SFT 0
  1181. #define RT5677_DSP_BUS_PD_1 (0x0 << 0)
  1182. #define RT5677_DSP_BUS_PD_2 (0x1 << 0)
  1183. #define RT5677_DSP_BUS_PD_3 (0x2 << 0)
  1184. #define RT5677_DSP_BUS_PD_4 (0x3 << 0)
  1185. #define RT5677_DSP_BUS_PD_6 (0x4 << 0)
  1186. #define RT5677_DSP_BUS_PD_8 (0x5 << 0)
  1187. #define RT5677_DSP_BUS_PD_12 (0x6 << 0)
  1188. #define RT5677_DSP_BUS_PD_16 (0x7 << 0)
  1189. #define RT5677_PLL_INP_MAX 40000000
  1190. #define RT5677_PLL_INP_MIN 2048000
  1191. /* PLL M/N/K Code Control 1 (0x7a 0x7c) */
  1192. #define RT5677_PLL_N_MAX 0x1ff
  1193. #define RT5677_PLL_N_MASK (RT5677_PLL_N_MAX << 7)
  1194. #define RT5677_PLL_N_SFT 7
  1195. #define RT5677_PLL_K_BP (0x1 << 5)
  1196. #define RT5677_PLL_K_BP_SFT 5
  1197. #define RT5677_PLL_K_MAX 0x1f
  1198. #define RT5677_PLL_K_MASK (RT5677_PLL_K_MAX)
  1199. #define RT5677_PLL_K_SFT 0
  1200. /* PLL M/N/K Code Control 2 (0x7b 0x7d) */
  1201. #define RT5677_PLL_M_MAX 0xf
  1202. #define RT5677_PLL_M_MASK (RT5677_PLL_M_MAX << 12)
  1203. #define RT5677_PLL_M_SFT 12
  1204. #define RT5677_PLL_M_BP (0x1 << 11)
  1205. #define RT5677_PLL_M_BP_SFT 11
  1206. /* Global Clock Control 1 (0x80) */
  1207. #define RT5677_SCLK_SRC_MASK (0x3 << 14)
  1208. #define RT5677_SCLK_SRC_SFT 14
  1209. #define RT5677_SCLK_SRC_MCLK (0x0 << 14)
  1210. #define RT5677_SCLK_SRC_PLL1 (0x1 << 14)
  1211. #define RT5677_SCLK_SRC_RCCLK (0x2 << 14) /* 25MHz */
  1212. #define RT5677_SCLK_SRC_SLIM (0x3 << 14)
  1213. #define RT5677_PLL1_SRC_MASK (0x7 << 11)
  1214. #define RT5677_PLL1_SRC_SFT 11
  1215. #define RT5677_PLL1_SRC_MCLK (0x0 << 11)
  1216. #define RT5677_PLL1_SRC_BCLK1 (0x1 << 11)
  1217. #define RT5677_PLL1_SRC_BCLK2 (0x2 << 11)
  1218. #define RT5677_PLL1_SRC_BCLK3 (0x3 << 11)
  1219. #define RT5677_PLL1_SRC_BCLK4 (0x4 << 11)
  1220. #define RT5677_PLL1_SRC_RCCLK (0x5 << 11)
  1221. #define RT5677_PLL1_SRC_SLIM (0x6 << 11)
  1222. #define RT5677_MCLK_SRC_MASK (0x1 << 10)
  1223. #define RT5677_MCLK_SRC_SFT 10
  1224. #define RT5677_MCLK1_SRC (0x0 << 10)
  1225. #define RT5677_MCLK2_SRC (0x1 << 10)
  1226. #define RT5677_PLL1_PD_MASK (0x1 << 8)
  1227. #define RT5677_PLL1_PD_SFT 8
  1228. #define RT5677_PLL1_PD_1 (0x0 << 8)
  1229. #define RT5677_PLL1_PD_2 (0x1 << 8)
  1230. #define RT5671_DAC_OSR_MASK (0x3 << 6)
  1231. #define RT5671_DAC_OSR_SFT 6
  1232. #define RT5671_DAC_OSR_128 (0x0 << 6)
  1233. #define RT5671_DAC_OSR_64 (0x1 << 6)
  1234. #define RT5671_DAC_OSR_32 (0x2 << 6)
  1235. #define RT5671_ADC_OSR_MASK (0x3 << 4)
  1236. #define RT5671_ADC_OSR_SFT 4
  1237. #define RT5671_ADC_OSR_128 (0x0 << 4)
  1238. #define RT5671_ADC_OSR_64 (0x1 << 4)
  1239. #define RT5671_ADC_OSR_32 (0x2 << 4)
  1240. /* Global Clock Control 2 (0x81) */
  1241. #define RT5677_PLL2_PR_SRC_MASK (0x1 << 15)
  1242. #define RT5677_PLL2_PR_SRC_SFT 15
  1243. #define RT5677_PLL2_PR_SRC_MCLK1 (0x0 << 15)
  1244. #define RT5677_PLL2_PR_SRC_MCLK2 (0x1 << 15)
  1245. #define RT5677_PLL2_SRC_MASK (0x7 << 12)
  1246. #define RT5677_PLL2_SRC_SFT 12
  1247. #define RT5677_PLL2_SRC_MCLK (0x0 << 12)
  1248. #define RT5677_PLL2_SRC_BCLK1 (0x1 << 12)
  1249. #define RT5677_PLL2_SRC_BCLK2 (0x2 << 12)
  1250. #define RT5677_PLL2_SRC_BCLK3 (0x3 << 12)
  1251. #define RT5677_PLL2_SRC_BCLK4 (0x4 << 12)
  1252. #define RT5677_PLL2_SRC_RCCLK (0x5 << 12)
  1253. #define RT5677_PLL2_SRC_SLIM (0x6 << 12)
  1254. #define RT5671_DSP_ASRC_O_SRC (0x3 << 10)
  1255. #define RT5671_DSP_ASRC_O_SRC_SFT 10
  1256. #define RT5671_DSP_ASRC_O_MCLK (0x0 << 10)
  1257. #define RT5671_DSP_ASRC_O_PLL1 (0x1 << 10)
  1258. #define RT5671_DSP_ASRC_O_SLIM (0x2 << 10)
  1259. #define RT5671_DSP_ASRC_O_RCCLK (0x3 << 10)
  1260. #define RT5671_DSP_ASRC_I_SRC (0x3 << 8)
  1261. #define RT5671_DSP_ASRC_I_SRC_SFT 8
  1262. #define RT5671_DSP_ASRC_I_MCLK (0x0 << 8)
  1263. #define RT5671_DSP_ASRC_I_PLL1 (0x1 << 8)
  1264. #define RT5671_DSP_ASRC_I_SLIM (0x2 << 8)
  1265. #define RT5671_DSP_ASRC_I_RCCLK (0x3 << 8)
  1266. #define RT5677_DSP_CLK_SRC_MASK (0x1 << 7)
  1267. #define RT5677_DSP_CLK_SRC_SFT 7
  1268. #define RT5677_DSP_CLK_SRC_PLL2 (0x0 << 7)
  1269. #define RT5677_DSP_CLK_SRC_BYPASS (0x1 << 7)
  1270. /* VAD Function Control 4 (0x9f) */
  1271. #define RT5677_VAD_SRC_MASK (0x7 << 8)
  1272. #define RT5677_VAD_SRC_SFT 8
  1273. /* DSP InBound Control (0xa3) */
  1274. #define RT5677_IB01_SRC_MASK (0x7 << 12)
  1275. #define RT5677_IB01_SRC_SFT 12
  1276. #define RT5677_IB23_SRC_MASK (0x7 << 8)
  1277. #define RT5677_IB23_SRC_SFT 8
  1278. #define RT5677_IB45_SRC_MASK (0x7 << 4)
  1279. #define RT5677_IB45_SRC_SFT 4
  1280. #define RT5677_IB6_SRC_MASK (0x7 << 0)
  1281. #define RT5677_IB6_SRC_SFT 0
  1282. /* DSP InBound Control (0xa4) */
  1283. #define RT5677_IB7_SRC_MASK (0x7 << 12)
  1284. #define RT5677_IB7_SRC_SFT 12
  1285. #define RT5677_IB8_SRC_MASK (0x7 << 8)
  1286. #define RT5677_IB8_SRC_SFT 8
  1287. #define RT5677_IB9_SRC_MASK (0x7 << 4)
  1288. #define RT5677_IB9_SRC_SFT 4
  1289. /* DSP In/OutBound Control (0xa5) */
  1290. #define RT5677_SEL_SRC_OB23 (0x1 << 4)
  1291. #define RT5677_SEL_SRC_OB23_SFT 4
  1292. #define RT5677_SEL_SRC_OB01 (0x1 << 3)
  1293. #define RT5677_SEL_SRC_OB01_SFT 3
  1294. #define RT5677_SEL_SRC_IB45 (0x1 << 2)
  1295. #define RT5677_SEL_SRC_IB45_SFT 2
  1296. #define RT5677_SEL_SRC_IB23 (0x1 << 1)
  1297. #define RT5677_SEL_SRC_IB23_SFT 1
  1298. #define RT5677_SEL_SRC_IB01 (0x1 << 0)
  1299. #define RT5677_SEL_SRC_IB01_SFT 0
  1300. /* Virtual DSP Mixer Control (0xf7 0xf8 0xf9) */
  1301. #define RT5677_DSP_IB_01_H (0x1 << 15)
  1302. #define RT5677_DSP_IB_01_H_SFT 15
  1303. #define RT5677_DSP_IB_23_H (0x1 << 14)
  1304. #define RT5677_DSP_IB_23_H_SFT 14
  1305. #define RT5677_DSP_IB_45_H (0x1 << 13)
  1306. #define RT5677_DSP_IB_45_H_SFT 13
  1307. #define RT5677_DSP_IB_6_H (0x1 << 12)
  1308. #define RT5677_DSP_IB_6_H_SFT 12
  1309. #define RT5677_DSP_IB_7_H (0x1 << 11)
  1310. #define RT5677_DSP_IB_7_H_SFT 11
  1311. #define RT5677_DSP_IB_8_H (0x1 << 10)
  1312. #define RT5677_DSP_IB_8_H_SFT 10
  1313. #define RT5677_DSP_IB_9_H (0x1 << 9)
  1314. #define RT5677_DSP_IB_9_H_SFT 9
  1315. #define RT5677_DSP_IB_01_L (0x1 << 7)
  1316. #define RT5677_DSP_IB_01_L_SFT 7
  1317. #define RT5677_DSP_IB_23_L (0x1 << 6)
  1318. #define RT5677_DSP_IB_23_L_SFT 6
  1319. #define RT5677_DSP_IB_45_L (0x1 << 5)
  1320. #define RT5677_DSP_IB_45_L_SFT 5
  1321. #define RT5677_DSP_IB_6_L (0x1 << 4)
  1322. #define RT5677_DSP_IB_6_L_SFT 4
  1323. #define RT5677_DSP_IB_7_L (0x1 << 3)
  1324. #define RT5677_DSP_IB_7_L_SFT 3
  1325. #define RT5677_DSP_IB_8_L (0x1 << 2)
  1326. #define RT5677_DSP_IB_8_L_SFT 2
  1327. #define RT5677_DSP_IB_9_L (0x1 << 1)
  1328. #define RT5677_DSP_IB_9_L_SFT 1
  1329. #define RT5677_SW_RESET 0x10EC
  1330. /* System Clock Source */
  1331. enum {
  1332. RT5677_SCLK_S_MCLK,
  1333. RT5677_SCLK_S_PLL1,
  1334. RT5677_SCLK_S_RCCLK,
  1335. };
  1336. /* PLL1 Source */
  1337. enum {
  1338. RT5677_PLL1_S_MCLK,
  1339. RT5677_PLL1_S_BCLK1,
  1340. RT5677_PLL1_S_BCLK2,
  1341. RT5677_PLL1_S_BCLK3,
  1342. RT5677_PLL1_S_BCLK4,
  1343. };
  1344. enum {
  1345. RT5677_AIF1,
  1346. RT5677_AIF2,
  1347. RT5677_AIF3,
  1348. RT5677_AIF4,
  1349. RT5677_AIF5,
  1350. RT5677_AIFS,
  1351. };
  1352. #endif /* __DRIVERS_SOUND_RT5677_H__ */