max98095.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * max98095.c -- MAX98095 ALSA SoC Audio driver
  4. *
  5. * Copyright 2011 Maxim Integrated Products
  6. *
  7. * Modified for U-Boot by R. Chandrasekar (rcsekar@samsung.com)
  8. */
  9. #include <common.h>
  10. #include <audio_codec.h>
  11. #include <dm.h>
  12. #include <div64.h>
  13. #include <fdtdec.h>
  14. #include <i2c.h>
  15. #include <log.h>
  16. #include <sound.h>
  17. #include <asm/gpio.h>
  18. #include "i2s.h"
  19. #include "max98095.h"
  20. /* Index 0 is reserved. */
  21. int rate_table[] = {0, 8000, 11025, 16000, 22050, 24000, 32000, 44100, 48000,
  22. 88200, 96000};
  23. /*
  24. * codec mclk clock divider coefficients based on sampling rate
  25. *
  26. * @param rate sampling rate
  27. * @param value address of indexvalue to be stored
  28. *
  29. * @return 0 for success or negative error code.
  30. */
  31. static int rate_value(int rate, u8 *value)
  32. {
  33. int i;
  34. for (i = 1; i < ARRAY_SIZE(rate_table); i++) {
  35. if (rate_table[i] >= rate) {
  36. *value = i;
  37. return 0;
  38. }
  39. }
  40. *value = 1;
  41. return -EINVAL;
  42. }
  43. /*
  44. * Sets hw params for max98095
  45. *
  46. * @param priv max98095 information pointer
  47. * @param rate Sampling rate
  48. * @param bits_per_sample Bits per sample
  49. *
  50. * @return 0 for success or negative error code.
  51. */
  52. static int max98095_hw_params(struct maxim_priv *priv,
  53. enum en_max_audio_interface aif_id,
  54. unsigned int rate, unsigned int bits_per_sample)
  55. {
  56. u8 regval;
  57. int error;
  58. unsigned short M98095_DAI_CLKMODE;
  59. unsigned short M98095_DAI_FORMAT;
  60. unsigned short M98095_DAI_FILTERS;
  61. if (aif_id == AIF1) {
  62. M98095_DAI_CLKMODE = M98095_027_DAI1_CLKMODE;
  63. M98095_DAI_FORMAT = M98095_02A_DAI1_FORMAT;
  64. M98095_DAI_FILTERS = M98095_02E_DAI1_FILTERS;
  65. } else {
  66. M98095_DAI_CLKMODE = M98095_031_DAI2_CLKMODE;
  67. M98095_DAI_FORMAT = M98095_034_DAI2_FORMAT;
  68. M98095_DAI_FILTERS = M98095_038_DAI2_FILTERS;
  69. }
  70. switch (bits_per_sample) {
  71. case 16:
  72. error = maxim_bic_or(priv, M98095_DAI_FORMAT, M98095_DAI_WS, 0);
  73. break;
  74. case 24:
  75. error = maxim_bic_or(priv, M98095_DAI_FORMAT, M98095_DAI_WS,
  76. M98095_DAI_WS);
  77. break;
  78. default:
  79. debug("%s: Illegal bits per sample %d.\n",
  80. __func__, bits_per_sample);
  81. return -EINVAL;
  82. }
  83. if (rate_value(rate, &regval)) {
  84. debug("%s: Failed to set sample rate to %d.\n",
  85. __func__, rate);
  86. return -EINVAL;
  87. }
  88. priv->rate = rate;
  89. error |= maxim_bic_or(priv, M98095_DAI_CLKMODE, M98095_CLKMODE_MASK,
  90. regval);
  91. /* Update sample rate mode */
  92. if (rate < 50000)
  93. error |= maxim_bic_or(priv, M98095_DAI_FILTERS,
  94. M98095_DAI_DHF, 0);
  95. else
  96. error |= maxim_bic_or(priv, M98095_DAI_FILTERS,
  97. M98095_DAI_DHF, M98095_DAI_DHF);
  98. if (error < 0) {
  99. debug("%s: Error setting hardware params.\n", __func__);
  100. return -EIO;
  101. }
  102. return 0;
  103. }
  104. /*
  105. * Configures Audio interface system clock for the given frequency
  106. *
  107. * @param priv max98095 information
  108. * @param freq Sampling frequency in Hz
  109. *
  110. * @return 0 for success or negative error code.
  111. */
  112. static int max98095_set_sysclk(struct maxim_priv *priv, unsigned int freq)
  113. {
  114. int error = 0;
  115. /* Requested clock frequency is already setup */
  116. if (freq == priv->sysclk)
  117. return 0;
  118. /* Setup clocks for slave mode, and using the PLL
  119. * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
  120. * 0x02 (when master clk is 20MHz to 40MHz)..
  121. * 0x03 (when master clk is 40MHz to 60MHz)..
  122. */
  123. if ((freq >= 10000000) && (freq < 20000000)) {
  124. error = maxim_i2c_write(priv, M98095_026_SYS_CLK, 0x10);
  125. } else if ((freq >= 20000000) && (freq < 40000000)) {
  126. error = maxim_i2c_write(priv, M98095_026_SYS_CLK, 0x20);
  127. } else if ((freq >= 40000000) && (freq < 60000000)) {
  128. error = maxim_i2c_write(priv, M98095_026_SYS_CLK, 0x30);
  129. } else {
  130. debug("%s: Invalid master clock frequency\n", __func__);
  131. return -EINVAL;
  132. }
  133. debug("%s: Clock at %uHz\n", __func__, freq);
  134. if (error < 0)
  135. return -EIO;
  136. priv->sysclk = freq;
  137. return 0;
  138. }
  139. /*
  140. * Sets Max98095 I2S format
  141. *
  142. * @param priv max98095 information
  143. * @param fmt i2S format - supports a subset of the options defined
  144. * in i2s.h.
  145. *
  146. * @return 0 for success or negative error code.
  147. */
  148. static int max98095_set_fmt(struct maxim_priv *priv, int fmt,
  149. enum en_max_audio_interface aif_id)
  150. {
  151. u8 regval = 0;
  152. int error = 0;
  153. unsigned short M98095_DAI_CLKCFG_HI;
  154. unsigned short M98095_DAI_CLKCFG_LO;
  155. unsigned short M98095_DAI_FORMAT;
  156. unsigned short M98095_DAI_CLOCK;
  157. if (fmt == priv->fmt)
  158. return 0;
  159. priv->fmt = fmt;
  160. if (aif_id == AIF1) {
  161. M98095_DAI_CLKCFG_HI = M98095_028_DAI1_CLKCFG_HI;
  162. M98095_DAI_CLKCFG_LO = M98095_029_DAI1_CLKCFG_LO;
  163. M98095_DAI_FORMAT = M98095_02A_DAI1_FORMAT;
  164. M98095_DAI_CLOCK = M98095_02B_DAI1_CLOCK;
  165. } else {
  166. M98095_DAI_CLKCFG_HI = M98095_032_DAI2_CLKCFG_HI;
  167. M98095_DAI_CLKCFG_LO = M98095_033_DAI2_CLKCFG_LO;
  168. M98095_DAI_FORMAT = M98095_034_DAI2_FORMAT;
  169. M98095_DAI_CLOCK = M98095_035_DAI2_CLOCK;
  170. }
  171. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  172. case SND_SOC_DAIFMT_CBS_CFS:
  173. /* Slave mode PLL */
  174. error |= maxim_i2c_write(priv, M98095_DAI_CLKCFG_HI, 0x80);
  175. error |= maxim_i2c_write(priv, M98095_DAI_CLKCFG_LO, 0x00);
  176. break;
  177. case SND_SOC_DAIFMT_CBM_CFM:
  178. /* Set to master mode */
  179. regval |= M98095_DAI_MAS;
  180. break;
  181. case SND_SOC_DAIFMT_CBS_CFM:
  182. case SND_SOC_DAIFMT_CBM_CFS:
  183. default:
  184. debug("%s: Clock mode unsupported\n", __func__);
  185. return -EINVAL;
  186. }
  187. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  188. case SND_SOC_DAIFMT_I2S:
  189. regval |= M98095_DAI_DLY;
  190. break;
  191. case SND_SOC_DAIFMT_LEFT_J:
  192. break;
  193. default:
  194. debug("%s: Unrecognized format.\n", __func__);
  195. return -EINVAL;
  196. }
  197. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  198. case SND_SOC_DAIFMT_NB_NF:
  199. break;
  200. case SND_SOC_DAIFMT_NB_IF:
  201. regval |= M98095_DAI_WCI;
  202. break;
  203. case SND_SOC_DAIFMT_IB_NF:
  204. regval |= M98095_DAI_BCI;
  205. break;
  206. case SND_SOC_DAIFMT_IB_IF:
  207. regval |= M98095_DAI_BCI | M98095_DAI_WCI;
  208. break;
  209. default:
  210. debug("%s: Unrecognized inversion settings.\n", __func__);
  211. return -EINVAL;
  212. }
  213. error |= maxim_bic_or(priv, M98095_DAI_FORMAT,
  214. M98095_DAI_MAS | M98095_DAI_DLY |
  215. M98095_DAI_BCI | M98095_DAI_WCI, regval);
  216. error |= maxim_i2c_write(priv, M98095_DAI_CLOCK, M98095_DAI_BSEL64);
  217. if (error < 0) {
  218. debug("%s: Error setting i2s format.\n", __func__);
  219. return -EIO;
  220. }
  221. return 0;
  222. }
  223. /*
  224. * resets the audio codec
  225. *
  226. * @param priv Private data for driver
  227. * @return 0 for success or negative error code.
  228. */
  229. static int max98095_reset(struct maxim_priv *priv)
  230. {
  231. int i, ret;
  232. /*
  233. * Gracefully reset the DSP core and the codec hardware in a proper
  234. * sequence.
  235. */
  236. ret = maxim_i2c_write(priv, M98095_00F_HOST_CFG, 0);
  237. if (ret != 0) {
  238. debug("%s: Failed to reset DSP: %d\n", __func__, ret);
  239. return ret;
  240. }
  241. ret = maxim_i2c_write(priv, M98095_097_PWR_SYS, 0);
  242. if (ret != 0) {
  243. debug("%s: Failed to reset codec: %d\n", __func__, ret);
  244. return ret;
  245. }
  246. /*
  247. * Reset to hardware default for registers, as there is not a soft
  248. * reset hardware control register.
  249. */
  250. for (i = M98095_010_HOST_INT_CFG; i < M98095_REG_MAX_CACHED; i++) {
  251. ret = maxim_i2c_write(priv, i, 0);
  252. if (ret < 0) {
  253. debug("%s: Failed to reset: %d\n", __func__, ret);
  254. return ret;
  255. }
  256. }
  257. return 0;
  258. }
  259. /*
  260. * Intialise max98095 codec device
  261. *
  262. * @param priv max98095 information
  263. * @return 0 for success or negative error code.
  264. */
  265. static int max98095_device_init(struct maxim_priv *priv)
  266. {
  267. unsigned char id;
  268. int ret;
  269. /* reset the codec, the DSP core, and disable all interrupts */
  270. ret = max98095_reset(priv);
  271. if (ret != 0) {
  272. debug("Reset\n");
  273. return ret;
  274. }
  275. /* initialize private data */
  276. priv->sysclk = -1U;
  277. priv->rate = -1U;
  278. priv->fmt = -1U;
  279. ret = maxim_i2c_read(priv, M98095_0FF_REV_ID, &id);
  280. if (ret < 0) {
  281. debug("%s: Failure reading hardware revision: %d\n",
  282. __func__, id);
  283. return ret;
  284. }
  285. debug("%s: Hardware revision: %c\n", __func__, (id - 0x40) + 'A');
  286. return 0;
  287. }
  288. static int max98095_setup_interface(struct maxim_priv *priv,
  289. enum en_max_audio_interface aif_id)
  290. {
  291. int error;
  292. error = maxim_i2c_write(priv, M98095_097_PWR_SYS, M98095_PWRSV);
  293. /*
  294. * initialize registers to hardware default configuring audio
  295. * interface2 to DAC
  296. */
  297. if (aif_id == AIF1)
  298. error |= maxim_i2c_write(priv, M98095_048_MIX_DAC_LR,
  299. M98095_DAI1L_TO_DACL |
  300. M98095_DAI1R_TO_DACR);
  301. else
  302. error |= maxim_i2c_write(priv, M98095_048_MIX_DAC_LR,
  303. M98095_DAI2M_TO_DACL |
  304. M98095_DAI2M_TO_DACR);
  305. error |= maxim_i2c_write(priv, M98095_092_PWR_EN_OUT,
  306. M98095_SPK_SPREADSPECTRUM);
  307. error |= maxim_i2c_write(priv, M98095_04E_CFG_HP, M98095_HPNORMAL);
  308. if (aif_id == AIF1)
  309. error |= maxim_i2c_write(priv, M98095_02C_DAI1_IOCFG,
  310. M98095_S1NORMAL | M98095_SDATA);
  311. else
  312. error |= maxim_i2c_write(priv, M98095_036_DAI2_IOCFG,
  313. M98095_S2NORMAL | M98095_SDATA);
  314. /* take the codec out of the shut down */
  315. error |= maxim_bic_or(priv, M98095_097_PWR_SYS, M98095_SHDNRUN,
  316. M98095_SHDNRUN);
  317. /*
  318. * route DACL and DACR output to HO and Speakers
  319. * Ordering: DACL, DACR, DACL, DACR
  320. */
  321. error |= maxim_i2c_write(priv, M98095_050_MIX_SPK_LEFT, 0x01);
  322. error |= maxim_i2c_write(priv, M98095_051_MIX_SPK_RIGHT, 0x01);
  323. error |= maxim_i2c_write(priv, M98095_04C_MIX_HP_LEFT, 0x01);
  324. error |= maxim_i2c_write(priv, M98095_04D_MIX_HP_RIGHT, 0x01);
  325. /* power Enable */
  326. error |= maxim_i2c_write(priv, M98095_091_PWR_EN_OUT, 0xF3);
  327. /* set Volume */
  328. error |= maxim_i2c_write(priv, M98095_064_LVL_HP_L, 15);
  329. error |= maxim_i2c_write(priv, M98095_065_LVL_HP_R, 15);
  330. error |= maxim_i2c_write(priv, M98095_067_LVL_SPK_L, 16);
  331. error |= maxim_i2c_write(priv, M98095_068_LVL_SPK_R, 16);
  332. /* Enable DAIs */
  333. error |= maxim_i2c_write(priv, M98095_093_BIAS_CTRL, 0x30);
  334. if (aif_id == AIF1)
  335. error |= maxim_i2c_write(priv, M98095_096_PWR_DAC_CK, 0x01);
  336. else
  337. error |= maxim_i2c_write(priv, M98095_096_PWR_DAC_CK, 0x07);
  338. if (error < 0)
  339. return -EIO;
  340. return 0;
  341. }
  342. static int max98095_do_init(struct maxim_priv *priv,
  343. enum en_max_audio_interface aif_id,
  344. int sampling_rate, int mclk_freq,
  345. int bits_per_sample)
  346. {
  347. int ret = 0;
  348. ret = max98095_setup_interface(priv, aif_id);
  349. if (ret < 0) {
  350. debug("%s: max98095 setup interface failed\n", __func__);
  351. return ret;
  352. }
  353. ret = max98095_set_sysclk(priv, mclk_freq);
  354. if (ret < 0) {
  355. debug("%s: max98095 codec set sys clock failed\n", __func__);
  356. return ret;
  357. }
  358. ret = max98095_hw_params(priv, aif_id, sampling_rate,
  359. bits_per_sample);
  360. if (ret == 0) {
  361. ret = max98095_set_fmt(priv, SND_SOC_DAIFMT_I2S |
  362. SND_SOC_DAIFMT_NB_NF |
  363. SND_SOC_DAIFMT_CBS_CFS,
  364. aif_id);
  365. }
  366. return ret;
  367. }
  368. static int max98095_set_params(struct udevice *dev, int interface, int rate,
  369. int mclk_freq, int bits_per_sample,
  370. uint channels)
  371. {
  372. struct maxim_priv *priv = dev_get_priv(dev);
  373. return max98095_do_init(priv, interface, rate, mclk_freq,
  374. bits_per_sample);
  375. }
  376. static int max98095_probe(struct udevice *dev)
  377. {
  378. struct maxim_priv *priv = dev_get_priv(dev);
  379. int ret;
  380. priv->dev = dev;
  381. ret = max98095_device_init(priv);
  382. if (ret < 0) {
  383. debug("%s: max98095 codec chip init failed\n", __func__);
  384. return ret;
  385. }
  386. return 0;
  387. }
  388. static const struct audio_codec_ops max98095_ops = {
  389. .set_params = max98095_set_params,
  390. };
  391. static const struct udevice_id max98095_ids[] = {
  392. { .compatible = "maxim,max98095" },
  393. { }
  394. };
  395. U_BOOT_DRIVER(max98095) = {
  396. .name = "max98095",
  397. .id = UCLASS_AUDIO_CODEC,
  398. .of_match = max98095_ids,
  399. .probe = max98095_probe,
  400. .ops = &max98095_ops,
  401. .priv_auto_alloc_size = sizeof(struct maxim_priv),
  402. };