max98090.h 24 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * max98090.h -- MAX98090 ALSA SoC Audio driver
  4. *
  5. * Copyright 2011 Maxim Integrated Products
  6. */
  7. #ifndef _MAX98090_H
  8. #define _MAX98090_H
  9. #include "maxim_codec.h"
  10. /* MAX98090 Registers Definition */
  11. #define M98090_REG_SOFTWARE_RESET 0x00
  12. #define M98090_REG_DEVICE_STATUS 0x01
  13. #define M98090_REG_QUICK_SAMPLE_RATE 0x05
  14. #define M98090_REG_DAI_INTERFACE 0x06
  15. #define M98090_REG_DAC_PATH 0x07
  16. #define M98090_REG_MIC_BIAS_VOLTAGE 0x12
  17. #define M98090_REG_DIGITAL_MIC_ENABLE 0x13
  18. #define M98090_REG_DIGITAL_MIC_CONFIG 0x14
  19. #define M98090_REG_SYSTEM_CLOCK 0x1B
  20. #define M98090_REG_CLOCK_RATIO_NI_MSB 0x1D
  21. #define M98090_REG_CLOCK_MODE 0x1C
  22. #define M98090_REG_CLOCK_RATIO_NI_LSB 0x1E
  23. #define M98090_REG_MASTER_MODE 0x21
  24. #define M98090_REG_INTERFACE_FORMAT 0x22
  25. #define M98090_REG_IO_CONFIGURATION 0x25
  26. #define M98090_REG_FILTER_CONFIG 0x26
  27. #define M98090_REG_LEFT_HP_MIXER 0x29
  28. #define M98090_REG_RIGHT_HP_MIXER 0x2a
  29. #define M98090_REG_HP_CONTROL 0x2b
  30. #define M98090_REG_LEFT_HP_VOLUME 0x2c
  31. #define M98090_REG_RIGHT_HP_VOLUME 0x2d
  32. #define M98090_REG_LEFT_SPK_MIXER 0x2e
  33. #define M98090_REG_RIGHT_SPK_MIXER 0x2f
  34. #define M98090_REG_SPK_CONTROL 0x30
  35. #define M98090_REG_LEFT_SPK_VOLUME 0x31
  36. #define M98090_REG_RIGHT_SPK_VOLUME 0x32
  37. #define M98090_REG_RCV_LOUTL_CONTROL 0x38
  38. #define M98090_REG_RCV_LOUTL_VOLUME 0x39
  39. #define M98090_REG_LOUTR_MIXER 0x3a
  40. #define M98090_REG_LOUTR_CONTROL 0x3b
  41. #define M98090_REG_LOUTR_VOLUME 0x3c
  42. #define M98090_REG_JACK_DETECT 0x3d
  43. #define M98090_REG_INPUT_ENABLE 0x3e
  44. #define M98090_REG_OUTPUT_ENABLE 0x3f
  45. #define M98090_REG_LEVEL_CONTROL 0x40
  46. #define M98090_REG_DSP_FILTER_ENABLE 0x41
  47. #define M98090_REG_BIAS_CONTROL 0x42
  48. #define M98090_REG_DAC_CONTROL 0x43
  49. #define M98090_REG_ADC_CONTROL 0x44
  50. #define M98090_REG_DEVICE_SHUTDOWN 0x45
  51. #define M98090_REG_REVISION_ID 0xff
  52. #define M98090_REG_CNT (0xff + 1)
  53. #define M98090_REG_MAX_CACHed 0x45
  54. /* MAX98090 Registers Bit Fields */
  55. /*
  56. * M98090_REG_SOFTWARE_RESET 0x00
  57. */
  58. #define M98090_SWRESET_MASK BIT(7)
  59. /*
  60. * M98090_REG_QUICK_SAMPLE_RATE 0x05
  61. */
  62. #define M98090_SR_96K_MASK BIT(5)
  63. #define M98090_SR_96K_SHIFT 5
  64. #define M98090_SR_96K_WIDTH 1
  65. #define M98090_SR_32K_MASK BIT(4)
  66. #define M98090_SR_32K_SHIFT 4
  67. #define M98090_SR_32K_WIDTH 1
  68. #define M98090_SR_48K_MASK BIT(3)
  69. #define M98090_SR_48K_SHIFT 3
  70. #define M98090_SR_48K_WIDTH 1
  71. #define M98090_SR_44K1_MASK BIT(2)
  72. #define M98090_SR_44K1_SHIFT 2
  73. #define M98090_SR_44K1_WIDTH 1
  74. #define M98090_SR_16K_MASK BIT(1)
  75. #define M98090_SR_16K_SHIFT 1
  76. #define M98090_SR_16K_WIDTH 1
  77. #define M98090_SR_8K_MASK BIT(0)
  78. #define M98090_SR_8K_SHIFT 0
  79. #define M98090_SR_8K_WIDTH 1
  80. #define M98090_SR_MASK 0x3F
  81. #define M98090_SR_ALL_SHIFT 0
  82. #define M98090_SR_ALL_WIDTH 8
  83. #define M98090_SR_ALL_NUM BIT(M98090_SR_ALL_WIDTH)
  84. /*
  85. * M98090_REG_DAI_INTERFACE 0x06
  86. */
  87. #define M98090_RJ_M_MASK BIT(5)
  88. #define M98090_RJ_M_SHIFT 5
  89. #define M98090_RJ_M_WIDTH 1
  90. #define M98090_RJ_S_MASK BIT(4)
  91. #define M98090_RJ_S_SHIFT 4
  92. #define M98090_RJ_S_WIDTH 1
  93. #define M98090_LJ_M_MASK BIT(3)
  94. #define M98090_LJ_M_SHIFT 3
  95. #define M98090_LJ_M_WIDTH 1
  96. #define M98090_LJ_S_MASK BIT(2)
  97. #define M98090_LJ_S_SHIFT 2
  98. #define M98090_LJ_S_WIDTH 1
  99. #define M98090_I2S_M_MASK BIT(1)
  100. #define M98090_I2S_M_SHIFT 1
  101. #define M98090_I2S_M_WIDTH 1
  102. #define M98090_I2S_S_MASK BIT(0)
  103. #define M98090_I2S_S_SHIFT 0
  104. #define M98090_I2S_S_WIDTH 1
  105. #define M98090_DAI_ALL_SHIFT 0
  106. #define M98090_DAI_ALL_WIDTH 8
  107. #define M98090_DAI_ALL_NUM BIT(M98090_DAI_ALL_WIDTH)
  108. /*
  109. * M98090_REG_DAC_PATH 0x07
  110. */
  111. #define M98090_DIG2_HP_MASK BIT(7)
  112. #define M98090_DIG2_HP_SHIFT 7
  113. #define M98090_DIG2_HP_WIDTH 1
  114. #define M98090_DIG2_EAR_MASK BIT(6)
  115. #define M98090_DIG2_EAR_SHIFT 6
  116. #define M98090_DIG2_EAR_WIDTH 1
  117. #define M98090_DIG2_SPK_MASK BIT(5)
  118. #define M98090_DIG2_SPK_SHIFT 5
  119. #define M98090_DIG2_SPK_WIDTH 1
  120. #define M98090_DIG2_LOUT_MASK BIT(4)
  121. #define M98090_DIG2_LOUT_SHIFT 4
  122. #define M98090_DIG2_LOUT_WIDTH 1
  123. #define M98090_DIG2_ALL_SHIFT 0
  124. #define M98090_DIG2_ALL_WIDTH 8
  125. #define M98090_DIG2_ALL_NUM BIT(M98090_DIG2_ALL_WIDTH)
  126. /*
  127. * M98090_REG_MIC_BIAS_VOLTAGE 0x12
  128. */
  129. #define M98090_MBVSEL_MASK (3 << 0)
  130. #define M98090_MBVSEL_SHIFT 0
  131. #define M98090_MBVSEL_WIDTH 2
  132. #define M98090_MBVSEL_2V8 (3 << 0)
  133. #define M98090_MBVSEL_2V55 (2 << 0)
  134. #define M98090_MBVSEL_2V4 BIT(0)
  135. #define M98090_MBVSEL_2V2 (0 << 0)
  136. /*
  137. * M98090_REG_DIGITAL_MIC_ENABLE 0x13
  138. */
  139. #define M98090_MICCLK_MASK (7 << 4)
  140. #define M98090_MICCLK_SHIFT 4
  141. #define M98090_MICCLK_WIDTH 3
  142. #define M98090_DIGMIC4_MASK BIT(3)
  143. #define M98090_DIGMIC4_SHIFT 3
  144. #define M98090_DIGMIC4_WIDTH 1
  145. #define M98090_DIGMIC4_NUM BIT(M98090_DIGMIC4_WIDTH)
  146. #define M98090_DIGMIC3_MASK BIT(2)
  147. #define M98090_DIGMIC3_SHIFT 2
  148. #define M98090_DIGMIC3_WIDTH 1
  149. #define M98090_DIGMIC3_NUM BIT(M98090_DIGMIC3_WIDTH)
  150. #define M98090_DIGMICR_MASK BIT(1)
  151. #define M98090_DIGMICR_SHIFT 1
  152. #define M98090_DIGMICR_WIDTH 1
  153. #define M98090_DIGMICR_NUM BIT(M98090_DIGMICR_WIDTH)
  154. #define M98090_DIGMICL_MASK BIT(0)
  155. #define M98090_DIGMICL_SHIFT 0
  156. #define M98090_DIGMICL_WIDTH 1
  157. #define M98090_DIGMICL_NUM BIT(M98090_DIGMICL_WIDTH)
  158. /*
  159. * M98090_REG_DIGITAL_MIC_CONFIG 0x14
  160. */
  161. #define M98090_DMIC_COMP_MASK (15 << 4)
  162. #define M98090_DMIC_COMP_SHIFT 4
  163. #define M98090_DMIC_COMP_WIDTH 4
  164. #define M98090_DMIC_COMP_NUM BIT(M98090_DMIC_COMP_WIDTH)
  165. #define M98090_DMIC_FREQ_MASK (3 << 0)
  166. #define M98090_DMIC_FREQ_SHIFT 0
  167. #define M98090_DMIC_FREQ_WIDTH 2
  168. /*
  169. * M98090_REG_CLOCK_MODE 0x1B
  170. */
  171. #define M98090_PSCLK_MASK (3 << 4)
  172. #define M98090_PSCLK_SHIFT 4
  173. #define M98090_PSCLK_WIDTH 2
  174. #define M98090_PSCLK_DISABLED (0 << 4)
  175. #define M98090_PSCLK_DIV1 BIT(4)
  176. #define M98090_PSCLK_DIV2 (2 << 4)
  177. #define M98090_PSCLK_DIV4 (3 << 4)
  178. /*
  179. * M98090_REG_INTERFACE_FORMAT 0x22
  180. */
  181. #define M98090_RJ_MASK BIT(5)
  182. #define M98090_RJ_SHIFT 5
  183. #define M98090_RJ_WIDTH 1
  184. #define M98090_WCI_MASK BIT(4)
  185. #define M98090_WCI_SHIFT 4
  186. #define M98090_WCI_WIDTH 1
  187. #define M98090_BCI_MASK BIT(3)
  188. #define M98090_BCI_SHIFT 3
  189. #define M98090_BCI_WIDTH 1
  190. #define M98090_DLY_MASK BIT(2)
  191. #define M98090_DLY_SHIFT 2
  192. #define M98090_DLY_WIDTH 1
  193. #define M98090_WS_MASK (3 << 0)
  194. #define M98090_WS_SHIFT 0
  195. #define M98090_WS_WIDTH 2
  196. #define M98090_WS_NUM BIT(M98090_WS_WIDTH)
  197. /* M98090_REG_IO_CONFIGURATION 0x25 */
  198. #define M98090_LTEN_MASK BIT(5)
  199. #define M98090_LTEN_SHIFT 5
  200. #define M98090_LTEN_WIDTH 1
  201. #define M98090_LTEN_NUM BIT(M98090_LTEN_WIDTH)
  202. #define M98090_LBEN_MASK BIT(4)
  203. #define M98090_LBEN_SHIFT 4
  204. #define M98090_LBEN_WIDTH 1
  205. #define M98090_LBEN_NUM BIT(M98090_LBEN_WIDTH)
  206. #define M98090_DMONO_MASK BIT(3)
  207. #define M98090_DMONO_SHIFT 3
  208. #define M98090_DMONO_WIDTH 1
  209. #define M98090_DMONO_NUM BIT(M98090_DMONO_WIDTH)
  210. #define M98090_HIZOFF_MASK BIT(2)
  211. #define M98090_HIZOFF_SHIFT 2
  212. #define M98090_HIZOFF_WIDTH 1
  213. #define M98090_HIZOFF_NUM BIT(M98090_HIZOFF_WIDTH)
  214. #define M98090_SDOEN_MASK BIT(1)
  215. #define M98090_SDOEN_SHIFT 1
  216. #define M98090_SDOEN_WIDTH 1
  217. #define M98090_SDOEN_NUM BIT(M98090_SDOEN_WIDTH)
  218. #define M98090_SDIEN_MASK BIT(0)
  219. #define M98090_SDIEN_SHIFT 0
  220. #define M98090_SDIEN_WIDTH 1
  221. #define M98090_SDIEN_NUM BIT(M98090_SDIEN_WIDTH)
  222. /*
  223. * M98090_REG_FILTER_CONFIG 0x26
  224. */
  225. #define M98090_MODE_MASK BIT(7)
  226. #define M98090_MODE_SHIFT 7
  227. #define M98090_MODE_WIDTH 1
  228. #define M98090_AHPF_MASK BIT(6)
  229. #define M98090_AHPF_SHIFT 6
  230. #define M98090_AHPF_WIDTH 1
  231. #define M98090_AHPF_NUM BIT(M98090_AHPF_WIDTH)
  232. #define M98090_DHPF_MASK BIT(5)
  233. #define M98090_DHPF_SHIFT 5
  234. #define M98090_DHPF_WIDTH 1
  235. #define M98090_DHPF_NUM BIT(M98090_DHPF_WIDTH)
  236. #define M98090_DHF_MASK BIT(4)
  237. #define M98090_DHF_SHIFT 4
  238. #define M98090_DHF_WIDTH 1
  239. #define M98090_FLT_DMIC34MODE_MASK BIT(3)
  240. #define M98090_FLT_DMIC34MODE_SHIFT 3
  241. #define M98090_FLT_DMIC34MODE_WIDTH 1
  242. #define M98090_FLT_DMIC34HPF_MASK BIT(2)
  243. #define M98090_FLT_DMIC34HPF_SHIFT 2
  244. #define M98090_FLT_DMIC34HPF_WIDTH 1
  245. #define M98090_FLT_DMIC34HPF_NUM BIT(M98090_FLT_DMIC34HPF_WIDTH)
  246. /*
  247. * M98090_REG_CLOCK_MODE
  248. */
  249. #define M98090_FREQ_MASK (15 << 4)
  250. #define M98090_FREQ_SHIFT 4
  251. #define M98090_FREQ_WIDTH 4
  252. #define M98090_USE_M1_MASK BIT(0)
  253. #define M98090_USE_M1_SHIFT 0
  254. #define M98090_USE_M1_WIDTH 1
  255. #define M98090_USE_M1_NUM BIT(M98090_USE_M1_WIDTH)
  256. /*
  257. * M98090_REG_LEFT_HP_MIXER 0x29
  258. */
  259. #define M98090_MIXHPL_MIC2_MASK BIT(5)
  260. #define M98090_MIXHPL_MIC2_SHIFT 5
  261. #define M98090_MIXHPL_MIC2_WIDTH 1
  262. #define M98090_MIXHPL_MIC1_MASK BIT(4)
  263. #define M98090_MIXHPL_MIC1_SHIFT 4
  264. #define M98090_MIXHPL_MIC1_WIDTH 1
  265. #define M98090_MIXHPL_LINEB_MASK BIT(3)
  266. #define M98090_MIXHPL_LINEB_SHIFT 3
  267. #define M98090_MIXHPL_LINEB_WIDTH 1
  268. #define M98090_MIXHPL_LINEA_MASK BIT(2)
  269. #define M98090_MIXHPL_LINEA_SHIFT 2
  270. #define M98090_MIXHPL_LINEA_WIDTH 1
  271. #define M98090_MIXHPL_DACR_MASK BIT(1)
  272. #define M98090_MIXHPL_DACR_SHIFT 1
  273. #define M98090_MIXHPL_DACR_WIDTH 1
  274. #define M98090_MIXHPL_DACL_MASK BIT(0)
  275. #define M98090_MIXHPL_DACL_SHIFT 0
  276. #define M98090_MIXHPL_DACL_WIDTH 1
  277. #define M98090_MIXHPL_MASK (63 << 0)
  278. #define M98090_MIXHPL_SHIFT 0
  279. #define M98090_MIXHPL_WIDTH 6
  280. /*
  281. * M98090_REG_RIGHT_HP_MIXER 0x2A
  282. */
  283. #define M98090_MIXHPR_MIC2_MASK BIT(5)
  284. #define M98090_MIXHPR_MIC2_SHIFT 5
  285. #define M98090_MIXHPR_MIC2_WIDTH 1
  286. #define M98090_MIXHPR_MIC1_MASK BIT(4)
  287. #define M98090_MIXHPR_MIC1_SHIFT 4
  288. #define M98090_MIXHPR_MIC1_WIDTH 1
  289. #define M98090_MIXHPR_LINEB_MASK BIT(3)
  290. #define M98090_MIXHPR_LINEB_SHIFT 3
  291. #define M98090_MIXHPR_LINEB_WIDTH 1
  292. #define M98090_MIXHPR_LINEA_MASK BIT(2)
  293. #define M98090_MIXHPR_LINEA_SHIFT 2
  294. #define M98090_MIXHPR_LINEA_WIDTH 1
  295. #define M98090_MIXHPR_DACR_MASK BIT(1)
  296. #define M98090_MIXHPR_DACR_SHIFT 1
  297. #define M98090_MIXHPR_DACR_WIDTH 1
  298. #define M98090_MIXHPR_DACL_MASK BIT(0)
  299. #define M98090_MIXHPR_DACL_SHIFT 0
  300. #define M98090_MIXHPR_DACL_WIDTH 1
  301. #define M98090_MIXHPR_MASK (63 << 0)
  302. #define M98090_MIXHPR_SHIFT 0
  303. #define M98090_MIXHPR_WIDTH 6
  304. /*
  305. * M98090_REG_LEFT_HP_VOLUME 0x2C
  306. */
  307. #define M98090_HPLM_MASK BIT(7)
  308. #define M98090_HPLM_SHIFT 7
  309. #define M98090_HPLM_WIDTH 1
  310. #define M98090_HPVOLL_MASK (31 << 0)
  311. #define M98090_HPVOLL_SHIFT 0
  312. #define M98090_HPVOLL_WIDTH 5
  313. #define M98090_HPVOLL_NUM BIT(M98090_HPVOLL_WIDTH)
  314. /*
  315. * M98090_REG_RIGHT_HP_VOLUME 0x2D
  316. */
  317. #define M98090_HPRM_MASK BIT(7)
  318. #define M98090_HPRM_SHIFT 7
  319. #define M98090_HPRM_WIDTH 1
  320. #define M98090_HPVOLR_MASK (31 << 0)
  321. #define M98090_HPVOLR_SHIFT 0
  322. #define M98090_HPVOLR_WIDTH 5
  323. #define M98090_HPVOLR_NUM BIT(M98090_HPVOLR_WIDTH)
  324. /*
  325. * M98090_REG_LEFT_SPK_MIXER 0x2E
  326. */
  327. #define M98090_MIXSPL_MIC2_MASK BIT(5)
  328. #define M98090_MIXSPL_MIC2_SHIFT 5
  329. #define M98090_MIXSPL_MIC2_WIDTH 1
  330. #define M98090_MIXSPL_MIC1_MASK BIT(4)
  331. #define M98090_MIXSPL_MIC1_SHIFT 4
  332. #define M98090_MIXSPL_MIC1_WIDTH 1
  333. #define M98090_MIXSPL_LINEB_MASK BIT(3)
  334. #define M98090_MIXSPL_LINEB_SHIFT 3
  335. #define M98090_MIXSPL_LINEB_WIDTH 1
  336. #define M98090_MIXSPL_LINEA_MASK BIT(2)
  337. #define M98090_MIXSPL_LINEA_SHIFT 2
  338. #define M98090_MIXSPL_LINEA_WIDTH 1
  339. #define M98090_MIXSPL_DACR_MASK BIT(1)
  340. #define M98090_MIXSPL_DACR_SHIFT 1
  341. #define M98090_MIXSPL_DACR_WIDTH 1
  342. #define M98090_MIXSPL_DACL_MASK BIT(0)
  343. #define M98090_MIXSPL_DACL_SHIFT 0
  344. #define M98090_MIXSPL_DACL_WIDTH 1
  345. #define M98090_MIXSPL_MASK (63 << 0)
  346. #define M98090_MIXSPL_SHIFT 0
  347. #define M98090_MIXSPL_WIDTH 6
  348. #define M98090_MIXSPR_DACR_MASK BIT(1)
  349. #define M98090_MIXSPR_DACR_SHIFT 1
  350. #define M98090_MIXSPR_DACR_WIDTH 1
  351. /*
  352. * M98090_REG_RIGHT_SPK_MIXER 0x2F
  353. */
  354. #define M98090_SPK_SLAVE_MASK BIT(6)
  355. #define M98090_SPK_SLAVE_SHIFT 6
  356. #define M98090_SPK_SLAVE_WIDTH 1
  357. #define M98090_MIXSPR_MIC2_MASK BIT(5)
  358. #define M98090_MIXSPR_MIC2_SHIFT 5
  359. #define M98090_MIXSPR_MIC2_WIDTH 1
  360. #define M98090_MIXSPR_MIC1_MASK BIT(4)
  361. #define M98090_MIXSPR_MIC1_SHIFT 4
  362. #define M98090_MIXSPR_MIC1_WIDTH 1
  363. #define M98090_MIXSPR_LINEB_MASK BIT(3)
  364. #define M98090_MIXSPR_LINEB_SHIFT 3
  365. #define M98090_MIXSPR_LINEB_WIDTH 1
  366. #define M98090_MIXSPR_LINEA_MASK BIT(2)
  367. #define M98090_MIXSPR_LINEA_SHIFT 2
  368. #define M98090_MIXSPR_LINEA_WIDTH 1
  369. #define M98090_MIXSPR_DACR_MASK BIT(1)
  370. #define M98090_MIXSPR_DACR_SHIFT 1
  371. #define M98090_MIXSPR_DACR_WIDTH 1
  372. #define M98090_MIXSPR_DACL_MASK BIT(0)
  373. #define M98090_MIXSPR_DACL_SHIFT 0
  374. #define M98090_MIXSPR_DACL_WIDTH 1
  375. #define M98090_MIXSPR_MASK (63 << 0)
  376. #define M98090_MIXSPR_SHIFT 0
  377. #define M98090_MIXSPR_WIDTH 6
  378. /*
  379. * M98090_REG_LEFT_SPK_VOLUME 0x31
  380. */
  381. #define M98090_SPLM_MASK BIT(7)
  382. #define M98090_SPLM_SHIFT 7
  383. #define M98090_SPLM_WIDTH 1
  384. #define M98090_SPVOLL_MASK (63 << 0)
  385. #define M98090_SPVOLL_SHIFT 0
  386. #define M98090_SPVOLL_WIDTH 6
  387. #define M98090_SPVOLL_NUM 40
  388. /*
  389. * M98090_REG_RIGHT_SPK_VOLUME 0x32
  390. */
  391. #define M98090_SPRM_MASK BIT(7)
  392. #define M98090_SPRM_SHIFT 7
  393. #define M98090_SPRM_WIDTH 1
  394. #define M98090_SPVOLR_MASK (63 << 0)
  395. #define M98090_SPVOLR_SHIFT 0
  396. #define M98090_SPVOLR_WIDTH 6
  397. #define M98090_SPVOLR_NUM 40
  398. /*
  399. * M98090_REG_RCV_LOUTL_MIXER 0x37
  400. */
  401. #define M98090_MIXRCVL_MIC2_MASK BIT(5)
  402. #define M98090_MIXRCVL_MIC2_SHIFT 5
  403. #define M98090_MIXRCVL_MIC2_WIDTH 1
  404. #define M98090_MIXRCVL_MIC1_MASK BIT(4)
  405. #define M98090_MIXRCVL_MIC1_SHIFT 4
  406. #define M98090_MIXRCVL_MIC1_WIDTH 1
  407. #define M98090_MIXRCVL_LINEB_MASK BIT(3)
  408. #define M98090_MIXRCVL_LINEB_SHIFT 3
  409. #define M98090_MIXRCVL_LINEB_WIDTH 1
  410. #define M98090_MIXRCVL_LINEA_MASK BIT(2)
  411. #define M98090_MIXRCVL_LINEA_SHIFT 2
  412. #define M98090_MIXRCVL_LINEA_WIDTH 1
  413. #define M98090_MIXRCVL_DACR_MASK BIT(1)
  414. #define M98090_MIXRCVL_DACR_SHIFT 1
  415. #define M98090_MIXRCVL_DACR_WIDTH 1
  416. #define M98090_MIXRCVL_DACL_MASK BIT(0)
  417. #define M98090_MIXRCVL_DACL_SHIFT 0
  418. #define M98090_MIXRCVL_DACL_WIDTH 1
  419. #define M98090_MIXRCVL_MASK (63 << 0)
  420. #define M98090_MIXRCVL_SHIFT 0
  421. #define M98090_MIXRCVL_WIDTH 6
  422. /*
  423. * M98090_REG_RCV_LOUTL_CONTROL 0x38
  424. */
  425. #define M98090_MIXRCVLG_MASK (3 << 0)
  426. #define M98090_MIXRCVLG_SHIFT 0
  427. #define M98090_MIXRCVLG_WIDTH 2
  428. #define M98090_MIXRCVLG_NUM BIT(M98090_MIXRCVLG_WIDTH)
  429. /*
  430. * M98090_REG_RCV_LOUTL_VOLUME 0x39
  431. */
  432. #define M98090_RCVLM_MASK BIT(7)
  433. #define M98090_RCVLM_SHIFT 7
  434. #define M98090_RCVLM_WIDTH 1
  435. #define M98090_RCVLVOL_MASK (31 << 0)
  436. #define M98090_RCVLVOL_SHIFT 0
  437. #define M98090_RCVLVOL_WIDTH 5
  438. #define M98090_RCVLVOL_NUM BIT(M98090_RCVLVOL_WIDTH)
  439. /*
  440. * M98090_REG_LOUTR_MIXER 0x3A
  441. */
  442. #define M98090_LINMOD_MASK BIT(7)
  443. #define M98090_LINMOD_SHIFT 7
  444. #define M98090_LINMOD_WIDTH 1
  445. #define M98090_MIXRCVR_MIC2_MASK BIT(5)
  446. #define M98090_MIXRCVR_MIC2_SHIFT 5
  447. #define M98090_MIXRCVR_MIC2_WIDTH 1
  448. #define M98090_MIXRCVR_MIC1_MASK BIT(4)
  449. #define M98090_MIXRCVR_MIC1_SHIFT 4
  450. #define M98090_MIXRCVR_MIC1_WIDTH 1
  451. #define M98090_MIXRCVR_LINEB_MASK BIT(3)
  452. #define M98090_MIXRCVR_LINEB_SHIFT 3
  453. #define M98090_MIXRCVR_LINEB_WIDTH 1
  454. #define M98090_MIXRCVR_LINEA_MASK BIT(2)
  455. #define M98090_MIXRCVR_LINEA_SHIFT 2
  456. #define M98090_MIXRCVR_LINEA_WIDTH 1
  457. #define M98090_MIXRCVR_DACR_MASK BIT(1)
  458. #define M98090_MIXRCVR_DACR_SHIFT 1
  459. #define M98090_MIXRCVR_DACR_WIDTH 1
  460. #define M98090_MIXRCVR_DACL_MASK BIT(0)
  461. #define M98090_MIXRCVR_DACL_SHIFT 0
  462. #define M98090_MIXRCVR_DACL_WIDTH 1
  463. #define M98090_MIXRCVR_MASK (63 << 0)
  464. #define M98090_MIXRCVR_SHIFT 0
  465. #define M98090_MIXRCVR_WIDTH 6
  466. /*
  467. * M98090_REG_LOUTR_VOLUME 0x3C
  468. */
  469. #define M98090_RCVRM_MASK BIT(7)
  470. #define M98090_RCVRM_SHIFT 7
  471. #define M98090_RCVRM_WIDTH 1
  472. #define M98090_RCVRVOL_MASK (31 << 0)
  473. #define M98090_RCVRVOL_SHIFT 0
  474. #define M98090_RCVRVOL_WIDTH 5
  475. #define M98090_RCVRVOL_NUM BIT(M98090_RCVRVOL_WIDTH)
  476. /*
  477. * M98090_REG_JACK_DETECT 0x3D
  478. */
  479. #define M98090_JDETEN_MASK BIT(7)
  480. #define M98090_JDETEN_SHIFT 7
  481. #define M98090_JDETEN_WIDTH 1
  482. #define M98090_JDWK_MASK BIT(6)
  483. #define M98090_JDWK_SHIFT 6
  484. #define M98090_JDWK_WIDTH 1
  485. #define M98090_JDEB_MASK (3 << 0)
  486. #define M98090_JDEB_SHIFT 0
  487. #define M98090_JDEB_WIDTH 2
  488. #define M98090_JDEB_25MS (0 << 0)
  489. #define M98090_JDEB_50MS BIT(0)
  490. #define M98090_JDEB_100MS (2 << 0)
  491. #define M98090_JDEB_200MS (3 << 0)
  492. /*
  493. * M98090_REG_INPUT_ENABLE 0x3E
  494. */
  495. #define M98090_MBEN_MASK BIT(4)
  496. #define M98090_MBEN_SHIFT 4
  497. #define M98090_MBEN_WIDTH 1
  498. #define M98090_LINEAEN_MASK BIT(3)
  499. #define M98090_LINEAEN_SHIFT 3
  500. #define M98090_LINEAEN_WIDTH 1
  501. #define M98090_LINEBEN_MASK BIT(2)
  502. #define M98090_LINEBEN_SHIFT 2
  503. #define M98090_LINEBEN_WIDTH 1
  504. #define M98090_ADREN_MASK BIT(1)
  505. #define M98090_ADREN_SHIFT 1
  506. #define M98090_ADREN_WIDTH 1
  507. #define M98090_ADLEN_MASK BIT(0)
  508. #define M98090_ADLEN_SHIFT 0
  509. #define M98090_ADLEN_WIDTH 1
  510. /*
  511. * M98090_REG_OUTPUT_ENABLE 0x3F
  512. */
  513. #define M98090_HPREN_MASK BIT(7)
  514. #define M98090_HPREN_SHIFT 7
  515. #define M98090_HPREN_WIDTH 1
  516. #define M98090_HPLEN_MASK BIT(6)
  517. #define M98090_HPLEN_SHIFT 6
  518. #define M98090_HPLEN_WIDTH 1
  519. #define M98090_SPREN_MASK BIT(5)
  520. #define M98090_SPREN_SHIFT 5
  521. #define M98090_SPREN_WIDTH 1
  522. #define M98090_SPLEN_MASK BIT(4)
  523. #define M98090_SPLEN_SHIFT 4
  524. #define M98090_SPLEN_WIDTH 1
  525. #define M98090_RCVLEN_MASK BIT(3)
  526. #define M98090_RCVLEN_SHIFT 3
  527. #define M98090_RCVLEN_WIDTH 1
  528. #define M98090_RCVREN_MASK BIT(2)
  529. #define M98090_RCVREN_SHIFT 2
  530. #define M98090_RCVREN_WIDTH 1
  531. #define M98090_DAREN_MASK BIT(1)
  532. #define M98090_DAREN_SHIFT 1
  533. #define M98090_DAREN_WIDTH 1
  534. #define M98090_DALEN_MASK BIT(0)
  535. #define M98090_DALEN_SHIFT 0
  536. #define M98090_DALEN_WIDTH 1
  537. /*
  538. * M98090_REG_LEVEL_CONTROL 0x40
  539. */
  540. #define M98090_ZDENN_MASK BIT(2)
  541. #define M98090_ZDENN_SHIFT 2
  542. #define M98090_ZDENN_WIDTH 1
  543. #define M98090_ZDENN_NUM BIT(M98090_ZDENN_WIDTH)
  544. #define M98090_VS2ENN_MASK BIT(1)
  545. #define M98090_VS2ENN_SHIFT 1
  546. #define M98090_VS2ENN_WIDTH 1
  547. #define M98090_VS2ENN_NUM BIT(M98090_VS2ENN_WIDTH)
  548. #define M98090_VSENN_MASK BIT(0)
  549. #define M98090_VSENN_SHIFT 0
  550. #define M98090_VSENN_WIDTH 1
  551. #define M98090_VSENN_NUM BIT(M98090_VSENN_WIDTH)
  552. /*
  553. * M98090_REG_BIAS_CONTROL 0x42
  554. */
  555. #define M98090_VCM_MODE_MASK BIT(0)
  556. #define M98090_VCM_MODE_SHIFT 0
  557. #define M98090_VCM_MODE_WIDTH 1
  558. #define M98090_VCM_MODE_NUM BIT(M98090_VCM_MODE_WIDTH)
  559. /*
  560. * M98090_REG_DAC_CONTROL 0x43
  561. */
  562. #define M98090_PERFMODE_MASK BIT(1)
  563. #define M98090_PERFMODE_SHIFT 1
  564. #define M98090_PERFMODE_WIDTH 1
  565. #define M98090_PERFMODE_NUM BIT(M98090_PERFMODE_WIDTH)
  566. #define M98090_DACHP_MASK BIT(0)
  567. #define M98090_DACHP_SHIFT 0
  568. #define M98090_DACHP_WIDTH 1
  569. #define M98090_DACHP_NUM BIT(M98090_DACHP_WIDTH)
  570. /*
  571. * M98090_REG_ADC_CONTROL 0x44
  572. */
  573. #define M98090_OSR128_MASK BIT(2)
  574. #define M98090_OSR128_SHIFT 2
  575. #define M98090_OSR128_WIDTH 1
  576. #define M98090_ADCDITHER_MASK BIT(1)
  577. #define M98090_ADCDITHER_SHIFT 1
  578. #define M98090_ADCDITHER_WIDTH 1
  579. #define M98090_ADCDITHER_NUM BIT(M98090_ADCDITHER_WIDTH)
  580. #define M98090_ADCHP_MASK BIT(0)
  581. #define M98090_ADCHP_SHIFT 0
  582. #define M98090_ADCHP_WIDTH 1
  583. #define M98090_ADCHP_NUM BIT(M98090_ADCHP_WIDTH)
  584. /*
  585. * M98090_REG_DEVICE_SHUTDOWN 0x45
  586. */
  587. #define M98090_SHDNN_MASK BIT(7)
  588. #define M98090_SHDNN_SHIFT 7
  589. #define M98090_SHDNN_WIDTH 1
  590. /*
  591. * M98090_REG_REVISION_ID 0xFF
  592. */
  593. #define M98090_REVID_MASK (255 << 0)
  594. #define M98090_REVID_SHIFT 0
  595. #define M98090_REVID_WIDTH 8
  596. #define M98090_REVID_NUM BIT(M98090_REVID_WIDTH)
  597. /* function prototype */
  598. /*
  599. * initialise max98090 sound codec device for the given configuration
  600. *
  601. * @param blob FDT node for codec values
  602. * @param sampling_rate Sampling rate (Hz)
  603. * @param mclk_freq MCLK Frequency (Hz)
  604. * @param bits_per_sample bits per Sample (must be 16 or 24)
  605. *
  606. * @returns -1 for error and 0 Success.
  607. */
  608. int max98090_init(const void *blob, int sampling_rate, int mclk_freq,
  609. int bits_per_sample);
  610. int max98090_set_sysclk(struct maxim_priv *max98090, uint freq);
  611. int max98090_hw_params(struct maxim_priv *max98090, uint rate,
  612. uint bits_per_sample);
  613. int max98090_device_init(struct maxim_priv *max98090);
  614. int max98090_set_fmt(struct maxim_priv *max98090, int fmt);
  615. #endif