max98090.c 8.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * max98090.c -- MAX98090 ALSA SoC Audio driver
  4. *
  5. * Copyright 2011 Maxim Integrated Products
  6. */
  7. #include <common.h>
  8. #include <audio_codec.h>
  9. #include <div64.h>
  10. #include <dm.h>
  11. #include <i2c.h>
  12. #include <i2s.h>
  13. #include <log.h>
  14. #include <sound.h>
  15. #include <asm/gpio.h>
  16. #include <linux/delay.h>
  17. #include "maxim_codec.h"
  18. #include "max98090.h"
  19. /*
  20. * Sets hw params for max98090
  21. *
  22. * @priv: max98090 information pointer
  23. * @rate: Sampling rate
  24. * @bits_per_sample: Bits per sample
  25. *
  26. * @return -EIO for error, 0 for success.
  27. */
  28. int max98090_hw_params(struct maxim_priv *priv, unsigned int rate,
  29. unsigned int bits_per_sample)
  30. {
  31. int error;
  32. unsigned char value;
  33. switch (bits_per_sample) {
  34. case 16:
  35. maxim_i2c_read(priv, M98090_REG_INTERFACE_FORMAT, &value);
  36. error = maxim_bic_or(priv, M98090_REG_INTERFACE_FORMAT,
  37. M98090_WS_MASK, 0);
  38. maxim_i2c_read(priv, M98090_REG_INTERFACE_FORMAT, &value);
  39. break;
  40. default:
  41. debug("%s: Illegal bits per sample %d.\n",
  42. __func__, bits_per_sample);
  43. return -1;
  44. }
  45. /* Update filter mode */
  46. if (rate < 240000)
  47. error |= maxim_bic_or(priv, M98090_REG_FILTER_CONFIG,
  48. M98090_MODE_MASK, 0);
  49. else
  50. error |= maxim_bic_or(priv, M98090_REG_FILTER_CONFIG,
  51. M98090_MODE_MASK, M98090_MODE_MASK);
  52. /* Update sample rate mode */
  53. if (rate < 50000)
  54. error |= maxim_bic_or(priv, M98090_REG_FILTER_CONFIG,
  55. M98090_DHF_MASK, 0);
  56. else
  57. error |= maxim_bic_or(priv, M98090_REG_FILTER_CONFIG,
  58. M98090_DHF_MASK, M98090_DHF_MASK);
  59. if (error < 0) {
  60. debug("%s: Error setting hardware params.\n", __func__);
  61. return -EIO;
  62. }
  63. priv->rate = rate;
  64. return 0;
  65. }
  66. /*
  67. * Configures Audio interface system clock for the given frequency
  68. *
  69. * @priv: max98090 information
  70. * @freq: Sampling frequency in Hz
  71. *
  72. * @return -EIO for error, 0 for success.
  73. */
  74. int max98090_set_sysclk(struct maxim_priv *priv, unsigned int freq)
  75. {
  76. int error = 0;
  77. /* Requested clock frequency is already setup */
  78. if (freq == priv->sysclk)
  79. return 0;
  80. /* Setup clocks for slave mode, and using the PLL
  81. * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
  82. * 0x02 (when master clk is 20MHz to 40MHz)..
  83. * 0x03 (when master clk is 40MHz to 60MHz)..
  84. */
  85. if (freq >= 10000000 && freq < 20000000) {
  86. error = maxim_i2c_write(priv, M98090_REG_SYSTEM_CLOCK,
  87. M98090_PSCLK_DIV1);
  88. } else if (freq >= 20000000 && freq < 40000000) {
  89. error = maxim_i2c_write(priv, M98090_REG_SYSTEM_CLOCK,
  90. M98090_PSCLK_DIV2);
  91. } else if (freq >= 40000000 && freq < 60000000) {
  92. error = maxim_i2c_write(priv, M98090_REG_SYSTEM_CLOCK,
  93. M98090_PSCLK_DIV4);
  94. } else {
  95. debug("%s: Invalid master clock frequency\n", __func__);
  96. return -1;
  97. }
  98. debug("%s: Clock at %uHz\n", __func__, freq);
  99. if (error < 0)
  100. return -1;
  101. priv->sysclk = freq;
  102. return 0;
  103. }
  104. /*
  105. * Sets Max98090 I2S format
  106. *
  107. * @priv: max98090 information
  108. * @fmt: i2S format - supports a subset of the options defined in i2s.h.
  109. *
  110. * @return -EIO for error, 0 for success.
  111. */
  112. int max98090_set_fmt(struct maxim_priv *priv, int fmt)
  113. {
  114. u8 regval = 0;
  115. int error = 0;
  116. if (fmt == priv->fmt)
  117. return 0;
  118. priv->fmt = fmt;
  119. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  120. case SND_SOC_DAIFMT_CBS_CFS:
  121. /* Set to slave mode PLL - MAS mode off */
  122. error |= maxim_i2c_write(priv, M98090_REG_CLOCK_RATIO_NI_MSB,
  123. 0x00);
  124. error |= maxim_i2c_write(priv, M98090_REG_CLOCK_RATIO_NI_LSB,
  125. 0x00);
  126. error |= maxim_bic_or(priv, M98090_REG_CLOCK_MODE,
  127. M98090_USE_M1_MASK, 0);
  128. break;
  129. case SND_SOC_DAIFMT_CBM_CFM:
  130. /* Set to master mode */
  131. debug("Master mode not supported\n");
  132. break;
  133. case SND_SOC_DAIFMT_CBS_CFM:
  134. case SND_SOC_DAIFMT_CBM_CFS:
  135. default:
  136. debug("%s: Clock mode unsupported\n", __func__);
  137. return -EINVAL;
  138. }
  139. error |= maxim_i2c_write(priv, M98090_REG_MASTER_MODE, regval);
  140. regval = 0;
  141. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  142. case SND_SOC_DAIFMT_I2S:
  143. regval |= M98090_DLY_MASK;
  144. break;
  145. case SND_SOC_DAIFMT_LEFT_J:
  146. break;
  147. case SND_SOC_DAIFMT_RIGHT_J:
  148. regval |= M98090_RJ_MASK;
  149. break;
  150. case SND_SOC_DAIFMT_DSP_A:
  151. /* Not supported mode */
  152. default:
  153. debug("%s: Unrecognized format.\n", __func__);
  154. return -EINVAL;
  155. }
  156. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  157. case SND_SOC_DAIFMT_NB_NF:
  158. break;
  159. case SND_SOC_DAIFMT_NB_IF:
  160. regval |= M98090_WCI_MASK;
  161. break;
  162. case SND_SOC_DAIFMT_IB_NF:
  163. regval |= M98090_BCI_MASK;
  164. break;
  165. case SND_SOC_DAIFMT_IB_IF:
  166. regval |= M98090_BCI_MASK | M98090_WCI_MASK;
  167. break;
  168. default:
  169. debug("%s: Unrecognized inversion settings.\n", __func__);
  170. return -EINVAL;
  171. }
  172. error |= maxim_i2c_write(priv, M98090_REG_INTERFACE_FORMAT, regval);
  173. if (error < 0) {
  174. debug("%s: Error setting i2s format.\n", __func__);
  175. return -EIO;
  176. }
  177. return 0;
  178. }
  179. /*
  180. * resets the audio codec
  181. *
  182. * @priv: max98090 information
  183. * @return -EIO for error, 0 for success.
  184. */
  185. static int max98090_reset(struct maxim_priv *priv)
  186. {
  187. int ret;
  188. /*
  189. * Gracefully reset the DSP core and the codec hardware in a proper
  190. * sequence.
  191. */
  192. ret = maxim_i2c_write(priv, M98090_REG_SOFTWARE_RESET,
  193. M98090_SWRESET_MASK);
  194. if (ret != 0) {
  195. debug("%s: Failed to reset DSP: %d\n", __func__, ret);
  196. return ret;
  197. }
  198. mdelay(20);
  199. return 0;
  200. }
  201. /*
  202. * Initialise max98090 codec device
  203. *
  204. * @priv: max98090 information
  205. *
  206. * @return -EIO for error, 0 for success.
  207. */
  208. int max98090_device_init(struct maxim_priv *priv)
  209. {
  210. unsigned char id;
  211. int error = 0;
  212. /* reset the codec, the DSP core, and disable all interrupts */
  213. error = max98090_reset(priv);
  214. if (error != 0) {
  215. debug("Reset\n");
  216. return error;
  217. }
  218. /* initialize private data */
  219. priv->sysclk = -1U;
  220. priv->rate = -1U;
  221. priv->fmt = -1U;
  222. error = maxim_i2c_read(priv, M98090_REG_REVISION_ID, &id);
  223. if (error < 0) {
  224. debug("%s: Failure reading hardware revision: %d\n",
  225. __func__, id);
  226. return -EIO;
  227. }
  228. debug("%s: Hardware revision: %d\n", __func__, id);
  229. return 0;
  230. }
  231. static int max98090_setup_interface(struct maxim_priv *priv)
  232. {
  233. unsigned char id;
  234. int error;
  235. /* Reading interrupt status to clear them */
  236. error = maxim_i2c_read(priv, M98090_REG_DEVICE_STATUS, &id);
  237. error |= maxim_i2c_write(priv, M98090_REG_DAC_CONTROL,
  238. M98090_DACHP_MASK);
  239. error |= maxim_i2c_write(priv, M98090_REG_BIAS_CONTROL,
  240. M98090_VCM_MODE_MASK);
  241. error |= maxim_i2c_write(priv, M98090_REG_LEFT_SPK_MIXER, 0x1);
  242. error |= maxim_i2c_write(priv, M98090_REG_RIGHT_SPK_MIXER, 0x2);
  243. error |= maxim_i2c_write(priv, M98090_REG_LEFT_SPK_VOLUME, 0x25);
  244. error |= maxim_i2c_write(priv, M98090_REG_RIGHT_SPK_VOLUME, 0x25);
  245. error |= maxim_i2c_write(priv, M98090_REG_CLOCK_RATIO_NI_MSB, 0x0);
  246. error |= maxim_i2c_write(priv, M98090_REG_CLOCK_RATIO_NI_LSB, 0x0);
  247. error |= maxim_i2c_write(priv, M98090_REG_MASTER_MODE, 0x0);
  248. error |= maxim_i2c_write(priv, M98090_REG_INTERFACE_FORMAT, 0x0);
  249. error |= maxim_i2c_write(priv, M98090_REG_IO_CONFIGURATION,
  250. M98090_SDIEN_MASK);
  251. error |= maxim_i2c_write(priv, M98090_REG_DEVICE_SHUTDOWN,
  252. M98090_SHDNN_MASK);
  253. error |= maxim_i2c_write(priv, M98090_REG_OUTPUT_ENABLE,
  254. M98090_HPREN_MASK | M98090_HPLEN_MASK |
  255. M98090_SPREN_MASK | M98090_SPLEN_MASK |
  256. M98090_DAREN_MASK | M98090_DALEN_MASK);
  257. error |= maxim_i2c_write(priv, M98090_REG_IO_CONFIGURATION,
  258. M98090_SDOEN_MASK | M98090_SDIEN_MASK);
  259. if (error < 0)
  260. return -EIO;
  261. return 0;
  262. }
  263. static int max98090_do_init(struct maxim_priv *priv, int sampling_rate,
  264. int mclk_freq, int bits_per_sample)
  265. {
  266. int ret = 0;
  267. ret = max98090_setup_interface(priv);
  268. if (ret < 0) {
  269. debug("%s: max98090 setup interface failed\n", __func__);
  270. return ret;
  271. }
  272. ret = max98090_set_sysclk(priv, mclk_freq);
  273. if (ret < 0) {
  274. debug("%s: max98090 codec set sys clock failed\n", __func__);
  275. return ret;
  276. }
  277. ret = max98090_hw_params(priv, sampling_rate, bits_per_sample);
  278. if (ret == 0) {
  279. ret = max98090_set_fmt(priv, SND_SOC_DAIFMT_I2S |
  280. SND_SOC_DAIFMT_NB_NF |
  281. SND_SOC_DAIFMT_CBS_CFS);
  282. }
  283. return ret;
  284. }
  285. static int max98090_set_params(struct udevice *dev, int interface, int rate,
  286. int mclk_freq, int bits_per_sample,
  287. uint channels)
  288. {
  289. struct maxim_priv *priv = dev_get_priv(dev);
  290. return max98090_do_init(priv, rate, mclk_freq, bits_per_sample);
  291. }
  292. static int max98090_probe(struct udevice *dev)
  293. {
  294. struct maxim_priv *priv = dev_get_priv(dev);
  295. int ret;
  296. priv->dev = dev;
  297. ret = max98090_device_init(priv);
  298. if (ret < 0) {
  299. debug("%s: max98090 codec chip init failed\n", __func__);
  300. return ret;
  301. }
  302. return 0;
  303. }
  304. static const struct audio_codec_ops max98090_ops = {
  305. .set_params = max98090_set_params,
  306. };
  307. static const struct udevice_id max98090_ids[] = {
  308. { .compatible = "maxim,max98090" },
  309. { }
  310. };
  311. U_BOOT_DRIVER(max98090) = {
  312. .name = "max98090",
  313. .id = UCLASS_AUDIO_CODEC,
  314. .of_match = max98090_ids,
  315. .probe = max98090_probe,
  316. .ops = &max98090_ops,
  317. .priv_auto_alloc_size = sizeof(struct maxim_priv),
  318. };