max98088.c 9.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * max98088.c -- MAX98088 ALSA SoC Audio driver
  4. *
  5. * Copyright 2010 Maxim Integrated Products
  6. *
  7. * Modified for U-Boot by Chih-Chung Chang (chihchung@chromium.org),
  8. * following the changes made in max98095.c
  9. */
  10. #include <common.h>
  11. #include <audio_codec.h>
  12. #include <div64.h>
  13. #include <dm.h>
  14. #include <i2c.h>
  15. #include <i2s.h>
  16. #include <log.h>
  17. #include <sound.h>
  18. #include <asm/gpio.h>
  19. #include "maxim_codec.h"
  20. #include "max98088.h"
  21. /* codec mclk clock divider coefficients. Index 0 is reserved. */
  22. static const int rate_table[] = {0, 8000, 11025, 16000, 22050, 24000, 32000,
  23. 44100, 48000, 88200, 96000};
  24. /*
  25. * codec mclk clock divider coefficients based on sampling rate
  26. *
  27. * @param rate sampling rate
  28. * @param value address of indexvalue to be stored
  29. *
  30. * @return 0 for success or negative error code.
  31. */
  32. static int rate_value(int rate, u8 *value)
  33. {
  34. int i;
  35. for (i = 1; i < ARRAY_SIZE(rate_table); i++) {
  36. if (rate_table[i] >= rate) {
  37. *value = i;
  38. return 0;
  39. }
  40. }
  41. *value = 1;
  42. return -EINVAL;
  43. }
  44. /*
  45. * Sets hw params for max98088
  46. *
  47. * @priv: max98088 information pointer
  48. * @rate: Sampling rate
  49. * @bits_per_sample: Bits per sample
  50. *
  51. * @return -EIO for error, 0 for success.
  52. */
  53. int max98088_hw_params(struct maxim_priv *priv, unsigned int rate,
  54. unsigned int bits_per_sample)
  55. {
  56. int error;
  57. u8 regval;
  58. switch (bits_per_sample) {
  59. case 16:
  60. error = maxim_bic_or(priv, M98088_REG_DAI1_FORMAT,
  61. M98088_DAI_WS, 0);
  62. break;
  63. case 24:
  64. error = maxim_bic_or(priv, M98088_REG_DAI1_FORMAT,
  65. M98088_DAI_WS, M98088_DAI_WS);
  66. break;
  67. default:
  68. debug("%s: Illegal bits per sample %d.\n",
  69. __func__, bits_per_sample);
  70. return -EINVAL;
  71. }
  72. error |= maxim_bic_or(priv, M98088_REG_PWR_SYS, M98088_SHDNRUN, 0);
  73. if (rate_value(rate, &regval)) {
  74. debug("%s: Failed to set sample rate to %d.\n",
  75. __func__, rate);
  76. return -EIO;
  77. }
  78. error |= maxim_bic_or(priv, M98088_REG_DAI1_CLKMODE,
  79. M98088_CLKMODE_MASK, regval << 4);
  80. priv->rate = rate;
  81. /* Update sample rate mode */
  82. if (rate < 50000)
  83. error |= maxim_bic_or(priv, M98088_REG_DAI1_FILTERS,
  84. M98088_DAI_DHF, 0);
  85. else
  86. error |= maxim_bic_or(priv, M98088_REG_DAI1_FILTERS,
  87. M98088_DAI_DHF, M98088_DAI_DHF);
  88. error |= maxim_bic_or(priv, M98088_REG_PWR_SYS, M98088_SHDNRUN,
  89. M98088_SHDNRUN);
  90. if (error < 0) {
  91. debug("%s: Error setting hardware params.\n", __func__);
  92. return -EIO;
  93. }
  94. priv->rate = rate;
  95. return 0;
  96. }
  97. /*
  98. * Configures Audio interface system clock for the given frequency
  99. *
  100. * @priv: max98088 information
  101. * @freq: Sampling frequency in Hz
  102. *
  103. * @return -EIO for error, 0 for success.
  104. */
  105. int max98088_set_sysclk(struct maxim_priv *priv, unsigned int freq)
  106. {
  107. int error = 0;
  108. u8 pwr;
  109. /* Requested clock frequency is already setup */
  110. if (freq == priv->sysclk)
  111. return 0;
  112. /*
  113. * Setup clocks for slave mode, and using the PLL
  114. * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
  115. * 0x02 (when master clk is 20MHz to 30MHz)..
  116. */
  117. if (freq >= 10000000 && freq < 20000000) {
  118. error = maxim_i2c_write(priv, M98088_REG_SYS_CLK, 0x10);
  119. } else if ((freq >= 20000000) && (freq < 30000000)) {
  120. error = maxim_i2c_write(priv, M98088_REG_SYS_CLK, 0x20);
  121. } else {
  122. debug("%s: Invalid master clock frequency\n", __func__);
  123. return -EIO;
  124. }
  125. error |= maxim_i2c_read(priv, M98088_REG_PWR_SYS, &pwr);
  126. if (pwr & M98088_SHDNRUN) {
  127. error |= maxim_bic_or(priv, M98088_REG_PWR_SYS,
  128. M98088_SHDNRUN, 0);
  129. error |= maxim_bic_or(priv, M98088_REG_PWR_SYS,
  130. M98088_SHDNRUN, M98088_SHDNRUN);
  131. }
  132. debug("%s: Clock at %uHz\n", __func__, freq);
  133. if (error < 0)
  134. return -EIO;
  135. priv->sysclk = freq;
  136. return 0;
  137. }
  138. /*
  139. * Sets Max98090 I2S format
  140. *
  141. * @priv: max98088 information
  142. * @fmt: i2S format - supports a subset of the options defined in i2s.h.
  143. *
  144. * @return -EIO for error, 0 for success.
  145. */
  146. int max98088_set_fmt(struct maxim_priv *priv, int fmt)
  147. {
  148. u8 reg15val;
  149. u8 reg14val = 0;
  150. int error = 0;
  151. if (fmt == priv->fmt)
  152. return 0;
  153. priv->fmt = fmt;
  154. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  155. case SND_SOC_DAIFMT_CBS_CFS:
  156. /* Slave mode PLL */
  157. error |= maxim_i2c_write(priv, M98088_REG_DAI1_CLKCFG_HI,
  158. 0x80);
  159. error |= maxim_i2c_write(priv, M98088_REG_DAI1_CLKCFG_LO,
  160. 0x00);
  161. break;
  162. case SND_SOC_DAIFMT_CBM_CFM:
  163. /* Set to master mode */
  164. reg14val |= M98088_DAI_MAS;
  165. break;
  166. case SND_SOC_DAIFMT_CBS_CFM:
  167. case SND_SOC_DAIFMT_CBM_CFS:
  168. default:
  169. debug("%s: Clock mode unsupported\n", __func__);
  170. return -EINVAL;
  171. }
  172. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  173. case SND_SOC_DAIFMT_I2S:
  174. reg14val |= M98088_DAI_DLY;
  175. break;
  176. case SND_SOC_DAIFMT_LEFT_J:
  177. break;
  178. default:
  179. debug("%s: Unrecognized format.\n", __func__);
  180. return -EINVAL;
  181. }
  182. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  183. case SND_SOC_DAIFMT_NB_NF:
  184. break;
  185. case SND_SOC_DAIFMT_NB_IF:
  186. reg14val |= M98088_DAI_WCI;
  187. break;
  188. case SND_SOC_DAIFMT_IB_NF:
  189. reg14val |= M98088_DAI_BCI;
  190. break;
  191. case SND_SOC_DAIFMT_IB_IF:
  192. reg14val |= M98088_DAI_BCI | M98088_DAI_WCI;
  193. break;
  194. default:
  195. debug("%s: Unrecognized inversion settings.\n", __func__);
  196. return -EINVAL;
  197. }
  198. error |= maxim_bic_or(priv, M98088_REG_DAI1_FORMAT,
  199. M98088_DAI_MAS | M98088_DAI_DLY | M98088_DAI_BCI |
  200. M98088_DAI_WCI, reg14val);
  201. reg15val = M98088_DAI_BSEL64;
  202. error |= maxim_i2c_write(priv, M98088_REG_DAI1_CLOCK, reg15val);
  203. if (error < 0) {
  204. debug("%s: Error setting i2s format.\n", __func__);
  205. return -EIO;
  206. }
  207. return 0;
  208. }
  209. /*
  210. * max98088_reset() - reset the audio codec
  211. *
  212. * @priv: max98088 information
  213. * @return -EIO for error, 0 for success.
  214. */
  215. static int max98088_reset(struct maxim_priv *priv)
  216. {
  217. int ret, i;
  218. u8 val;
  219. /*
  220. * Reset to hardware default for registers, as there is not a soft
  221. * reset hardware control register.
  222. */
  223. for (i = M98088_REG_IRQ_ENABLE; i <= M98088_REG_PWR_SYS; i++) {
  224. switch (i) {
  225. case M98088_REG_BIAS_CNTL:
  226. val = 0xf0;
  227. break;
  228. case M98088_REG_DAC_BIAS2:
  229. val = 0x0f;
  230. break;
  231. default:
  232. val = 0;
  233. }
  234. ret = maxim_i2c_write(priv, i, val);
  235. if (ret < 0) {
  236. debug("%s: Failed to reset: %d\n", __func__, ret);
  237. return ret;
  238. }
  239. }
  240. return 0;
  241. }
  242. /**
  243. * max98088_device_init() - Initialise max98088 codec device
  244. *
  245. * @priv: max98088 information
  246. *
  247. * @return -EIO for error, 0 for success.
  248. */
  249. static int max98088_device_init(struct maxim_priv *priv)
  250. {
  251. unsigned char id;
  252. int error = 0;
  253. /* reset the codec, the DSP core, and disable all interrupts */
  254. error = max98088_reset(priv);
  255. if (error != 0) {
  256. debug("Reset\n");
  257. return error;
  258. }
  259. /* initialize private data */
  260. priv->sysclk = -1U;
  261. priv->rate = -1U;
  262. priv->fmt = -1U;
  263. error = maxim_i2c_read(priv, M98088_REG_REV_ID, &id);
  264. if (error < 0) {
  265. debug("%s: Failure reading hardware revision: %d\n",
  266. __func__, id);
  267. return -EIO;
  268. }
  269. debug("%s: Hardware revision: %d\n", __func__, id);
  270. return 0;
  271. }
  272. static int max98088_setup_interface(struct maxim_priv *priv)
  273. {
  274. int error;
  275. /* Reading interrupt status to clear them */
  276. error = maxim_i2c_write(priv, M98088_REG_PWR_SYS, M98088_PWRSV);
  277. error |= maxim_i2c_write(priv, M98088_REG_IRQ_ENABLE, 0x00);
  278. /*
  279. * initialize registers to hardware default configuring audio
  280. * interface2 to DAI1
  281. */
  282. error |= maxim_i2c_write(priv, M98088_REG_MIX_DAC,
  283. M98088_DAI1L_TO_DACL | M98088_DAI1R_TO_DACR);
  284. error |= maxim_i2c_write(priv, M98088_REG_BIAS_CNTL, 0xF0);
  285. error |= maxim_i2c_write(priv, M98088_REG_DAC_BIAS2, 0x0F);
  286. error |= maxim_i2c_write(priv, M98088_REG_DAI1_IOCFG,
  287. M98088_S2NORMAL | M98088_SDATA);
  288. /*
  289. * route DACL and DACR output to headphone and speakers
  290. * Ordering: DACL, DACR, DACL, DACR
  291. */
  292. error |= maxim_i2c_write(priv, M98088_REG_MIX_SPK_LEFT, 1);
  293. error |= maxim_i2c_write(priv, M98088_REG_MIX_SPK_RIGHT, 1);
  294. error |= maxim_i2c_write(priv, M98088_REG_MIX_HP_LEFT, 1);
  295. error |= maxim_i2c_write(priv, M98088_REG_MIX_HP_RIGHT, 1);
  296. /* set volume: -12db */
  297. error |= maxim_i2c_write(priv, M98088_REG_LVL_SPK_L, 0x0f);
  298. error |= maxim_i2c_write(priv, M98088_REG_LVL_SPK_R, 0x0f);
  299. /* set volume: -22db */
  300. error |= maxim_i2c_write(priv, M98088_REG_LVL_HP_L, 0x0d);
  301. error |= maxim_i2c_write(priv, M98088_REG_LVL_HP_R, 0x0d);
  302. /* power enable */
  303. error |= maxim_i2c_write(priv, M98088_REG_PWR_EN_OUT,
  304. M98088_HPLEN | M98088_HPREN | M98088_SPLEN |
  305. M98088_SPREN | M98088_DALEN | M98088_DAREN);
  306. if (error < 0)
  307. return -EIO;
  308. return 0;
  309. }
  310. static int max98088_do_init(struct maxim_priv *priv, int sampling_rate,
  311. int mclk_freq, int bits_per_sample)
  312. {
  313. int ret = 0;
  314. ret = max98088_setup_interface(priv);
  315. if (ret < 0) {
  316. debug("%s: max98088 setup interface failed\n", __func__);
  317. return ret;
  318. }
  319. ret = max98088_set_sysclk(priv, mclk_freq);
  320. if (ret < 0) {
  321. debug("%s: max98088 codec set sys clock failed\n", __func__);
  322. return ret;
  323. }
  324. ret = max98088_hw_params(priv, sampling_rate, bits_per_sample);
  325. if (ret == 0) {
  326. ret = max98088_set_fmt(priv, SND_SOC_DAIFMT_I2S |
  327. SND_SOC_DAIFMT_NB_NF |
  328. SND_SOC_DAIFMT_CBS_CFS);
  329. }
  330. return ret;
  331. }
  332. static int max98088_set_params(struct udevice *dev, int interface, int rate,
  333. int mclk_freq, int bits_per_sample,
  334. uint channels)
  335. {
  336. struct maxim_priv *priv = dev_get_priv(dev);
  337. return max98088_do_init(priv, rate, mclk_freq, bits_per_sample);
  338. }
  339. static int max98088_probe(struct udevice *dev)
  340. {
  341. struct maxim_priv *priv = dev_get_priv(dev);
  342. int ret;
  343. priv->dev = dev;
  344. ret = max98088_device_init(priv);
  345. if (ret < 0) {
  346. debug("%s: max98088 codec chip init failed\n", __func__);
  347. return ret;
  348. }
  349. return 0;
  350. }
  351. static const struct audio_codec_ops max98088_ops = {
  352. .set_params = max98088_set_params,
  353. };
  354. static const struct udevice_id max98088_ids[] = {
  355. { .compatible = "maxim,max98088" },
  356. { }
  357. };
  358. U_BOOT_DRIVER(max98088) = {
  359. .name = "max98088",
  360. .id = UCLASS_AUDIO_CODEC,
  361. .of_match = max98088_ids,
  362. .probe = max98088_probe,
  363. .ops = &max98088_ops,
  364. .priv_auto_alloc_size = sizeof(struct maxim_priv),
  365. };