broadwell_i2s.c 7.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Intel Broadwell I2S driver
  4. *
  5. * Copyright 2019 Google LLC
  6. *
  7. * Modified from dc i2s/broadwell/broadwell.c
  8. */
  9. #define LOG_CATEGORY UCLASS_I2S
  10. #include <common.h>
  11. #include <dm.h>
  12. #include <i2s.h>
  13. #include <log.h>
  14. #include <time.h>
  15. #include <asm/io.h>
  16. #include "broadwell_i2s.h"
  17. enum {
  18. BDW_SHIM_START_ADDRESS = 0xfb000,
  19. BDW_SSP0_START_ADDRESS = 0xfc000,
  20. BDW_SSP1_START_ADDRESS = 0xfd000,
  21. };
  22. struct broadwell_i2s_priv {
  23. enum frame_sync_rel_timing_t rel_timing;
  24. enum frame_sync_pol_t sfrm_polarity;
  25. enum end_transfer_state_t end_transfer_state;
  26. enum clock_mode_t sclk_mode;
  27. uint sclk_dummy_stop; /* 0-31 */
  28. uint sclk_frame_width; /* 1-38 */
  29. struct i2s_shim_regs *shim;
  30. struct broadwell_i2s_regs *regs;
  31. };
  32. static void init_shim_csr(struct broadwell_i2s_priv *priv)
  33. {
  34. /*
  35. * Select SSP clock
  36. * Turn off low power clock
  37. * Set PIO mode
  38. * Stall DSP core
  39. */
  40. clrsetbits_le32(&priv->shim->csr,
  41. SHIM_CS_S0IOCS | SHIM_CS_LPCS | SHIM_CS_DCS_MASK,
  42. SHIM_CS_S1IOCS | SHIM_CS_SBCS_SSP1_24MHZ |
  43. SHIM_CS_SBCS_SSP0_24MHZ | SHIM_CS_SDPM_PIO_SSP1 |
  44. SHIM_CS_SDPM_PIO_SSP0 | SHIM_CS_STALL |
  45. SHIM_CS_DCS_DSP32_AF32);
  46. }
  47. static void init_shim_clkctl(struct i2s_uc_priv *uc_priv,
  48. struct broadwell_i2s_priv *priv)
  49. {
  50. u32 clkctl = readl(&priv->shim->clkctl);
  51. /* Set 24Mhz mclk, prevent local clock gating, enable SSP0 clock */
  52. clkctl &= SHIM_CLKCTL_RESERVED;
  53. clkctl |= SHIM_CLKCTL_MCLK_24MHZ | SHIM_CLKCTL_DCPLCG;
  54. /* Enable requested SSP interface */
  55. if (uc_priv->id)
  56. clkctl |= SHIM_CLKCTL_SCOE_SSP1 | SHIM_CLKCTL_SFLCGB_SSP1_CGD;
  57. else
  58. clkctl |= SHIM_CLKCTL_SCOE_SSP0 | SHIM_CLKCTL_SFLCGB_SSP0_CGD;
  59. writel(clkctl, &priv->shim->clkctl);
  60. }
  61. static void init_sscr0(struct i2s_uc_priv *uc_priv,
  62. struct broadwell_i2s_priv *priv)
  63. {
  64. u32 sscr0;
  65. uint scale;
  66. /* Set data size based on BPS */
  67. if (uc_priv->bitspersample > 16)
  68. sscr0 = (uc_priv->bitspersample - 16 - 1) << SSP_SSC0_DSS_SHIFT
  69. | SSP_SSC0_EDSS;
  70. else
  71. sscr0 = (uc_priv->bitspersample - 1) << SSP_SSC0_DSS_SHIFT;
  72. /* Set network mode, Stereo PSP frame format */
  73. sscr0 |= SSP_SSC0_MODE_NETWORK |
  74. SSP_SSC0_FRDC_STEREO |
  75. SSP_SSC0_FRF_PSP |
  76. SSP_SSC0_TIM |
  77. SSP_SSC0_RIM |
  78. SSP_SSC0_ECS_PCH |
  79. SSP_SSC0_NCS_PCH |
  80. SSP_SSC0_ACS_PCH;
  81. /* Scale 24MHz MCLK */
  82. scale = uc_priv->audio_pll_clk / uc_priv->samplingrate / uc_priv->bfs;
  83. sscr0 |= scale << SSP_SSC0_SCR_SHIFT;
  84. writel(sscr0, &priv->regs->sscr0);
  85. }
  86. static void init_sscr1(struct broadwell_i2s_priv *priv)
  87. {
  88. u32 sscr1 = readl(&priv->regs->sscr1);
  89. sscr1 &= SSP_SSC1_RESERVED;
  90. /* Set as I2S master */
  91. sscr1 |= SSP_SSC1_SCLKDIR_MASTER | SSP_SSC1_SCLKDIR_MASTER;
  92. /* Enable TXD tristate behavior for PCH */
  93. sscr1 |= SSP_SSC1_TTELP | SSP_SSC1_TTE;
  94. /* Disable DMA Tx/Rx service request */
  95. sscr1 |= SSP_SSC1_TSRE | SSP_SSC1_RSRE;
  96. /* Clock on during transfer */
  97. sscr1 |= SSP_SSC1_SCFR;
  98. /* Set FIFO thresholds */
  99. sscr1 |= SSP_FIFO_SIZE << SSP_SSC1_RFT_SHIFT;
  100. sscr1 |= SSP_FIFO_SIZE << SSP_SSC1_TFT_SHIFT;
  101. /* Disable interrupts */
  102. sscr1 &= ~(SSP_SSC1_EBCEI | SSP_SSC1_TINTE | SSP_SSC1_PINTE);
  103. sscr1 &= ~(SSP_SSC1_LBM | SSP_SSC1_RWOT);
  104. writel(sscr1, &priv->regs->sscr1);
  105. }
  106. static void init_sspsp(struct broadwell_i2s_priv *priv)
  107. {
  108. u32 sspsp = readl(&priv->regs->sspsp);
  109. sspsp &= SSP_PSP_RESERVED;
  110. sspsp |= priv->sclk_mode << SSP_PSP_SCMODE_SHIFT;
  111. sspsp |= (priv->sclk_dummy_stop << SSP_PSP_DMYSTOP_SHIFT) &
  112. SSP_PSP_DMYSTOP_MASK;
  113. sspsp |= (priv->sclk_dummy_stop >> 2 << SSP_PSP_EDYMSTOP_SHIFT) &
  114. SSP_PSP_EDMYSTOP_MASK;
  115. sspsp |= priv->sclk_frame_width << SSP_PSP_SFRMWDTH_SHIFT;
  116. /* Frame Sync Relative Timing */
  117. if (priv->rel_timing == NEXT_FRMS_AFTER_END_OF_T4)
  118. sspsp |= SSP_PSP_FSRT;
  119. else
  120. sspsp &= ~SSP_PSP_FSRT;
  121. /* Serial Frame Polarity */
  122. if (priv->sfrm_polarity == SSP_FRMS_ACTIVE_HIGH)
  123. sspsp |= SSP_PSP_SFRMP;
  124. else
  125. sspsp &= ~SSP_PSP_SFRMP;
  126. /* End Data Transfer State */
  127. if (priv->end_transfer_state == SSP_END_TRANSFER_STATE_LOW)
  128. sspsp &= ~SSP_PSP_ETDS;
  129. else
  130. sspsp |= SSP_PSP_ETDS;
  131. writel(sspsp, &priv->regs->sspsp);
  132. }
  133. static void init_ssp_time_slot(struct broadwell_i2s_priv *priv)
  134. {
  135. writel(3, &priv->regs->sstsa);
  136. writel(3, &priv->regs->ssrsa);
  137. }
  138. static int bdw_i2s_init(struct udevice *dev)
  139. {
  140. struct i2s_uc_priv *uc_priv = dev_get_uclass_priv(dev);
  141. struct broadwell_i2s_priv *priv = dev_get_priv(dev);
  142. init_shim_csr(priv);
  143. init_shim_clkctl(uc_priv, priv);
  144. init_sscr0(uc_priv, priv);
  145. init_sscr1(priv);
  146. init_sspsp(priv);
  147. init_ssp_time_slot(priv);
  148. return 0;
  149. }
  150. static void bdw_i2s_enable(struct broadwell_i2s_priv *priv)
  151. {
  152. setbits_le32(&priv->regs->sscr0, SSP_SSC0_SSE);
  153. setbits_le32(&priv->regs->sstsa, SSP_SSTSA_EN);
  154. }
  155. static void bdw_i2s_disable(struct broadwell_i2s_priv *priv)
  156. {
  157. clrbits_le32(&priv->regs->sstsa, SSP_SSTSA_EN);
  158. clrbits_le32(&priv->regs->sstsa, SSP_SSTSA_EN);
  159. }
  160. static int broadwell_i2s_tx_data(struct udevice *dev, void *data,
  161. uint data_size)
  162. {
  163. struct broadwell_i2s_priv *priv = dev_get_priv(dev);
  164. u32 *ptr = data;
  165. log_debug("data=%p, data_size=%x\n", data, data_size);
  166. if (data_size < SSP_FIFO_SIZE) {
  167. log_err("Invalid I2S data size\n");
  168. return -ENODATA;
  169. }
  170. /* Enable I2S interface */
  171. bdw_i2s_enable(priv);
  172. /* Transfer data */
  173. while (data_size > 0) {
  174. ulong start = timer_get_us() + 100000;
  175. /* Write data if transmit FIFO has room */
  176. if (readl(&priv->regs->sssr) & SSP_SSS_TNF) {
  177. writel(*ptr++, &priv->regs->ssdr);
  178. data_size -= sizeof(*ptr);
  179. } else {
  180. if ((long)(timer_get_us() - start) > 0) {
  181. /* Disable I2S interface */
  182. bdw_i2s_disable(priv);
  183. log_debug("I2S Transfer Timeout\n");
  184. return -ETIMEDOUT;
  185. }
  186. }
  187. }
  188. /* Disable I2S interface */
  189. bdw_i2s_disable(priv);
  190. log_debug("done\n");
  191. return 0;
  192. }
  193. static int broadwell_i2s_probe(struct udevice *dev)
  194. {
  195. struct i2s_uc_priv *uc_priv = dev_get_uclass_priv(dev);
  196. struct broadwell_i2s_priv *priv = dev_get_priv(dev);
  197. struct udevice *adsp = dev_get_parent(dev);
  198. u32 bar0, offset;
  199. int ret;
  200. bar0 = dm_pci_read_bar32(adsp, 0);
  201. if (!bar0) {
  202. log_debug("Cannot read adsp bar0\n");
  203. return -EINVAL;
  204. }
  205. offset = dev_read_addr_index(dev, 0);
  206. if (offset == FDT_ADDR_T_NONE) {
  207. log_debug("Cannot read address index 0\n");
  208. return -EINVAL;
  209. }
  210. uc_priv->base_address = bar0 + offset;
  211. /*
  212. * Hard-code these values. If other settings are required we can add
  213. * this to the device tree.
  214. */
  215. uc_priv->rfs = 64;
  216. uc_priv->bfs = 32;
  217. uc_priv->audio_pll_clk = 24 * 1000 * 1000;
  218. uc_priv->samplingrate = 48000;
  219. uc_priv->bitspersample = 16;
  220. uc_priv->channels = 2;
  221. uc_priv->id = 0;
  222. priv->shim = (struct i2s_shim_regs *)uc_priv->base_address;
  223. priv->sfrm_polarity = SSP_FRMS_ACTIVE_LOW;
  224. priv->end_transfer_state = SSP_END_TRANSFER_STATE_LOW;
  225. priv->sclk_mode = SCLK_MODE_DDF_DSR_ISL;
  226. priv->rel_timing = NEXT_FRMS_WITH_LSB_PREVIOUS_FRM;
  227. priv->sclk_dummy_stop = 0;
  228. priv->sclk_frame_width = 31;
  229. offset = dev_read_addr_index(dev, 1 + uc_priv->id);
  230. if (offset == FDT_ADDR_T_NONE) {
  231. log_debug("Cannot read address index %d\n", 1 + uc_priv->id);
  232. return -EINVAL;
  233. }
  234. log_debug("bar0=%x, uc_priv->base_address=%x, offset=%x\n", bar0,
  235. uc_priv->base_address, offset);
  236. priv->regs = (struct broadwell_i2s_regs *)(bar0 + offset);
  237. ret = bdw_i2s_init(dev);
  238. if (ret)
  239. return ret;
  240. return 0;
  241. }
  242. static const struct i2s_ops broadwell_i2s_ops = {
  243. .tx_data = broadwell_i2s_tx_data,
  244. };
  245. static const struct udevice_id broadwell_i2s_ids[] = {
  246. { .compatible = "intel,broadwell-i2s" },
  247. { }
  248. };
  249. U_BOOT_DRIVER(broadwell_i2s) = {
  250. .name = "broadwell_i2s",
  251. .id = UCLASS_I2S,
  252. .of_match = broadwell_i2s_ids,
  253. .probe = broadwell_i2s_probe,
  254. .ops = &broadwell_i2s_ops,
  255. .priv_auto_alloc_size = sizeof(struct broadwell_i2s_priv),
  256. };