serial_uniphier.c 5.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012-2015 Panasonic Corporation
  4. * Copyright (C) 2015-2016 Socionext Inc.
  5. * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  6. */
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <linux/bitfield.h>
  10. #include <linux/bitops.h>
  11. #include <linux/bug.h>
  12. #include <linux/io.h>
  13. #include <linux/serial_reg.h>
  14. #include <linux/sizes.h>
  15. #include <linux/errno.h>
  16. #include <serial.h>
  17. #include <fdtdec.h>
  18. #define UNIPHIER_UART_REGSHIFT 2
  19. #define UNIPHIER_UART_RX (0 << (UNIPHIER_UART_REGSHIFT))
  20. #define UNIPHIER_UART_TX UNIPHIER_UART_RX
  21. /* bit[15:8] = CHAR, bit[7:0] = FCR */
  22. #define UNIPHIER_UART_CHAR_FCR (3 << (UNIPHIER_UART_REGSHIFT))
  23. #define UNIPHIER_UART_FCR_MASK GENMASK(7, 0)
  24. /* bit[15:8] = LCR, bit[7:0] = MCR */
  25. #define UNIPHIER_UART_LCR_MCR (4 << (UNIPHIER_UART_REGSHIFT))
  26. #define UNIPHIER_UART_LCR_MASK GENMASK(15, 8)
  27. #define UNIPHIER_UART_LSR (5 << (UNIPHIER_UART_REGSHIFT))
  28. /* Divisor Latch Register */
  29. #define UNIPHIER_UART_DLR (9 << (UNIPHIER_UART_REGSHIFT))
  30. struct uniphier_serial_priv {
  31. void __iomem *membase;
  32. unsigned int uartclk;
  33. };
  34. static int uniphier_serial_setbrg(struct udevice *dev, int baudrate)
  35. {
  36. struct uniphier_serial_priv *priv = dev_get_priv(dev);
  37. static const unsigned int mode_x_div = 16;
  38. unsigned int divisor;
  39. divisor = DIV_ROUND_CLOSEST(priv->uartclk, mode_x_div * baudrate);
  40. /* flush the trasmitter before changing hw setting */
  41. while (!(readl(priv->membase + UNIPHIER_UART_LSR) & UART_LSR_TEMT))
  42. ;
  43. writel(divisor, priv->membase + UNIPHIER_UART_DLR);
  44. return 0;
  45. }
  46. static int uniphier_serial_getc(struct udevice *dev)
  47. {
  48. struct uniphier_serial_priv *priv = dev_get_priv(dev);
  49. if (!(readl(priv->membase + UNIPHIER_UART_LSR) & UART_LSR_DR))
  50. return -EAGAIN;
  51. return readl(priv->membase + UNIPHIER_UART_RX);
  52. }
  53. static int uniphier_serial_putc(struct udevice *dev, const char c)
  54. {
  55. struct uniphier_serial_priv *priv = dev_get_priv(dev);
  56. if (!(readl(priv->membase + UNIPHIER_UART_LSR) & UART_LSR_THRE))
  57. return -EAGAIN;
  58. writel(c, priv->membase + UNIPHIER_UART_TX);
  59. return 0;
  60. }
  61. static int uniphier_serial_pending(struct udevice *dev, bool input)
  62. {
  63. struct uniphier_serial_priv *priv = dev_get_priv(dev);
  64. if (input)
  65. return readl(priv->membase + UNIPHIER_UART_LSR) & UART_LSR_DR;
  66. else
  67. return !(readl(priv->membase + UNIPHIER_UART_LSR) & UART_LSR_THRE);
  68. }
  69. /*
  70. * SPL does not have enough memory footprint for the clock driver.
  71. * Hardcode clock frequency for each SoC.
  72. */
  73. struct uniphier_serial_clk_data {
  74. const char *compatible;
  75. unsigned int clk_rate;
  76. };
  77. static const struct uniphier_serial_clk_data uniphier_serial_clk_data[] = {
  78. { .compatible = "socionext,uniphier-ld4", .clk_rate = 36864000 },
  79. { .compatible = "socionext,uniphier-pro4", .clk_rate = 73728000 },
  80. { .compatible = "socionext,uniphier-sld8", .clk_rate = 80000000 },
  81. { .compatible = "socionext,uniphier-pro5", .clk_rate = 73728000 },
  82. { .compatible = "socionext,uniphier-pxs2", .clk_rate = 88888888 },
  83. { .compatible = "socionext,uniphier-ld6b", .clk_rate = 88888888 },
  84. { .compatible = "socionext,uniphier-ld11", .clk_rate = 58823529 },
  85. { .compatible = "socionext,uniphier-ld20", .clk_rate = 58823529 },
  86. { .compatible = "socionext,uniphier-pxs3", .clk_rate = 58823529 },
  87. { /* sentinel */ },
  88. };
  89. static int uniphier_serial_probe(struct udevice *dev)
  90. {
  91. struct uniphier_serial_priv *priv = dev_get_priv(dev);
  92. const struct uniphier_serial_clk_data *clk_data;
  93. ofnode root_node;
  94. fdt_addr_t base;
  95. u32 tmp;
  96. base = dev_read_addr(dev);
  97. if (base == FDT_ADDR_T_NONE)
  98. return -EINVAL;
  99. priv->membase = devm_ioremap(dev, base, SZ_64);
  100. if (!priv->membase)
  101. return -ENOMEM;
  102. root_node = ofnode_path("/");
  103. clk_data = uniphier_serial_clk_data;
  104. while (clk_data->compatible) {
  105. if (ofnode_device_is_compatible(root_node,
  106. clk_data->compatible))
  107. break;
  108. clk_data++;
  109. }
  110. if (WARN_ON(!clk_data->compatible))
  111. return -ENOTSUPP;
  112. priv->uartclk = clk_data->clk_rate;
  113. /* flush the trasmitter before changing hw setting */
  114. while (!(readl(priv->membase + UNIPHIER_UART_LSR) & UART_LSR_TEMT))
  115. ;
  116. /* enable FIFO */
  117. tmp = readl(priv->membase + UNIPHIER_UART_CHAR_FCR);
  118. tmp &= ~UNIPHIER_UART_FCR_MASK;
  119. tmp |= FIELD_PREP(UNIPHIER_UART_FCR_MASK, UART_FCR_ENABLE_FIFO);
  120. writel(tmp, priv->membase + UNIPHIER_UART_CHAR_FCR);
  121. tmp = readl(priv->membase + UNIPHIER_UART_LCR_MCR);
  122. tmp &= ~UNIPHIER_UART_LCR_MASK;
  123. tmp |= FIELD_PREP(UNIPHIER_UART_LCR_MASK, UART_LCR_WLEN8);
  124. writel(tmp, priv->membase + UNIPHIER_UART_LCR_MCR);
  125. return 0;
  126. }
  127. static const struct udevice_id uniphier_uart_of_match[] = {
  128. { .compatible = "socionext,uniphier-uart" },
  129. { /* sentinel */ }
  130. };
  131. static const struct dm_serial_ops uniphier_serial_ops = {
  132. .setbrg = uniphier_serial_setbrg,
  133. .getc = uniphier_serial_getc,
  134. .putc = uniphier_serial_putc,
  135. .pending = uniphier_serial_pending,
  136. };
  137. U_BOOT_DRIVER(uniphier_serial) = {
  138. .name = "uniphier-uart",
  139. .id = UCLASS_SERIAL,
  140. .of_match = uniphier_uart_of_match,
  141. .probe = uniphier_serial_probe,
  142. .priv_auto_alloc_size = sizeof(struct uniphier_serial_priv),
  143. .ops = &uniphier_serial_ops,
  144. };