serial_stm32.h 2.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
  4. * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
  5. */
  6. #ifndef _SERIAL_STM32_
  7. #define _SERIAL_STM32_
  8. #include <linux/bitops.h>
  9. #define CR1_OFFSET(x) (x ? 0x0c : 0x00)
  10. #define CR3_OFFSET(x) (x ? 0x14 : 0x08)
  11. #define BRR_OFFSET(x) (x ? 0x08 : 0x0c)
  12. #define ISR_OFFSET(x) (x ? 0x00 : 0x1c)
  13. #define ICR_OFFSET 0x20
  14. /*
  15. * STM32F4 has one Data Register (DR) for received or transmitted
  16. * data, so map Receive Data Register (RDR) and Transmit Data
  17. * Register (TDR) at the same offset
  18. */
  19. #define RDR_OFFSET(x) (x ? 0x04 : 0x24)
  20. #define TDR_OFFSET(x) (x ? 0x04 : 0x28)
  21. struct stm32_uart_info {
  22. u8 uart_enable_bit; /* UART_CR1_UE */
  23. bool stm32f4; /* true for STM32F4, false otherwise */
  24. bool has_fifo;
  25. };
  26. struct stm32_uart_info stm32f4_info = {
  27. .stm32f4 = true,
  28. .uart_enable_bit = 13,
  29. .has_fifo = false,
  30. };
  31. struct stm32_uart_info stm32f7_info = {
  32. .uart_enable_bit = 0,
  33. .stm32f4 = false,
  34. .has_fifo = true,
  35. };
  36. struct stm32_uart_info stm32h7_info = {
  37. .uart_enable_bit = 0,
  38. .stm32f4 = false,
  39. .has_fifo = true,
  40. };
  41. /* Information about a serial port */
  42. struct stm32x7_serial_platdata {
  43. fdt_addr_t base; /* address of registers in physical memory */
  44. struct stm32_uart_info *uart_info;
  45. unsigned long int clock_rate;
  46. };
  47. #define USART_CR1_FIFOEN BIT(29)
  48. #define USART_CR1_M1 BIT(28)
  49. #define USART_CR1_OVER8 BIT(15)
  50. #define USART_CR1_M0 BIT(12)
  51. #define USART_CR1_PCE BIT(10)
  52. #define USART_CR1_PS BIT(9)
  53. #define USART_CR1_TE BIT(3)
  54. #define USART_CR1_RE BIT(2)
  55. #define USART_CR3_OVRDIS BIT(12)
  56. #define USART_ISR_TXE BIT(7)
  57. #define USART_ISR_RXNE BIT(5)
  58. #define USART_ISR_ORE BIT(3)
  59. #define USART_ISR_FE BIT(1)
  60. #define USART_ISR_PE BIT(0)
  61. #define USART_BRR_F_MASK GENMASK(7, 0)
  62. #define USART_BRR_M_SHIFT 4
  63. #define USART_BRR_M_MASK GENMASK(15, 4)
  64. #define USART_ICR_ORECF BIT(3)
  65. #define USART_ICR_FECF BIT(1)
  66. #define USART_ICR_PCECF BIT(0)
  67. #endif