serial_sh.c 7.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * SuperH SCIF device driver.
  4. * Copyright (C) 2013 Renesas Electronics Corporation
  5. * Copyright (C) 2007,2008,2010, 2014 Nobuhiro Iwamatsu
  6. * Copyright (C) 2002 - 2008 Paul Mundt
  7. */
  8. #include <common.h>
  9. #include <errno.h>
  10. #include <clk.h>
  11. #include <dm.h>
  12. #include <asm/io.h>
  13. #include <asm/processor.h>
  14. #include <serial.h>
  15. #include <linux/compiler.h>
  16. #include <dm/platform_data/serial_sh.h>
  17. #include <linux/delay.h>
  18. #include "serial_sh.h"
  19. DECLARE_GLOBAL_DATA_PTR;
  20. #if defined(CONFIG_CPU_SH7780)
  21. static int scif_rxfill(struct uart_port *port)
  22. {
  23. return sci_in(port, SCRFDR) & 0xff;
  24. }
  25. #elif defined(CONFIG_CPU_SH7763)
  26. static int scif_rxfill(struct uart_port *port)
  27. {
  28. if ((port->mapbase == 0xffe00000) ||
  29. (port->mapbase == 0xffe08000)) {
  30. /* SCIF0/1*/
  31. return sci_in(port, SCRFDR) & 0xff;
  32. } else {
  33. /* SCIF2 */
  34. return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
  35. }
  36. }
  37. #else
  38. static int scif_rxfill(struct uart_port *port)
  39. {
  40. return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
  41. }
  42. #endif
  43. static void sh_serial_init_generic(struct uart_port *port)
  44. {
  45. sci_out(port, SCSCR , SCSCR_INIT(port));
  46. sci_out(port, SCSCR , SCSCR_INIT(port));
  47. sci_out(port, SCSMR, 0);
  48. sci_out(port, SCSMR, 0);
  49. sci_out(port, SCFCR, SCFCR_RFRST|SCFCR_TFRST);
  50. sci_in(port, SCFCR);
  51. sci_out(port, SCFCR, 0);
  52. #if defined(CONFIG_RZA1)
  53. sci_out(port, SCSPTR, 0x0003);
  54. #endif
  55. }
  56. static void
  57. sh_serial_setbrg_generic(struct uart_port *port, int clk, int baudrate)
  58. {
  59. if (port->clk_mode == EXT_CLK) {
  60. unsigned short dl = DL_VALUE(baudrate, clk);
  61. sci_out(port, DL, dl);
  62. /* Need wait: Clock * 1/dl * 1/16 */
  63. udelay((1000000 * dl * 16 / clk) * 1000 + 1);
  64. } else {
  65. sci_out(port, SCBRR, SCBRR_VALUE(baudrate, clk));
  66. }
  67. }
  68. static void handle_error(struct uart_port *port)
  69. {
  70. sci_in(port, SCxSR);
  71. sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
  72. sci_in(port, SCLSR);
  73. sci_out(port, SCLSR, 0x00);
  74. }
  75. static int serial_raw_putc(struct uart_port *port, const char c)
  76. {
  77. /* Tx fifo is empty */
  78. if (!(sci_in(port, SCxSR) & SCxSR_TEND(port)))
  79. return -EAGAIN;
  80. sci_out(port, SCxTDR, c);
  81. sci_out(port, SCxSR, sci_in(port, SCxSR) & ~SCxSR_TEND(port));
  82. return 0;
  83. }
  84. static int serial_rx_fifo_level(struct uart_port *port)
  85. {
  86. return scif_rxfill(port);
  87. }
  88. static int sh_serial_tstc_generic(struct uart_port *port)
  89. {
  90. if (sci_in(port, SCxSR) & SCIF_ERRORS) {
  91. handle_error(port);
  92. return 0;
  93. }
  94. return serial_rx_fifo_level(port) ? 1 : 0;
  95. }
  96. static int serial_getc_check(struct uart_port *port)
  97. {
  98. unsigned short status;
  99. status = sci_in(port, SCxSR);
  100. if (status & SCIF_ERRORS)
  101. handle_error(port);
  102. if (sci_in(port, SCLSR) & SCxSR_ORER(port))
  103. handle_error(port);
  104. status &= (SCIF_DR | SCxSR_RDxF(port));
  105. if (status)
  106. return status;
  107. return scif_rxfill(port);
  108. }
  109. static int sh_serial_getc_generic(struct uart_port *port)
  110. {
  111. unsigned short status;
  112. char ch;
  113. if (!serial_getc_check(port))
  114. return -EAGAIN;
  115. ch = sci_in(port, SCxRDR);
  116. status = sci_in(port, SCxSR);
  117. sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
  118. if (status & SCIF_ERRORS)
  119. handle_error(port);
  120. if (sci_in(port, SCLSR) & SCxSR_ORER(port))
  121. handle_error(port);
  122. return ch;
  123. }
  124. #if CONFIG_IS_ENABLED(DM_SERIAL)
  125. static int sh_serial_pending(struct udevice *dev, bool input)
  126. {
  127. struct uart_port *priv = dev_get_priv(dev);
  128. return sh_serial_tstc_generic(priv);
  129. }
  130. static int sh_serial_putc(struct udevice *dev, const char ch)
  131. {
  132. struct uart_port *priv = dev_get_priv(dev);
  133. return serial_raw_putc(priv, ch);
  134. }
  135. static int sh_serial_getc(struct udevice *dev)
  136. {
  137. struct uart_port *priv = dev_get_priv(dev);
  138. return sh_serial_getc_generic(priv);
  139. }
  140. static int sh_serial_setbrg(struct udevice *dev, int baudrate)
  141. {
  142. struct sh_serial_platdata *plat = dev_get_platdata(dev);
  143. struct uart_port *priv = dev_get_priv(dev);
  144. sh_serial_setbrg_generic(priv, plat->clk, baudrate);
  145. return 0;
  146. }
  147. static int sh_serial_probe(struct udevice *dev)
  148. {
  149. struct sh_serial_platdata *plat = dev_get_platdata(dev);
  150. struct uart_port *priv = dev_get_priv(dev);
  151. priv->membase = (unsigned char *)plat->base;
  152. priv->mapbase = plat->base;
  153. priv->type = plat->type;
  154. priv->clk_mode = plat->clk_mode;
  155. sh_serial_init_generic(priv);
  156. return 0;
  157. }
  158. static const struct dm_serial_ops sh_serial_ops = {
  159. .putc = sh_serial_putc,
  160. .pending = sh_serial_pending,
  161. .getc = sh_serial_getc,
  162. .setbrg = sh_serial_setbrg,
  163. };
  164. #if CONFIG_IS_ENABLED(OF_CONTROL)
  165. static const struct udevice_id sh_serial_id[] ={
  166. {.compatible = "renesas,sci", .data = PORT_SCI},
  167. {.compatible = "renesas,scif", .data = PORT_SCIF},
  168. {.compatible = "renesas,scifa", .data = PORT_SCIFA},
  169. {}
  170. };
  171. static int sh_serial_ofdata_to_platdata(struct udevice *dev)
  172. {
  173. struct sh_serial_platdata *plat = dev_get_platdata(dev);
  174. struct clk sh_serial_clk;
  175. fdt_addr_t addr;
  176. int ret;
  177. addr = dev_read_addr(dev);
  178. if (!addr)
  179. return -EINVAL;
  180. plat->base = addr;
  181. ret = clk_get_by_name(dev, "fck", &sh_serial_clk);
  182. if (!ret) {
  183. ret = clk_enable(&sh_serial_clk);
  184. if (!ret)
  185. plat->clk = clk_get_rate(&sh_serial_clk);
  186. } else {
  187. plat->clk = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
  188. "clock", 1);
  189. }
  190. plat->type = dev_get_driver_data(dev);
  191. return 0;
  192. }
  193. #endif
  194. U_BOOT_DRIVER(serial_sh) = {
  195. .name = "serial_sh",
  196. .id = UCLASS_SERIAL,
  197. .of_match = of_match_ptr(sh_serial_id),
  198. .ofdata_to_platdata = of_match_ptr(sh_serial_ofdata_to_platdata),
  199. .platdata_auto_alloc_size = sizeof(struct sh_serial_platdata),
  200. .probe = sh_serial_probe,
  201. .ops = &sh_serial_ops,
  202. #if !CONFIG_IS_ENABLED(OF_CONTROL)
  203. .flags = DM_FLAG_PRE_RELOC,
  204. #endif
  205. .priv_auto_alloc_size = sizeof(struct uart_port),
  206. };
  207. #else /* CONFIG_DM_SERIAL */
  208. #if defined(CONFIG_CONS_SCIF0)
  209. # define SCIF_BASE SCIF0_BASE
  210. #elif defined(CONFIG_CONS_SCIF1)
  211. # define SCIF_BASE SCIF1_BASE
  212. #elif defined(CONFIG_CONS_SCIF2)
  213. # define SCIF_BASE SCIF2_BASE
  214. #elif defined(CONFIG_CONS_SCIF3)
  215. # define SCIF_BASE SCIF3_BASE
  216. #elif defined(CONFIG_CONS_SCIF4)
  217. # define SCIF_BASE SCIF4_BASE
  218. #elif defined(CONFIG_CONS_SCIF5)
  219. # define SCIF_BASE SCIF5_BASE
  220. #elif defined(CONFIG_CONS_SCIF6)
  221. # define SCIF_BASE SCIF6_BASE
  222. #elif defined(CONFIG_CONS_SCIF7)
  223. # define SCIF_BASE SCIF7_BASE
  224. #elif defined(CONFIG_CONS_SCIFA0)
  225. # define SCIF_BASE SCIFA0_BASE
  226. #else
  227. # error "Default SCIF doesn't set....."
  228. #endif
  229. #if defined(CONFIG_SCIF_A)
  230. #define SCIF_BASE_PORT PORT_SCIFA
  231. #elif defined(CONFIG_SCI)
  232. #define SCIF_BASE_PORT PORT_SCI
  233. #else
  234. #define SCIF_BASE_PORT PORT_SCIF
  235. #endif
  236. static struct uart_port sh_sci = {
  237. .membase = (unsigned char *)SCIF_BASE,
  238. .mapbase = SCIF_BASE,
  239. .type = SCIF_BASE_PORT,
  240. #ifdef CONFIG_SCIF_USE_EXT_CLK
  241. .clk_mode = EXT_CLK,
  242. #endif
  243. };
  244. static void sh_serial_setbrg(void)
  245. {
  246. DECLARE_GLOBAL_DATA_PTR;
  247. struct uart_port *port = &sh_sci;
  248. sh_serial_setbrg_generic(port, CONFIG_SH_SCIF_CLK_FREQ, gd->baudrate);
  249. }
  250. static int sh_serial_init(void)
  251. {
  252. struct uart_port *port = &sh_sci;
  253. sh_serial_init_generic(port);
  254. serial_setbrg();
  255. return 0;
  256. }
  257. static void sh_serial_putc(const char c)
  258. {
  259. struct uart_port *port = &sh_sci;
  260. if (c == '\n') {
  261. while (1) {
  262. if (serial_raw_putc(port, '\r') != -EAGAIN)
  263. break;
  264. }
  265. }
  266. while (1) {
  267. if (serial_raw_putc(port, c) != -EAGAIN)
  268. break;
  269. }
  270. }
  271. static int sh_serial_tstc(void)
  272. {
  273. struct uart_port *port = &sh_sci;
  274. return sh_serial_tstc_generic(port);
  275. }
  276. static int sh_serial_getc(void)
  277. {
  278. struct uart_port *port = &sh_sci;
  279. int ch;
  280. while (1) {
  281. ch = sh_serial_getc_generic(port);
  282. if (ch != -EAGAIN)
  283. break;
  284. }
  285. return ch;
  286. }
  287. static struct serial_device sh_serial_drv = {
  288. .name = "sh_serial",
  289. .start = sh_serial_init,
  290. .stop = NULL,
  291. .setbrg = sh_serial_setbrg,
  292. .putc = sh_serial_putc,
  293. .puts = default_serial_puts,
  294. .getc = sh_serial_getc,
  295. .tstc = sh_serial_tstc,
  296. };
  297. void sh_serial_initialize(void)
  298. {
  299. serial_register(&sh_serial_drv);
  300. }
  301. __weak struct serial_device *default_serial_console(void)
  302. {
  303. return &sh_serial_drv;
  304. }
  305. #endif /* CONFIG_DM_SERIAL */