serial_pl01x.c 9.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2000
  4. * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
  5. *
  6. * (C) Copyright 2004
  7. * ARM Ltd.
  8. * Philippe Robin, <philippe.robin@arm.com>
  9. */
  10. /* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */
  11. #include <common.h>
  12. /* For get_bus_freq() */
  13. #include <clock_legacy.h>
  14. #include <dm.h>
  15. #include <clk.h>
  16. #include <errno.h>
  17. #include <watchdog.h>
  18. #include <asm/io.h>
  19. #include <serial.h>
  20. #include <dm/device_compat.h>
  21. #include <dm/platform_data/serial_pl01x.h>
  22. #include <linux/compiler.h>
  23. #include "serial_pl01x_internal.h"
  24. DECLARE_GLOBAL_DATA_PTR;
  25. #ifndef CONFIG_DM_SERIAL
  26. static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS;
  27. static enum pl01x_type pl01x_type __attribute__ ((section(".data")));
  28. static struct pl01x_regs *base_regs __attribute__ ((section(".data")));
  29. #define NUM_PORTS (sizeof(port)/sizeof(port[0]))
  30. #endif
  31. static int pl01x_putc(struct pl01x_regs *regs, char c)
  32. {
  33. /* Wait until there is space in the FIFO */
  34. if (readl(&regs->fr) & UART_PL01x_FR_TXFF)
  35. return -EAGAIN;
  36. /* Send the character */
  37. writel(c, &regs->dr);
  38. return 0;
  39. }
  40. static int pl01x_getc(struct pl01x_regs *regs)
  41. {
  42. unsigned int data;
  43. /* Wait until there is data in the FIFO */
  44. if (readl(&regs->fr) & UART_PL01x_FR_RXFE)
  45. return -EAGAIN;
  46. data = readl(&regs->dr);
  47. /* Check for an error flag */
  48. if (data & 0xFFFFFF00) {
  49. /* Clear the error */
  50. writel(0xFFFFFFFF, &regs->ecr);
  51. return -1;
  52. }
  53. return (int) data;
  54. }
  55. static int pl01x_tstc(struct pl01x_regs *regs)
  56. {
  57. WATCHDOG_RESET();
  58. return !(readl(&regs->fr) & UART_PL01x_FR_RXFE);
  59. }
  60. static int pl01x_generic_serial_init(struct pl01x_regs *regs,
  61. enum pl01x_type type)
  62. {
  63. switch (type) {
  64. case TYPE_PL010:
  65. /* disable everything */
  66. writel(0, &regs->pl010_cr);
  67. break;
  68. case TYPE_PL011:
  69. /* disable everything */
  70. writel(0, &regs->pl011_cr);
  71. break;
  72. default:
  73. return -EINVAL;
  74. }
  75. return 0;
  76. }
  77. static int pl011_set_line_control(struct pl01x_regs *regs)
  78. {
  79. unsigned int lcr;
  80. /*
  81. * Internal update of baud rate register require line
  82. * control register write
  83. */
  84. lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN;
  85. writel(lcr, &regs->pl011_lcrh);
  86. return 0;
  87. }
  88. static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type,
  89. int clock, int baudrate)
  90. {
  91. switch (type) {
  92. case TYPE_PL010: {
  93. unsigned int divisor;
  94. /* disable everything */
  95. writel(0, &regs->pl010_cr);
  96. switch (baudrate) {
  97. case 9600:
  98. divisor = UART_PL010_BAUD_9600;
  99. break;
  100. case 19200:
  101. divisor = UART_PL010_BAUD_19200;
  102. break;
  103. case 38400:
  104. divisor = UART_PL010_BAUD_38400;
  105. break;
  106. case 57600:
  107. divisor = UART_PL010_BAUD_57600;
  108. break;
  109. case 115200:
  110. divisor = UART_PL010_BAUD_115200;
  111. break;
  112. default:
  113. divisor = UART_PL010_BAUD_38400;
  114. }
  115. writel((divisor & 0xf00) >> 8, &regs->pl010_lcrm);
  116. writel(divisor & 0xff, &regs->pl010_lcrl);
  117. /*
  118. * Set line control for the PL010 to be 8 bits, 1 stop bit,
  119. * no parity, fifo enabled
  120. */
  121. writel(UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN,
  122. &regs->pl010_lcrh);
  123. /* Finally, enable the UART */
  124. writel(UART_PL010_CR_UARTEN, &regs->pl010_cr);
  125. break;
  126. }
  127. case TYPE_PL011: {
  128. unsigned int temp;
  129. unsigned int divider;
  130. unsigned int remainder;
  131. unsigned int fraction;
  132. /* Without a valid clock rate we cannot set up the baudrate. */
  133. if (clock) {
  134. /*
  135. * Set baud rate
  136. *
  137. * IBRD = UART_CLK / (16 * BAUD_RATE)
  138. * FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE)))
  139. * / (16 * BAUD_RATE))
  140. */
  141. temp = 16 * baudrate;
  142. divider = clock / temp;
  143. remainder = clock % temp;
  144. temp = (8 * remainder) / baudrate;
  145. fraction = (temp >> 1) + (temp & 1);
  146. writel(divider, &regs->pl011_ibrd);
  147. writel(fraction, &regs->pl011_fbrd);
  148. }
  149. pl011_set_line_control(regs);
  150. /* Finally, enable the UART */
  151. writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE |
  152. UART_PL011_CR_RXE | UART_PL011_CR_RTS, &regs->pl011_cr);
  153. break;
  154. }
  155. default:
  156. return -EINVAL;
  157. }
  158. return 0;
  159. }
  160. #ifndef CONFIG_DM_SERIAL
  161. static void pl01x_serial_init_baud(int baudrate)
  162. {
  163. int clock = 0;
  164. #if defined(CONFIG_PL010_SERIAL)
  165. pl01x_type = TYPE_PL010;
  166. #elif defined(CONFIG_PL011_SERIAL)
  167. pl01x_type = TYPE_PL011;
  168. clock = CONFIG_PL011_CLOCK;
  169. #endif
  170. base_regs = (struct pl01x_regs *)port[CONFIG_CONS_INDEX];
  171. pl01x_generic_serial_init(base_regs, pl01x_type);
  172. pl01x_generic_setbrg(base_regs, pl01x_type, clock, baudrate);
  173. }
  174. /*
  175. * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1
  176. * Integrator CP has two UARTs, use the first one, at 38400-8-N-1
  177. * Versatile PB has four UARTs.
  178. */
  179. int pl01x_serial_init(void)
  180. {
  181. pl01x_serial_init_baud(CONFIG_BAUDRATE);
  182. return 0;
  183. }
  184. static void pl01x_serial_putc(const char c)
  185. {
  186. if (c == '\n')
  187. while (pl01x_putc(base_regs, '\r') == -EAGAIN);
  188. while (pl01x_putc(base_regs, c) == -EAGAIN);
  189. }
  190. static int pl01x_serial_getc(void)
  191. {
  192. while (1) {
  193. int ch = pl01x_getc(base_regs);
  194. if (ch == -EAGAIN) {
  195. WATCHDOG_RESET();
  196. continue;
  197. }
  198. return ch;
  199. }
  200. }
  201. static int pl01x_serial_tstc(void)
  202. {
  203. return pl01x_tstc(base_regs);
  204. }
  205. static void pl01x_serial_setbrg(void)
  206. {
  207. /*
  208. * Flush FIFO and wait for non-busy before changing baudrate to avoid
  209. * crap in console
  210. */
  211. while (!(readl(&base_regs->fr) & UART_PL01x_FR_TXFE))
  212. WATCHDOG_RESET();
  213. while (readl(&base_regs->fr) & UART_PL01x_FR_BUSY)
  214. WATCHDOG_RESET();
  215. pl01x_serial_init_baud(gd->baudrate);
  216. }
  217. static struct serial_device pl01x_serial_drv = {
  218. .name = "pl01x_serial",
  219. .start = pl01x_serial_init,
  220. .stop = NULL,
  221. .setbrg = pl01x_serial_setbrg,
  222. .putc = pl01x_serial_putc,
  223. .puts = default_serial_puts,
  224. .getc = pl01x_serial_getc,
  225. .tstc = pl01x_serial_tstc,
  226. };
  227. void pl01x_serial_initialize(void)
  228. {
  229. serial_register(&pl01x_serial_drv);
  230. }
  231. __weak struct serial_device *default_serial_console(void)
  232. {
  233. return &pl01x_serial_drv;
  234. }
  235. #endif /* nCONFIG_DM_SERIAL */
  236. #ifdef CONFIG_DM_SERIAL
  237. int pl01x_serial_setbrg(struct udevice *dev, int baudrate)
  238. {
  239. struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
  240. struct pl01x_priv *priv = dev_get_priv(dev);
  241. if (!plat->skip_init) {
  242. pl01x_generic_setbrg(priv->regs, priv->type, plat->clock,
  243. baudrate);
  244. }
  245. return 0;
  246. }
  247. int pl01x_serial_probe(struct udevice *dev)
  248. {
  249. struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
  250. struct pl01x_priv *priv = dev_get_priv(dev);
  251. priv->regs = (struct pl01x_regs *)plat->base;
  252. priv->type = plat->type;
  253. if (!plat->skip_init)
  254. return pl01x_generic_serial_init(priv->regs, priv->type);
  255. else
  256. return 0;
  257. }
  258. int pl01x_serial_getc(struct udevice *dev)
  259. {
  260. struct pl01x_priv *priv = dev_get_priv(dev);
  261. return pl01x_getc(priv->regs);
  262. }
  263. int pl01x_serial_putc(struct udevice *dev, const char ch)
  264. {
  265. struct pl01x_priv *priv = dev_get_priv(dev);
  266. return pl01x_putc(priv->regs, ch);
  267. }
  268. int pl01x_serial_pending(struct udevice *dev, bool input)
  269. {
  270. struct pl01x_priv *priv = dev_get_priv(dev);
  271. unsigned int fr = readl(&priv->regs->fr);
  272. if (input)
  273. return pl01x_tstc(priv->regs);
  274. else
  275. return fr & UART_PL01x_FR_TXFF ? 0 : 1;
  276. }
  277. static const struct dm_serial_ops pl01x_serial_ops = {
  278. .putc = pl01x_serial_putc,
  279. .pending = pl01x_serial_pending,
  280. .getc = pl01x_serial_getc,
  281. .setbrg = pl01x_serial_setbrg,
  282. };
  283. #if CONFIG_IS_ENABLED(OF_CONTROL)
  284. static const struct udevice_id pl01x_serial_id[] ={
  285. {.compatible = "arm,pl011", .data = TYPE_PL011},
  286. {.compatible = "arm,pl010", .data = TYPE_PL010},
  287. {}
  288. };
  289. #ifndef CONFIG_PL011_CLOCK
  290. #define CONFIG_PL011_CLOCK 0
  291. #endif
  292. int pl01x_serial_ofdata_to_platdata(struct udevice *dev)
  293. {
  294. struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
  295. struct clk clk;
  296. fdt_addr_t addr;
  297. int ret;
  298. addr = dev_read_addr(dev);
  299. if (addr == FDT_ADDR_T_NONE)
  300. return -EINVAL;
  301. plat->base = addr;
  302. plat->clock = dev_read_u32_default(dev, "clock", CONFIG_PL011_CLOCK);
  303. ret = clk_get_by_index(dev, 0, &clk);
  304. if (!ret) {
  305. ret = clk_enable(&clk);
  306. if (ret && ret != -ENOSYS) {
  307. dev_err(dev, "failed to enable clock\n");
  308. return ret;
  309. }
  310. plat->clock = clk_get_rate(&clk);
  311. if (IS_ERR_VALUE(plat->clock)) {
  312. dev_err(dev, "failed to get rate\n");
  313. return plat->clock;
  314. }
  315. debug("%s: CLK %d\n", __func__, plat->clock);
  316. }
  317. plat->type = dev_get_driver_data(dev);
  318. plat->skip_init = dev_read_bool(dev, "skip-init");
  319. return 0;
  320. }
  321. #endif
  322. U_BOOT_DRIVER(serial_pl01x) = {
  323. .name = "serial_pl01x",
  324. .id = UCLASS_SERIAL,
  325. .of_match = of_match_ptr(pl01x_serial_id),
  326. .ofdata_to_platdata = of_match_ptr(pl01x_serial_ofdata_to_platdata),
  327. .platdata_auto_alloc_size = sizeof(struct pl01x_serial_platdata),
  328. .probe = pl01x_serial_probe,
  329. .ops = &pl01x_serial_ops,
  330. .flags = DM_FLAG_PRE_RELOC,
  331. .priv_auto_alloc_size = sizeof(struct pl01x_priv),
  332. };
  333. #endif
  334. #if defined(CONFIG_DEBUG_UART_PL010) || defined(CONFIG_DEBUG_UART_PL011)
  335. #include <debug_uart.h>
  336. static void _debug_uart_init(void)
  337. {
  338. #ifndef CONFIG_DEBUG_UART_SKIP_INIT
  339. struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_DEBUG_UART_BASE;
  340. enum pl01x_type type = CONFIG_IS_ENABLED(DEBUG_UART_PL011) ?
  341. TYPE_PL011 : TYPE_PL010;
  342. pl01x_generic_serial_init(regs, type);
  343. pl01x_generic_setbrg(regs, type,
  344. CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
  345. #endif
  346. }
  347. static inline void _debug_uart_putc(int ch)
  348. {
  349. struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_DEBUG_UART_BASE;
  350. pl01x_putc(regs, ch);
  351. }
  352. DEBUG_UART_FUNCS
  353. #endif