serial_mxc.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <errno.h>
  8. #include <watchdog.h>
  9. #include <asm/arch/imx-regs.h>
  10. #include <asm/arch/clock.h>
  11. #include <dm/platform_data/serial_mxc.h>
  12. #include <serial.h>
  13. #include <linux/compiler.h>
  14. /* UART Control Register Bit Fields.*/
  15. #define URXD_CHARRDY (1<<15)
  16. #define URXD_ERR (1<<14)
  17. #define URXD_OVRRUN (1<<13)
  18. #define URXD_FRMERR (1<<12)
  19. #define URXD_BRK (1<<11)
  20. #define URXD_PRERR (1<<10)
  21. #define URXD_RX_DATA (0xFF)
  22. #define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
  23. #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
  24. #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
  25. #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
  26. #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
  27. #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
  28. #define UCR1_IREN (1<<7) /* Infrared interface enable */
  29. #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
  30. #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
  31. #define UCR1_SNDBRK (1<<4) /* Send break */
  32. #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
  33. #define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
  34. #define UCR1_DOZE (1<<1) /* Doze */
  35. #define UCR1_UARTEN (1<<0) /* UART enabled */
  36. #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
  37. #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
  38. #define UCR2_CTSC (1<<13) /* CTS pin control */
  39. #define UCR2_CTS (1<<12) /* Clear to send */
  40. #define UCR2_ESCEN (1<<11) /* Escape enable */
  41. #define UCR2_PREN (1<<8) /* Parity enable */
  42. #define UCR2_PROE (1<<7) /* Parity odd/even */
  43. #define UCR2_STPB (1<<6) /* Stop */
  44. #define UCR2_WS (1<<5) /* Word size */
  45. #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
  46. #define UCR2_TXEN (1<<2) /* Transmitter enabled */
  47. #define UCR2_RXEN (1<<1) /* Receiver enabled */
  48. #define UCR2_SRST (1<<0) /* SW reset */
  49. #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
  50. #define UCR3_PARERREN (1<<12) /* Parity enable */
  51. #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
  52. #define UCR3_DSR (1<<10) /* Data set ready */
  53. #define UCR3_DCD (1<<9) /* Data carrier detect */
  54. #define UCR3_RI (1<<8) /* Ring indicator */
  55. #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
  56. #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
  57. #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
  58. #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
  59. #define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
  60. #define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
  61. #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
  62. #define UCR3_BPEN (1<<0) /* Preset registers enable */
  63. #define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
  64. #define UCR4_INVR (1<<9) /* Inverted infrared reception */
  65. #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
  66. #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
  67. #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
  68. #define UCR4_IRSC (1<<5) /* IR special case */
  69. #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
  70. #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
  71. #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
  72. #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
  73. #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
  74. #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
  75. #define UFCR_RFDIV_SHF 7 /* Reference freq divider shift */
  76. #define RFDIV 4 /* divide input clock by 2 */
  77. #define UFCR_DCEDTE (1<<6) /* DTE mode select */
  78. #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
  79. #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
  80. #define USR1_RTSS (1<<14) /* RTS pin status */
  81. #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
  82. #define USR1_RTSD (1<<12) /* RTS delta */
  83. #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
  84. #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
  85. #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
  86. #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
  87. #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
  88. #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
  89. #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
  90. #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
  91. #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
  92. #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
  93. #define USR2_IDLE (1<<12) /* Idle condition */
  94. #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
  95. #define USR2_WAKE (1<<7) /* Wake */
  96. #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
  97. #define USR2_TXDC (1<<3) /* Transmitter complete */
  98. #define USR2_BRCD (1<<2) /* Break condition */
  99. #define USR2_ORE (1<<1) /* Overrun error */
  100. #define USR2_RDR (1<<0) /* Recv data ready */
  101. #define UTS_FRCPERR (1<<13) /* Force parity error */
  102. #define UTS_LOOP (1<<12) /* Loop tx and rx */
  103. #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
  104. #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
  105. #define UTS_TXFULL (1<<4) /* TxFIFO full */
  106. #define UTS_RXFULL (1<<3) /* RxFIFO full */
  107. #define UTS_SOFTRS (1<<0) /* Software reset */
  108. #define TXTL 2 /* reset default */
  109. #define RXTL 1 /* reset default */
  110. DECLARE_GLOBAL_DATA_PTR;
  111. struct mxc_uart {
  112. u32 rxd;
  113. u32 spare0[15];
  114. u32 txd;
  115. u32 spare1[15];
  116. u32 cr1;
  117. u32 cr2;
  118. u32 cr3;
  119. u32 cr4;
  120. u32 fcr;
  121. u32 sr1;
  122. u32 sr2;
  123. u32 esc;
  124. u32 tim;
  125. u32 bir;
  126. u32 bmr;
  127. u32 brc;
  128. u32 onems;
  129. u32 ts;
  130. };
  131. static void _mxc_serial_init(struct mxc_uart *base, int use_dte)
  132. {
  133. writel(0, &base->cr1);
  134. writel(0, &base->cr2);
  135. while (!(readl(&base->cr2) & UCR2_SRST));
  136. if (use_dte)
  137. writel(0x404 | UCR3_ADNIMP, &base->cr3);
  138. else
  139. writel(0x704 | UCR3_ADNIMP, &base->cr3);
  140. writel(0x704 | UCR3_ADNIMP, &base->cr3);
  141. writel(0x8000, &base->cr4);
  142. writel(0x2b, &base->esc);
  143. writel(0, &base->tim);
  144. writel(0, &base->ts);
  145. }
  146. static void _mxc_serial_setbrg(struct mxc_uart *base, unsigned long clk,
  147. unsigned long baudrate, bool use_dte)
  148. {
  149. u32 tmp;
  150. tmp = RFDIV << UFCR_RFDIV_SHF;
  151. if (use_dte)
  152. tmp |= UFCR_DCEDTE;
  153. else
  154. tmp |= (TXTL << UFCR_TXTL_SHF) | (RXTL << UFCR_RXTL_SHF);
  155. writel(tmp, &base->fcr);
  156. writel(0xf, &base->bir);
  157. writel(clk / (2 * baudrate), &base->bmr);
  158. writel(UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST,
  159. &base->cr2);
  160. writel(UCR1_UARTEN, &base->cr1);
  161. }
  162. #if !CONFIG_IS_ENABLED(DM_SERIAL)
  163. #ifndef CONFIG_MXC_UART_BASE
  164. #error "define CONFIG_MXC_UART_BASE to use the MXC UART driver"
  165. #endif
  166. #define mxc_base ((struct mxc_uart *)CONFIG_MXC_UART_BASE)
  167. static void mxc_serial_setbrg(void)
  168. {
  169. u32 clk = imx_get_uartclk();
  170. if (!gd->baudrate)
  171. gd->baudrate = CONFIG_BAUDRATE;
  172. _mxc_serial_setbrg(mxc_base, clk, gd->baudrate, false);
  173. }
  174. static int mxc_serial_getc(void)
  175. {
  176. while (readl(&mxc_base->ts) & UTS_RXEMPTY)
  177. WATCHDOG_RESET();
  178. return (readl(&mxc_base->rxd) & URXD_RX_DATA); /* mask out status from upper word */
  179. }
  180. static void mxc_serial_putc(const char c)
  181. {
  182. /* If \n, also do \r */
  183. if (c == '\n')
  184. serial_putc('\r');
  185. writel(c, &mxc_base->txd);
  186. /* wait for transmitter to be ready */
  187. while (!(readl(&mxc_base->ts) & UTS_TXEMPTY))
  188. WATCHDOG_RESET();
  189. }
  190. /* Test whether a character is in the RX buffer */
  191. static int mxc_serial_tstc(void)
  192. {
  193. /* If receive fifo is empty, return false */
  194. if (readl(&mxc_base->ts) & UTS_RXEMPTY)
  195. return 0;
  196. return 1;
  197. }
  198. /*
  199. * Initialise the serial port with the given baudrate. The settings
  200. * are always 8 data bits, no parity, 1 stop bit, no start bits.
  201. */
  202. static int mxc_serial_init(void)
  203. {
  204. _mxc_serial_init(mxc_base, false);
  205. serial_setbrg();
  206. return 0;
  207. }
  208. static struct serial_device mxc_serial_drv = {
  209. .name = "mxc_serial",
  210. .start = mxc_serial_init,
  211. .stop = NULL,
  212. .setbrg = mxc_serial_setbrg,
  213. .putc = mxc_serial_putc,
  214. .puts = default_serial_puts,
  215. .getc = mxc_serial_getc,
  216. .tstc = mxc_serial_tstc,
  217. };
  218. void mxc_serial_initialize(void)
  219. {
  220. serial_register(&mxc_serial_drv);
  221. }
  222. __weak struct serial_device *default_serial_console(void)
  223. {
  224. return &mxc_serial_drv;
  225. }
  226. #endif
  227. #if CONFIG_IS_ENABLED(DM_SERIAL)
  228. int mxc_serial_setbrg(struct udevice *dev, int baudrate)
  229. {
  230. struct mxc_serial_platdata *plat = dev->platdata;
  231. u32 clk = imx_get_uartclk();
  232. _mxc_serial_setbrg(plat->reg, clk, baudrate, plat->use_dte);
  233. return 0;
  234. }
  235. static int mxc_serial_probe(struct udevice *dev)
  236. {
  237. struct mxc_serial_platdata *plat = dev->platdata;
  238. _mxc_serial_init(plat->reg, plat->use_dte);
  239. return 0;
  240. }
  241. static int mxc_serial_getc(struct udevice *dev)
  242. {
  243. struct mxc_serial_platdata *plat = dev->platdata;
  244. struct mxc_uart *const uart = plat->reg;
  245. if (readl(&uart->ts) & UTS_RXEMPTY)
  246. return -EAGAIN;
  247. return readl(&uart->rxd) & URXD_RX_DATA;
  248. }
  249. static int mxc_serial_putc(struct udevice *dev, const char ch)
  250. {
  251. struct mxc_serial_platdata *plat = dev->platdata;
  252. struct mxc_uart *const uart = plat->reg;
  253. if (!(readl(&uart->ts) & UTS_TXEMPTY))
  254. return -EAGAIN;
  255. writel(ch, &uart->txd);
  256. return 0;
  257. }
  258. static int mxc_serial_pending(struct udevice *dev, bool input)
  259. {
  260. struct mxc_serial_platdata *plat = dev->platdata;
  261. struct mxc_uart *const uart = plat->reg;
  262. uint32_t sr2 = readl(&uart->sr2);
  263. if (input)
  264. return sr2 & USR2_RDR ? 1 : 0;
  265. else
  266. return sr2 & USR2_TXDC ? 0 : 1;
  267. }
  268. static const struct dm_serial_ops mxc_serial_ops = {
  269. .putc = mxc_serial_putc,
  270. .pending = mxc_serial_pending,
  271. .getc = mxc_serial_getc,
  272. .setbrg = mxc_serial_setbrg,
  273. };
  274. #if CONFIG_IS_ENABLED(OF_CONTROL)
  275. static int mxc_serial_ofdata_to_platdata(struct udevice *dev)
  276. {
  277. struct mxc_serial_platdata *plat = dev->platdata;
  278. fdt_addr_t addr;
  279. addr = dev_read_addr(dev);
  280. if (addr == FDT_ADDR_T_NONE)
  281. return -EINVAL;
  282. plat->reg = (struct mxc_uart *)addr;
  283. plat->use_dte = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
  284. "fsl,dte-mode");
  285. return 0;
  286. }
  287. static const struct udevice_id mxc_serial_ids[] = {
  288. { .compatible = "fsl,imx21-uart" },
  289. { .compatible = "fsl,imx53-uart" },
  290. { .compatible = "fsl,imx6sx-uart" },
  291. { .compatible = "fsl,imx6ul-uart" },
  292. { .compatible = "fsl,imx7d-uart" },
  293. { .compatible = "fsl,imx6q-uart" },
  294. { }
  295. };
  296. #endif
  297. U_BOOT_DRIVER(serial_mxc) = {
  298. .name = "serial_mxc",
  299. .id = UCLASS_SERIAL,
  300. #if CONFIG_IS_ENABLED(OF_CONTROL)
  301. .of_match = mxc_serial_ids,
  302. .ofdata_to_platdata = mxc_serial_ofdata_to_platdata,
  303. .platdata_auto_alloc_size = sizeof(struct mxc_serial_platdata),
  304. #endif
  305. .probe = mxc_serial_probe,
  306. .ops = &mxc_serial_ops,
  307. .flags = DM_FLAG_PRE_RELOC,
  308. };
  309. #endif
  310. #ifdef CONFIG_DEBUG_UART_MXC
  311. #include <debug_uart.h>
  312. static inline void _debug_uart_init(void)
  313. {
  314. struct mxc_uart *base = (struct mxc_uart *)CONFIG_DEBUG_UART_BASE;
  315. _mxc_serial_init(base, false);
  316. _mxc_serial_setbrg(base, CONFIG_DEBUG_UART_CLOCK,
  317. CONFIG_BAUDRATE, false);
  318. }
  319. static inline void _debug_uart_putc(int ch)
  320. {
  321. struct mxc_uart *base = (struct mxc_uart *)CONFIG_DEBUG_UART_BASE;
  322. while (!(readl(&base->ts) & UTS_TXEMPTY))
  323. WATCHDOG_RESET();
  324. writel(ch, &base->txd);
  325. }
  326. DEBUG_UART_FUNCS
  327. #endif