serial_mtk.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * MediaTek High-speed UART driver
  4. *
  5. * Copyright (C) 2018 MediaTek Inc.
  6. * Author: Weijie Gao <weijie.gao@mediatek.com>
  7. */
  8. #include <clk.h>
  9. #include <common.h>
  10. #include <div64.h>
  11. #include <dm.h>
  12. #include <errno.h>
  13. #include <log.h>
  14. #include <serial.h>
  15. #include <watchdog.h>
  16. #include <asm/io.h>
  17. #include <asm/types.h>
  18. #include <linux/err.h>
  19. struct mtk_serial_regs {
  20. u32 rbr;
  21. u32 ier;
  22. u32 fcr;
  23. u32 lcr;
  24. u32 mcr;
  25. u32 lsr;
  26. u32 msr;
  27. u32 spr;
  28. u32 mdr1;
  29. u32 highspeed;
  30. u32 sample_count;
  31. u32 sample_point;
  32. u32 fracdiv_l;
  33. u32 fracdiv_m;
  34. u32 escape_en;
  35. u32 guard;
  36. u32 rx_sel;
  37. };
  38. #define thr rbr
  39. #define iir fcr
  40. #define dll rbr
  41. #define dlm ier
  42. #define UART_LCR_WLS_8 0x03 /* 8 bit character length */
  43. #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
  44. #define UART_LSR_DR 0x01 /* Data ready */
  45. #define UART_LSR_THRE 0x20 /* Xmit holding register empty */
  46. #define UART_LSR_TEMT 0x40 /* Xmitter empty */
  47. #define UART_MCR_DTR 0x01 /* DTR */
  48. #define UART_MCR_RTS 0x02 /* RTS */
  49. #define UART_FCR_FIFO_EN 0x01 /* Fifo enable */
  50. #define UART_FCR_RXSR 0x02 /* Receiver soft reset */
  51. #define UART_FCR_TXSR 0x04 /* Transmitter soft reset */
  52. #define UART_MCRVAL (UART_MCR_DTR | \
  53. UART_MCR_RTS)
  54. /* Clear & enable FIFOs */
  55. #define UART_FCRVAL (UART_FCR_FIFO_EN | \
  56. UART_FCR_RXSR | \
  57. UART_FCR_TXSR)
  58. /* the data is correct if the real baud is within 3%. */
  59. #define BAUD_ALLOW_MAX(baud) ((baud) + (baud) * 3 / 100)
  60. #define BAUD_ALLOW_MIX(baud) ((baud) - (baud) * 3 / 100)
  61. struct mtk_serial_priv {
  62. struct mtk_serial_regs __iomem *regs;
  63. u32 clock;
  64. };
  65. static void _mtk_serial_setbrg(struct mtk_serial_priv *priv, int baud)
  66. {
  67. bool support_clk12m_baud115200;
  68. u32 quot, samplecount, realbaud;
  69. if ((baud <= 115200) && (priv->clock == 12000000))
  70. support_clk12m_baud115200 = true;
  71. else
  72. support_clk12m_baud115200 = false;
  73. if (baud <= 115200) {
  74. writel(0, &priv->regs->highspeed);
  75. quot = DIV_ROUND_CLOSEST(priv->clock, 16 * baud);
  76. if (support_clk12m_baud115200) {
  77. writel(3, &priv->regs->highspeed);
  78. quot = DIV_ROUND_CLOSEST(priv->clock, 256 * baud);
  79. if (quot == 0)
  80. quot = 1;
  81. samplecount = DIV_ROUND_CLOSEST(priv->clock,
  82. quot * baud);
  83. if (samplecount != 0) {
  84. realbaud = priv->clock / samplecount / quot;
  85. if ((realbaud > BAUD_ALLOW_MAX(baud)) ||
  86. (realbaud < BAUD_ALLOW_MIX(baud))) {
  87. pr_info("baud %d can't be handled\n",
  88. baud);
  89. }
  90. } else {
  91. pr_info("samplecount is 0\n");
  92. }
  93. }
  94. } else if (baud <= 576000) {
  95. writel(2, &priv->regs->highspeed);
  96. /* Set to next lower baudrate supported */
  97. if ((baud == 500000) || (baud == 576000))
  98. baud = 460800;
  99. quot = DIV_ROUND_UP(priv->clock, 4 * baud);
  100. } else {
  101. writel(3, &priv->regs->highspeed);
  102. quot = DIV_ROUND_UP(priv->clock, 256 * baud);
  103. }
  104. /* set divisor */
  105. writel(UART_LCR_WLS_8 | UART_LCR_DLAB, &priv->regs->lcr);
  106. writel(quot & 0xff, &priv->regs->dll);
  107. writel((quot >> 8) & 0xff, &priv->regs->dlm);
  108. writel(UART_LCR_WLS_8, &priv->regs->lcr);
  109. if (baud > 460800) {
  110. u32 tmp;
  111. tmp = DIV_ROUND_CLOSEST(priv->clock, quot * baud);
  112. writel(tmp - 1, &priv->regs->sample_count);
  113. writel((tmp - 2) >> 1, &priv->regs->sample_point);
  114. } else {
  115. writel(0, &priv->regs->sample_count);
  116. writel(0xff, &priv->regs->sample_point);
  117. }
  118. if (support_clk12m_baud115200) {
  119. writel(samplecount - 1, &priv->regs->sample_count);
  120. writel((samplecount - 2) >> 1, &priv->regs->sample_point);
  121. }
  122. }
  123. static int _mtk_serial_putc(struct mtk_serial_priv *priv, const char ch)
  124. {
  125. if (!(readl(&priv->regs->lsr) & UART_LSR_THRE))
  126. return -EAGAIN;
  127. writel(ch, &priv->regs->thr);
  128. if (ch == '\n')
  129. WATCHDOG_RESET();
  130. return 0;
  131. }
  132. static int _mtk_serial_getc(struct mtk_serial_priv *priv)
  133. {
  134. if (!(readl(&priv->regs->lsr) & UART_LSR_DR))
  135. return -EAGAIN;
  136. return readl(&priv->regs->rbr);
  137. }
  138. static int _mtk_serial_pending(struct mtk_serial_priv *priv, bool input)
  139. {
  140. if (input)
  141. return (readl(&priv->regs->lsr) & UART_LSR_DR) ? 1 : 0;
  142. else
  143. return (readl(&priv->regs->lsr) & UART_LSR_THRE) ? 0 : 1;
  144. }
  145. #if defined(CONFIG_DM_SERIAL) && \
  146. (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_DM))
  147. static int mtk_serial_setbrg(struct udevice *dev, int baudrate)
  148. {
  149. struct mtk_serial_priv *priv = dev_get_priv(dev);
  150. _mtk_serial_setbrg(priv, baudrate);
  151. return 0;
  152. }
  153. static int mtk_serial_putc(struct udevice *dev, const char ch)
  154. {
  155. struct mtk_serial_priv *priv = dev_get_priv(dev);
  156. return _mtk_serial_putc(priv, ch);
  157. }
  158. static int mtk_serial_getc(struct udevice *dev)
  159. {
  160. struct mtk_serial_priv *priv = dev_get_priv(dev);
  161. return _mtk_serial_getc(priv);
  162. }
  163. static int mtk_serial_pending(struct udevice *dev, bool input)
  164. {
  165. struct mtk_serial_priv *priv = dev_get_priv(dev);
  166. return _mtk_serial_pending(priv, input);
  167. }
  168. static int mtk_serial_probe(struct udevice *dev)
  169. {
  170. struct mtk_serial_priv *priv = dev_get_priv(dev);
  171. /* Disable interrupt */
  172. writel(0, &priv->regs->ier);
  173. writel(UART_MCRVAL, &priv->regs->mcr);
  174. writel(UART_FCRVAL, &priv->regs->fcr);
  175. return 0;
  176. }
  177. static int mtk_serial_ofdata_to_platdata(struct udevice *dev)
  178. {
  179. struct mtk_serial_priv *priv = dev_get_priv(dev);
  180. fdt_addr_t addr;
  181. struct clk clk;
  182. int err;
  183. addr = dev_read_addr(dev);
  184. if (addr == FDT_ADDR_T_NONE)
  185. return -EINVAL;
  186. priv->regs = map_physmem(addr, 0, MAP_NOCACHE);
  187. err = clk_get_by_index(dev, 0, &clk);
  188. if (!err) {
  189. err = clk_get_rate(&clk);
  190. if (!IS_ERR_VALUE(err))
  191. priv->clock = err;
  192. } else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) {
  193. debug("mtk_serial: failed to get clock\n");
  194. return err;
  195. }
  196. if (!priv->clock)
  197. priv->clock = dev_read_u32_default(dev, "clock-frequency", 0);
  198. if (!priv->clock) {
  199. debug("mtk_serial: clock not defined\n");
  200. return -EINVAL;
  201. }
  202. return 0;
  203. }
  204. static const struct dm_serial_ops mtk_serial_ops = {
  205. .putc = mtk_serial_putc,
  206. .pending = mtk_serial_pending,
  207. .getc = mtk_serial_getc,
  208. .setbrg = mtk_serial_setbrg,
  209. };
  210. static const struct udevice_id mtk_serial_ids[] = {
  211. { .compatible = "mediatek,hsuart" },
  212. { .compatible = "mediatek,mt6577-uart" },
  213. { }
  214. };
  215. U_BOOT_DRIVER(serial_mtk) = {
  216. .name = "serial_mtk",
  217. .id = UCLASS_SERIAL,
  218. .of_match = mtk_serial_ids,
  219. .ofdata_to_platdata = mtk_serial_ofdata_to_platdata,
  220. .priv_auto_alloc_size = sizeof(struct mtk_serial_priv),
  221. .probe = mtk_serial_probe,
  222. .ops = &mtk_serial_ops,
  223. .flags = DM_FLAG_PRE_RELOC,
  224. };
  225. #else
  226. DECLARE_GLOBAL_DATA_PTR;
  227. #define DECLARE_HSUART_PRIV(port) \
  228. static struct mtk_serial_priv mtk_hsuart##port = { \
  229. .regs = (struct mtk_serial_regs *)CONFIG_SYS_NS16550_COM##port, \
  230. .clock = CONFIG_SYS_NS16550_CLK \
  231. };
  232. #define DECLARE_HSUART_FUNCTIONS(port) \
  233. static int mtk_serial##port##_init(void) \
  234. { \
  235. writel(0, &mtk_hsuart##port.regs->ier); \
  236. writel(UART_MCRVAL, &mtk_hsuart##port.regs->mcr); \
  237. writel(UART_FCRVAL, &mtk_hsuart##port.regs->fcr); \
  238. _mtk_serial_setbrg(&mtk_hsuart##port, gd->baudrate); \
  239. return 0 ; \
  240. } \
  241. static void mtk_serial##port##_setbrg(void) \
  242. { \
  243. _mtk_serial_setbrg(&mtk_hsuart##port, gd->baudrate); \
  244. } \
  245. static int mtk_serial##port##_getc(void) \
  246. { \
  247. int err; \
  248. do { \
  249. err = _mtk_serial_getc(&mtk_hsuart##port); \
  250. if (err == -EAGAIN) \
  251. WATCHDOG_RESET(); \
  252. } while (err == -EAGAIN); \
  253. return err >= 0 ? err : 0; \
  254. } \
  255. static int mtk_serial##port##_tstc(void) \
  256. { \
  257. return _mtk_serial_pending(&mtk_hsuart##port, true); \
  258. } \
  259. static void mtk_serial##port##_putc(const char c) \
  260. { \
  261. int err; \
  262. if (c == '\n') \
  263. mtk_serial##port##_putc('\r'); \
  264. do { \
  265. err = _mtk_serial_putc(&mtk_hsuart##port, c); \
  266. } while (err == -EAGAIN); \
  267. } \
  268. static void mtk_serial##port##_puts(const char *s) \
  269. { \
  270. while (*s) { \
  271. mtk_serial##port##_putc(*s++); \
  272. } \
  273. }
  274. /* Serial device descriptor */
  275. #define INIT_HSUART_STRUCTURE(port, __name) { \
  276. .name = __name, \
  277. .start = mtk_serial##port##_init, \
  278. .stop = NULL, \
  279. .setbrg = mtk_serial##port##_setbrg, \
  280. .getc = mtk_serial##port##_getc, \
  281. .tstc = mtk_serial##port##_tstc, \
  282. .putc = mtk_serial##port##_putc, \
  283. .puts = mtk_serial##port##_puts, \
  284. }
  285. #define DECLARE_HSUART(port, __name) \
  286. DECLARE_HSUART_PRIV(port); \
  287. DECLARE_HSUART_FUNCTIONS(port); \
  288. struct serial_device mtk_hsuart##port##_device = \
  289. INIT_HSUART_STRUCTURE(port, __name);
  290. #if !defined(CONFIG_CONS_INDEX)
  291. #elif (CONFIG_CONS_INDEX < 1) || (CONFIG_CONS_INDEX > 6)
  292. #error "Invalid console index value."
  293. #endif
  294. #if CONFIG_CONS_INDEX == 1 && !defined(CONFIG_SYS_NS16550_COM1)
  295. #error "Console port 1 defined but not configured."
  296. #elif CONFIG_CONS_INDEX == 2 && !defined(CONFIG_SYS_NS16550_COM2)
  297. #error "Console port 2 defined but not configured."
  298. #elif CONFIG_CONS_INDEX == 3 && !defined(CONFIG_SYS_NS16550_COM3)
  299. #error "Console port 3 defined but not configured."
  300. #elif CONFIG_CONS_INDEX == 4 && !defined(CONFIG_SYS_NS16550_COM4)
  301. #error "Console port 4 defined but not configured."
  302. #elif CONFIG_CONS_INDEX == 5 && !defined(CONFIG_SYS_NS16550_COM5)
  303. #error "Console port 5 defined but not configured."
  304. #elif CONFIG_CONS_INDEX == 6 && !defined(CONFIG_SYS_NS16550_COM6)
  305. #error "Console port 6 defined but not configured."
  306. #endif
  307. #if defined(CONFIG_SYS_NS16550_COM1)
  308. DECLARE_HSUART(1, "mtk-hsuart0");
  309. #endif
  310. #if defined(CONFIG_SYS_NS16550_COM2)
  311. DECLARE_HSUART(2, "mtk-hsuart1");
  312. #endif
  313. #if defined(CONFIG_SYS_NS16550_COM3)
  314. DECLARE_HSUART(3, "mtk-hsuart2");
  315. #endif
  316. #if defined(CONFIG_SYS_NS16550_COM4)
  317. DECLARE_HSUART(4, "mtk-hsuart3");
  318. #endif
  319. #if defined(CONFIG_SYS_NS16550_COM5)
  320. DECLARE_HSUART(5, "mtk-hsuart4");
  321. #endif
  322. #if defined(CONFIG_SYS_NS16550_COM6)
  323. DECLARE_HSUART(6, "mtk-hsuart5");
  324. #endif
  325. __weak struct serial_device *default_serial_console(void)
  326. {
  327. #if CONFIG_CONS_INDEX == 1
  328. return &mtk_hsuart1_device;
  329. #elif CONFIG_CONS_INDEX == 2
  330. return &mtk_hsuart2_device;
  331. #elif CONFIG_CONS_INDEX == 3
  332. return &mtk_hsuart3_device;
  333. #elif CONFIG_CONS_INDEX == 4
  334. return &mtk_hsuart4_device;
  335. #elif CONFIG_CONS_INDEX == 5
  336. return &mtk_hsuart5_device;
  337. #elif CONFIG_CONS_INDEX == 6
  338. return &mtk_hsuart6_device;
  339. #else
  340. #error "Bad CONFIG_CONS_INDEX."
  341. #endif
  342. }
  343. void mtk_serial_initialize(void)
  344. {
  345. #if defined(CONFIG_SYS_NS16550_COM1)
  346. serial_register(&mtk_hsuart1_device);
  347. #endif
  348. #if defined(CONFIG_SYS_NS16550_COM2)
  349. serial_register(&mtk_hsuart2_device);
  350. #endif
  351. #if defined(CONFIG_SYS_NS16550_COM3)
  352. serial_register(&mtk_hsuart3_device);
  353. #endif
  354. #if defined(CONFIG_SYS_NS16550_COM4)
  355. serial_register(&mtk_hsuart4_device);
  356. #endif
  357. #if defined(CONFIG_SYS_NS16550_COM5)
  358. serial_register(&mtk_hsuart5_device);
  359. #endif
  360. #if defined(CONFIG_SYS_NS16550_COM6)
  361. serial_register(&mtk_hsuart6_device);
  362. #endif
  363. }
  364. #endif
  365. #ifdef CONFIG_DEBUG_UART_MTK
  366. #include <debug_uart.h>
  367. static inline void _debug_uart_init(void)
  368. {
  369. struct mtk_serial_priv priv;
  370. priv.regs = (void *) CONFIG_DEBUG_UART_BASE;
  371. priv.clock = CONFIG_DEBUG_UART_CLOCK;
  372. writel(0, &priv.regs->ier);
  373. writel(UART_MCRVAL, &priv.regs->mcr);
  374. writel(UART_FCRVAL, &priv.regs->fcr);
  375. _mtk_serial_setbrg(&priv, CONFIG_BAUDRATE);
  376. }
  377. static inline void _debug_uart_putc(int ch)
  378. {
  379. struct mtk_serial_regs __iomem *regs =
  380. (void *) CONFIG_DEBUG_UART_BASE;
  381. while (!(readl(&regs->lsr) & UART_LSR_THRE))
  382. ;
  383. writel(ch, &regs->thr);
  384. }
  385. DEBUG_UART_FUNCS
  386. #endif