serial_msm.c 6.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Qualcomm UART driver
  4. *
  5. * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
  6. *
  7. * UART will work in Data Mover mode.
  8. * Based on Linux driver.
  9. */
  10. #include <common.h>
  11. #include <clk.h>
  12. #include <dm.h>
  13. #include <errno.h>
  14. #include <malloc.h>
  15. #include <serial.h>
  16. #include <watchdog.h>
  17. #include <asm/io.h>
  18. #include <linux/compiler.h>
  19. #include <dm/pinctrl.h>
  20. /* Serial registers - this driver works in uartdm mode*/
  21. #define UARTDM_DMRX 0x34 /* Max RX transfer length */
  22. #define UARTDM_NCF_TX 0x40 /* Number of chars to TX */
  23. #define UARTDM_RXFS 0x50 /* RX channel status register */
  24. #define UARTDM_RXFS_BUF_SHIFT 0x7 /* Number of bytes in the packing buffer */
  25. #define UARTDM_RXFS_BUF_MASK 0x7
  26. #define UARTDM_MR1 0x00
  27. #define UARTDM_MR2 0x04
  28. #define UARTDM_CSR 0xA0
  29. #define UARTDM_SR 0xA4 /* Status register */
  30. #define UARTDM_SR_RX_READY (1 << 0) /* Word is the receiver FIFO */
  31. #define UARTDM_SR_TX_EMPTY (1 << 3) /* Transmitter underrun */
  32. #define UARTDM_SR_UART_OVERRUN (1 << 4) /* Receive overrun */
  33. #define UARTDM_CR 0xA8 /* Command register */
  34. #define UARTDM_CR_CMD_RESET_ERR (3 << 4) /* Clear overrun error */
  35. #define UARTDM_CR_CMD_RESET_STALE_INT (8 << 4) /* Clears stale irq */
  36. #define UARTDM_CR_CMD_RESET_TX_READY (3 << 8) /* Clears TX Ready irq*/
  37. #define UARTDM_CR_CMD_FORCE_STALE (4 << 8) /* Causes stale event */
  38. #define UARTDM_CR_CMD_STALE_EVENT_DISABLE (6 << 8) /* Disable stale event */
  39. #define UARTDM_IMR 0xB0 /* Interrupt mask register */
  40. #define UARTDM_ISR 0xB4 /* Interrupt status register */
  41. #define UARTDM_ISR_TX_READY 0x80 /* TX FIFO empty */
  42. #define UARTDM_TF 0x100 /* UART Transmit FIFO register */
  43. #define UARTDM_RF 0x140 /* UART Receive FIFO register */
  44. #define UART_DM_CLK_RX_TX_BIT_RATE 0xCC
  45. #define MSM_BOOT_UART_DM_8_N_1_MODE 0x34
  46. #define MSM_BOOT_UART_DM_CMD_RESET_RX 0x10
  47. #define MSM_BOOT_UART_DM_CMD_RESET_TX 0x20
  48. DECLARE_GLOBAL_DATA_PTR;
  49. struct msm_serial_data {
  50. phys_addr_t base;
  51. unsigned chars_cnt; /* number of buffered chars */
  52. uint32_t chars_buf; /* buffered chars */
  53. uint32_t clk_bit_rate; /* data mover mode bit rate register value */
  54. };
  55. static int msm_serial_fetch(struct udevice *dev)
  56. {
  57. struct msm_serial_data *priv = dev_get_priv(dev);
  58. unsigned sr;
  59. if (priv->chars_cnt)
  60. return priv->chars_cnt;
  61. /* Clear error in case of buffer overrun */
  62. if (readl(priv->base + UARTDM_SR) & UARTDM_SR_UART_OVERRUN)
  63. writel(UARTDM_CR_CMD_RESET_ERR, priv->base + UARTDM_CR);
  64. /* We need to fetch new character */
  65. sr = readl(priv->base + UARTDM_SR);
  66. if (sr & UARTDM_SR_RX_READY) {
  67. /* There are at least 4 bytes in fifo */
  68. priv->chars_buf = readl(priv->base + UARTDM_RF);
  69. priv->chars_cnt = 4;
  70. } else {
  71. /* Check if there is anything in fifo */
  72. priv->chars_cnt = readl(priv->base + UARTDM_RXFS);
  73. /* Extract number of characters in UART packing buffer*/
  74. priv->chars_cnt = (priv->chars_cnt >>
  75. UARTDM_RXFS_BUF_SHIFT) &
  76. UARTDM_RXFS_BUF_MASK;
  77. if (!priv->chars_cnt)
  78. return 0;
  79. /* There is at least one charcter, move it to fifo */
  80. writel(UARTDM_CR_CMD_FORCE_STALE,
  81. priv->base + UARTDM_CR);
  82. priv->chars_buf = readl(priv->base + UARTDM_RF);
  83. writel(UARTDM_CR_CMD_RESET_STALE_INT,
  84. priv->base + UARTDM_CR);
  85. writel(0x7, priv->base + UARTDM_DMRX);
  86. }
  87. return priv->chars_cnt;
  88. }
  89. static int msm_serial_getc(struct udevice *dev)
  90. {
  91. struct msm_serial_data *priv = dev_get_priv(dev);
  92. char c;
  93. if (!msm_serial_fetch(dev))
  94. return -EAGAIN;
  95. c = priv->chars_buf & 0xFF;
  96. priv->chars_buf >>= 8;
  97. priv->chars_cnt--;
  98. return c;
  99. }
  100. static int msm_serial_putc(struct udevice *dev, const char ch)
  101. {
  102. struct msm_serial_data *priv = dev_get_priv(dev);
  103. if (!(readl(priv->base + UARTDM_SR) & UARTDM_SR_TX_EMPTY) &&
  104. !(readl(priv->base + UARTDM_ISR) & UARTDM_ISR_TX_READY))
  105. return -EAGAIN;
  106. writel(UARTDM_CR_CMD_RESET_TX_READY, priv->base + UARTDM_CR);
  107. writel(1, priv->base + UARTDM_NCF_TX);
  108. writel(ch, priv->base + UARTDM_TF);
  109. return 0;
  110. }
  111. static int msm_serial_pending(struct udevice *dev, bool input)
  112. {
  113. if (input) {
  114. if (msm_serial_fetch(dev))
  115. return 1;
  116. }
  117. return 0;
  118. }
  119. static const struct dm_serial_ops msm_serial_ops = {
  120. .putc = msm_serial_putc,
  121. .pending = msm_serial_pending,
  122. .getc = msm_serial_getc,
  123. };
  124. static int msm_uart_clk_init(struct udevice *dev)
  125. {
  126. uint clk_rate = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
  127. "clock-frequency", 115200);
  128. uint clkd[2]; /* clk_id and clk_no */
  129. int clk_offset;
  130. struct udevice *clk_dev;
  131. struct clk clk;
  132. int ret;
  133. ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev), "clock",
  134. clkd, 2);
  135. if (ret)
  136. return ret;
  137. clk_offset = fdt_node_offset_by_phandle(gd->fdt_blob, clkd[0]);
  138. if (clk_offset < 0)
  139. return clk_offset;
  140. ret = uclass_get_device_by_of_offset(UCLASS_CLK, clk_offset, &clk_dev);
  141. if (ret)
  142. return ret;
  143. clk.id = clkd[1];
  144. ret = clk_request(clk_dev, &clk);
  145. if (ret < 0)
  146. return ret;
  147. ret = clk_set_rate(&clk, clk_rate);
  148. clk_free(&clk);
  149. if (ret < 0)
  150. return ret;
  151. return 0;
  152. }
  153. static void uart_dm_init(struct msm_serial_data *priv)
  154. {
  155. writel(priv->clk_bit_rate, priv->base + UARTDM_CSR);
  156. writel(0x0, priv->base + UARTDM_MR1);
  157. writel(MSM_BOOT_UART_DM_8_N_1_MODE, priv->base + UARTDM_MR2);
  158. writel(MSM_BOOT_UART_DM_CMD_RESET_RX, priv->base + UARTDM_CR);
  159. writel(MSM_BOOT_UART_DM_CMD_RESET_TX, priv->base + UARTDM_CR);
  160. }
  161. static int msm_serial_probe(struct udevice *dev)
  162. {
  163. int ret;
  164. struct msm_serial_data *priv = dev_get_priv(dev);
  165. /* No need to reinitialize the UART after relocation */
  166. if (gd->flags & GD_FLG_RELOC)
  167. return 0;
  168. ret = msm_uart_clk_init(dev);
  169. if (ret)
  170. return ret;
  171. pinctrl_select_state(dev, "uart");
  172. uart_dm_init(priv);
  173. return 0;
  174. }
  175. static int msm_serial_ofdata_to_platdata(struct udevice *dev)
  176. {
  177. struct msm_serial_data *priv = dev_get_priv(dev);
  178. priv->base = dev_read_addr(dev);
  179. if (priv->base == FDT_ADDR_T_NONE)
  180. return -EINVAL;
  181. priv->clk_bit_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
  182. "bit-rate", UART_DM_CLK_RX_TX_BIT_RATE);
  183. return 0;
  184. }
  185. static const struct udevice_id msm_serial_ids[] = {
  186. { .compatible = "qcom,msm-uartdm-v1.4" },
  187. { }
  188. };
  189. U_BOOT_DRIVER(serial_msm) = {
  190. .name = "serial_msm",
  191. .id = UCLASS_SERIAL,
  192. .of_match = msm_serial_ids,
  193. .ofdata_to_platdata = msm_serial_ofdata_to_platdata,
  194. .priv_auto_alloc_size = sizeof(struct msm_serial_data),
  195. .probe = msm_serial_probe,
  196. .ops = &msm_serial_ops,
  197. };