serial_lpuart.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2019 NXP
  4. * Copyright 2013 Freescale Semiconductor, Inc.
  5. */
  6. #include <common.h>
  7. #include <clk.h>
  8. #include <dm.h>
  9. #include <fsl_lpuart.h>
  10. #include <log.h>
  11. #include <watchdog.h>
  12. #include <asm/io.h>
  13. #include <serial.h>
  14. #include <dm/device_compat.h>
  15. #include <linux/bitops.h>
  16. #include <linux/compiler.h>
  17. #include <asm/arch/imx-regs.h>
  18. #include <asm/arch/clock.h>
  19. #define US1_TDRE (1 << 7)
  20. #define US1_RDRF (1 << 5)
  21. #define US1_OR (1 << 3)
  22. #define UC2_TE (1 << 3)
  23. #define UC2_RE (1 << 2)
  24. #define CFIFO_TXFLUSH (1 << 7)
  25. #define CFIFO_RXFLUSH (1 << 6)
  26. #define SFIFO_RXOF (1 << 2)
  27. #define SFIFO_RXUF (1 << 0)
  28. #define STAT_LBKDIF (1 << 31)
  29. #define STAT_RXEDGIF (1 << 30)
  30. #define STAT_TDRE (1 << 23)
  31. #define STAT_RDRF (1 << 21)
  32. #define STAT_IDLE (1 << 20)
  33. #define STAT_OR (1 << 19)
  34. #define STAT_NF (1 << 18)
  35. #define STAT_FE (1 << 17)
  36. #define STAT_PF (1 << 16)
  37. #define STAT_MA1F (1 << 15)
  38. #define STAT_MA2F (1 << 14)
  39. #define STAT_FLAGS (STAT_LBKDIF | STAT_RXEDGIF | STAT_IDLE | STAT_OR | \
  40. STAT_NF | STAT_FE | STAT_PF | STAT_MA1F | STAT_MA2F)
  41. #define CTRL_TE (1 << 19)
  42. #define CTRL_RE (1 << 18)
  43. #define FIFO_RXFLUSH BIT(14)
  44. #define FIFO_TXFLUSH BIT(15)
  45. #define FIFO_TXSIZE_MASK 0x70
  46. #define FIFO_TXSIZE_OFF 4
  47. #define FIFO_RXSIZE_MASK 0x7
  48. #define FIFO_RXSIZE_OFF 0
  49. #define FIFO_TXFE 0x80
  50. #if defined(CONFIG_ARCH_IMX8) || defined(CONFIG_ARCH_IMXRT)
  51. #define FIFO_RXFE 0x08
  52. #else
  53. #define FIFO_RXFE 0x40
  54. #endif
  55. #define WATER_TXWATER_OFF 0
  56. #define WATER_RXWATER_OFF 16
  57. DECLARE_GLOBAL_DATA_PTR;
  58. #define LPUART_FLAG_REGMAP_32BIT_REG BIT(0)
  59. #define LPUART_FLAG_REGMAP_ENDIAN_BIG BIT(1)
  60. enum lpuart_devtype {
  61. DEV_VF610 = 1,
  62. DEV_LS1021A,
  63. DEV_MX7ULP,
  64. DEV_IMX8,
  65. DEV_IMXRT,
  66. };
  67. struct lpuart_serial_platdata {
  68. void *reg;
  69. enum lpuart_devtype devtype;
  70. ulong flags;
  71. };
  72. static void lpuart_read32(u32 flags, u32 *addr, u32 *val)
  73. {
  74. if (flags & LPUART_FLAG_REGMAP_32BIT_REG) {
  75. if (flags & LPUART_FLAG_REGMAP_ENDIAN_BIG)
  76. *(u32 *)val = in_be32(addr);
  77. else
  78. *(u32 *)val = in_le32(addr);
  79. }
  80. }
  81. static void lpuart_write32(u32 flags, u32 *addr, u32 val)
  82. {
  83. if (flags & LPUART_FLAG_REGMAP_32BIT_REG) {
  84. if (flags & LPUART_FLAG_REGMAP_ENDIAN_BIG)
  85. out_be32(addr, val);
  86. else
  87. out_le32(addr, val);
  88. }
  89. }
  90. #ifndef CONFIG_SYS_CLK_FREQ
  91. #define CONFIG_SYS_CLK_FREQ 0
  92. #endif
  93. u32 __weak get_lpuart_clk(void)
  94. {
  95. return CONFIG_SYS_CLK_FREQ;
  96. }
  97. #if CONFIG_IS_ENABLED(CLK)
  98. static int get_lpuart_clk_rate(struct udevice *dev, u32 *clk)
  99. {
  100. struct clk per_clk;
  101. ulong rate;
  102. int ret;
  103. ret = clk_get_by_name(dev, "per", &per_clk);
  104. if (ret) {
  105. dev_err(dev, "Failed to get per clk: %d\n", ret);
  106. return ret;
  107. }
  108. rate = clk_get_rate(&per_clk);
  109. if ((long)rate <= 0) {
  110. dev_err(dev, "Failed to get per clk rate: %ld\n", (long)rate);
  111. return ret;
  112. }
  113. *clk = rate;
  114. return 0;
  115. }
  116. #else
  117. static inline int get_lpuart_clk_rate(struct udevice *dev, u32 *clk)
  118. { return -ENOSYS; }
  119. #endif
  120. static bool is_lpuart32(struct udevice *dev)
  121. {
  122. struct lpuart_serial_platdata *plat = dev->platdata;
  123. return plat->flags & LPUART_FLAG_REGMAP_32BIT_REG;
  124. }
  125. static void _lpuart_serial_setbrg(struct udevice *dev,
  126. int baudrate)
  127. {
  128. struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
  129. struct lpuart_fsl *base = plat->reg;
  130. u32 clk;
  131. u16 sbr;
  132. int ret;
  133. if (CONFIG_IS_ENABLED(CLK)) {
  134. ret = get_lpuart_clk_rate(dev, &clk);
  135. if (ret)
  136. return;
  137. } else {
  138. clk = get_lpuart_clk();
  139. }
  140. sbr = (u16)(clk / (16 * baudrate));
  141. /* place adjustment later - n/32 BRFA */
  142. __raw_writeb(sbr >> 8, &base->ubdh);
  143. __raw_writeb(sbr & 0xff, &base->ubdl);
  144. }
  145. static int _lpuart_serial_getc(struct lpuart_serial_platdata *plat)
  146. {
  147. struct lpuart_fsl *base = plat->reg;
  148. while (!(__raw_readb(&base->us1) & (US1_RDRF | US1_OR)))
  149. WATCHDOG_RESET();
  150. barrier();
  151. return __raw_readb(&base->ud);
  152. }
  153. static void _lpuart_serial_putc(struct lpuart_serial_platdata *plat,
  154. const char c)
  155. {
  156. struct lpuart_fsl *base = plat->reg;
  157. while (!(__raw_readb(&base->us1) & US1_TDRE))
  158. WATCHDOG_RESET();
  159. __raw_writeb(c, &base->ud);
  160. }
  161. /* Test whether a character is in the RX buffer */
  162. static int _lpuart_serial_tstc(struct lpuart_serial_platdata *plat)
  163. {
  164. struct lpuart_fsl *base = plat->reg;
  165. if (__raw_readb(&base->urcfifo) == 0)
  166. return 0;
  167. return 1;
  168. }
  169. /*
  170. * Initialise the serial port with the given baudrate. The settings
  171. * are always 8 data bits, no parity, 1 stop bit, no start bits.
  172. */
  173. static int _lpuart_serial_init(struct udevice *dev)
  174. {
  175. struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
  176. struct lpuart_fsl *base = (struct lpuart_fsl *)plat->reg;
  177. u8 ctrl;
  178. ctrl = __raw_readb(&base->uc2);
  179. ctrl &= ~UC2_RE;
  180. ctrl &= ~UC2_TE;
  181. __raw_writeb(ctrl, &base->uc2);
  182. __raw_writeb(0, &base->umodem);
  183. __raw_writeb(0, &base->uc1);
  184. /* Disable FIFO and flush buffer */
  185. __raw_writeb(0x0, &base->upfifo);
  186. __raw_writeb(0x0, &base->utwfifo);
  187. __raw_writeb(0x1, &base->urwfifo);
  188. __raw_writeb(CFIFO_TXFLUSH | CFIFO_RXFLUSH, &base->ucfifo);
  189. /* provide data bits, parity, stop bit, etc */
  190. _lpuart_serial_setbrg(dev, gd->baudrate);
  191. __raw_writeb(UC2_RE | UC2_TE, &base->uc2);
  192. return 0;
  193. }
  194. static void _lpuart32_serial_setbrg_7ulp(struct udevice *dev,
  195. int baudrate)
  196. {
  197. struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
  198. struct lpuart_fsl_reg32 *base = plat->reg;
  199. u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp;
  200. u32 clk;
  201. int ret;
  202. if (CONFIG_IS_ENABLED(CLK)) {
  203. ret = get_lpuart_clk_rate(dev, &clk);
  204. if (ret)
  205. return;
  206. } else {
  207. clk = get_lpuart_clk();
  208. }
  209. baud_diff = baudrate;
  210. osr = 0;
  211. sbr = 0;
  212. for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) {
  213. tmp_sbr = (clk / (baudrate * tmp_osr));
  214. if (tmp_sbr == 0)
  215. tmp_sbr = 1;
  216. /*calculate difference in actual buad w/ current values */
  217. tmp_diff = (clk / (tmp_osr * tmp_sbr));
  218. tmp_diff = tmp_diff - baudrate;
  219. /* select best values between sbr and sbr+1 */
  220. if (tmp_diff > (baudrate - (clk / (tmp_osr * (tmp_sbr + 1))))) {
  221. tmp_diff = baudrate - (clk / (tmp_osr * (tmp_sbr + 1)));
  222. tmp_sbr++;
  223. }
  224. if (tmp_diff <= baud_diff) {
  225. baud_diff = tmp_diff;
  226. osr = tmp_osr;
  227. sbr = tmp_sbr;
  228. }
  229. }
  230. /*
  231. * TODO: handle buadrate outside acceptable rate
  232. * if (baudDiff > ((config->baudRate_Bps / 100) * 3))
  233. * {
  234. * Unacceptable baud rate difference of more than 3%
  235. * return kStatus_LPUART_BaudrateNotSupport;
  236. * }
  237. */
  238. tmp = in_le32(&base->baud);
  239. if ((osr > 3) && (osr < 8))
  240. tmp |= LPUART_BAUD_BOTHEDGE_MASK;
  241. tmp &= ~LPUART_BAUD_OSR_MASK;
  242. tmp |= LPUART_BAUD_OSR(osr-1);
  243. tmp &= ~LPUART_BAUD_SBR_MASK;
  244. tmp |= LPUART_BAUD_SBR(sbr);
  245. /* explicitly disable 10 bit mode & set 1 stop bit */
  246. tmp &= ~(LPUART_BAUD_M10_MASK | LPUART_BAUD_SBNS_MASK);
  247. out_le32(&base->baud, tmp);
  248. }
  249. static void _lpuart32_serial_setbrg(struct udevice *dev,
  250. int baudrate)
  251. {
  252. struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
  253. struct lpuart_fsl_reg32 *base = plat->reg;
  254. u32 clk;
  255. u32 sbr;
  256. int ret;
  257. if (CONFIG_IS_ENABLED(CLK)) {
  258. ret = get_lpuart_clk_rate(dev, &clk);
  259. if (ret)
  260. return;
  261. } else {
  262. clk = get_lpuart_clk();
  263. }
  264. sbr = (clk / (16 * baudrate));
  265. /* place adjustment later - n/32 BRFA */
  266. lpuart_write32(plat->flags, &base->baud, sbr);
  267. }
  268. static int _lpuart32_serial_getc(struct lpuart_serial_platdata *plat)
  269. {
  270. struct lpuart_fsl_reg32 *base = plat->reg;
  271. u32 stat, val;
  272. lpuart_read32(plat->flags, &base->stat, &stat);
  273. while ((stat & STAT_RDRF) == 0) {
  274. lpuart_write32(plat->flags, &base->stat, STAT_FLAGS);
  275. WATCHDOG_RESET();
  276. lpuart_read32(plat->flags, &base->stat, &stat);
  277. }
  278. lpuart_read32(plat->flags, &base->data, &val);
  279. lpuart_read32(plat->flags, &base->stat, &stat);
  280. if (stat & STAT_OR)
  281. lpuart_write32(plat->flags, &base->stat, STAT_OR);
  282. return val & 0x3ff;
  283. }
  284. static void _lpuart32_serial_putc(struct lpuart_serial_platdata *plat,
  285. const char c)
  286. {
  287. struct lpuart_fsl_reg32 *base = plat->reg;
  288. u32 stat;
  289. if (c == '\n')
  290. serial_putc('\r');
  291. while (true) {
  292. lpuart_read32(plat->flags, &base->stat, &stat);
  293. if ((stat & STAT_TDRE))
  294. break;
  295. WATCHDOG_RESET();
  296. }
  297. lpuart_write32(plat->flags, &base->data, c);
  298. }
  299. /* Test whether a character is in the RX buffer */
  300. static int _lpuart32_serial_tstc(struct lpuart_serial_platdata *plat)
  301. {
  302. struct lpuart_fsl_reg32 *base = plat->reg;
  303. u32 water;
  304. lpuart_read32(plat->flags, &base->water, &water);
  305. if ((water >> 24) == 0)
  306. return 0;
  307. return 1;
  308. }
  309. /*
  310. * Initialise the serial port with the given baudrate. The settings
  311. * are always 8 data bits, no parity, 1 stop bit, no start bits.
  312. */
  313. static int _lpuart32_serial_init(struct udevice *dev)
  314. {
  315. struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
  316. struct lpuart_fsl_reg32 *base = (struct lpuart_fsl_reg32 *)plat->reg;
  317. u32 val, tx_fifo_size;
  318. lpuart_read32(plat->flags, &base->ctrl, &val);
  319. val &= ~CTRL_RE;
  320. val &= ~CTRL_TE;
  321. lpuart_write32(plat->flags, &base->ctrl, val);
  322. lpuart_write32(plat->flags, &base->modir, 0);
  323. lpuart_read32(plat->flags, &base->fifo, &val);
  324. tx_fifo_size = (val & FIFO_TXSIZE_MASK) >> FIFO_TXSIZE_OFF;
  325. /* Set the TX water to half of FIFO size */
  326. if (tx_fifo_size > 1)
  327. tx_fifo_size = tx_fifo_size >> 1;
  328. /* Set RX water to 0, to be triggered by any receive data */
  329. lpuart_write32(plat->flags, &base->water,
  330. (tx_fifo_size << WATER_TXWATER_OFF));
  331. /* Enable TX and RX FIFO */
  332. val |= (FIFO_TXFE | FIFO_RXFE | FIFO_TXFLUSH | FIFO_RXFLUSH);
  333. lpuart_write32(plat->flags, &base->fifo, val);
  334. lpuart_write32(plat->flags, &base->match, 0);
  335. if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8 ||
  336. plat->devtype == DEV_IMXRT) {
  337. _lpuart32_serial_setbrg_7ulp(dev, gd->baudrate);
  338. } else {
  339. /* provide data bits, parity, stop bit, etc */
  340. _lpuart32_serial_setbrg(dev, gd->baudrate);
  341. }
  342. lpuart_write32(plat->flags, &base->ctrl, CTRL_RE | CTRL_TE);
  343. return 0;
  344. }
  345. static int lpuart_serial_setbrg(struct udevice *dev, int baudrate)
  346. {
  347. struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
  348. if (is_lpuart32(dev)) {
  349. if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8 ||
  350. plat->devtype == DEV_IMXRT)
  351. _lpuart32_serial_setbrg_7ulp(dev, baudrate);
  352. else
  353. _lpuart32_serial_setbrg(dev, baudrate);
  354. } else {
  355. _lpuart_serial_setbrg(dev, baudrate);
  356. }
  357. return 0;
  358. }
  359. static int lpuart_serial_getc(struct udevice *dev)
  360. {
  361. struct lpuart_serial_platdata *plat = dev->platdata;
  362. if (is_lpuart32(dev))
  363. return _lpuart32_serial_getc(plat);
  364. return _lpuart_serial_getc(plat);
  365. }
  366. static int lpuart_serial_putc(struct udevice *dev, const char c)
  367. {
  368. struct lpuart_serial_platdata *plat = dev->platdata;
  369. if (is_lpuart32(dev))
  370. _lpuart32_serial_putc(plat, c);
  371. else
  372. _lpuart_serial_putc(plat, c);
  373. return 0;
  374. }
  375. static int lpuart_serial_pending(struct udevice *dev, bool input)
  376. {
  377. struct lpuart_serial_platdata *plat = dev->platdata;
  378. struct lpuart_fsl *reg = plat->reg;
  379. struct lpuart_fsl_reg32 *reg32 = plat->reg;
  380. u32 stat;
  381. if (is_lpuart32(dev)) {
  382. if (input) {
  383. return _lpuart32_serial_tstc(plat);
  384. } else {
  385. lpuart_read32(plat->flags, &reg32->stat, &stat);
  386. return stat & STAT_TDRE ? 0 : 1;
  387. }
  388. }
  389. if (input)
  390. return _lpuart_serial_tstc(plat);
  391. else
  392. return __raw_readb(&reg->us1) & US1_TDRE ? 0 : 1;
  393. }
  394. static int lpuart_serial_probe(struct udevice *dev)
  395. {
  396. #if CONFIG_IS_ENABLED(CLK)
  397. struct clk per_clk;
  398. int ret;
  399. ret = clk_get_by_name(dev, "per", &per_clk);
  400. if (!ret) {
  401. ret = clk_enable(&per_clk);
  402. if (ret) {
  403. dev_err(dev, "Failed to get per clk: %d\n", ret);
  404. return ret;
  405. }
  406. } else {
  407. debug("%s: Failed to get per clk: %d\n", __func__, ret);
  408. }
  409. #endif
  410. if (is_lpuart32(dev))
  411. return _lpuart32_serial_init(dev);
  412. else
  413. return _lpuart_serial_init(dev);
  414. }
  415. static int lpuart_serial_ofdata_to_platdata(struct udevice *dev)
  416. {
  417. struct lpuart_serial_platdata *plat = dev->platdata;
  418. const void *blob = gd->fdt_blob;
  419. int node = dev_of_offset(dev);
  420. fdt_addr_t addr;
  421. addr = dev_read_addr(dev);
  422. if (addr == FDT_ADDR_T_NONE)
  423. return -EINVAL;
  424. plat->reg = (void *)addr;
  425. plat->flags = dev_get_driver_data(dev);
  426. if (fdtdec_get_bool(blob, node, "little-endian"))
  427. plat->flags &= ~LPUART_FLAG_REGMAP_ENDIAN_BIG;
  428. if (!fdt_node_check_compatible(blob, node, "fsl,ls1021a-lpuart"))
  429. plat->devtype = DEV_LS1021A;
  430. else if (!fdt_node_check_compatible(blob, node, "fsl,imx7ulp-lpuart"))
  431. plat->devtype = DEV_MX7ULP;
  432. else if (!fdt_node_check_compatible(blob, node, "fsl,vf610-lpuart"))
  433. plat->devtype = DEV_VF610;
  434. else if (!fdt_node_check_compatible(blob, node, "fsl,imx8qm-lpuart"))
  435. plat->devtype = DEV_IMX8;
  436. else if (!fdt_node_check_compatible(blob, node, "fsl,imxrt-lpuart"))
  437. plat->devtype = DEV_IMXRT;
  438. return 0;
  439. }
  440. static const struct dm_serial_ops lpuart_serial_ops = {
  441. .putc = lpuart_serial_putc,
  442. .pending = lpuart_serial_pending,
  443. .getc = lpuart_serial_getc,
  444. .setbrg = lpuart_serial_setbrg,
  445. };
  446. static const struct udevice_id lpuart_serial_ids[] = {
  447. { .compatible = "fsl,ls1021a-lpuart", .data =
  448. LPUART_FLAG_REGMAP_32BIT_REG | LPUART_FLAG_REGMAP_ENDIAN_BIG },
  449. { .compatible = "fsl,imx7ulp-lpuart",
  450. .data = LPUART_FLAG_REGMAP_32BIT_REG },
  451. { .compatible = "fsl,vf610-lpuart"},
  452. { .compatible = "fsl,imx8qm-lpuart",
  453. .data = LPUART_FLAG_REGMAP_32BIT_REG },
  454. { .compatible = "fsl,imxrt-lpuart",
  455. .data = LPUART_FLAG_REGMAP_32BIT_REG },
  456. { }
  457. };
  458. U_BOOT_DRIVER(serial_lpuart) = {
  459. .name = "serial_lpuart",
  460. .id = UCLASS_SERIAL,
  461. .of_match = lpuart_serial_ids,
  462. .ofdata_to_platdata = lpuart_serial_ofdata_to_platdata,
  463. .platdata_auto_alloc_size = sizeof(struct lpuart_serial_platdata),
  464. .probe = lpuart_serial_probe,
  465. .ops = &lpuart_serial_ops,
  466. };