altera_uart.c 3.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
  4. * Scott McNutt <smcnutt@psyent.com>
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <errno.h>
  9. #include <serial.h>
  10. #include <asm/io.h>
  11. #include <linux/bitops.h>
  12. /* status register */
  13. #define ALTERA_UART_TMT BIT(5) /* tx empty */
  14. #define ALTERA_UART_TRDY BIT(6) /* tx ready */
  15. #define ALTERA_UART_RRDY BIT(7) /* rx ready */
  16. struct altera_uart_regs {
  17. u32 rxdata; /* Rx data reg */
  18. u32 txdata; /* Tx data reg */
  19. u32 status; /* Status reg */
  20. u32 control; /* Control reg */
  21. u32 divisor; /* Baud rate divisor reg */
  22. u32 endofpacket; /* End-of-packet reg */
  23. };
  24. struct altera_uart_platdata {
  25. struct altera_uart_regs *regs;
  26. unsigned int uartclk;
  27. };
  28. static int altera_uart_setbrg(struct udevice *dev, int baudrate)
  29. {
  30. struct altera_uart_platdata *plat = dev->platdata;
  31. struct altera_uart_regs *const regs = plat->regs;
  32. u32 div;
  33. div = (plat->uartclk / baudrate) - 1;
  34. writel(div, &regs->divisor);
  35. return 0;
  36. }
  37. static int altera_uart_putc(struct udevice *dev, const char ch)
  38. {
  39. struct altera_uart_platdata *plat = dev->platdata;
  40. struct altera_uart_regs *const regs = plat->regs;
  41. if (!(readl(&regs->status) & ALTERA_UART_TRDY))
  42. return -EAGAIN;
  43. writel(ch, &regs->txdata);
  44. return 0;
  45. }
  46. static int altera_uart_pending(struct udevice *dev, bool input)
  47. {
  48. struct altera_uart_platdata *plat = dev->platdata;
  49. struct altera_uart_regs *const regs = plat->regs;
  50. u32 st = readl(&regs->status);
  51. if (input)
  52. return st & ALTERA_UART_RRDY ? 1 : 0;
  53. else
  54. return !(st & ALTERA_UART_TMT);
  55. }
  56. static int altera_uart_getc(struct udevice *dev)
  57. {
  58. struct altera_uart_platdata *plat = dev->platdata;
  59. struct altera_uart_regs *const regs = plat->regs;
  60. if (!(readl(&regs->status) & ALTERA_UART_RRDY))
  61. return -EAGAIN;
  62. return readl(&regs->rxdata) & 0xff;
  63. }
  64. static int altera_uart_probe(struct udevice *dev)
  65. {
  66. return 0;
  67. }
  68. static int altera_uart_ofdata_to_platdata(struct udevice *dev)
  69. {
  70. struct altera_uart_platdata *plat = dev_get_platdata(dev);
  71. plat->regs = map_physmem(dev_read_addr(dev),
  72. sizeof(struct altera_uart_regs),
  73. MAP_NOCACHE);
  74. plat->uartclk = dev_read_u32_default(dev, "clock-frequency", 0);
  75. return 0;
  76. }
  77. static const struct dm_serial_ops altera_uart_ops = {
  78. .putc = altera_uart_putc,
  79. .pending = altera_uart_pending,
  80. .getc = altera_uart_getc,
  81. .setbrg = altera_uart_setbrg,
  82. };
  83. static const struct udevice_id altera_uart_ids[] = {
  84. { .compatible = "altr,uart-1.0" },
  85. {}
  86. };
  87. U_BOOT_DRIVER(altera_uart) = {
  88. .name = "altera_uart",
  89. .id = UCLASS_SERIAL,
  90. .of_match = altera_uart_ids,
  91. .ofdata_to_platdata = altera_uart_ofdata_to_platdata,
  92. .platdata_auto_alloc_size = sizeof(struct altera_uart_platdata),
  93. .probe = altera_uart_probe,
  94. .ops = &altera_uart_ops,
  95. };
  96. #ifdef CONFIG_DEBUG_UART_ALTERA_UART
  97. #include <debug_uart.h>
  98. static inline void _debug_uart_init(void)
  99. {
  100. struct altera_uart_regs *regs = (void *)CONFIG_DEBUG_UART_BASE;
  101. u32 div;
  102. div = (CONFIG_DEBUG_UART_CLOCK / CONFIG_BAUDRATE) - 1;
  103. writel(div, &regs->divisor);
  104. }
  105. static inline void _debug_uart_putc(int ch)
  106. {
  107. struct altera_uart_regs *regs = (void *)CONFIG_DEBUG_UART_BASE;
  108. while (1) {
  109. u32 st = readl(&regs->status);
  110. if (st & ALTERA_UART_TRDY)
  111. break;
  112. }
  113. writel(ch, &regs->txdata);
  114. }
  115. DEBUG_UART_FUNCS
  116. #endif