stm32_rtc.c 8.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
  4. */
  5. #include <common.h>
  6. #include <clk.h>
  7. #include <dm.h>
  8. #include <malloc.h>
  9. #include <rtc.h>
  10. #include <asm/io.h>
  11. #include <dm/device_compat.h>
  12. #include <linux/bitops.h>
  13. #include <linux/iopoll.h>
  14. #define STM32_RTC_TR 0x00
  15. #define STM32_RTC_DR 0x04
  16. #define STM32_RTC_ISR 0x0C
  17. #define STM32_RTC_PRER 0x10
  18. #define STM32_RTC_CR 0x18
  19. #define STM32_RTC_WPR 0x24
  20. /* STM32_RTC_TR bit fields */
  21. #define STM32_RTC_SEC_SHIFT 0
  22. #define STM32_RTC_SEC GENMASK(6, 0)
  23. #define STM32_RTC_MIN_SHIFT 8
  24. #define STM32_RTC_MIN GENMASK(14, 8)
  25. #define STM32_RTC_HOUR_SHIFT 16
  26. #define STM32_RTC_HOUR GENMASK(21, 16)
  27. /* STM32_RTC_DR bit fields */
  28. #define STM32_RTC_DATE_SHIFT 0
  29. #define STM32_RTC_DATE GENMASK(5, 0)
  30. #define STM32_RTC_MONTH_SHIFT 8
  31. #define STM32_RTC_MONTH GENMASK(12, 8)
  32. #define STM32_RTC_WDAY_SHIFT 13
  33. #define STM32_RTC_WDAY GENMASK(15, 13)
  34. #define STM32_RTC_YEAR_SHIFT 16
  35. #define STM32_RTC_YEAR GENMASK(23, 16)
  36. /* STM32_RTC_CR bit fields */
  37. #define STM32_RTC_CR_FMT BIT(6)
  38. /* STM32_RTC_ISR/STM32_RTC_ICSR bit fields */
  39. #define STM32_RTC_ISR_INITS BIT(4)
  40. #define STM32_RTC_ISR_RSF BIT(5)
  41. #define STM32_RTC_ISR_INITF BIT(6)
  42. #define STM32_RTC_ISR_INIT BIT(7)
  43. /* STM32_RTC_PRER bit fields */
  44. #define STM32_RTC_PRER_PRED_S_SHIFT 0
  45. #define STM32_RTC_PRER_PRED_S GENMASK(14, 0)
  46. #define STM32_RTC_PRER_PRED_A_SHIFT 16
  47. #define STM32_RTC_PRER_PRED_A GENMASK(22, 16)
  48. /* STM32_RTC_WPR key constants */
  49. #define RTC_WPR_1ST_KEY 0xCA
  50. #define RTC_WPR_2ND_KEY 0x53
  51. #define RTC_WPR_WRONG_KEY 0xFF
  52. struct stm32_rtc_priv {
  53. fdt_addr_t base;
  54. };
  55. static int stm32_rtc_get(struct udevice *dev, struct rtc_time *tm)
  56. {
  57. struct stm32_rtc_priv *priv = dev_get_priv(dev);
  58. u32 tr, dr;
  59. tr = readl(priv->base + STM32_RTC_TR);
  60. dr = readl(priv->base + STM32_RTC_DR);
  61. tm->tm_sec = bcd2bin((tr & STM32_RTC_SEC) >> STM32_RTC_SEC_SHIFT);
  62. tm->tm_min = bcd2bin((tr & STM32_RTC_MIN) >> STM32_RTC_MIN_SHIFT);
  63. tm->tm_hour = bcd2bin((tr & STM32_RTC_HOUR) >> STM32_RTC_HOUR_SHIFT);
  64. tm->tm_mday = bcd2bin((dr & STM32_RTC_DATE) >> STM32_RTC_DATE_SHIFT);
  65. tm->tm_mon = bcd2bin((dr & STM32_RTC_MONTH) >> STM32_RTC_MONTH_SHIFT);
  66. tm->tm_year = 2000 +
  67. bcd2bin((dr & STM32_RTC_YEAR) >> STM32_RTC_YEAR_SHIFT);
  68. tm->tm_wday = bcd2bin((dr & STM32_RTC_WDAY) >> STM32_RTC_WDAY_SHIFT);
  69. tm->tm_yday = 0;
  70. tm->tm_isdst = 0;
  71. dev_dbg(dev, "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
  72. tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
  73. tm->tm_hour, tm->tm_min, tm->tm_sec);
  74. return 0;
  75. }
  76. static void stm32_rtc_unlock(struct udevice *dev)
  77. {
  78. struct stm32_rtc_priv *priv = dev_get_priv(dev);
  79. writel(RTC_WPR_1ST_KEY, priv->base + STM32_RTC_WPR);
  80. writel(RTC_WPR_2ND_KEY, priv->base + STM32_RTC_WPR);
  81. }
  82. static void stm32_rtc_lock(struct udevice *dev)
  83. {
  84. struct stm32_rtc_priv *priv = dev_get_priv(dev);
  85. writel(RTC_WPR_WRONG_KEY, priv->base + STM32_RTC_WPR);
  86. }
  87. static int stm32_rtc_enter_init_mode(struct udevice *dev)
  88. {
  89. struct stm32_rtc_priv *priv = dev_get_priv(dev);
  90. u32 isr = readl(priv->base + STM32_RTC_ISR);
  91. if (!(isr & STM32_RTC_ISR_INITF)) {
  92. isr |= STM32_RTC_ISR_INIT;
  93. writel(isr, priv->base + STM32_RTC_ISR);
  94. return readl_poll_timeout(priv->base + STM32_RTC_ISR,
  95. isr,
  96. (isr & STM32_RTC_ISR_INITF),
  97. 100000);
  98. }
  99. return 0;
  100. }
  101. static int stm32_rtc_wait_sync(struct udevice *dev)
  102. {
  103. struct stm32_rtc_priv *priv = dev_get_priv(dev);
  104. u32 isr = readl(priv->base + STM32_RTC_ISR);
  105. isr &= ~STM32_RTC_ISR_RSF;
  106. writel(isr, priv->base + STM32_RTC_ISR);
  107. /*
  108. * Wait for RSF to be set to ensure the calendar registers are
  109. * synchronised, it takes around 2 rtc_ck clock cycles
  110. */
  111. return readl_poll_timeout(priv->base + STM32_RTC_ISR,
  112. isr, (isr & STM32_RTC_ISR_RSF),
  113. 100000);
  114. }
  115. static void stm32_rtc_exit_init_mode(struct udevice *dev)
  116. {
  117. struct stm32_rtc_priv *priv = dev_get_priv(dev);
  118. u32 isr = readl(priv->base + STM32_RTC_ISR);
  119. isr &= ~STM32_RTC_ISR_INIT;
  120. writel(isr, priv->base + STM32_RTC_ISR);
  121. }
  122. static int stm32_rtc_set_time(struct udevice *dev, u32 time, u32 date)
  123. {
  124. struct stm32_rtc_priv *priv = dev_get_priv(dev);
  125. int ret;
  126. stm32_rtc_unlock(dev);
  127. ret = stm32_rtc_enter_init_mode(dev);
  128. if (ret)
  129. goto lock;
  130. writel(time, priv->base + STM32_RTC_TR);
  131. writel(date, priv->base + STM32_RTC_DR);
  132. stm32_rtc_exit_init_mode(dev);
  133. ret = stm32_rtc_wait_sync(dev);
  134. lock:
  135. stm32_rtc_lock(dev);
  136. return ret;
  137. }
  138. static int stm32_rtc_set(struct udevice *dev, const struct rtc_time *tm)
  139. {
  140. u32 t, d;
  141. dev_dbg(dev, "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
  142. tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
  143. tm->tm_hour, tm->tm_min, tm->tm_sec);
  144. if (tm->tm_year < 2000 || tm->tm_year > 2099)
  145. return -EINVAL;
  146. /* Time in BCD format */
  147. t = (bin2bcd(tm->tm_sec) << STM32_RTC_SEC_SHIFT) & STM32_RTC_SEC;
  148. t |= (bin2bcd(tm->tm_min) << STM32_RTC_MIN_SHIFT) & STM32_RTC_MIN;
  149. t |= (bin2bcd(tm->tm_hour) << STM32_RTC_HOUR_SHIFT) & STM32_RTC_HOUR;
  150. /* Date in BCD format */
  151. d = (bin2bcd(tm->tm_mday) << STM32_RTC_DATE_SHIFT) & STM32_RTC_DATE;
  152. d |= (bin2bcd(tm->tm_mon) << STM32_RTC_MONTH_SHIFT) & STM32_RTC_MONTH;
  153. d |= (bin2bcd(tm->tm_year - 2000) << STM32_RTC_YEAR_SHIFT) &
  154. STM32_RTC_YEAR;
  155. d |= (bin2bcd(tm->tm_wday) << STM32_RTC_WDAY_SHIFT) & STM32_RTC_WDAY;
  156. return stm32_rtc_set_time(dev, t, d);
  157. }
  158. static int stm32_rtc_reset(struct udevice *dev)
  159. {
  160. dev_dbg(dev, "Reset DATE\n");
  161. return stm32_rtc_set_time(dev, 0, 0);
  162. }
  163. static int stm32_rtc_init(struct udevice *dev)
  164. {
  165. struct stm32_rtc_priv *priv = dev_get_priv(dev);
  166. unsigned int prer, pred_a, pred_s, pred_a_max, pred_s_max, cr;
  167. unsigned int rate;
  168. struct clk clk;
  169. int ret;
  170. u32 isr = readl(priv->base + STM32_RTC_ISR);
  171. if (isr & STM32_RTC_ISR_INITS)
  172. return 0;
  173. ret = clk_get_by_index(dev, 1, &clk);
  174. if (ret)
  175. return ret;
  176. ret = clk_enable(&clk);
  177. if (ret) {
  178. clk_free(&clk);
  179. return ret;
  180. }
  181. rate = clk_get_rate(&clk);
  182. /* Find prediv_a and prediv_s to obtain the 1Hz calendar clock */
  183. pred_a_max = STM32_RTC_PRER_PRED_A >> STM32_RTC_PRER_PRED_A_SHIFT;
  184. pred_s_max = STM32_RTC_PRER_PRED_S >> STM32_RTC_PRER_PRED_S_SHIFT;
  185. for (pred_a = pred_a_max; pred_a + 1 > 0; pred_a--) {
  186. pred_s = (rate / (pred_a + 1)) - 1;
  187. if (((pred_s + 1) * (pred_a + 1)) == rate)
  188. break;
  189. }
  190. /*
  191. * Can't find a 1Hz, so give priority to RTC power consumption
  192. * by choosing the higher possible value for prediv_a
  193. */
  194. if (pred_s > pred_s_max || pred_a > pred_a_max) {
  195. pred_a = pred_a_max;
  196. pred_s = (rate / (pred_a + 1)) - 1;
  197. }
  198. stm32_rtc_unlock(dev);
  199. ret = stm32_rtc_enter_init_mode(dev);
  200. if (ret) {
  201. dev_err(dev,
  202. "Can't enter in init mode. Prescaler config failed.\n");
  203. goto unlock;
  204. }
  205. prer = (pred_s << STM32_RTC_PRER_PRED_S_SHIFT) & STM32_RTC_PRER_PRED_S;
  206. prer |= (pred_a << STM32_RTC_PRER_PRED_A_SHIFT) & STM32_RTC_PRER_PRED_A;
  207. writel(prer, priv->base + STM32_RTC_PRER);
  208. /* Force 24h time format */
  209. cr = readl(priv->base + STM32_RTC_CR);
  210. cr &= ~STM32_RTC_CR_FMT;
  211. writel(cr, priv->base + STM32_RTC_CR);
  212. stm32_rtc_exit_init_mode(dev);
  213. ret = stm32_rtc_wait_sync(dev);
  214. unlock:
  215. stm32_rtc_lock(dev);
  216. if (ret) {
  217. clk_disable(&clk);
  218. clk_free(&clk);
  219. }
  220. return ret;
  221. }
  222. static int stm32_rtc_probe(struct udevice *dev)
  223. {
  224. struct stm32_rtc_priv *priv = dev_get_priv(dev);
  225. struct clk clk;
  226. int ret;
  227. priv->base = dev_read_addr(dev);
  228. if (priv->base == FDT_ADDR_T_NONE)
  229. return -EINVAL;
  230. ret = clk_get_by_index(dev, 0, &clk);
  231. if (ret)
  232. return ret;
  233. ret = clk_enable(&clk);
  234. if (ret) {
  235. clk_free(&clk);
  236. return ret;
  237. }
  238. ret = stm32_rtc_init(dev);
  239. if (ret) {
  240. clk_disable(&clk);
  241. clk_free(&clk);
  242. }
  243. return ret;
  244. }
  245. static const struct rtc_ops stm32_rtc_ops = {
  246. .get = stm32_rtc_get,
  247. .set = stm32_rtc_set,
  248. .reset = stm32_rtc_reset,
  249. };
  250. static const struct udevice_id stm32_rtc_ids[] = {
  251. { .compatible = "st,stm32mp1-rtc" },
  252. { }
  253. };
  254. U_BOOT_DRIVER(rtc_stm32) = {
  255. .name = "rtc-stm32",
  256. .id = UCLASS_RTC,
  257. .probe = stm32_rtc_probe,
  258. .of_match = stm32_rtc_ids,
  259. .ops = &stm32_rtc_ops,
  260. .priv_auto_alloc_size = sizeof(struct stm32_rtc_priv),
  261. };