msm_rng.c 3.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * PRNG driver for Qualcomm IPQ40xx
  4. *
  5. * Copyright (c) 2020 Sartura Ltd.
  6. *
  7. * Author: Robert Marko <robert.marko@sartura.hr>
  8. *
  9. * Based on Linux driver
  10. */
  11. #include <asm/io.h>
  12. #include <clk.h>
  13. #include <common.h>
  14. #include <dm.h>
  15. #include <linux/bitops.h>
  16. #include <rng.h>
  17. /* Device specific register offsets */
  18. #define PRNG_DATA_OUT 0x0000
  19. #define PRNG_STATUS 0x0004
  20. #define PRNG_LFSR_CFG 0x0100
  21. #define PRNG_CONFIG 0x0104
  22. /* Device specific register masks and config values */
  23. #define PRNG_LFSR_CFG_MASK 0x0000ffff
  24. #define PRNG_LFSR_CFG_CLOCKS 0x0000dddd
  25. #define PRNG_CONFIG_HW_ENABLE BIT(1)
  26. #define PRNG_STATUS_DATA_AVAIL BIT(0)
  27. #define MAX_HW_FIFO_DEPTH 16
  28. #define MAX_HW_FIFO_SIZE (MAX_HW_FIFO_DEPTH * 4)
  29. #define WORD_SZ 4
  30. struct msm_rng_priv {
  31. phys_addr_t base;
  32. struct clk clk;
  33. };
  34. static int msm_rng_read(struct udevice *dev, void *data, size_t len)
  35. {
  36. struct msm_rng_priv *priv = dev_get_priv(dev);
  37. size_t currsize = 0;
  38. u32 *retdata = data;
  39. size_t maxsize;
  40. u32 val;
  41. /* calculate max size bytes to transfer back to caller */
  42. maxsize = min_t(size_t, MAX_HW_FIFO_SIZE, len);
  43. /* read random data from hardware */
  44. do {
  45. val = readl_relaxed(priv->base + PRNG_STATUS);
  46. if (!(val & PRNG_STATUS_DATA_AVAIL))
  47. break;
  48. val = readl_relaxed(priv->base + PRNG_DATA_OUT);
  49. if (!val)
  50. break;
  51. *retdata++ = val;
  52. currsize += WORD_SZ;
  53. /* make sure we stay on 32bit boundary */
  54. if ((maxsize - currsize) < WORD_SZ)
  55. break;
  56. } while (currsize < maxsize);
  57. return 0;
  58. }
  59. static int msm_rng_enable(struct msm_rng_priv *priv, int enable)
  60. {
  61. u32 val;
  62. if (enable) {
  63. /* Enable PRNG only if it is not already enabled */
  64. val = readl_relaxed(priv->base + PRNG_CONFIG);
  65. if (val & PRNG_CONFIG_HW_ENABLE) {
  66. val = readl_relaxed(priv->base + PRNG_LFSR_CFG);
  67. val &= ~PRNG_LFSR_CFG_MASK;
  68. val |= PRNG_LFSR_CFG_CLOCKS;
  69. writel(val, priv->base + PRNG_LFSR_CFG);
  70. val = readl_relaxed(priv->base + PRNG_CONFIG);
  71. val |= PRNG_CONFIG_HW_ENABLE;
  72. writel(val, priv->base + PRNG_CONFIG);
  73. }
  74. } else {
  75. val = readl_relaxed(priv->base + PRNG_CONFIG);
  76. val &= ~PRNG_CONFIG_HW_ENABLE;
  77. writel(val, priv->base + PRNG_CONFIG);
  78. }
  79. return 0;
  80. }
  81. static int msm_rng_probe(struct udevice *dev)
  82. {
  83. struct msm_rng_priv *priv = dev_get_priv(dev);
  84. int ret;
  85. priv->base = dev_read_addr(dev);
  86. if (priv->base == FDT_ADDR_T_NONE)
  87. return -EINVAL;
  88. ret = clk_get_by_index(dev, 0, &priv->clk);
  89. if (ret)
  90. return ret;
  91. ret = clk_enable(&priv->clk);
  92. if (ret < 0)
  93. return ret;
  94. return msm_rng_enable(priv, 1);
  95. }
  96. static int msm_rng_remove(struct udevice *dev)
  97. {
  98. struct msm_rng_priv *priv = dev_get_priv(dev);
  99. return msm_rng_enable(priv, 0);
  100. }
  101. static const struct dm_rng_ops msm_rng_ops = {
  102. .read = msm_rng_read,
  103. };
  104. static const struct udevice_id msm_rng_match[] = {
  105. { .compatible = "qcom,prng", },
  106. {},
  107. };
  108. U_BOOT_DRIVER(msm_rng) = {
  109. .name = "msm-rng",
  110. .id = UCLASS_RNG,
  111. .of_match = msm_rng_match,
  112. .ops = &msm_rng_ops,
  113. .probe = msm_rng_probe,
  114. .remove = msm_rng_remove,
  115. .priv_auto_alloc_size = sizeof(struct msm_rng_priv),
  116. };