sti-reset.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
  4. * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
  5. */
  6. #include <common.h>
  7. #include <errno.h>
  8. #include <log.h>
  9. #include <malloc.h>
  10. #include <wait_bit.h>
  11. #include <dm.h>
  12. #include <reset-uclass.h>
  13. #include <regmap.h>
  14. #include <syscon.h>
  15. #include <dt-bindings/reset/stih407-resets.h>
  16. #include <linux/bitops.h>
  17. DECLARE_GLOBAL_DATA_PTR;
  18. struct sti_reset {
  19. const struct syscfg_reset_controller_data *data;
  20. };
  21. /**
  22. * Reset channel description for a system configuration register based
  23. * reset controller.
  24. *
  25. * @compatible: Compatible string of the syscon containing this
  26. * channel's control and ack (status) bits.
  27. * @reset_offset: Reset register offset in sysconf bank.
  28. * @reset_bit: Bit number in reset register.
  29. * @ack_offset: Ack reset register offset in syscon bank.
  30. * @ack_bit: Bit number in Ack reset register.
  31. * @deassert_cnt: incremented when reset is deasserted, reset can only be
  32. * asserted when equal to 0
  33. */
  34. struct syscfg_reset_channel_data {
  35. const char *compatible;
  36. int reset_offset;
  37. int reset_bit;
  38. int ack_offset;
  39. int ack_bit;
  40. int deassert_cnt;
  41. };
  42. /**
  43. * Description of a system configuration register based reset controller.
  44. *
  45. * @wait_for_ack: The controller will wait for reset assert and de-assert to
  46. * be "ack'd" in a channel's ack field.
  47. * @active_low: Are the resets in this controller active low, i.e. clearing
  48. * the reset bit puts the hardware into reset.
  49. * @nr_channels: The number of reset channels in this controller.
  50. * @channels: An array of reset channel descriptions.
  51. */
  52. struct syscfg_reset_controller_data {
  53. bool wait_for_ack;
  54. bool active_low;
  55. int nr_channels;
  56. struct syscfg_reset_channel_data *channels;
  57. };
  58. /* STiH407 Peripheral powerdown definitions. */
  59. static const char stih407_core[] = "st,stih407-core-syscfg";
  60. static const char stih407_sbc_reg[] = "st,stih407-sbc-reg-syscfg";
  61. static const char stih407_lpm[] = "st,stih407-lpm-syscfg";
  62. #define _SYSCFG_RST_CH(_c, _rr, _rb, _ar, _ab) \
  63. { .compatible = _c, \
  64. .reset_offset = _rr, \
  65. .reset_bit = _rb, \
  66. .ack_offset = _ar, \
  67. .ack_bit = _ab, }
  68. #define _SYSCFG_RST_CH_NO_ACK(_c, _rr, _rb) \
  69. { .compatible = _c, \
  70. .reset_offset = _rr, \
  71. .reset_bit = _rb, }
  72. #define STIH407_SRST_CORE(_reg, _bit) \
  73. _SYSCFG_RST_CH_NO_ACK(stih407_core, _reg, _bit)
  74. #define STIH407_SRST_SBC(_reg, _bit) \
  75. _SYSCFG_RST_CH_NO_ACK(stih407_sbc_reg, _reg, _bit)
  76. #define STIH407_SRST_LPM(_reg, _bit) \
  77. _SYSCFG_RST_CH_NO_ACK(stih407_lpm, _reg, _bit)
  78. #define STIH407_PDN_0(_bit) \
  79. _SYSCFG_RST_CH(stih407_core, SYSCFG_5000, _bit, SYSSTAT_5500, _bit)
  80. #define STIH407_PDN_1(_bit) \
  81. _SYSCFG_RST_CH(stih407_core, SYSCFG_5001, _bit, SYSSTAT_5501, _bit)
  82. #define STIH407_PDN_ETH(_bit, _stat) \
  83. _SYSCFG_RST_CH(stih407_sbc_reg, SYSCFG_4032, _bit, SYSSTAT_4520, _stat)
  84. /* Powerdown requests control 0 */
  85. #define SYSCFG_5000 0x0
  86. #define SYSSTAT_5500 0x7d0
  87. /* Powerdown requests control 1 (High Speed Links) */
  88. #define SYSCFG_5001 0x4
  89. #define SYSSTAT_5501 0x7d4
  90. /* Ethernet powerdown/status/reset */
  91. #define SYSCFG_4032 0x80
  92. #define SYSSTAT_4520 0x820
  93. #define SYSCFG_4002 0x8
  94. static struct syscfg_reset_channel_data stih407_powerdowns[] = {
  95. [STIH407_EMISS_POWERDOWN] = STIH407_PDN_0(1),
  96. [STIH407_NAND_POWERDOWN] = STIH407_PDN_0(0),
  97. [STIH407_USB3_POWERDOWN] = STIH407_PDN_1(6),
  98. [STIH407_USB2_PORT1_POWERDOWN] = STIH407_PDN_1(5),
  99. [STIH407_USB2_PORT0_POWERDOWN] = STIH407_PDN_1(4),
  100. [STIH407_PCIE1_POWERDOWN] = STIH407_PDN_1(3),
  101. [STIH407_PCIE0_POWERDOWN] = STIH407_PDN_1(2),
  102. [STIH407_SATA1_POWERDOWN] = STIH407_PDN_1(1),
  103. [STIH407_SATA0_POWERDOWN] = STIH407_PDN_1(0),
  104. [STIH407_ETH1_POWERDOWN] = STIH407_PDN_ETH(0, 2),
  105. };
  106. /* Reset Generator control 0/1 */
  107. #define SYSCFG_5128 0x200
  108. #define SYSCFG_5131 0x20c
  109. #define SYSCFG_5132 0x210
  110. #define LPM_SYSCFG_1 0x4 /* Softreset IRB & SBC UART */
  111. static struct syscfg_reset_channel_data stih407_softresets[] = {
  112. [STIH407_ETH1_SOFTRESET] = STIH407_SRST_SBC(SYSCFG_4002, 4),
  113. [STIH407_MMC1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 3),
  114. [STIH407_USB2_PORT0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 28),
  115. [STIH407_USB2_PORT1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 29),
  116. [STIH407_PICOPHY_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 30),
  117. [STIH407_IRB_SOFTRESET] = STIH407_SRST_LPM(LPM_SYSCFG_1, 6),
  118. [STIH407_PCIE0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 6),
  119. [STIH407_PCIE1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 15),
  120. [STIH407_SATA0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 7),
  121. [STIH407_SATA1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 16),
  122. [STIH407_MIPHY0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 4),
  123. [STIH407_MIPHY1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 13),
  124. [STIH407_MIPHY2_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 22),
  125. [STIH407_SATA0_PWR_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 5),
  126. [STIH407_SATA1_PWR_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 14),
  127. [STIH407_DELTA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 3),
  128. [STIH407_BLITTER_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 10),
  129. [STIH407_HDTVOUT_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 11),
  130. [STIH407_HDQVDP_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 12),
  131. [STIH407_VDP_AUX_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 14),
  132. [STIH407_COMPO_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 15),
  133. [STIH407_HDMI_TX_PHY_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 21),
  134. [STIH407_JPEG_DEC_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 23),
  135. [STIH407_VP8_DEC_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 24),
  136. [STIH407_GPU_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 30),
  137. [STIH407_HVA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 0),
  138. [STIH407_ERAM_HVA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 1),
  139. [STIH407_LPM_SOFTRESET] = STIH407_SRST_SBC(SYSCFG_4002, 2),
  140. [STIH407_KEYSCAN_SOFTRESET] = STIH407_SRST_LPM(LPM_SYSCFG_1, 8),
  141. [STIH407_ST231_AUD_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 26),
  142. [STIH407_ST231_DMU_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 27),
  143. [STIH407_ST231_GP0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 28),
  144. [STIH407_ST231_GP1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5128, 2),
  145. };
  146. /* PicoPHY reset/control */
  147. #define SYSCFG_5061 0x0f4
  148. static struct syscfg_reset_channel_data stih407_picophyresets[] = {
  149. [STIH407_PICOPHY0_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 5),
  150. [STIH407_PICOPHY1_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 6),
  151. [STIH407_PICOPHY2_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 7),
  152. };
  153. static const struct
  154. syscfg_reset_controller_data stih407_powerdown_controller = {
  155. .wait_for_ack = true,
  156. .nr_channels = ARRAY_SIZE(stih407_powerdowns),
  157. .channels = stih407_powerdowns,
  158. };
  159. static const struct
  160. syscfg_reset_controller_data stih407_softreset_controller = {
  161. .wait_for_ack = false,
  162. .active_low = true,
  163. .nr_channels = ARRAY_SIZE(stih407_softresets),
  164. .channels = stih407_softresets,
  165. };
  166. static const struct
  167. syscfg_reset_controller_data stih407_picophyreset_controller = {
  168. .wait_for_ack = false,
  169. .nr_channels = ARRAY_SIZE(stih407_picophyresets),
  170. .channels = stih407_picophyresets,
  171. };
  172. phys_addr_t sti_reset_get_regmap(const char *compatible)
  173. {
  174. struct udevice *syscon;
  175. struct regmap *regmap;
  176. int node, ret;
  177. node = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
  178. compatible);
  179. if (node < 0) {
  180. pr_err("unable to find %s node\n", compatible);
  181. return node;
  182. }
  183. ret = uclass_get_device_by_of_offset(UCLASS_SYSCON, node, &syscon);
  184. if (ret) {
  185. pr_err("%s: uclass_get_device_by_of_offset failed: %d\n",
  186. __func__, ret);
  187. return ret;
  188. }
  189. regmap = syscon_get_regmap(syscon);
  190. if (!regmap) {
  191. pr_err("unable to get regmap for %s\n", syscon->name);
  192. return -ENODEV;
  193. }
  194. return regmap->ranges[0].start;
  195. }
  196. static int sti_reset_program_hw(struct reset_ctl *reset_ctl, int assert)
  197. {
  198. struct udevice *dev = reset_ctl->dev;
  199. struct syscfg_reset_controller_data *reset_desc =
  200. (struct syscfg_reset_controller_data *)(dev->driver_data);
  201. struct syscfg_reset_channel_data *ch;
  202. phys_addr_t base;
  203. u32 ctrl_val = reset_desc->active_low ? !assert : !!assert;
  204. void __iomem *reg;
  205. /* check if reset id is inside available range */
  206. if (reset_ctl->id >= reset_desc->nr_channels)
  207. return -EINVAL;
  208. /* get reset sysconf register base address */
  209. base = sti_reset_get_regmap(reset_desc->channels[reset_ctl->id].compatible);
  210. ch = &reset_desc->channels[reset_ctl->id];
  211. /* check the deassert counter to assert reset when it reaches 0 */
  212. if (!assert) {
  213. ch->deassert_cnt++;
  214. if (ch->deassert_cnt > 1)
  215. return 0;
  216. } else {
  217. if (ch->deassert_cnt > 0) {
  218. ch->deassert_cnt--;
  219. if (ch->deassert_cnt > 0)
  220. return 0;
  221. } else
  222. pr_err("Reset balancing error: reset_ctl=%p dev=%p id=%lu\n",
  223. reset_ctl, reset_ctl->dev, reset_ctl->id);
  224. }
  225. reg = (void __iomem *)base + ch->reset_offset;
  226. if (ctrl_val)
  227. generic_set_bit(ch->reset_bit, reg);
  228. else
  229. generic_clear_bit(ch->reset_bit, reg);
  230. if (!reset_desc->wait_for_ack)
  231. return 0;
  232. reg = (void __iomem *)base + ch->ack_offset;
  233. if (wait_for_bit_le32(reg, BIT(ch->ack_bit), ctrl_val,
  234. 1000, false)) {
  235. pr_err("Stuck on waiting ack reset_ctl=%p dev=%p id=%lu\n",
  236. reset_ctl, reset_ctl->dev, reset_ctl->id);
  237. return -ETIMEDOUT;
  238. }
  239. return 0;
  240. }
  241. static int sti_reset_request(struct reset_ctl *reset_ctl)
  242. {
  243. return 0;
  244. }
  245. static int sti_reset_free(struct reset_ctl *reset_ctl)
  246. {
  247. return 0;
  248. }
  249. static int sti_reset_assert(struct reset_ctl *reset_ctl)
  250. {
  251. return sti_reset_program_hw(reset_ctl, true);
  252. }
  253. static int sti_reset_deassert(struct reset_ctl *reset_ctl)
  254. {
  255. return sti_reset_program_hw(reset_ctl, false);
  256. }
  257. struct reset_ops sti_reset_ops = {
  258. .request = sti_reset_request,
  259. .rfree = sti_reset_free,
  260. .rst_assert = sti_reset_assert,
  261. .rst_deassert = sti_reset_deassert,
  262. };
  263. static int sti_reset_probe(struct udevice *dev)
  264. {
  265. struct sti_reset *priv = dev_get_priv(dev);
  266. priv->data = (void *)dev_get_driver_data(dev);
  267. return 0;
  268. }
  269. static const struct udevice_id sti_reset_ids[] = {
  270. {
  271. .compatible = "st,stih407-picophyreset",
  272. .data = (ulong)&stih407_picophyreset_controller,
  273. },
  274. {
  275. .compatible = "st,stih407-powerdown",
  276. .data = (ulong)&stih407_powerdown_controller,
  277. },
  278. {
  279. .compatible = "st,stih407-softreset",
  280. .data = (ulong)&stih407_softreset_controller,
  281. },
  282. { }
  283. };
  284. U_BOOT_DRIVER(sti_reset) = {
  285. .name = "sti_reset",
  286. .id = UCLASS_RESET,
  287. .of_match = sti_reset_ids,
  288. .probe = sti_reset_probe,
  289. .priv_auto_alloc_size = sizeof(struct sti_reset),
  290. .ops = &sti_reset_ops,
  291. };