Kconfig 5.8 KB

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  1. menu "Reset Controller Support"
  2. config DM_RESET
  3. bool "Enable reset controllers using Driver Model"
  4. depends on DM && OF_CONTROL
  5. help
  6. Enable support for the reset controller driver class. Many hardware
  7. modules are equipped with a reset signal, typically driven by some
  8. reset controller hardware module within the chip. In U-Boot, reset
  9. controller drivers allow control over these reset signals. In some
  10. cases this API is applicable to chips outside the CPU as well,
  11. although driving such reset isgnals using GPIOs may be more
  12. appropriate in this case.
  13. config SANDBOX_RESET
  14. bool "Enable the sandbox reset test driver"
  15. depends on DM_MAILBOX && SANDBOX
  16. help
  17. Enable support for a test reset controller implementation, which
  18. simply accepts requests to reset various HW modules without actually
  19. doing anything beyond a little error checking.
  20. config STI_RESET
  21. bool "Enable the STi reset"
  22. depends on ARCH_STI
  23. help
  24. Support for reset controllers on STMicroelectronics STiH407 family SoCs.
  25. Say Y if you want to control reset signals provided by system config
  26. block.
  27. config STM32_RESET
  28. bool "Enable the STM32 reset"
  29. depends on ARCH_STM32 || ARCH_STM32MP
  30. help
  31. Support for reset controllers on STMicroelectronics STM32 family SoCs.
  32. This reset driver is compatible with STM32 F4/F7 and H7 SoCs.
  33. config TEGRA_CAR_RESET
  34. bool "Enable Tegra CAR-based reset driver"
  35. depends on TEGRA_CAR
  36. help
  37. Enable support for manipulating Tegra's on-SoC reset signals via
  38. direct register access to the Tegra CAR (Clock And Reset controller).
  39. config TEGRA186_RESET
  40. bool "Enable Tegra186 BPMP-based reset driver"
  41. depends on TEGRA186_BPMP
  42. help
  43. Enable support for manipulating Tegra's on-SoC reset signals via IPC
  44. requests to the BPMP (Boot and Power Management Processor).
  45. config RESET_TI_SCI
  46. bool "TI System Control Interface (TI SCI) reset driver"
  47. depends on DM_RESET && TI_SCI_PROTOCOL
  48. help
  49. This enables the reset driver support over TI System Control Interface
  50. available on some new TI's SoCs. If you wish to use reset resources
  51. managed by the TI System Controller, say Y here. Otherwise, say N.
  52. config RESET_BCM6345
  53. bool "Reset controller driver for BCM6345"
  54. depends on DM_RESET && ARCH_BMIPS
  55. help
  56. Support reset controller on BCM6345.
  57. config RESET_UNIPHIER
  58. bool "Reset controller driver for UniPhier SoCs"
  59. depends on ARCH_UNIPHIER
  60. default y
  61. help
  62. Support for reset controllers on UniPhier SoCs.
  63. Say Y if you want to control reset signals provided by System Control
  64. block, Media I/O block, Peripheral Block.
  65. config RESET_AST2500
  66. bool "Reset controller driver for AST2500 SoCs"
  67. depends on DM_RESET
  68. default y if ASPEED_AST2500
  69. help
  70. Support for reset controller on AST2500 SoC.
  71. Say Y if you want to control reset signals of different peripherals
  72. through System Control Unit (SCU).
  73. config RESET_ROCKCHIP
  74. bool "Reset controller driver for Rockchip SoCs"
  75. depends on DM_RESET && ARCH_ROCKCHIP && CLK
  76. default y
  77. help
  78. Support for reset controller on rockchip SoC. The main limitation
  79. though is that some reset signals, like I2C or MISC reset multiple
  80. devices.
  81. config RESET_HSDK
  82. bool "Synopsys HSDK Reset Driver"
  83. depends on DM_RESET && TARGET_HSDK
  84. default y
  85. help
  86. This enables the reset controller driver for HSDK board.
  87. config RESET_MESON
  88. bool "Reset controller driver for Amlogic Meson SoCs"
  89. depends on DM_RESET && ARCH_MESON
  90. imply REGMAP
  91. default y
  92. help
  93. Support for reset controller on Amlogic Meson SoC.
  94. config RESET_SOCFPGA
  95. bool "Reset controller driver for SoCFPGA"
  96. depends on DM_RESET && ARCH_SOCFPGA
  97. default y
  98. help
  99. Support for reset controller on SoCFPGA platform.
  100. config RESET_MEDIATEK
  101. bool "Reset controller driver for MediaTek SoCs"
  102. depends on DM_RESET && ARCH_MEDIATEK && CLK
  103. default y
  104. help
  105. Support for reset controller on MediaTek SoCs.
  106. config RESET_MTMIPS
  107. bool "Reset controller driver for MediaTek MIPS platform"
  108. depends on DM_RESET && ARCH_MTMIPS
  109. default y
  110. help
  111. Support for reset controller on MediaTek MIPS platform.
  112. config RESET_SUNXI
  113. bool "RESET support for Allwinner SoCs"
  114. depends on DM_RESET && ARCH_SUNXI
  115. default y
  116. help
  117. This enables support for common reset driver for
  118. Allwinner SoCs.
  119. config RESET_HISILICON
  120. bool "Reset controller driver for HiSilicon SoCs"
  121. depends on DM_RESET
  122. help
  123. Support for reset controller on HiSilicon SoCs.
  124. config RESET_IMX7
  125. bool "i.MX7/8 Reset Driver"
  126. depends on DM_RESET && (ARCH_MX7 || ARCH_IMX8M)
  127. default y
  128. help
  129. Support for reset controller on i.MX7/8 SoCs.
  130. config RESET_IPQ419
  131. bool "Reset driver for Qualcomm IPQ40xx SoCs"
  132. depends on DM_RESET && ARCH_IPQ40XX
  133. default y
  134. help
  135. Support for reset controller on Qualcomm
  136. IPQ40xx SoCs.
  137. config RESET_SIFIVE
  138. bool "Reset Driver for SiFive SoC's"
  139. depends on DM_RESET && CLK_SIFIVE_FU540_PRCI && TARGET_SIFIVE_FU540
  140. default y
  141. help
  142. PRCI module within SiFive SoC's provides mechanism to reset
  143. different hw blocks like DDR, gemgxl. With this driver we leverage
  144. U-Boot's reset framework to reset these hardware blocks.
  145. config RESET_SYSCON
  146. bool "Enable generic syscon reset driver support"
  147. depends on DM_RESET
  148. help
  149. Support generic syscon mapped register reset devices.
  150. config RESET_RASPBERRYPI
  151. bool "Raspberry Pi 4 Firmware Reset Controller Driver"
  152. depends on DM_RESET && ARCH_BCM283X
  153. default USB_XHCI_PCI
  154. help
  155. Raspberry Pi 4's co-processor controls some of the board's HW
  156. initialization process, but it's up to Linux to trigger it when
  157. relevant. This driver provides a reset controller capable of
  158. interfacing with RPi4's co-processor and model these firmware
  159. initialization routines as reset lines.
  160. config RESET_SCMI
  161. bool "Enable SCMI reset domain driver"
  162. select SCMI_FIRMWARE
  163. help
  164. Enable this option if you want to support reset controller
  165. devices exposed by a SCMI agent based on SCMI reset domain
  166. protocol communication with a SCMI server.
  167. endmenu