stm32mp1_tuning.c 43 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
  4. */
  5. #include <common.h>
  6. #include <console.h>
  7. #include <clk.h>
  8. #include <log.h>
  9. #include <ram.h>
  10. #include <rand.h>
  11. #include <reset.h>
  12. #include <asm/io.h>
  13. #include <linux/bitops.h>
  14. #include <linux/delay.h>
  15. #include <linux/iopoll.h>
  16. #include "stm32mp1_ddr_regs.h"
  17. #include "stm32mp1_ddr.h"
  18. #include "stm32mp1_tests.h"
  19. #define MAX_DQS_PHASE_IDX _144deg
  20. #define MAX_DQS_UNIT_IDX 7
  21. #define MAX_GSL_IDX 5
  22. #define MAX_GPS_IDX 3
  23. /* Number of bytes used in this SW. ( min 1--> max 4). */
  24. #define NUM_BYTES 4
  25. enum dqs_phase_enum {
  26. _36deg = 0,
  27. _54deg = 1,
  28. _72deg = 2,
  29. _90deg = 3,
  30. _108deg = 4,
  31. _126deg = 5,
  32. _144deg = 6
  33. };
  34. /* BIST Result struct */
  35. struct BIST_result {
  36. /* Overall test result:
  37. * 0 Fail (any bit failed) ,
  38. * 1 Success (All bits success)
  39. */
  40. bool test_result;
  41. /* 1: true, all fail / 0: False, not all bits fail */
  42. bool all_bits_fail;
  43. bool bit_i_test_result[8]; /* 0 fail / 1 success */
  44. };
  45. /* a struct that defines tuning parameters of a byte. */
  46. struct tuning_position {
  47. u8 phase; /* DQS phase */
  48. u8 unit; /* DQS unit delay */
  49. u32 bits_delay; /* Bits deskew in this byte */
  50. };
  51. /* 36deg, 54deg, 72deg, 90deg, 108deg, 126deg, 144deg */
  52. const u8 dx_dll_phase[7] = {3, 2, 1, 0, 14, 13, 12};
  53. static u8 BIST_error_max = 1;
  54. static u32 BIST_seed = 0x1234ABCD;
  55. static u8 get_nb_bytes(struct stm32mp1_ddrctl *ctl)
  56. {
  57. u32 data_bus = readl(&ctl->mstr) & DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK;
  58. u8 nb_bytes = NUM_BYTES;
  59. switch (data_bus) {
  60. case DDRCTRL_MSTR_DATA_BUS_WIDTH_HALF:
  61. nb_bytes /= 2;
  62. break;
  63. case DDRCTRL_MSTR_DATA_BUS_WIDTH_QUARTER:
  64. nb_bytes /= 4;
  65. break;
  66. default:
  67. break;
  68. }
  69. return nb_bytes;
  70. }
  71. static u8 get_nb_bank(struct stm32mp1_ddrctl *ctl)
  72. {
  73. /* Count bank address bits */
  74. u8 bits = 0;
  75. u32 reg, val;
  76. reg = readl(&ctl->addrmap1);
  77. /* addrmap1.addrmap_bank_b1 */
  78. val = (reg & GENMASK(5, 0)) >> 0;
  79. if (val <= 31)
  80. bits++;
  81. /* addrmap1.addrmap_bank_b2 */
  82. val = (reg & GENMASK(13, 8)) >> 8;
  83. if (val <= 31)
  84. bits++;
  85. /* addrmap1.addrmap_bank_b3 */
  86. val = (reg & GENMASK(21, 16)) >> 16;
  87. if (val <= 31)
  88. bits++;
  89. return bits;
  90. }
  91. static u8 get_nb_col(struct stm32mp1_ddrctl *ctl)
  92. {
  93. u8 bits;
  94. u32 reg, val;
  95. /* Count column address bits, start at 2 for b0 and b1 (fixed) */
  96. bits = 2;
  97. reg = readl(&ctl->addrmap2);
  98. /* addrmap2.addrmap_col_b2 */
  99. val = (reg & GENMASK(3, 0)) >> 0;
  100. if (val <= 7)
  101. bits++;
  102. /* addrmap2.addrmap_col_b3 */
  103. val = (reg & GENMASK(11, 8)) >> 8;
  104. if (val <= 7)
  105. bits++;
  106. /* addrmap2.addrmap_col_b4 */
  107. val = (reg & GENMASK(19, 16)) >> 16;
  108. if (val <= 7)
  109. bits++;
  110. /* addrmap2.addrmap_col_b5 */
  111. val = (reg & GENMASK(27, 24)) >> 24;
  112. if (val <= 7)
  113. bits++;
  114. reg = readl(&ctl->addrmap3);
  115. /* addrmap3.addrmap_col_b6 */
  116. val = (reg & GENMASK(3, 0)) >> 0;
  117. if (val <= 7)
  118. bits++;
  119. /* addrmap3.addrmap_col_b7 */
  120. val = (reg & GENMASK(11, 8)) >> 8;
  121. if (val <= 7)
  122. bits++;
  123. /* addrmap3.addrmap_col_b8 */
  124. val = (reg & GENMASK(19, 16)) >> 16;
  125. if (val <= 7)
  126. bits++;
  127. /* addrmap3.addrmap_col_b9 */
  128. val = (reg & GENMASK(27, 24)) >> 24;
  129. if (val <= 7)
  130. bits++;
  131. reg = readl(&ctl->addrmap4);
  132. /* addrmap4.addrmap_col_b10 */
  133. val = (reg & GENMASK(3, 0)) >> 0;
  134. if (val <= 7)
  135. bits++;
  136. /* addrmap4.addrmap_col_b11 */
  137. val = (reg & GENMASK(11, 8)) >> 8;
  138. if (val <= 7)
  139. bits++;
  140. return bits;
  141. }
  142. static u8 get_nb_row(struct stm32mp1_ddrctl *ctl)
  143. {
  144. /* Count row address bits */
  145. u8 bits = 0;
  146. u32 reg, val;
  147. reg = readl(&ctl->addrmap5);
  148. /* addrmap5.addrmap_row_b0 */
  149. val = (reg & GENMASK(3, 0)) >> 0;
  150. if (val <= 11)
  151. bits++;
  152. /* addrmap5.addrmap_row_b1 */
  153. val = (reg & GENMASK(11, 8)) >> 8;
  154. if (val <= 11)
  155. bits++;
  156. /* addrmap5.addrmap_row_b2_10 */
  157. val = (reg & GENMASK(19, 16)) >> 16;
  158. if (val <= 11)
  159. bits += 9;
  160. else
  161. printf("warning: addrmap5.addrmap_row_b2_10 not supported\n");
  162. /* addrmap5.addrmap_row_b11 */
  163. val = (reg & GENMASK(27, 24)) >> 24;
  164. if (val <= 11)
  165. bits++;
  166. reg = readl(&ctl->addrmap6);
  167. /* addrmap6.addrmap_row_b12 */
  168. val = (reg & GENMASK(3, 0)) >> 0;
  169. if (val <= 7)
  170. bits++;
  171. /* addrmap6.addrmap_row_b13 */
  172. val = (reg & GENMASK(11, 8)) >> 8;
  173. if (val <= 7)
  174. bits++;
  175. /* addrmap6.addrmap_row_b14 */
  176. val = (reg & GENMASK(19, 16)) >> 16;
  177. if (val <= 7)
  178. bits++;
  179. /* addrmap6.addrmap_row_b15 */
  180. val = (reg & GENMASK(27, 24)) >> 24;
  181. if (val <= 7)
  182. bits++;
  183. return bits;
  184. }
  185. static void itm_soft_reset(struct stm32mp1_ddrphy *phy)
  186. {
  187. stm32mp1_ddrphy_init(phy, DDRPHYC_PIR_ITMSRST);
  188. }
  189. /* Read DQ unit delay register and provides the retrieved value for DQS
  190. * We are assuming that we have the same delay when clocking
  191. * by DQS and when clocking by DQSN
  192. */
  193. static u8 DQ_unit_index(struct stm32mp1_ddrphy *phy, u8 byte, u8 bit)
  194. {
  195. u32 index;
  196. u32 addr = DXNDQTR(phy, byte);
  197. /* We are assuming that we have the same delay when clocking by DQS
  198. * and when clocking by DQSN : use only the low bits
  199. */
  200. index = (readl(addr) >> DDRPHYC_DXNDQTR_DQDLY_SHIFT(bit))
  201. & DDRPHYC_DXNDQTR_DQDLY_LOW_MASK;
  202. pr_debug("%s: [%x]: %x => DQ unit index = %x\n",
  203. __func__, addr, readl(addr), index);
  204. return index;
  205. }
  206. /* Sets the DQS phase delay for a byte lane.
  207. *phase delay is specified by giving the index of the desired delay
  208. * in the dx_dll_phase array.
  209. */
  210. static void DQS_phase_delay(struct stm32mp1_ddrphy *phy, u8 byte, u8 phase_idx)
  211. {
  212. u8 sdphase_val = 0;
  213. /* Write DXNDLLCR.SDPHASE = dx_dll_phase(phase_index); */
  214. sdphase_val = dx_dll_phase[phase_idx];
  215. clrsetbits_le32(DXNDLLCR(phy, byte),
  216. DDRPHYC_DXNDLLCR_SDPHASE_MASK,
  217. sdphase_val << DDRPHYC_DXNDLLCR_SDPHASE_SHIFT);
  218. }
  219. /* Sets the DQS unit delay for a byte lane.
  220. * unit delay is specified by giving the index of the desired delay
  221. * for dgsdly and dqsndly (same value).
  222. */
  223. static void DQS_unit_delay(struct stm32mp1_ddrphy *phy,
  224. u8 byte, u8 unit_dly_idx)
  225. {
  226. /* Write the same value in DXNDQSTR.DQSDLY and DXNDQSTR.DQSNDLY */
  227. clrsetbits_le32(DXNDQSTR(phy, byte),
  228. DDRPHYC_DXNDQSTR_DQSDLY_MASK |
  229. DDRPHYC_DXNDQSTR_DQSNDLY_MASK,
  230. (unit_dly_idx << DDRPHYC_DXNDQSTR_DQSDLY_SHIFT) |
  231. (unit_dly_idx << DDRPHYC_DXNDQSTR_DQSNDLY_SHIFT));
  232. /* After changing this value, an ITM soft reset (PIR.ITMSRST=1,
  233. * plus PIR.INIT=1) must be issued.
  234. */
  235. stm32mp1_ddrphy_init(phy, DDRPHYC_PIR_ITMSRST);
  236. }
  237. /* Sets the DQ unit delay for a bit line in particular byte lane.
  238. * unit delay is specified by giving the desired delay
  239. */
  240. static void set_DQ_unit_delay(struct stm32mp1_ddrphy *phy,
  241. u8 byte, u8 bit,
  242. u8 dq_delay_index)
  243. {
  244. u8 dq_bit_delay_val = dq_delay_index | (dq_delay_index << 2);
  245. /* same value on delay for clock DQ an DQS_b */
  246. clrsetbits_le32(DXNDQTR(phy, byte),
  247. DDRPHYC_DXNDQTR_DQDLY_MASK
  248. << DDRPHYC_DXNDQTR_DQDLY_SHIFT(bit),
  249. dq_bit_delay_val << DDRPHYC_DXNDQTR_DQDLY_SHIFT(bit));
  250. }
  251. static void set_r0dgsl_delay(struct stm32mp1_ddrphy *phy,
  252. u8 byte, u8 r0dgsl_idx)
  253. {
  254. clrsetbits_le32(DXNDQSTR(phy, byte),
  255. DDRPHYC_DXNDQSTR_R0DGSL_MASK,
  256. r0dgsl_idx << DDRPHYC_DXNDQSTR_R0DGSL_SHIFT);
  257. }
  258. static void set_r0dgps_delay(struct stm32mp1_ddrphy *phy,
  259. u8 byte, u8 r0dgps_idx)
  260. {
  261. clrsetbits_le32(DXNDQSTR(phy, byte),
  262. DDRPHYC_DXNDQSTR_R0DGPS_MASK,
  263. r0dgps_idx << DDRPHYC_DXNDQSTR_R0DGPS_SHIFT);
  264. }
  265. /* Basic BIST configuration for data lane tests. */
  266. static void config_BIST(struct stm32mp1_ddrctl *ctl,
  267. struct stm32mp1_ddrphy *phy)
  268. {
  269. u8 nb_bank = get_nb_bank(ctl);
  270. u8 nb_row = get_nb_row(ctl);
  271. u8 nb_col = get_nb_col(ctl);
  272. /* Selects the SDRAM bank address to be used during BIST. */
  273. u32 bbank = 0;
  274. /* Selects the SDRAM row address to be used during BIST. */
  275. u32 brow = 0;
  276. /* Selects the SDRAM column address to be used during BIST. */
  277. u32 bcol = 0;
  278. /* Selects the value by which the SDRAM address is incremented
  279. * for each write/read access.
  280. */
  281. u32 bainc = 0x00000008;
  282. /* Specifies the maximum SDRAM rank to be used during BIST.
  283. * The default value is set to maximum ranks minus 1.
  284. * must be 0 with single rank
  285. */
  286. u32 bmrank = 0;
  287. /* Selects the SDRAM rank to be used during BIST.
  288. * must be 0 with single rank
  289. */
  290. u32 brank = 0;
  291. /* Specifies the maximum SDRAM bank address to be used during
  292. * BIST before the address & increments to the next rank.
  293. */
  294. u32 bmbank = (1 << nb_bank) - 1;
  295. /* Specifies the maximum SDRAM row address to be used during
  296. * BIST before the address & increments to the next bank.
  297. */
  298. u32 bmrow = (1 << nb_row) - 1;
  299. /* Specifies the maximum SDRAM column address to be used during
  300. * BIST before the address & increments to the next row.
  301. */
  302. u32 bmcol = (1 << nb_col) - 1;
  303. u32 bmode_conf = 0x00000001; /* DRam mode */
  304. u32 bdxen_conf = 0x00000001; /* BIST on Data byte */
  305. u32 bdpat_conf = 0x00000002; /* Select LFSR pattern */
  306. /*Setup BIST for DRAM mode, and LFSR-random data pattern.*/
  307. /*Write BISTRR.BMODE = 1?b1;*/
  308. /*Write BISTRR.BDXEN = 1?b1;*/
  309. /*Write BISTRR.BDPAT = 2?b10;*/
  310. /* reset BIST */
  311. writel(0x3, &phy->bistrr);
  312. writel((bmode_conf << 3) | (bdxen_conf << 14) | (bdpat_conf << 17),
  313. &phy->bistrr);
  314. /*Setup BIST Word Count*/
  315. /*Write BISTWCR.BWCNT = 16?b0008;*/
  316. writel(0x00000200, &phy->bistwcr); /* A multiple of BL/2 */
  317. writel(bcol | (brow << 12) | (bbank << 28), &phy->bistar0);
  318. writel(brank | (bmrank << 2) | (bainc << 4), &phy->bistar1);
  319. writel(bmcol | (bmrow << 12) | (bmbank << 28), &phy->bistar2);
  320. }
  321. /* Select the Byte lane to be tested by BIST. */
  322. static void BIST_datx8_sel(struct stm32mp1_ddrphy *phy, u8 datx8)
  323. {
  324. clrsetbits_le32(&phy->bistrr,
  325. DDRPHYC_BISTRR_BDXSEL_MASK,
  326. datx8 << DDRPHYC_BISTRR_BDXSEL_SHIFT);
  327. /*(For example, selecting Byte Lane 3, BISTRR.BDXSEL = 4?b0011)*/
  328. /* Write BISTRR.BDXSEL = datx8; */
  329. }
  330. /* Perform BIST Write_Read test on a byte lane and return test result. */
  331. static void BIST_test(struct stm32mp1_ddrphy *phy, u8 byte,
  332. struct BIST_result *bist)
  333. {
  334. bool result = true; /* BIST_SUCCESS */
  335. u32 cnt = 0;
  336. u32 error = 0;
  337. u32 val;
  338. int ret;
  339. bist->test_result = true;
  340. run:
  341. itm_soft_reset(phy);
  342. /*Perform BIST Reset*/
  343. /* Write BISTRR.BINST = 3?b011; */
  344. clrsetbits_le32(&phy->bistrr,
  345. 0x00000007,
  346. 0x00000003);
  347. /*Re-seed LFSR*/
  348. /* Write BISTLSR.SEED = 32'h1234ABCD; */
  349. if (BIST_seed)
  350. writel(BIST_seed, &phy->bistlsr);
  351. else
  352. writel(rand(), &phy->bistlsr);
  353. /* some delay to reset BIST */
  354. udelay(10);
  355. /*Perform BIST Run*/
  356. clrsetbits_le32(&phy->bistrr,
  357. 0x00000007,
  358. 0x00000001);
  359. /* Write BISTRR.BINST = 3?b001; */
  360. /* poll on BISTGSR.BDONE and wait max 1000 us */
  361. ret = readl_poll_timeout(&phy->bistgsr, val,
  362. val & DDRPHYC_BISTGSR_BDDONE, 1000);
  363. if (ret < 0) {
  364. printf("warning: BIST timeout\n");
  365. result = false; /* BIST_FAIL; */
  366. /*Perform BIST Stop */
  367. clrsetbits_le32(&phy->bistrr, 0x00000007, 0x00000002);
  368. } else {
  369. /*Check if received correct number of words*/
  370. /* if (Read BISTWCSR.DXWCNT = Read BISTWCR.BWCNT) */
  371. if (((readl(&phy->bistwcsr)) >> DDRPHYC_BISTWCSR_DXWCNT_SHIFT)
  372. == readl(&phy->bistwcr)) {
  373. /*Determine if there is a data comparison error*/
  374. /* if (Read BISTGSR.BDXERR = 1?b0) */
  375. if (readl(&phy->bistgsr) & DDRPHYC_BISTGSR_BDXERR)
  376. result = false; /* BIST_FAIL; */
  377. else
  378. result = true; /* BIST_SUCCESS; */
  379. } else {
  380. result = false; /* BIST_FAIL; */
  381. }
  382. }
  383. /* loop while success */
  384. cnt++;
  385. if (result && cnt != 1000)
  386. goto run;
  387. if (!result)
  388. error++;
  389. if (error < BIST_error_max) {
  390. if (cnt != 1000)
  391. goto run;
  392. bist->test_result = true;
  393. } else {
  394. bist->test_result = false;
  395. }
  396. }
  397. /* After running the deskew algo, this function applies the new DQ delays
  398. * by reading them from the array "deskew_delay"and writing in PHY registers.
  399. * The bits that are not deskewed parfectly (too much skew on them,
  400. * or data eye very wide) are marked in the array deskew_non_converge.
  401. */
  402. static void apply_deskew_results(struct stm32mp1_ddrphy *phy, u8 byte,
  403. u8 deskew_delay[NUM_BYTES][8],
  404. u8 deskew_non_converge[NUM_BYTES][8])
  405. {
  406. u8 bit_i;
  407. u8 index;
  408. for (bit_i = 0; bit_i < 8; bit_i++) {
  409. set_DQ_unit_delay(phy, byte, bit_i, deskew_delay[byte][bit_i]);
  410. index = DQ_unit_index(phy, byte, bit_i);
  411. pr_debug("Byte %d ; bit %d : The new DQ delay (%d) index=%d [delta=%d, 3 is the default]",
  412. byte, bit_i, deskew_delay[byte][bit_i],
  413. index, index - 3);
  414. printf("Byte %d, bit %d, DQ delay = %d",
  415. byte, bit_i, deskew_delay[byte][bit_i]);
  416. if (deskew_non_converge[byte][bit_i] == 1)
  417. pr_debug(" - not converged : still more skew");
  418. printf("\n");
  419. }
  420. }
  421. /* DQ Bit de-skew algorithm.
  422. * Deskews data lines as much as possible.
  423. * 1. Add delay to DQS line until finding the failure
  424. * (normally a hold time violation)
  425. * 2. Reduce DQS line by small steps until finding the very first time
  426. * we go back to "Pass" condition.
  427. * 3. For each DQ line, Reduce DQ delay until finding the very first failure
  428. * (normally a hold time fail)
  429. * 4. When all bits are at their first failure delay, we can consider them
  430. * aligned.
  431. * Handle conrer situation (Can't find Pass-fail, or fail-pass transitions
  432. * at any step)
  433. * TODO Provide a return Status. Improve doc
  434. */
  435. static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
  436. struct stm32mp1_ddrphy *phy, char *string)
  437. {
  438. /* New DQ delay value (index), set during Deskew algo */
  439. u8 deskew_delay[NUM_BYTES][8];
  440. /*If there is still skew on a bit, mark this bit. */
  441. u8 deskew_non_converge[NUM_BYTES][8];
  442. struct BIST_result result;
  443. s8 dqs_unit_delay_index = 0;
  444. u8 datx8 = 0;
  445. u8 bit_i = 0;
  446. s8 phase_idx = 0;
  447. s8 bit_i_delay_index = 0;
  448. u8 success = 0;
  449. struct tuning_position last_right_ok;
  450. u8 force_stop = 0;
  451. u8 fail_found;
  452. u8 error = 0;
  453. u8 nb_bytes = get_nb_bytes(ctl);
  454. /* u8 last_pass_dqs_unit = 0; */
  455. memset(deskew_delay, 0, sizeof(deskew_delay));
  456. memset(deskew_non_converge, 0, sizeof(deskew_non_converge));
  457. /*Disable DQS Drift Compensation*/
  458. clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_DFTCMP);
  459. /*Disable all bytes*/
  460. /* Disable automatic power down of DLL and IOs when disabling
  461. * a byte (To avoid having to add programming and delay
  462. * for a DLL re-lock when later re-enabling a disabled Byte Lane)
  463. */
  464. clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_PDDISDX);
  465. /* Disable all data bytes */
  466. clrbits_le32(&phy->dx0gcr, DDRPHYC_DXNGCR_DXEN);
  467. clrbits_le32(&phy->dx1gcr, DDRPHYC_DXNGCR_DXEN);
  468. clrbits_le32(&phy->dx2gcr, DDRPHYC_DXNGCR_DXEN);
  469. clrbits_le32(&phy->dx3gcr, DDRPHYC_DXNGCR_DXEN);
  470. /* Config the BIST block */
  471. config_BIST(ctl, phy);
  472. pr_debug("BIST Config done.\n");
  473. /* Train each byte */
  474. for (datx8 = 0; datx8 < nb_bytes; datx8++) {
  475. if (ctrlc()) {
  476. sprintf(string, "interrupted at byte %d/%d, error=%d",
  477. datx8 + 1, nb_bytes, error);
  478. return TEST_FAILED;
  479. }
  480. pr_debug("\n======================\n");
  481. pr_debug("Start deskew byte %d .\n", datx8);
  482. pr_debug("======================\n");
  483. /* Enable Byte (DXNGCR, bit DXEN) */
  484. setbits_le32(DXNGCR(phy, datx8), DDRPHYC_DXNGCR_DXEN);
  485. /* Select the byte lane for comparison of read data */
  486. BIST_datx8_sel(phy, datx8);
  487. /* Set all DQDLYn to maximum value. All bits within the byte
  488. * will be delayed with DQSTR = 2 instead of max = 3
  489. * to avoid inter bits fail influence
  490. */
  491. writel(0xAAAAAAAA, DXNDQTR(phy, datx8));
  492. /* Set the DQS phase delay to 90 DEG (default).
  493. * What is defined here is the index of the desired config
  494. * in the PHASE array.
  495. */
  496. phase_idx = _90deg;
  497. /* Set DQS unit delay to the max value. */
  498. dqs_unit_delay_index = MAX_DQS_UNIT_IDX;
  499. DQS_unit_delay(phy, datx8, dqs_unit_delay_index);
  500. DQS_phase_delay(phy, datx8, phase_idx);
  501. /* Issue a DLL soft reset */
  502. clrbits_le32(DXNDLLCR(phy, datx8), DDRPHYC_DXNDLLCR_DLLSRST);
  503. setbits_le32(DXNDLLCR(phy, datx8), DDRPHYC_DXNDLLCR_DLLSRST);
  504. /* Test this typical init condition */
  505. BIST_test(phy, datx8, &result);
  506. success = result.test_result;
  507. /* If the test pass in this typical condition,
  508. * start the algo with it.
  509. * Else, look for Pass init condition
  510. */
  511. if (!success) {
  512. pr_debug("Fail at init condtion. Let's look for a good init condition.\n");
  513. success = 0; /* init */
  514. /* Make sure we start with a PASS condition before
  515. * looking for a fail condition.
  516. * Find the first PASS PHASE condition
  517. */
  518. /* escape if we find a PASS */
  519. pr_debug("increase Phase idx\n");
  520. while (!success && (phase_idx <= MAX_DQS_PHASE_IDX)) {
  521. DQS_phase_delay(phy, datx8, phase_idx);
  522. BIST_test(phy, datx8, &result);
  523. success = result.test_result;
  524. phase_idx++;
  525. }
  526. /* if ended with success
  527. * ==>> Restore the fist success condition
  528. */
  529. if (success)
  530. phase_idx--; /* because it ended with ++ */
  531. }
  532. if (ctrlc()) {
  533. sprintf(string, "interrupted at byte %d/%d, error=%d",
  534. datx8 + 1, nb_bytes, error);
  535. return TEST_FAILED;
  536. }
  537. /* We couldn't find a successful condition, its seems
  538. * we have hold violation, lets try reduce DQS_unit Delay
  539. */
  540. if (!success) {
  541. /* We couldn't find a successful condition, its seems
  542. * we have hold violation, lets try reduce DQS_unit
  543. * Delay
  544. */
  545. pr_debug("Still fail. Try decrease DQS Unit delay\n");
  546. phase_idx = 0;
  547. dqs_unit_delay_index = 0;
  548. DQS_phase_delay(phy, datx8, phase_idx);
  549. /* escape if we find a PASS */
  550. while (!success &&
  551. (dqs_unit_delay_index <=
  552. MAX_DQS_UNIT_IDX)) {
  553. DQS_unit_delay(phy, datx8,
  554. dqs_unit_delay_index);
  555. BIST_test(phy, datx8, &result);
  556. success = result.test_result;
  557. dqs_unit_delay_index++;
  558. }
  559. if (success) {
  560. /* Restore the first success condition*/
  561. dqs_unit_delay_index--;
  562. /* last_pass_dqs_unit = dqs_unit_delay_index;*/
  563. DQS_unit_delay(phy, datx8,
  564. dqs_unit_delay_index);
  565. } else {
  566. /* No need to continue,
  567. * there is no pass region.
  568. */
  569. force_stop = 1;
  570. }
  571. }
  572. /* There is an initial PASS condition
  573. * Look for the first failing condition by PHASE stepping.
  574. * This part of the algo can finish without converging.
  575. */
  576. if (force_stop) {
  577. printf("Result: Failed ");
  578. printf("[Cannot Deskew lines, ");
  579. printf("there is no PASS region]\n");
  580. error++;
  581. continue;
  582. }
  583. if (ctrlc()) {
  584. sprintf(string, "interrupted at byte %d/%d, error=%d",
  585. datx8 + 1, nb_bytes, error);
  586. return TEST_FAILED;
  587. }
  588. pr_debug("there is a pass region for phase idx %d\n",
  589. phase_idx);
  590. pr_debug("Step1: Find the first failing condition\n");
  591. /* Look for the first failing condition by PHASE stepping.
  592. * This part of the algo can finish without converging.
  593. */
  594. /* escape if we find a fail (hold time violation)
  595. * condition at any bit or if out of delay range.
  596. */
  597. while (success && (phase_idx <= MAX_DQS_PHASE_IDX)) {
  598. DQS_phase_delay(phy, datx8, phase_idx);
  599. BIST_test(phy, datx8, &result);
  600. success = result.test_result;
  601. phase_idx++;
  602. }
  603. if (ctrlc()) {
  604. sprintf(string, "interrupted at byte %d/%d, error=%d",
  605. datx8 + 1, nb_bytes, error);
  606. return TEST_FAILED;
  607. }
  608. /* if the loop ended with a failing condition at any bit,
  609. * lets look for the first previous success condition by unit
  610. * stepping (minimal delay)
  611. */
  612. if (!success) {
  613. pr_debug("Fail region (PHASE) found phase idx %d\n",
  614. phase_idx);
  615. pr_debug("Let's look for first success by DQS Unit steps\n");
  616. /* This part, the algo always converge */
  617. phase_idx--;
  618. /* escape if we find a success condition
  619. * or if out of delay range.
  620. */
  621. while (!success && dqs_unit_delay_index >= 0) {
  622. DQS_unit_delay(phy, datx8,
  623. dqs_unit_delay_index);
  624. BIST_test(phy, datx8, &result);
  625. success = result.test_result;
  626. dqs_unit_delay_index--;
  627. }
  628. /* if the loop ended with a success condition,
  629. * the last delay Right OK (before hold violation)
  630. * condition is then defined as following:
  631. */
  632. if (success) {
  633. /* Hold the dely parameters of the the last
  634. * delay Right OK condition.
  635. * -1 to get back to current condition
  636. */
  637. last_right_ok.phase = phase_idx;
  638. /*+1 to get back to current condition */
  639. last_right_ok.unit = dqs_unit_delay_index + 1;
  640. last_right_ok.bits_delay = 0xFFFFFFFF;
  641. pr_debug("Found %d\n", dqs_unit_delay_index);
  642. } else {
  643. /* the last OK condition is then with the
  644. * previous phase_idx.
  645. * -2 instead of -1 because at the last
  646. * iteration of the while(),
  647. * we incremented phase_idx
  648. */
  649. last_right_ok.phase = phase_idx - 1;
  650. /* Nominal+1. Because we want the previous
  651. * delay after reducing the phase delay.
  652. */
  653. last_right_ok.unit = 1;
  654. last_right_ok.bits_delay = 0xFFFFFFFF;
  655. pr_debug("Not Found : try previous phase %d\n",
  656. phase_idx - 1);
  657. DQS_phase_delay(phy, datx8, phase_idx - 1);
  658. dqs_unit_delay_index = 0;
  659. success = true;
  660. while (success &&
  661. (dqs_unit_delay_index <
  662. MAX_DQS_UNIT_IDX)) {
  663. DQS_unit_delay(phy, datx8,
  664. dqs_unit_delay_index);
  665. BIST_test(phy, datx8, &result);
  666. success = result.test_result;
  667. dqs_unit_delay_index++;
  668. pr_debug("dqs_unit_delay_index = %d, result = %d\n",
  669. dqs_unit_delay_index, success);
  670. }
  671. if (!success) {
  672. last_right_ok.unit =
  673. dqs_unit_delay_index - 1;
  674. } else {
  675. last_right_ok.unit = 0;
  676. pr_debug("ERROR: failed region not FOUND");
  677. }
  678. }
  679. } else {
  680. /* we can't find a failing condition at all bits
  681. * ==> Just hold the last test condition
  682. * (the max DQS delay)
  683. * which is the most likely,
  684. * the closest to a hold violation
  685. * If we can't find a Fail condition after
  686. * the Pass region, stick at this position
  687. * In order to have max chances to find a fail
  688. * when reducing DQ delays.
  689. */
  690. last_right_ok.phase = MAX_DQS_PHASE_IDX;
  691. last_right_ok.unit = MAX_DQS_UNIT_IDX;
  692. last_right_ok.bits_delay = 0xFFFFFFFF;
  693. pr_debug("Can't find the a fail condition\n");
  694. }
  695. /* step 2:
  696. * if we arrive at this stage, it means that we found the last
  697. * Right OK condition (by tweeking the DQS delay). Or we simply
  698. * pushed DQS delay to the max
  699. * This means that by reducing the delay on some DQ bits,
  700. * we should find a failing condition.
  701. */
  702. printf("Byte %d, DQS unit = %d, phase = %d\n",
  703. datx8, last_right_ok.unit, last_right_ok.phase);
  704. pr_debug("Step2, unit = %d, phase = %d, bits delay=%x\n",
  705. last_right_ok.unit, last_right_ok.phase,
  706. last_right_ok.bits_delay);
  707. /* Restore the last_right_ok condtion. */
  708. DQS_unit_delay(phy, datx8, last_right_ok.unit);
  709. DQS_phase_delay(phy, datx8, last_right_ok.phase);
  710. writel(last_right_ok.bits_delay, DXNDQTR(phy, datx8));
  711. /* train each bit
  712. * reduce delay on each bit, and perform a write/read test
  713. * and stop at the very first time it fails.
  714. * the goal is the find the first failing condition
  715. * for each bit.
  716. * When we achieve this condition< for all the bits,
  717. * we are sure they are aligned (+/- step resolution)
  718. */
  719. fail_found = 0;
  720. for (bit_i = 0; bit_i < 8; bit_i++) {
  721. if (ctrlc()) {
  722. sprintf(string,
  723. "interrupted at byte %d/%d, error=%d",
  724. datx8 + 1, nb_bytes, error);
  725. return error;
  726. }
  727. pr_debug("deskewing bit %d:\n", bit_i);
  728. success = 1; /* init */
  729. /* Set all DQDLYn to maximum value.
  730. * Only bit_i will be down-delayed
  731. * ==> if we have a fail, it will be definitely
  732. * from bit_i
  733. */
  734. writel(0xFFFFFFFF, DXNDQTR(phy, datx8));
  735. /* Arriving at this stage,
  736. * we have a success condition with delay = 3;
  737. */
  738. bit_i_delay_index = 3;
  739. /* escape if bit delay is out of range or
  740. * if a fatil occurs
  741. */
  742. while ((bit_i_delay_index >= 0) && success) {
  743. set_DQ_unit_delay(phy, datx8,
  744. bit_i,
  745. bit_i_delay_index);
  746. BIST_test(phy, datx8, &result);
  747. success = result.test_result;
  748. bit_i_delay_index--;
  749. }
  750. /* if escape with a fail condition
  751. * ==> save this position for bit_i
  752. */
  753. if (!success) {
  754. /* save the delay position.
  755. * Add 1 because the while loop ended with a --,
  756. * and that we need to hold the last success
  757. * delay
  758. */
  759. deskew_delay[datx8][bit_i] =
  760. bit_i_delay_index + 2;
  761. if (deskew_delay[datx8][bit_i] > 3)
  762. deskew_delay[datx8][bit_i] = 3;
  763. /* A flag that states we found at least a fail
  764. * at one bit.
  765. */
  766. fail_found = 1;
  767. pr_debug("Fail found on bit %d, for delay = %d => deskew[%d][%d] = %d\n",
  768. bit_i, bit_i_delay_index + 1,
  769. datx8, bit_i,
  770. deskew_delay[datx8][bit_i]);
  771. } else {
  772. /* if we can find a success condition by
  773. * back-delaying this bit, just set the delay
  774. * to 0 (the best deskew
  775. * possible) and mark the bit.
  776. */
  777. deskew_delay[datx8][bit_i] = 0;
  778. /* set a flag that will be used later
  779. * in the report.
  780. */
  781. deskew_non_converge[datx8][bit_i] = 1;
  782. pr_debug("Fail not found on bit %d => deskew[%d][%d] = %d\n",
  783. bit_i, datx8, bit_i,
  784. deskew_delay[datx8][bit_i]);
  785. }
  786. }
  787. pr_debug("**********byte %d tuning complete************\n",
  788. datx8);
  789. /* If we can't find any failure by back delaying DQ lines,
  790. * hold the default values
  791. */
  792. if (!fail_found) {
  793. for (bit_i = 0; bit_i < 8; bit_i++)
  794. deskew_delay[datx8][bit_i] = 0;
  795. pr_debug("The Deskew algorithm can't converge, there is too much margin in your design. Good job!\n");
  796. }
  797. apply_deskew_results(phy, datx8, deskew_delay,
  798. deskew_non_converge);
  799. /* Restore nominal value for DQS delay */
  800. DQS_phase_delay(phy, datx8, 3);
  801. DQS_unit_delay(phy, datx8, 3);
  802. /* disable byte after byte bits deskew */
  803. clrbits_le32(DXNGCR(phy, datx8), DDRPHYC_DXNGCR_DXEN);
  804. } /* end of byte deskew */
  805. /* re-enable all data bytes */
  806. setbits_le32(&phy->dx0gcr, DDRPHYC_DXNGCR_DXEN);
  807. setbits_le32(&phy->dx1gcr, DDRPHYC_DXNGCR_DXEN);
  808. setbits_le32(&phy->dx2gcr, DDRPHYC_DXNGCR_DXEN);
  809. setbits_le32(&phy->dx3gcr, DDRPHYC_DXNGCR_DXEN);
  810. if (error) {
  811. sprintf(string, "error = %d", error);
  812. return TEST_FAILED;
  813. }
  814. return TEST_PASSED;
  815. } /* end function */
  816. /* Trim DQS timings and set it in the centre of data eye.
  817. * Look for a PPPPF region, then look for a FPPP region and finally select
  818. * the mid of the FPPPPPF region
  819. */
  820. static enum test_result eye_training(struct stm32mp1_ddrctl *ctl,
  821. struct stm32mp1_ddrphy *phy, char *string)
  822. {
  823. /*Stores the DQS trim values (PHASE index, unit index) */
  824. u8 eye_training_val[NUM_BYTES][2];
  825. u8 byte = 0;
  826. struct BIST_result result;
  827. s8 dqs_unit_delay_index = 0;
  828. s8 phase_idx = 0;
  829. s8 dqs_unit_delay_index_pass = 0;
  830. s8 phase_idx_pass = 0;
  831. u8 success = 0;
  832. u8 left_phase_bound_found, right_phase_bound_found;
  833. u8 left_unit_bound_found, right_unit_bound_found;
  834. u8 left_bound_found, right_bound_found;
  835. struct tuning_position left_bound, right_bound;
  836. u8 error = 0;
  837. u8 nb_bytes = get_nb_bytes(ctl);
  838. /*Disable DQS Drift Compensation*/
  839. clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_DFTCMP);
  840. /*Disable all bytes*/
  841. /* Disable automatic power down of DLL and IOs when disabling a byte
  842. * (To avoid having to add programming and delay
  843. * for a DLL re-lock when later re-enabling a disabled Byte Lane)
  844. */
  845. clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_PDDISDX);
  846. /*Disable all data bytes */
  847. clrbits_le32(&phy->dx0gcr, DDRPHYC_DXNGCR_DXEN);
  848. clrbits_le32(&phy->dx1gcr, DDRPHYC_DXNGCR_DXEN);
  849. clrbits_le32(&phy->dx2gcr, DDRPHYC_DXNGCR_DXEN);
  850. clrbits_le32(&phy->dx3gcr, DDRPHYC_DXNGCR_DXEN);
  851. /* Config the BIST block */
  852. config_BIST(ctl, phy);
  853. for (byte = 0; byte < nb_bytes; byte++) {
  854. if (ctrlc()) {
  855. sprintf(string, "interrupted at byte %d/%d, error=%d",
  856. byte + 1, nb_bytes, error);
  857. return TEST_FAILED;
  858. }
  859. right_bound.phase = 0;
  860. right_bound.unit = 0;
  861. left_bound.phase = 0;
  862. left_bound.unit = 0;
  863. left_phase_bound_found = 0;
  864. right_phase_bound_found = 0;
  865. left_unit_bound_found = 0;
  866. right_unit_bound_found = 0;
  867. left_bound_found = 0;
  868. right_bound_found = 0;
  869. /* Enable Byte (DXNGCR, bit DXEN) */
  870. setbits_le32(DXNGCR(phy, byte), DDRPHYC_DXNGCR_DXEN);
  871. /* Select the byte lane for comparison of read data */
  872. BIST_datx8_sel(phy, byte);
  873. /* Set DQS phase delay to the nominal value. */
  874. phase_idx = _90deg;
  875. phase_idx_pass = phase_idx;
  876. /* Set DQS unit delay to the nominal value. */
  877. dqs_unit_delay_index = 3;
  878. dqs_unit_delay_index_pass = dqs_unit_delay_index;
  879. success = 0;
  880. pr_debug("STEP0: Find Init delay\n");
  881. /* STEP0: Find Init delay: a delay that put the system
  882. * in a "Pass" condition then (TODO) update
  883. * dqs_unit_delay_index_pass & phase_idx_pass
  884. */
  885. DQS_unit_delay(phy, byte, dqs_unit_delay_index);
  886. DQS_phase_delay(phy, byte, phase_idx);
  887. BIST_test(phy, byte, &result);
  888. success = result.test_result;
  889. /* If we have a fail in the nominal condition */
  890. if (!success) {
  891. /* Look at the left */
  892. while (phase_idx >= 0 && !success) {
  893. phase_idx--;
  894. DQS_phase_delay(phy, byte, phase_idx);
  895. BIST_test(phy, byte, &result);
  896. success = result.test_result;
  897. }
  898. }
  899. if (!success) {
  900. /* if we can't find pass condition,
  901. * then look at the right
  902. */
  903. phase_idx = _90deg;
  904. while (phase_idx <= MAX_DQS_PHASE_IDX &&
  905. !success) {
  906. phase_idx++;
  907. DQS_phase_delay(phy, byte,
  908. phase_idx);
  909. BIST_test(phy, byte, &result);
  910. success = result.test_result;
  911. }
  912. }
  913. /* save the pass condition */
  914. if (success) {
  915. phase_idx_pass = phase_idx;
  916. } else {
  917. printf("Result: Failed ");
  918. printf("[Cannot DQS timings, ");
  919. printf("there is no PASS region]\n");
  920. error++;
  921. continue;
  922. }
  923. if (ctrlc()) {
  924. sprintf(string, "interrupted at byte %d/%d, error=%d",
  925. byte + 1, nb_bytes, error);
  926. return TEST_FAILED;
  927. }
  928. pr_debug("STEP1: Find LEFT PHASE DQS Bound\n");
  929. /* STEP1: Find LEFT PHASE DQS Bound */
  930. while ((phase_idx >= 0) &&
  931. (phase_idx <= MAX_DQS_PHASE_IDX) &&
  932. !left_phase_bound_found) {
  933. DQS_unit_delay(phy, byte,
  934. dqs_unit_delay_index);
  935. DQS_phase_delay(phy, byte,
  936. phase_idx);
  937. BIST_test(phy, byte, &result);
  938. success = result.test_result;
  939. /*TODO: Manage the case were at the beginning
  940. * there is already a fail
  941. */
  942. if (!success) {
  943. /* the last pass condition */
  944. left_bound.phase = ++phase_idx;
  945. left_phase_bound_found = 1;
  946. } else if (success) {
  947. phase_idx--;
  948. }
  949. }
  950. if (!left_phase_bound_found) {
  951. left_bound.phase = 0;
  952. phase_idx = 0;
  953. }
  954. /* If not found, lets take 0 */
  955. if (ctrlc()) {
  956. sprintf(string, "interrupted at byte %d/%d, error=%d",
  957. byte + 1, nb_bytes, error);
  958. return TEST_FAILED;
  959. }
  960. pr_debug("STEP2: Find UNIT left bound\n");
  961. /* STEP2: Find UNIT left bound */
  962. while ((dqs_unit_delay_index >= 0) &&
  963. !left_unit_bound_found) {
  964. DQS_unit_delay(phy, byte,
  965. dqs_unit_delay_index);
  966. DQS_phase_delay(phy, byte, phase_idx);
  967. BIST_test(phy, byte, &result);
  968. success = result.test_result;
  969. if (!success) {
  970. left_bound.unit =
  971. ++dqs_unit_delay_index;
  972. left_unit_bound_found = 1;
  973. left_bound_found = 1;
  974. } else if (success) {
  975. dqs_unit_delay_index--;
  976. }
  977. }
  978. /* If not found, lets take 0 */
  979. if (!left_unit_bound_found)
  980. left_bound.unit = 0;
  981. if (ctrlc()) {
  982. sprintf(string, "interrupted at byte %d/%d, error=%d",
  983. byte + 1, nb_bytes, error);
  984. return TEST_FAILED;
  985. }
  986. pr_debug("STEP3: Find PHase right bound\n");
  987. /* STEP3: Find PHase right bound, start with "pass"
  988. * condition
  989. */
  990. /* Set DQS phase delay to the pass value. */
  991. phase_idx = phase_idx_pass;
  992. /* Set DQS unit delay to the pass value. */
  993. dqs_unit_delay_index = dqs_unit_delay_index_pass;
  994. while ((phase_idx <= MAX_DQS_PHASE_IDX) &&
  995. !right_phase_bound_found) {
  996. DQS_unit_delay(phy, byte,
  997. dqs_unit_delay_index);
  998. DQS_phase_delay(phy, byte, phase_idx);
  999. BIST_test(phy, byte, &result);
  1000. success = result.test_result;
  1001. if (!success) {
  1002. /* the last pass condition */
  1003. right_bound.phase = --phase_idx;
  1004. right_phase_bound_found = 1;
  1005. } else if (success) {
  1006. phase_idx++;
  1007. }
  1008. }
  1009. /* If not found, lets take the max value */
  1010. if (!right_phase_bound_found) {
  1011. right_bound.phase = MAX_DQS_PHASE_IDX;
  1012. phase_idx = MAX_DQS_PHASE_IDX;
  1013. }
  1014. if (ctrlc()) {
  1015. sprintf(string, "interrupted at byte %d/%d, error=%d",
  1016. byte + 1, nb_bytes, error);
  1017. return TEST_FAILED;
  1018. }
  1019. pr_debug("STEP4: Find UNIT right bound\n");
  1020. /* STEP4: Find UNIT right bound */
  1021. while ((dqs_unit_delay_index <= MAX_DQS_UNIT_IDX) &&
  1022. !right_unit_bound_found) {
  1023. DQS_unit_delay(phy, byte,
  1024. dqs_unit_delay_index);
  1025. DQS_phase_delay(phy, byte, phase_idx);
  1026. BIST_test(phy, byte, &result);
  1027. success = result.test_result;
  1028. if (!success) {
  1029. right_bound.unit =
  1030. --dqs_unit_delay_index;
  1031. right_unit_bound_found = 1;
  1032. right_bound_found = 1;
  1033. } else if (success) {
  1034. dqs_unit_delay_index++;
  1035. }
  1036. }
  1037. /* If not found, lets take the max value */
  1038. if (!right_unit_bound_found)
  1039. right_bound.unit = MAX_DQS_UNIT_IDX;
  1040. /* If we found a regular FAil Pass FAil pattern
  1041. * FFPPPPPPFF
  1042. * OR PPPPPFF Or FFPPPPP
  1043. */
  1044. if (left_bound_found || right_bound_found) {
  1045. eye_training_val[byte][0] = (right_bound.phase +
  1046. left_bound.phase) / 2;
  1047. eye_training_val[byte][1] = (right_bound.unit +
  1048. left_bound.unit) / 2;
  1049. /* If we already lost 1/2PHASE Tuning,
  1050. * let's try to recover by ++ on unit
  1051. */
  1052. if (((right_bound.phase + left_bound.phase) % 2 == 1) &&
  1053. eye_training_val[byte][1] != MAX_DQS_UNIT_IDX)
  1054. eye_training_val[byte][1]++;
  1055. pr_debug("** found phase : %d - %d & unit %d - %d\n",
  1056. right_bound.phase, left_bound.phase,
  1057. right_bound.unit, left_bound.unit);
  1058. pr_debug("** calculating mid region: phase: %d unit: %d (nominal is 3)\n",
  1059. eye_training_val[byte][0],
  1060. eye_training_val[byte][1]);
  1061. } else {
  1062. /* PPPPPPPPPP, we're already good.
  1063. * Set nominal values.
  1064. */
  1065. eye_training_val[byte][0] = 3;
  1066. eye_training_val[byte][1] = 3;
  1067. }
  1068. DQS_phase_delay(phy, byte, eye_training_val[byte][0]);
  1069. DQS_unit_delay(phy, byte, eye_training_val[byte][1]);
  1070. printf("Byte %d, DQS unit = %d, phase = %d\n",
  1071. byte,
  1072. eye_training_val[byte][1],
  1073. eye_training_val[byte][0]);
  1074. }
  1075. if (error) {
  1076. sprintf(string, "error = %d", error);
  1077. return TEST_FAILED;
  1078. }
  1079. return TEST_PASSED;
  1080. }
  1081. static void display_reg_results(struct stm32mp1_ddrphy *phy, u8 byte)
  1082. {
  1083. u8 i = 0;
  1084. printf("Byte %d Dekew result, bit0 delay, bit1 delay...bit8 delay\n ",
  1085. byte);
  1086. for (i = 0; i < 8; i++)
  1087. printf("%d ", DQ_unit_index(phy, byte, i));
  1088. printf("\n");
  1089. printf("dxndllcr: [%08x] val:%08x\n",
  1090. DXNDLLCR(phy, byte),
  1091. readl(DXNDLLCR(phy, byte)));
  1092. printf("dxnqdstr: [%08x] val:%08x\n",
  1093. DXNDQSTR(phy, byte),
  1094. readl(DXNDQSTR(phy, byte)));
  1095. printf("dxndqtr: [%08x] val:%08x\n",
  1096. DXNDQTR(phy, byte),
  1097. readl(DXNDQTR(phy, byte)));
  1098. }
  1099. /* analyse the dgs gating log table, and determine the midpoint.*/
  1100. static u8 set_midpoint_read_dqs_gating(struct stm32mp1_ddrphy *phy, u8 byte,
  1101. u8 dqs_gating[NUM_BYTES]
  1102. [MAX_GSL_IDX + 1]
  1103. [MAX_GPS_IDX + 1])
  1104. {
  1105. /* stores the dqs gate values (gsl index, gps index) */
  1106. u8 dqs_gate_values[NUM_BYTES][2];
  1107. u8 gsl_idx, gps_idx = 0;
  1108. u8 left_bound_idx[2] = {0, 0};
  1109. u8 right_bound_idx[2] = {0, 0};
  1110. u8 left_bound_found = 0;
  1111. u8 right_bound_found = 0;
  1112. u8 intermittent = 0;
  1113. u8 value;
  1114. for (gsl_idx = 0; gsl_idx <= MAX_GSL_IDX; gsl_idx++) {
  1115. for (gps_idx = 0; gps_idx <= MAX_GPS_IDX; gps_idx++) {
  1116. value = dqs_gating[byte][gsl_idx][gps_idx];
  1117. if (value == 1 && left_bound_found == 0) {
  1118. left_bound_idx[0] = gsl_idx;
  1119. left_bound_idx[1] = gps_idx;
  1120. left_bound_found = 1;
  1121. } else if (value == 0 &&
  1122. left_bound_found == 1 &&
  1123. !right_bound_found) {
  1124. if (gps_idx == 0) {
  1125. right_bound_idx[0] = gsl_idx - 1;
  1126. right_bound_idx[1] = MAX_GPS_IDX;
  1127. } else {
  1128. right_bound_idx[0] = gsl_idx;
  1129. right_bound_idx[1] = gps_idx - 1;
  1130. }
  1131. right_bound_found = 1;
  1132. } else if (value == 1 &&
  1133. right_bound_found == 1) {
  1134. intermittent = 1;
  1135. }
  1136. }
  1137. }
  1138. /* if only ppppppp is found, there is no mid region. */
  1139. if (left_bound_idx[0] == 0 && left_bound_idx[1] == 0 &&
  1140. right_bound_idx[0] == 0 && right_bound_idx[1] == 0)
  1141. intermittent = 1;
  1142. /*if we found a regular fail pass fail pattern ffppppppff
  1143. * or pppppff or ffppppp
  1144. */
  1145. if (!intermittent) {
  1146. /*if we found a regular fail pass fail pattern ffppppppff
  1147. * or pppppff or ffppppp
  1148. */
  1149. if (left_bound_found || right_bound_found) {
  1150. pr_debug("idx0(%d): %d %d idx1(%d) : %d %d\n",
  1151. left_bound_found,
  1152. right_bound_idx[0], left_bound_idx[0],
  1153. right_bound_found,
  1154. right_bound_idx[1], left_bound_idx[1]);
  1155. dqs_gate_values[byte][0] =
  1156. (right_bound_idx[0] + left_bound_idx[0]) / 2;
  1157. dqs_gate_values[byte][1] =
  1158. (right_bound_idx[1] + left_bound_idx[1]) / 2;
  1159. /* if we already lost 1/2gsl tuning,
  1160. * let's try to recover by ++ on gps
  1161. */
  1162. if (((right_bound_idx[0] +
  1163. left_bound_idx[0]) % 2 == 1) &&
  1164. dqs_gate_values[byte][1] != MAX_GPS_IDX)
  1165. dqs_gate_values[byte][1]++;
  1166. /* if we already lost 1/2gsl tuning and gps is on max*/
  1167. else if (((right_bound_idx[0] +
  1168. left_bound_idx[0]) % 2 == 1) &&
  1169. dqs_gate_values[byte][1] == MAX_GPS_IDX) {
  1170. dqs_gate_values[byte][1] = 0;
  1171. dqs_gate_values[byte][0]++;
  1172. }
  1173. /* if we have gsl left and write limit too close
  1174. * (difference=1)
  1175. */
  1176. if (((right_bound_idx[0] - left_bound_idx[0]) == 1)) {
  1177. dqs_gate_values[byte][1] = (left_bound_idx[1] +
  1178. right_bound_idx[1] +
  1179. 4) / 2;
  1180. if (dqs_gate_values[byte][1] >= 4) {
  1181. dqs_gate_values[byte][0] =
  1182. right_bound_idx[0];
  1183. dqs_gate_values[byte][1] -= 4;
  1184. } else {
  1185. dqs_gate_values[byte][0] =
  1186. left_bound_idx[0];
  1187. }
  1188. }
  1189. pr_debug("*******calculating mid region: system latency: %d phase: %d********\n",
  1190. dqs_gate_values[byte][0],
  1191. dqs_gate_values[byte][1]);
  1192. pr_debug("*******the nominal values were system latency: 0 phase: 2*******\n");
  1193. }
  1194. } else {
  1195. /* if intermitant, restore defaut values */
  1196. pr_debug("dqs gating:no regular fail/pass/fail found. defaults values restored.\n");
  1197. dqs_gate_values[byte][0] = 0;
  1198. dqs_gate_values[byte][1] = 2;
  1199. }
  1200. set_r0dgsl_delay(phy, byte, dqs_gate_values[byte][0]);
  1201. set_r0dgps_delay(phy, byte, dqs_gate_values[byte][1]);
  1202. printf("Byte %d, R0DGSL = %d, R0DGPS = %d\n",
  1203. byte, dqs_gate_values[byte][0], dqs_gate_values[byte][1]);
  1204. /* return 0 if intermittent or if both left_bound
  1205. * and right_bound are not found
  1206. */
  1207. return !(intermittent || (left_bound_found && right_bound_found));
  1208. }
  1209. static enum test_result read_dqs_gating(struct stm32mp1_ddrctl *ctl,
  1210. struct stm32mp1_ddrphy *phy,
  1211. char *string)
  1212. {
  1213. /* stores the log of pass/fail */
  1214. u8 dqs_gating[NUM_BYTES][MAX_GSL_IDX + 1][MAX_GPS_IDX + 1];
  1215. u8 byte, gsl_idx, gps_idx = 0;
  1216. struct BIST_result result;
  1217. u8 success = 0;
  1218. u8 nb_bytes = get_nb_bytes(ctl);
  1219. memset(dqs_gating, 0x0, sizeof(dqs_gating));
  1220. /*disable dqs drift compensation*/
  1221. clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_DFTCMP);
  1222. /*disable all bytes*/
  1223. /* disable automatic power down of dll and ios when disabling a byte
  1224. * (to avoid having to add programming and delay
  1225. * for a dll re-lock when later re-enabling a disabled byte lane)
  1226. */
  1227. clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_PDDISDX);
  1228. /* disable all data bytes */
  1229. clrbits_le32(&phy->dx0gcr, DDRPHYC_DXNGCR_DXEN);
  1230. clrbits_le32(&phy->dx1gcr, DDRPHYC_DXNGCR_DXEN);
  1231. clrbits_le32(&phy->dx2gcr, DDRPHYC_DXNGCR_DXEN);
  1232. clrbits_le32(&phy->dx3gcr, DDRPHYC_DXNGCR_DXEN);
  1233. /* config the bist block */
  1234. config_BIST(ctl, phy);
  1235. for (byte = 0; byte < nb_bytes; byte++) {
  1236. if (ctrlc()) {
  1237. sprintf(string, "interrupted at byte %d/%d",
  1238. byte + 1, nb_bytes);
  1239. return TEST_FAILED;
  1240. }
  1241. /* enable byte x (dxngcr, bit dxen) */
  1242. setbits_le32(DXNGCR(phy, byte), DDRPHYC_DXNGCR_DXEN);
  1243. /* select the byte lane for comparison of read data */
  1244. BIST_datx8_sel(phy, byte);
  1245. for (gsl_idx = 0; gsl_idx <= MAX_GSL_IDX; gsl_idx++) {
  1246. for (gps_idx = 0; gps_idx <= MAX_GPS_IDX; gps_idx++) {
  1247. if (ctrlc()) {
  1248. sprintf(string,
  1249. "interrupted at byte %d/%d",
  1250. byte + 1, nb_bytes);
  1251. return TEST_FAILED;
  1252. }
  1253. /* write cfg to dxndqstr */
  1254. set_r0dgsl_delay(phy, byte, gsl_idx);
  1255. set_r0dgps_delay(phy, byte, gps_idx);
  1256. BIST_test(phy, byte, &result);
  1257. success = result.test_result;
  1258. if (success)
  1259. dqs_gating[byte][gsl_idx][gps_idx] = 1;
  1260. itm_soft_reset(phy);
  1261. }
  1262. }
  1263. set_midpoint_read_dqs_gating(phy, byte, dqs_gating);
  1264. /* dummy reads */
  1265. readl(0xc0000000);
  1266. readl(0xc0000000);
  1267. }
  1268. /* re-enable drift compensation */
  1269. /* setbits_le32(&phy->pgcr, DDRPHYC_PGCR_DFTCMP); */
  1270. return TEST_PASSED;
  1271. }
  1272. /****************************************************************
  1273. * TEST
  1274. ****************************************************************
  1275. */
  1276. static enum test_result do_read_dqs_gating(struct stm32mp1_ddrctl *ctl,
  1277. struct stm32mp1_ddrphy *phy,
  1278. char *string, int argc,
  1279. char *argv[])
  1280. {
  1281. u32 rfshctl3 = readl(&ctl->rfshctl3);
  1282. u32 pwrctl = readl(&ctl->pwrctl);
  1283. u32 derateen = readl(&ctl->derateen);
  1284. enum test_result res;
  1285. writel(0x0, &ctl->derateen);
  1286. stm32mp1_refresh_disable(ctl);
  1287. res = read_dqs_gating(ctl, phy, string);
  1288. stm32mp1_refresh_restore(ctl, rfshctl3, pwrctl);
  1289. writel(derateen, &ctl->derateen);
  1290. return res;
  1291. }
  1292. static enum test_result do_bit_deskew(struct stm32mp1_ddrctl *ctl,
  1293. struct stm32mp1_ddrphy *phy,
  1294. char *string, int argc, char *argv[])
  1295. {
  1296. u32 rfshctl3 = readl(&ctl->rfshctl3);
  1297. u32 pwrctl = readl(&ctl->pwrctl);
  1298. u32 derateen = readl(&ctl->derateen);
  1299. enum test_result res;
  1300. writel(0x0, &ctl->derateen);
  1301. stm32mp1_refresh_disable(ctl);
  1302. res = bit_deskew(ctl, phy, string);
  1303. stm32mp1_refresh_restore(ctl, rfshctl3, pwrctl);
  1304. writel(derateen, &ctl->derateen);
  1305. return res;
  1306. }
  1307. static enum test_result do_eye_training(struct stm32mp1_ddrctl *ctl,
  1308. struct stm32mp1_ddrphy *phy,
  1309. char *string, int argc, char *argv[])
  1310. {
  1311. u32 rfshctl3 = readl(&ctl->rfshctl3);
  1312. u32 pwrctl = readl(&ctl->pwrctl);
  1313. u32 derateen = readl(&ctl->derateen);
  1314. enum test_result res;
  1315. writel(0x0, &ctl->derateen);
  1316. stm32mp1_refresh_disable(ctl);
  1317. res = eye_training(ctl, phy, string);
  1318. stm32mp1_refresh_restore(ctl, rfshctl3, pwrctl);
  1319. writel(derateen, &ctl->derateen);
  1320. return res;
  1321. }
  1322. static enum test_result do_display(struct stm32mp1_ddrctl *ctl,
  1323. struct stm32mp1_ddrphy *phy,
  1324. char *string, int argc, char *argv[])
  1325. {
  1326. int byte;
  1327. u8 nb_bytes = get_nb_bytes(ctl);
  1328. for (byte = 0; byte < nb_bytes; byte++)
  1329. display_reg_results(phy, byte);
  1330. return TEST_PASSED;
  1331. }
  1332. static enum test_result do_bist_config(struct stm32mp1_ddrctl *ctl,
  1333. struct stm32mp1_ddrphy *phy,
  1334. char *string, int argc, char *argv[])
  1335. {
  1336. unsigned long value;
  1337. if (argc > 0) {
  1338. if (strict_strtoul(argv[0], 0, &value) < 0) {
  1339. sprintf(string, "invalid nbErr %s", argv[0]);
  1340. return TEST_FAILED;
  1341. }
  1342. BIST_error_max = value;
  1343. }
  1344. if (argc > 1) {
  1345. if (strict_strtoul(argv[1], 0, &value) < 0) {
  1346. sprintf(string, "invalid Seed %s", argv[1]);
  1347. return TEST_FAILED;
  1348. }
  1349. BIST_seed = value;
  1350. }
  1351. printf("Bist.nbErr = %d\n", BIST_error_max);
  1352. if (BIST_seed)
  1353. printf("Bist.Seed = 0x%x\n", BIST_seed);
  1354. else
  1355. printf("Bist.Seed = random\n");
  1356. return TEST_PASSED;
  1357. }
  1358. /****************************************************************
  1359. * TEST Description
  1360. ****************************************************************
  1361. */
  1362. const struct test_desc tuning[] = {
  1363. {do_read_dqs_gating, "Read DQS gating",
  1364. "software read DQS Gating", "", 0 },
  1365. {do_bit_deskew, "Bit de-skew", "", "", 0 },
  1366. {do_eye_training, "Eye Training", "or DQS training", "", 0 },
  1367. {do_display, "Display registers", "", "", 0 },
  1368. {do_bist_config, "Bist config", "[nbErr] [seed]",
  1369. "configure Bist test", 2},
  1370. };
  1371. const int tuning_nb = ARRAY_SIZE(tuning);