lpddr4_private.h 1.9 KB

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  1. /* SPDX-License-Identifier: BSD-3-Clause */
  2. /**********************************************************************
  3. * Copyright (C) 2012-2018 Cadence Design Systems, Inc.
  4. * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
  5. **********************************************************************
  6. * Cadence Core Driver for LPDDR4.
  7. **********************************************************************
  8. */
  9. #ifndef LPDDR4_PRIV_H
  10. #define LPDDR4_PRIV_H
  11. #define PRODUCT_ID (0x1046U)
  12. #define VERSION_0 (0x54d5da40U)
  13. #define VERSION_1 (0xc1865a1U)
  14. #define BIT_MASK (0x1U)
  15. #define BYTE_MASK (0xffU)
  16. #define NIBBLE_MASK (0xfU)
  17. #define WORD_SHIFT (32U)
  18. #define WORD_MASK (0xffffffffU)
  19. #define SLICE_WIDTH (0x100)
  20. /* Number of Data slices */
  21. #define DSLICE_NUM (4U)
  22. /*Number of Address Slices */
  23. #define ASLICE_NUM (1U)
  24. /* Number of accessible registers in each slice */
  25. #define DSLICE0_REG_COUNT (140U)
  26. #define DSLICE1_REG_COUNT (140U)
  27. #define DSLICE2_REG_COUNT (140U)
  28. #define DSLICE3_REG_COUNT (140U)
  29. #define ASLICE0_REG_COUNT (52U)
  30. #define PHY_CORE_REG_COUNT (140U)
  31. #define CTL_OFFSET 0
  32. #define PI_OFFSET (((uint32_t)1) << 11)
  33. #define PHY_OFFSET (((uint32_t)1) << 12)
  34. /* BIT[17] on INT_MASK_1 register. */
  35. #define CTL_INT_MASK_ALL ((uint32_t)LPDDR4_LOR_BITS - WORD_SHIFT)
  36. /* Init Error information bits */
  37. #define PLL_READY (0x3U)
  38. #define IO_CALIB_DONE ((uint32_t)0x1U << 23U)
  39. #define IO_CALIB_FIELD ((uint32_t)NIBBLE_MASK << 28U)
  40. #define IO_CALIB_STATE ((uint32_t)0xBU << 28U)
  41. #define RX_CAL_DONE ((uint32_t)BIT_MASK << 4U)
  42. #define CA_TRAIN_RL (((uint32_t)BIT_MASK << 5U) | ((uint32_t)BIT_MASK << 4U))
  43. #define WR_LVL_STATE (((uint32_t)NIBBLE_MASK) << 13U)
  44. #define GATE_LVL_ERROR_FIELDS (((uint32_t)BIT_MASK << 7U) | ((uint32_t)BIT_MASK << 6U))
  45. #define READ_LVL_ERROR_FIELDS ((((uint32_t)NIBBLE_MASK) << 28U) | (((uint32_t)BYTE_MASK) << 16U))
  46. #define DQ_LVL_STATUS (((uint32_t)BIT_MASK << 26U) | (((uint32_t)BYTE_MASK) << 18U))
  47. #endif /* LPDDR4_PRIV_H */