lpddr4_pi_macros.h 312 KB

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  1. /* SPDX-License-Identifier: BSD-3-Clause */
  2. /**********************************************************************
  3. * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
  4. *
  5. * THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT
  6. *
  7. **********************************************************************
  8. */
  9. #ifndef REG_LPDDR4_PI_MACROS_H_
  10. #define REG_LPDDR4_PI_MACROS_H_
  11. #define LPDDR4__DENALI_PI_0_READ_MASK 0x00000F01U
  12. #define LPDDR4__DENALI_PI_0_WRITE_MASK 0x00000F01U
  13. #define LPDDR4__DENALI_PI_0__PI_START_MASK 0x00000001U
  14. #define LPDDR4__DENALI_PI_0__PI_START_SHIFT 0U
  15. #define LPDDR4__DENALI_PI_0__PI_START_WIDTH 1U
  16. #define LPDDR4__DENALI_PI_0__PI_START_WOCLR 0U
  17. #define LPDDR4__DENALI_PI_0__PI_START_WOSET 0U
  18. #define LPDDR4__PI_START__REG DENALI_PI_0
  19. #define LPDDR4__PI_START__FLD LPDDR4__DENALI_PI_0__PI_START
  20. #define LPDDR4__DENALI_PI_0__PI_DRAM_CLASS_MASK 0x00000F00U
  21. #define LPDDR4__DENALI_PI_0__PI_DRAM_CLASS_SHIFT 8U
  22. #define LPDDR4__DENALI_PI_0__PI_DRAM_CLASS_WIDTH 4U
  23. #define LPDDR4__PI_DRAM_CLASS__REG DENALI_PI_0
  24. #define LPDDR4__PI_DRAM_CLASS__FLD LPDDR4__DENALI_PI_0__PI_DRAM_CLASS
  25. #define LPDDR4__DENALI_PI_1_READ_MASK 0xFFFFFFFFU
  26. #define LPDDR4__DENALI_PI_1_WRITE_MASK 0xFFFFFFFFU
  27. #define LPDDR4__DENALI_PI_1__PI_VERSION_0_MASK 0xFFFFFFFFU
  28. #define LPDDR4__DENALI_PI_1__PI_VERSION_0_SHIFT 0U
  29. #define LPDDR4__DENALI_PI_1__PI_VERSION_0_WIDTH 32U
  30. #define LPDDR4__PI_VERSION_0__REG DENALI_PI_1
  31. #define LPDDR4__PI_VERSION_0__FLD LPDDR4__DENALI_PI_1__PI_VERSION_0
  32. #define LPDDR4__DENALI_PI_2_READ_MASK 0xFFFFFFFFU
  33. #define LPDDR4__DENALI_PI_2_WRITE_MASK 0xFFFFFFFFU
  34. #define LPDDR4__DENALI_PI_2__PI_VERSION_1_MASK 0xFFFFFFFFU
  35. #define LPDDR4__DENALI_PI_2__PI_VERSION_1_SHIFT 0U
  36. #define LPDDR4__DENALI_PI_2__PI_VERSION_1_WIDTH 32U
  37. #define LPDDR4__PI_VERSION_1__REG DENALI_PI_2
  38. #define LPDDR4__PI_VERSION_1__FLD LPDDR4__DENALI_PI_2__PI_VERSION_1
  39. #define LPDDR4__DENALI_PI_3_READ_MASK 0x0000FFFFU
  40. #define LPDDR4__DENALI_PI_3_WRITE_MASK 0x0000FFFFU
  41. #define LPDDR4__DENALI_PI_3__PI_ID_MASK 0x0000FFFFU
  42. #define LPDDR4__DENALI_PI_3__PI_ID_SHIFT 0U
  43. #define LPDDR4__DENALI_PI_3__PI_ID_WIDTH 16U
  44. #define LPDDR4__PI_ID__REG DENALI_PI_3
  45. #define LPDDR4__PI_ID__FLD LPDDR4__DENALI_PI_3__PI_ID
  46. #define LPDDR4__DENALI_PI_4_READ_MASK 0xFFFFFFFFU
  47. #define LPDDR4__DENALI_PI_4_WRITE_MASK 0xFFFFFFFFU
  48. #define LPDDR4__DENALI_PI_4__DENALI_PI_UNUSED_REG_0_MASK 0xFFFFFFFFU
  49. #define LPDDR4__DENALI_PI_4__DENALI_PI_UNUSED_REG_0_SHIFT 0U
  50. #define LPDDR4__DENALI_PI_4__DENALI_PI_UNUSED_REG_0_WIDTH 32U
  51. #define LPDDR4__DENALI_PI_UNUSED_REG_0__REG DENALI_PI_4
  52. #define LPDDR4__DENALI_PI_UNUSED_REG_0__FLD LPDDR4__DENALI_PI_4__DENALI_PI_UNUSED_REG_0
  53. #define LPDDR4__DENALI_PI_5_READ_MASK 0x00010101U
  54. #define LPDDR4__DENALI_PI_5_WRITE_MASK 0x00010101U
  55. #define LPDDR4__DENALI_PI_5__PI_NORMAL_LVL_SEQ_MASK 0x00000001U
  56. #define LPDDR4__DENALI_PI_5__PI_NORMAL_LVL_SEQ_SHIFT 0U
  57. #define LPDDR4__DENALI_PI_5__PI_NORMAL_LVL_SEQ_WIDTH 1U
  58. #define LPDDR4__DENALI_PI_5__PI_NORMAL_LVL_SEQ_WOCLR 0U
  59. #define LPDDR4__DENALI_PI_5__PI_NORMAL_LVL_SEQ_WOSET 0U
  60. #define LPDDR4__PI_NORMAL_LVL_SEQ__REG DENALI_PI_5
  61. #define LPDDR4__PI_NORMAL_LVL_SEQ__FLD LPDDR4__DENALI_PI_5__PI_NORMAL_LVL_SEQ
  62. #define LPDDR4__DENALI_PI_5__PI_INIT_LVL_EN_MASK 0x00000100U
  63. #define LPDDR4__DENALI_PI_5__PI_INIT_LVL_EN_SHIFT 8U
  64. #define LPDDR4__DENALI_PI_5__PI_INIT_LVL_EN_WIDTH 1U
  65. #define LPDDR4__DENALI_PI_5__PI_INIT_LVL_EN_WOCLR 0U
  66. #define LPDDR4__DENALI_PI_5__PI_INIT_LVL_EN_WOSET 0U
  67. #define LPDDR4__PI_INIT_LVL_EN__REG DENALI_PI_5
  68. #define LPDDR4__PI_INIT_LVL_EN__FLD LPDDR4__DENALI_PI_5__PI_INIT_LVL_EN
  69. #define LPDDR4__DENALI_PI_5__PI_NOTCARE_PHYUPD_MASK 0x00010000U
  70. #define LPDDR4__DENALI_PI_5__PI_NOTCARE_PHYUPD_SHIFT 16U
  71. #define LPDDR4__DENALI_PI_5__PI_NOTCARE_PHYUPD_WIDTH 1U
  72. #define LPDDR4__DENALI_PI_5__PI_NOTCARE_PHYUPD_WOCLR 0U
  73. #define LPDDR4__DENALI_PI_5__PI_NOTCARE_PHYUPD_WOSET 0U
  74. #define LPDDR4__PI_NOTCARE_PHYUPD__REG DENALI_PI_5
  75. #define LPDDR4__PI_NOTCARE_PHYUPD__FLD LPDDR4__DENALI_PI_5__PI_NOTCARE_PHYUPD
  76. #define LPDDR4__DENALI_PI_6_READ_MASK 0x00FFFFFFU
  77. #define LPDDR4__DENALI_PI_6_WRITE_MASK 0x00FFFFFFU
  78. #define LPDDR4__DENALI_PI_6__PI_TCMD_GAP_MASK 0x0000FFFFU
  79. #define LPDDR4__DENALI_PI_6__PI_TCMD_GAP_SHIFT 0U
  80. #define LPDDR4__DENALI_PI_6__PI_TCMD_GAP_WIDTH 16U
  81. #define LPDDR4__PI_TCMD_GAP__REG DENALI_PI_6
  82. #define LPDDR4__PI_TCMD_GAP__FLD LPDDR4__DENALI_PI_6__PI_TCMD_GAP
  83. #define LPDDR4__DENALI_PI_6__PI_RESERVED0_MASK 0x00FF0000U
  84. #define LPDDR4__DENALI_PI_6__PI_RESERVED0_SHIFT 16U
  85. #define LPDDR4__DENALI_PI_6__PI_RESERVED0_WIDTH 8U
  86. #define LPDDR4__PI_RESERVED0__REG DENALI_PI_6
  87. #define LPDDR4__PI_RESERVED0__FLD LPDDR4__DENALI_PI_6__PI_RESERVED0
  88. #define LPDDR4__DENALI_PI_6__PI_TRAIN_ALL_FREQ_REQ_MASK 0x01000000U
  89. #define LPDDR4__DENALI_PI_6__PI_TRAIN_ALL_FREQ_REQ_SHIFT 24U
  90. #define LPDDR4__DENALI_PI_6__PI_TRAIN_ALL_FREQ_REQ_WIDTH 1U
  91. #define LPDDR4__DENALI_PI_6__PI_TRAIN_ALL_FREQ_REQ_WOCLR 0U
  92. #define LPDDR4__DENALI_PI_6__PI_TRAIN_ALL_FREQ_REQ_WOSET 0U
  93. #define LPDDR4__PI_TRAIN_ALL_FREQ_REQ__REG DENALI_PI_6
  94. #define LPDDR4__PI_TRAIN_ALL_FREQ_REQ__FLD LPDDR4__DENALI_PI_6__PI_TRAIN_ALL_FREQ_REQ
  95. #define LPDDR4__DENALI_PI_7_READ_MASK 0x01010301U
  96. #define LPDDR4__DENALI_PI_7_WRITE_MASK 0x01010301U
  97. #define LPDDR4__DENALI_PI_7__PI_DFI_VERSION_MASK 0x00000001U
  98. #define LPDDR4__DENALI_PI_7__PI_DFI_VERSION_SHIFT 0U
  99. #define LPDDR4__DENALI_PI_7__PI_DFI_VERSION_WIDTH 1U
  100. #define LPDDR4__DENALI_PI_7__PI_DFI_VERSION_WOCLR 0U
  101. #define LPDDR4__DENALI_PI_7__PI_DFI_VERSION_WOSET 0U
  102. #define LPDDR4__PI_DFI_VERSION__REG DENALI_PI_7
  103. #define LPDDR4__PI_DFI_VERSION__FLD LPDDR4__DENALI_PI_7__PI_DFI_VERSION
  104. #define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_TYPE_MASK 0x00000300U
  105. #define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_TYPE_SHIFT 8U
  106. #define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_TYPE_WIDTH 2U
  107. #define LPDDR4__PI_DFI_PHYMSTR_TYPE__REG DENALI_PI_7
  108. #define LPDDR4__PI_DFI_PHYMSTR_TYPE__FLD LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_TYPE
  109. #define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_CS_STATE_R_MASK 0x00010000U
  110. #define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_CS_STATE_R_SHIFT 16U
  111. #define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_CS_STATE_R_WIDTH 1U
  112. #define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_CS_STATE_R_WOCLR 0U
  113. #define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_CS_STATE_R_WOSET 0U
  114. #define LPDDR4__PI_DFI_PHYMSTR_CS_STATE_R__REG DENALI_PI_7
  115. #define LPDDR4__PI_DFI_PHYMSTR_CS_STATE_R__FLD LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_CS_STATE_R
  116. #define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_STATE_SEL_R_MASK 0x01000000U
  117. #define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_STATE_SEL_R_SHIFT 24U
  118. #define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_STATE_SEL_R_WIDTH 1U
  119. #define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_STATE_SEL_R_WOCLR 0U
  120. #define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_STATE_SEL_R_WOSET 0U
  121. #define LPDDR4__PI_DFI_PHYMSTR_STATE_SEL_R__REG DENALI_PI_7
  122. #define LPDDR4__PI_DFI_PHYMSTR_STATE_SEL_R__FLD LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_STATE_SEL_R
  123. #define LPDDR4__DENALI_PI_8_READ_MASK 0xFFFFFFFFU
  124. #define LPDDR4__DENALI_PI_8_WRITE_MASK 0xFFFFFFFFU
  125. #define LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_MAX_MASK 0xFFFFFFFFU
  126. #define LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_MAX_SHIFT 0U
  127. #define LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_MAX_WIDTH 32U
  128. #define LPDDR4__PI_TDFI_PHYMSTR_MAX__REG DENALI_PI_8
  129. #define LPDDR4__PI_TDFI_PHYMSTR_MAX__FLD LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_MAX
  130. #define LPDDR4__DENALI_PI_9_READ_MASK 0x000FFFFFU
  131. #define LPDDR4__DENALI_PI_9_WRITE_MASK 0x000FFFFFU
  132. #define LPDDR4__DENALI_PI_9__PI_TDFI_PHYMSTR_RESP_MASK 0x000FFFFFU
  133. #define LPDDR4__DENALI_PI_9__PI_TDFI_PHYMSTR_RESP_SHIFT 0U
  134. #define LPDDR4__DENALI_PI_9__PI_TDFI_PHYMSTR_RESP_WIDTH 20U
  135. #define LPDDR4__PI_TDFI_PHYMSTR_RESP__REG DENALI_PI_9
  136. #define LPDDR4__PI_TDFI_PHYMSTR_RESP__FLD LPDDR4__DENALI_PI_9__PI_TDFI_PHYMSTR_RESP
  137. #define LPDDR4__DENALI_PI_10_READ_MASK 0x000FFFFFU
  138. #define LPDDR4__DENALI_PI_10_WRITE_MASK 0x000FFFFFU
  139. #define LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_RESP_MASK 0x000FFFFFU
  140. #define LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_RESP_SHIFT 0U
  141. #define LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_RESP_WIDTH 20U
  142. #define LPDDR4__PI_TDFI_PHYUPD_RESP__REG DENALI_PI_10
  143. #define LPDDR4__PI_TDFI_PHYUPD_RESP__FLD LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_RESP
  144. #define LPDDR4__DENALI_PI_11_READ_MASK 0xFFFFFFFFU
  145. #define LPDDR4__DENALI_PI_11_WRITE_MASK 0xFFFFFFFFU
  146. #define LPDDR4__DENALI_PI_11__PI_TDFI_PHYUPD_MAX_MASK 0xFFFFFFFFU
  147. #define LPDDR4__DENALI_PI_11__PI_TDFI_PHYUPD_MAX_SHIFT 0U
  148. #define LPDDR4__DENALI_PI_11__PI_TDFI_PHYUPD_MAX_WIDTH 32U
  149. #define LPDDR4__PI_TDFI_PHYUPD_MAX__REG DENALI_PI_11
  150. #define LPDDR4__PI_TDFI_PHYUPD_MAX__FLD LPDDR4__DENALI_PI_11__PI_TDFI_PHYUPD_MAX
  151. #define LPDDR4__DENALI_PI_12_READ_MASK 0xFFFFFFFFU
  152. #define LPDDR4__DENALI_PI_12_WRITE_MASK 0xFFFFFFFFU
  153. #define LPDDR4__DENALI_PI_12__PI_FREQ_MAP_MASK 0xFFFFFFFFU
  154. #define LPDDR4__DENALI_PI_12__PI_FREQ_MAP_SHIFT 0U
  155. #define LPDDR4__DENALI_PI_12__PI_FREQ_MAP_WIDTH 32U
  156. #define LPDDR4__PI_FREQ_MAP__REG DENALI_PI_12
  157. #define LPDDR4__PI_FREQ_MAP__FLD LPDDR4__DENALI_PI_12__PI_FREQ_MAP
  158. #define LPDDR4__DENALI_PI_13_READ_MASK 0x0101011FU
  159. #define LPDDR4__DENALI_PI_13_WRITE_MASK 0x0101011FU
  160. #define LPDDR4__DENALI_PI_13__PI_INIT_WORK_FREQ_MASK 0x0000001FU
  161. #define LPDDR4__DENALI_PI_13__PI_INIT_WORK_FREQ_SHIFT 0U
  162. #define LPDDR4__DENALI_PI_13__PI_INIT_WORK_FREQ_WIDTH 5U
  163. #define LPDDR4__PI_INIT_WORK_FREQ__REG DENALI_PI_13
  164. #define LPDDR4__PI_INIT_WORK_FREQ__FLD LPDDR4__DENALI_PI_13__PI_INIT_WORK_FREQ
  165. #define LPDDR4__DENALI_PI_13__PI_INIT_DFS_CALVL_ONLY_MASK 0x00000100U
  166. #define LPDDR4__DENALI_PI_13__PI_INIT_DFS_CALVL_ONLY_SHIFT 8U
  167. #define LPDDR4__DENALI_PI_13__PI_INIT_DFS_CALVL_ONLY_WIDTH 1U
  168. #define LPDDR4__DENALI_PI_13__PI_INIT_DFS_CALVL_ONLY_WOCLR 0U
  169. #define LPDDR4__DENALI_PI_13__PI_INIT_DFS_CALVL_ONLY_WOSET 0U
  170. #define LPDDR4__PI_INIT_DFS_CALVL_ONLY__REG DENALI_PI_13
  171. #define LPDDR4__PI_INIT_DFS_CALVL_ONLY__FLD LPDDR4__DENALI_PI_13__PI_INIT_DFS_CALVL_ONLY
  172. #define LPDDR4__DENALI_PI_13__PI_SW_RST_N_MASK 0x00010000U
  173. #define LPDDR4__DENALI_PI_13__PI_SW_RST_N_SHIFT 16U
  174. #define LPDDR4__DENALI_PI_13__PI_SW_RST_N_WIDTH 1U
  175. #define LPDDR4__DENALI_PI_13__PI_SW_RST_N_WOCLR 0U
  176. #define LPDDR4__DENALI_PI_13__PI_SW_RST_N_WOSET 0U
  177. #define LPDDR4__PI_SW_RST_N__REG DENALI_PI_13
  178. #define LPDDR4__PI_SW_RST_N__FLD LPDDR4__DENALI_PI_13__PI_SW_RST_N
  179. #define LPDDR4__DENALI_PI_13__PI_RESERVED1_MASK 0x01000000U
  180. #define LPDDR4__DENALI_PI_13__PI_RESERVED1_SHIFT 24U
  181. #define LPDDR4__DENALI_PI_13__PI_RESERVED1_WIDTH 1U
  182. #define LPDDR4__DENALI_PI_13__PI_RESERVED1_WOCLR 0U
  183. #define LPDDR4__DENALI_PI_13__PI_RESERVED1_WOSET 0U
  184. #define LPDDR4__PI_RESERVED1__REG DENALI_PI_13
  185. #define LPDDR4__PI_RESERVED1__FLD LPDDR4__DENALI_PI_13__PI_RESERVED1
  186. #define LPDDR4__DENALI_PI_14_READ_MASK 0x0F011F0FU
  187. #define LPDDR4__DENALI_PI_14_WRITE_MASK 0x0F011F0FU
  188. #define LPDDR4__DENALI_PI_14__PI_CS_MAP_MASK 0x0000000FU
  189. #define LPDDR4__DENALI_PI_14__PI_CS_MAP_SHIFT 0U
  190. #define LPDDR4__DENALI_PI_14__PI_CS_MAP_WIDTH 4U
  191. #define LPDDR4__PI_CS_MAP__REG DENALI_PI_14
  192. #define LPDDR4__PI_CS_MAP__FLD LPDDR4__DENALI_PI_14__PI_CS_MAP
  193. #define LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE_MASK 0x00001F00U
  194. #define LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE_SHIFT 8U
  195. #define LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE_WIDTH 5U
  196. #define LPDDR4__PI_RANK_NUM_PER_CKE__REG DENALI_PI_14
  197. #define LPDDR4__PI_RANK_NUM_PER_CKE__FLD LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE
  198. #define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_MASK 0x00010000U
  199. #define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_SHIFT 16U
  200. #define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_WIDTH 1U
  201. #define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_WOCLR 0U
  202. #define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_WOSET 0U
  203. #define LPDDR4__PI_SRX_LVL_TARGET_CS_EN__REG DENALI_PI_14
  204. #define LPDDR4__PI_SRX_LVL_TARGET_CS_EN__FLD LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN
  205. #define LPDDR4__DENALI_PI_14__PI_TMRR_MASK 0x0F000000U
  206. #define LPDDR4__DENALI_PI_14__PI_TMRR_SHIFT 24U
  207. #define LPDDR4__DENALI_PI_14__PI_TMRR_WIDTH 4U
  208. #define LPDDR4__PI_TMRR__REG DENALI_PI_14
  209. #define LPDDR4__PI_TMRR__FLD LPDDR4__DENALI_PI_14__PI_TMRR
  210. #define LPDDR4__DENALI_PI_15_READ_MASK 0x00010103U
  211. #define LPDDR4__DENALI_PI_15_WRITE_MASK 0x00010103U
  212. #define LPDDR4__DENALI_PI_15__PI_PREAMBLE_SUPPORT_MASK 0x00000003U
  213. #define LPDDR4__DENALI_PI_15__PI_PREAMBLE_SUPPORT_SHIFT 0U
  214. #define LPDDR4__DENALI_PI_15__PI_PREAMBLE_SUPPORT_WIDTH 2U
  215. #define LPDDR4__PI_PREAMBLE_SUPPORT__REG DENALI_PI_15
  216. #define LPDDR4__PI_PREAMBLE_SUPPORT__FLD LPDDR4__DENALI_PI_15__PI_PREAMBLE_SUPPORT
  217. #define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_MASK 0x00000100U
  218. #define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_SHIFT 8U
  219. #define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_WIDTH 1U
  220. #define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_WOCLR 0U
  221. #define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_WOSET 0U
  222. #define LPDDR4__PI_MCAREF_FORWARD_ONLY__REG DENALI_PI_15
  223. #define LPDDR4__PI_MCAREF_FORWARD_ONLY__FLD LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY
  224. #define LPDDR4__DENALI_PI_15__PI_RESERVED2_MASK 0x00010000U
  225. #define LPDDR4__DENALI_PI_15__PI_RESERVED2_SHIFT 16U
  226. #define LPDDR4__DENALI_PI_15__PI_RESERVED2_WIDTH 1U
  227. #define LPDDR4__DENALI_PI_15__PI_RESERVED2_WOCLR 0U
  228. #define LPDDR4__DENALI_PI_15__PI_RESERVED2_WOSET 0U
  229. #define LPDDR4__PI_RESERVED2__REG DENALI_PI_15
  230. #define LPDDR4__PI_RESERVED2__FLD LPDDR4__DENALI_PI_15__PI_RESERVED2
  231. #define LPDDR4__DENALI_PI_16_READ_MASK 0x010FFFFFU
  232. #define LPDDR4__DENALI_PI_16_WRITE_MASK 0x010FFFFFU
  233. #define LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL_MASK 0x000FFFFFU
  234. #define LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL_SHIFT 0U
  235. #define LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL_WIDTH 20U
  236. #define LPDDR4__PI_TREF_INTERVAL__REG DENALI_PI_16
  237. #define LPDDR4__PI_TREF_INTERVAL__FLD LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL
  238. #define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_MASK 0x01000000U
  239. #define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_SHIFT 24U
  240. #define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_WIDTH 1U
  241. #define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_WOCLR 0U
  242. #define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_WOSET 0U
  243. #define LPDDR4__PI_ON_DFIBUS__REG DENALI_PI_16
  244. #define LPDDR4__PI_ON_DFIBUS__FLD LPDDR4__DENALI_PI_16__PI_ON_DFIBUS
  245. #define LPDDR4__DENALI_PI_17_READ_MASK 0x01010001U
  246. #define LPDDR4__DENALI_PI_17_WRITE_MASK 0x01010001U
  247. #define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_MASK 0x00000001U
  248. #define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_SHIFT 0U
  249. #define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_WIDTH 1U
  250. #define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_WOCLR 0U
  251. #define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_WOSET 0U
  252. #define LPDDR4__PI_DATA_RETENTION__REG DENALI_PI_17
  253. #define LPDDR4__PI_DATA_RETENTION__FLD LPDDR4__DENALI_PI_17__PI_DATA_RETENTION
  254. #define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_MASK 0x00000100U
  255. #define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_SHIFT 8U
  256. #define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_WIDTH 1U
  257. #define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_WOCLR 0U
  258. #define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_WOSET 0U
  259. #define LPDDR4__PI_SWLVL_LOAD__REG DENALI_PI_17
  260. #define LPDDR4__PI_SWLVL_LOAD__FLD LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD
  261. #define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_MASK 0x00010000U
  262. #define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_SHIFT 16U
  263. #define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_WIDTH 1U
  264. #define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_WOCLR 0U
  265. #define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_WOSET 0U
  266. #define LPDDR4__PI_SWLVL_OP_DONE__REG DENALI_PI_17
  267. #define LPDDR4__PI_SWLVL_OP_DONE__FLD LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE
  268. #define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_MASK 0x01000000U
  269. #define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_SHIFT 24U
  270. #define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_WIDTH 1U
  271. #define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_WOCLR 0U
  272. #define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_WOSET 0U
  273. #define LPDDR4__PI_SW_WRLVL_RESP_0__REG DENALI_PI_17
  274. #define LPDDR4__PI_SW_WRLVL_RESP_0__FLD LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0
  275. #define LPDDR4__DENALI_PI_18_READ_MASK 0x03010101U
  276. #define LPDDR4__DENALI_PI_18_WRITE_MASK 0x03010101U
  277. #define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_MASK 0x00000001U
  278. #define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_SHIFT 0U
  279. #define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_WIDTH 1U
  280. #define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_WOCLR 0U
  281. #define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_WOSET 0U
  282. #define LPDDR4__PI_SW_WRLVL_RESP_1__REG DENALI_PI_18
  283. #define LPDDR4__PI_SW_WRLVL_RESP_1__FLD LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1
  284. #define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_MASK 0x00000100U
  285. #define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_SHIFT 8U
  286. #define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_WIDTH 1U
  287. #define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_WOCLR 0U
  288. #define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_WOSET 0U
  289. #define LPDDR4__PI_SW_WRLVL_RESP_2__REG DENALI_PI_18
  290. #define LPDDR4__PI_SW_WRLVL_RESP_2__FLD LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2
  291. #define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_MASK 0x00010000U
  292. #define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_SHIFT 16U
  293. #define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_WIDTH 1U
  294. #define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_WOCLR 0U
  295. #define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_WOSET 0U
  296. #define LPDDR4__PI_SW_WRLVL_RESP_3__REG DENALI_PI_18
  297. #define LPDDR4__PI_SW_WRLVL_RESP_3__FLD LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3
  298. #define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0_MASK 0x03000000U
  299. #define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0_SHIFT 24U
  300. #define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0_WIDTH 2U
  301. #define LPDDR4__PI_SW_RDLVL_RESP_0__REG DENALI_PI_18
  302. #define LPDDR4__PI_SW_RDLVL_RESP_0__FLD LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0
  303. #define LPDDR4__DENALI_PI_19_READ_MASK 0x03030303U
  304. #define LPDDR4__DENALI_PI_19_WRITE_MASK 0x03030303U
  305. #define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_1_MASK 0x00000003U
  306. #define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_1_SHIFT 0U
  307. #define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_1_WIDTH 2U
  308. #define LPDDR4__PI_SW_RDLVL_RESP_1__REG DENALI_PI_19
  309. #define LPDDR4__PI_SW_RDLVL_RESP_1__FLD LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_1
  310. #define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_2_MASK 0x00000300U
  311. #define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_2_SHIFT 8U
  312. #define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_2_WIDTH 2U
  313. #define LPDDR4__PI_SW_RDLVL_RESP_2__REG DENALI_PI_19
  314. #define LPDDR4__PI_SW_RDLVL_RESP_2__FLD LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_2
  315. #define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_3_MASK 0x00030000U
  316. #define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_3_SHIFT 16U
  317. #define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_3_WIDTH 2U
  318. #define LPDDR4__PI_SW_RDLVL_RESP_3__REG DENALI_PI_19
  319. #define LPDDR4__PI_SW_RDLVL_RESP_3__FLD LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_3
  320. #define LPDDR4__DENALI_PI_19__PI_SW_CALVL_RESP_0_MASK 0x03000000U
  321. #define LPDDR4__DENALI_PI_19__PI_SW_CALVL_RESP_0_SHIFT 24U
  322. #define LPDDR4__DENALI_PI_19__PI_SW_CALVL_RESP_0_WIDTH 2U
  323. #define LPDDR4__PI_SW_CALVL_RESP_0__REG DENALI_PI_19
  324. #define LPDDR4__PI_SW_CALVL_RESP_0__FLD LPDDR4__DENALI_PI_19__PI_SW_CALVL_RESP_0
  325. #define LPDDR4__DENALI_PI_20_READ_MASK 0x00000007U
  326. #define LPDDR4__DENALI_PI_20_WRITE_MASK 0x00000007U
  327. #define LPDDR4__DENALI_PI_20__PI_SW_LEVELING_MODE_MASK 0x00000007U
  328. #define LPDDR4__DENALI_PI_20__PI_SW_LEVELING_MODE_SHIFT 0U
  329. #define LPDDR4__DENALI_PI_20__PI_SW_LEVELING_MODE_WIDTH 3U
  330. #define LPDDR4__PI_SW_LEVELING_MODE__REG DENALI_PI_20
  331. #define LPDDR4__PI_SW_LEVELING_MODE__FLD LPDDR4__DENALI_PI_20__PI_SW_LEVELING_MODE
  332. #define LPDDR4__DENALI_PI_20__PI_SWLVL_START_MASK 0x00000100U
  333. #define LPDDR4__DENALI_PI_20__PI_SWLVL_START_SHIFT 8U
  334. #define LPDDR4__DENALI_PI_20__PI_SWLVL_START_WIDTH 1U
  335. #define LPDDR4__DENALI_PI_20__PI_SWLVL_START_WOCLR 0U
  336. #define LPDDR4__DENALI_PI_20__PI_SWLVL_START_WOSET 0U
  337. #define LPDDR4__PI_SWLVL_START__REG DENALI_PI_20
  338. #define LPDDR4__PI_SWLVL_START__FLD LPDDR4__DENALI_PI_20__PI_SWLVL_START
  339. #define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_MASK 0x00010000U
  340. #define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_SHIFT 16U
  341. #define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_WIDTH 1U
  342. #define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_WOCLR 0U
  343. #define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_WOSET 0U
  344. #define LPDDR4__PI_SWLVL_EXIT__REG DENALI_PI_20
  345. #define LPDDR4__PI_SWLVL_EXIT__FLD LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT
  346. #define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_MASK 0x01000000U
  347. #define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_SHIFT 24U
  348. #define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_WIDTH 1U
  349. #define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_WOCLR 0U
  350. #define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_WOSET 0U
  351. #define LPDDR4__PI_SWLVL_WR_SLICE_0__REG DENALI_PI_20
  352. #define LPDDR4__PI_SWLVL_WR_SLICE_0__FLD LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0
  353. #define LPDDR4__DENALI_PI_21_READ_MASK 0x00030000U
  354. #define LPDDR4__DENALI_PI_21_WRITE_MASK 0x00030000U
  355. #define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_MASK 0x00000001U
  356. #define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_SHIFT 0U
  357. #define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_WIDTH 1U
  358. #define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_WOCLR 0U
  359. #define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_WOSET 0U
  360. #define LPDDR4__PI_SWLVL_RD_SLICE_0__REG DENALI_PI_21
  361. #define LPDDR4__PI_SWLVL_RD_SLICE_0__FLD LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0
  362. #define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_MASK 0x00000100U
  363. #define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_SHIFT 8U
  364. #define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_WIDTH 1U
  365. #define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_WOCLR 0U
  366. #define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_WOSET 0U
  367. #define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_0__REG DENALI_PI_21
  368. #define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_0__FLD LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0
  369. #define LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_0_MASK 0x00030000U
  370. #define LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_0_SHIFT 16U
  371. #define LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_0_WIDTH 2U
  372. #define LPDDR4__PI_SW_WDQLVL_RESP_0__REG DENALI_PI_21
  373. #define LPDDR4__PI_SW_WDQLVL_RESP_0__FLD LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_0
  374. #define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_MASK 0x01000000U
  375. #define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_SHIFT 24U
  376. #define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_WIDTH 1U
  377. #define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_WOCLR 0U
  378. #define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_WOSET 0U
  379. #define LPDDR4__PI_SWLVL_WR_SLICE_1__REG DENALI_PI_21
  380. #define LPDDR4__PI_SWLVL_WR_SLICE_1__FLD LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1
  381. #define LPDDR4__DENALI_PI_22_READ_MASK 0x00030000U
  382. #define LPDDR4__DENALI_PI_22_WRITE_MASK 0x00030000U
  383. #define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_MASK 0x00000001U
  384. #define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_SHIFT 0U
  385. #define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_WIDTH 1U
  386. #define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_WOCLR 0U
  387. #define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_WOSET 0U
  388. #define LPDDR4__PI_SWLVL_RD_SLICE_1__REG DENALI_PI_22
  389. #define LPDDR4__PI_SWLVL_RD_SLICE_1__FLD LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1
  390. #define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_MASK 0x00000100U
  391. #define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_SHIFT 8U
  392. #define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_WIDTH 1U
  393. #define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_WOCLR 0U
  394. #define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_WOSET 0U
  395. #define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_1__REG DENALI_PI_22
  396. #define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_1__FLD LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1
  397. #define LPDDR4__DENALI_PI_22__PI_SW_WDQLVL_RESP_1_MASK 0x00030000U
  398. #define LPDDR4__DENALI_PI_22__PI_SW_WDQLVL_RESP_1_SHIFT 16U
  399. #define LPDDR4__DENALI_PI_22__PI_SW_WDQLVL_RESP_1_WIDTH 2U
  400. #define LPDDR4__PI_SW_WDQLVL_RESP_1__REG DENALI_PI_22
  401. #define LPDDR4__PI_SW_WDQLVL_RESP_1__FLD LPDDR4__DENALI_PI_22__PI_SW_WDQLVL_RESP_1
  402. #define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_MASK 0x01000000U
  403. #define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_SHIFT 24U
  404. #define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_WIDTH 1U
  405. #define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_WOCLR 0U
  406. #define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_WOSET 0U
  407. #define LPDDR4__PI_SWLVL_WR_SLICE_2__REG DENALI_PI_22
  408. #define LPDDR4__PI_SWLVL_WR_SLICE_2__FLD LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2
  409. #define LPDDR4__DENALI_PI_23_READ_MASK 0x00030000U
  410. #define LPDDR4__DENALI_PI_23_WRITE_MASK 0x00030000U
  411. #define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_MASK 0x00000001U
  412. #define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_SHIFT 0U
  413. #define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_WIDTH 1U
  414. #define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_WOCLR 0U
  415. #define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_WOSET 0U
  416. #define LPDDR4__PI_SWLVL_RD_SLICE_2__REG DENALI_PI_23
  417. #define LPDDR4__PI_SWLVL_RD_SLICE_2__FLD LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2
  418. #define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_MASK 0x00000100U
  419. #define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_SHIFT 8U
  420. #define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_WIDTH 1U
  421. #define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_WOCLR 0U
  422. #define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_WOSET 0U
  423. #define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_2__REG DENALI_PI_23
  424. #define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_2__FLD LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2
  425. #define LPDDR4__DENALI_PI_23__PI_SW_WDQLVL_RESP_2_MASK 0x00030000U
  426. #define LPDDR4__DENALI_PI_23__PI_SW_WDQLVL_RESP_2_SHIFT 16U
  427. #define LPDDR4__DENALI_PI_23__PI_SW_WDQLVL_RESP_2_WIDTH 2U
  428. #define LPDDR4__PI_SW_WDQLVL_RESP_2__REG DENALI_PI_23
  429. #define LPDDR4__PI_SW_WDQLVL_RESP_2__FLD LPDDR4__DENALI_PI_23__PI_SW_WDQLVL_RESP_2
  430. #define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_MASK 0x01000000U
  431. #define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_SHIFT 24U
  432. #define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_WIDTH 1U
  433. #define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_WOCLR 0U
  434. #define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_WOSET 0U
  435. #define LPDDR4__PI_SWLVL_WR_SLICE_3__REG DENALI_PI_23
  436. #define LPDDR4__PI_SWLVL_WR_SLICE_3__FLD LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3
  437. #define LPDDR4__DENALI_PI_24_READ_MASK 0x00030000U
  438. #define LPDDR4__DENALI_PI_24_WRITE_MASK 0x00030000U
  439. #define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_MASK 0x00000001U
  440. #define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_SHIFT 0U
  441. #define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_WIDTH 1U
  442. #define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_WOCLR 0U
  443. #define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_WOSET 0U
  444. #define LPDDR4__PI_SWLVL_RD_SLICE_3__REG DENALI_PI_24
  445. #define LPDDR4__PI_SWLVL_RD_SLICE_3__FLD LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3
  446. #define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_MASK 0x00000100U
  447. #define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_SHIFT 8U
  448. #define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_WIDTH 1U
  449. #define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_WOCLR 0U
  450. #define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_WOSET 0U
  451. #define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_3__REG DENALI_PI_24
  452. #define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_3__FLD LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3
  453. #define LPDDR4__DENALI_PI_24__PI_SW_WDQLVL_RESP_3_MASK 0x00030000U
  454. #define LPDDR4__DENALI_PI_24__PI_SW_WDQLVL_RESP_3_SHIFT 16U
  455. #define LPDDR4__DENALI_PI_24__PI_SW_WDQLVL_RESP_3_WIDTH 2U
  456. #define LPDDR4__PI_SW_WDQLVL_RESP_3__REG DENALI_PI_24
  457. #define LPDDR4__PI_SW_WDQLVL_RESP_3__FLD LPDDR4__DENALI_PI_24__PI_SW_WDQLVL_RESP_3
  458. #define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_MASK 0x01000000U
  459. #define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_SHIFT 24U
  460. #define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_WIDTH 1U
  461. #define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_WOCLR 0U
  462. #define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_WOSET 0U
  463. #define LPDDR4__PI_SWLVL_SM2_START__REG DENALI_PI_24
  464. #define LPDDR4__PI_SWLVL_SM2_START__FLD LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START
  465. #define LPDDR4__DENALI_PI_25_READ_MASK 0x01000000U
  466. #define LPDDR4__DENALI_PI_25_WRITE_MASK 0x01000000U
  467. #define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_MASK 0x00000001U
  468. #define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_SHIFT 0U
  469. #define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_WIDTH 1U
  470. #define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_WOCLR 0U
  471. #define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_WOSET 0U
  472. #define LPDDR4__PI_SWLVL_SM2_WR__REG DENALI_PI_25
  473. #define LPDDR4__PI_SWLVL_SM2_WR__FLD LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR
  474. #define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_MASK 0x00000100U
  475. #define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_SHIFT 8U
  476. #define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_WIDTH 1U
  477. #define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_WOCLR 0U
  478. #define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_WOSET 0U
  479. #define LPDDR4__PI_SWLVL_SM2_RD__REG DENALI_PI_25
  480. #define LPDDR4__PI_SWLVL_SM2_RD__FLD LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD
  481. #define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_MASK 0x00010000U
  482. #define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_SHIFT 16U
  483. #define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_WIDTH 1U
  484. #define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_WOCLR 0U
  485. #define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_WOSET 0U
  486. #define LPDDR4__PI_SEQUENTIAL_LVL_REQ__REG DENALI_PI_25
  487. #define LPDDR4__PI_SEQUENTIAL_LVL_REQ__FLD LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ
  488. #define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_MASK 0x01000000U
  489. #define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_SHIFT 24U
  490. #define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_WIDTH 1U
  491. #define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_WOCLR 0U
  492. #define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_WOSET 0U
  493. #define LPDDR4__PI_DFS_PERIOD_EN__REG DENALI_PI_25
  494. #define LPDDR4__PI_DFS_PERIOD_EN__FLD LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN
  495. #define LPDDR4__DENALI_PI_26_READ_MASK 0x00010101U
  496. #define LPDDR4__DENALI_PI_26_WRITE_MASK 0x00010101U
  497. #define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_MASK 0x00000001U
  498. #define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_SHIFT 0U
  499. #define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_WIDTH 1U
  500. #define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_WOCLR 0U
  501. #define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_WOSET 0U
  502. #define LPDDR4__PI_SRE_PERIOD_EN__REG DENALI_PI_26
  503. #define LPDDR4__PI_SRE_PERIOD_EN__FLD LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN
  504. #define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_MASK 0x00000100U
  505. #define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_SHIFT 8U
  506. #define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_WIDTH 1U
  507. #define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_WOCLR 0U
  508. #define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_WOSET 0U
  509. #define LPDDR4__PI_DFI40_POLARITY__REG DENALI_PI_26
  510. #define LPDDR4__PI_DFI40_POLARITY__FLD LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY
  511. #define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_MASK 0x00010000U
  512. #define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_SHIFT 16U
  513. #define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_WIDTH 1U
  514. #define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_WOCLR 0U
  515. #define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_WOSET 0U
  516. #define LPDDR4__PI_16BIT_DRAM_CONNECT__REG DENALI_PI_26
  517. #define LPDDR4__PI_16BIT_DRAM_CONNECT__FLD LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT
  518. #define LPDDR4__DENALI_PI_26__PI_WRLVL_REQ_MASK 0x01000000U
  519. #define LPDDR4__DENALI_PI_26__PI_WRLVL_REQ_SHIFT 24U
  520. #define LPDDR4__DENALI_PI_26__PI_WRLVL_REQ_WIDTH 1U
  521. #define LPDDR4__DENALI_PI_26__PI_WRLVL_REQ_WOCLR 0U
  522. #define LPDDR4__DENALI_PI_26__PI_WRLVL_REQ_WOSET 0U
  523. #define LPDDR4__PI_WRLVL_REQ__REG DENALI_PI_26
  524. #define LPDDR4__PI_WRLVL_REQ__FLD LPDDR4__DENALI_PI_26__PI_WRLVL_REQ
  525. #define LPDDR4__DENALI_PI_27_READ_MASK 0x003F3F03U
  526. #define LPDDR4__DENALI_PI_27_WRITE_MASK 0x003F3F03U
  527. #define LPDDR4__DENALI_PI_27__PI_WRLVL_CS_MASK 0x00000003U
  528. #define LPDDR4__DENALI_PI_27__PI_WRLVL_CS_SHIFT 0U
  529. #define LPDDR4__DENALI_PI_27__PI_WRLVL_CS_WIDTH 2U
  530. #define LPDDR4__PI_WRLVL_CS__REG DENALI_PI_27
  531. #define LPDDR4__PI_WRLVL_CS__FLD LPDDR4__DENALI_PI_27__PI_WRLVL_CS
  532. #define LPDDR4__DENALI_PI_27__PI_WLDQSEN_MASK 0x00003F00U
  533. #define LPDDR4__DENALI_PI_27__PI_WLDQSEN_SHIFT 8U
  534. #define LPDDR4__DENALI_PI_27__PI_WLDQSEN_WIDTH 6U
  535. #define LPDDR4__PI_WLDQSEN__REG DENALI_PI_27
  536. #define LPDDR4__PI_WLDQSEN__FLD LPDDR4__DENALI_PI_27__PI_WLDQSEN
  537. #define LPDDR4__DENALI_PI_27__PI_WLMRD_MASK 0x003F0000U
  538. #define LPDDR4__DENALI_PI_27__PI_WLMRD_SHIFT 16U
  539. #define LPDDR4__DENALI_PI_27__PI_WLMRD_WIDTH 6U
  540. #define LPDDR4__PI_WLMRD__REG DENALI_PI_27
  541. #define LPDDR4__PI_WLMRD__FLD LPDDR4__DENALI_PI_27__PI_WLMRD
  542. #define LPDDR4__DENALI_PI_28_READ_MASK 0x0101FFFFU
  543. #define LPDDR4__DENALI_PI_28_WRITE_MASK 0x0101FFFFU
  544. #define LPDDR4__DENALI_PI_28__PI_WRLVL_INTERVAL_MASK 0x0000FFFFU
  545. #define LPDDR4__DENALI_PI_28__PI_WRLVL_INTERVAL_SHIFT 0U
  546. #define LPDDR4__DENALI_PI_28__PI_WRLVL_INTERVAL_WIDTH 16U
  547. #define LPDDR4__PI_WRLVL_INTERVAL__REG DENALI_PI_28
  548. #define LPDDR4__PI_WRLVL_INTERVAL__FLD LPDDR4__DENALI_PI_28__PI_WRLVL_INTERVAL
  549. #define LPDDR4__DENALI_PI_28__PI_WRLVL_PERIODIC_MASK 0x00010000U
  550. #define LPDDR4__DENALI_PI_28__PI_WRLVL_PERIODIC_SHIFT 16U
  551. #define LPDDR4__DENALI_PI_28__PI_WRLVL_PERIODIC_WIDTH 1U
  552. #define LPDDR4__DENALI_PI_28__PI_WRLVL_PERIODIC_WOCLR 0U
  553. #define LPDDR4__DENALI_PI_28__PI_WRLVL_PERIODIC_WOSET 0U
  554. #define LPDDR4__PI_WRLVL_PERIODIC__REG DENALI_PI_28
  555. #define LPDDR4__PI_WRLVL_PERIODIC__FLD LPDDR4__DENALI_PI_28__PI_WRLVL_PERIODIC
  556. #define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_MASK 0x01000000U
  557. #define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_SHIFT 24U
  558. #define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_WIDTH 1U
  559. #define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_WOCLR 0U
  560. #define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_WOSET 0U
  561. #define LPDDR4__PI_WRLVL_ON_SREF_EXIT__REG DENALI_PI_28
  562. #define LPDDR4__PI_WRLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT
  563. #define LPDDR4__DENALI_PI_29_READ_MASK 0x0F010F01U
  564. #define LPDDR4__DENALI_PI_29_WRITE_MASK 0x0F010F01U
  565. #define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_MASK 0x00000001U
  566. #define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_SHIFT 0U
  567. #define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_WIDTH 1U
  568. #define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_WOCLR 0U
  569. #define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_WOSET 0U
  570. #define LPDDR4__PI_WRLVL_DISABLE_DFS__REG DENALI_PI_29
  571. #define LPDDR4__PI_WRLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS
  572. #define LPDDR4__DENALI_PI_29__PI_WRLVL_RESP_MASK_MASK 0x00000F00U
  573. #define LPDDR4__DENALI_PI_29__PI_WRLVL_RESP_MASK_SHIFT 8U
  574. #define LPDDR4__DENALI_PI_29__PI_WRLVL_RESP_MASK_WIDTH 4U
  575. #define LPDDR4__PI_WRLVL_RESP_MASK__REG DENALI_PI_29
  576. #define LPDDR4__PI_WRLVL_RESP_MASK__FLD LPDDR4__DENALI_PI_29__PI_WRLVL_RESP_MASK
  577. #define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_MASK 0x00010000U
  578. #define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_SHIFT 16U
  579. #define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_WIDTH 1U
  580. #define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_WOCLR 0U
  581. #define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_WOSET 0U
  582. #define LPDDR4__PI_WRLVL_ROTATE__REG DENALI_PI_29
  583. #define LPDDR4__PI_WRLVL_ROTATE__FLD LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE
  584. #define LPDDR4__DENALI_PI_29__PI_WRLVL_CS_MAP_MASK 0x0F000000U
  585. #define LPDDR4__DENALI_PI_29__PI_WRLVL_CS_MAP_SHIFT 24U
  586. #define LPDDR4__DENALI_PI_29__PI_WRLVL_CS_MAP_WIDTH 4U
  587. #define LPDDR4__PI_WRLVL_CS_MAP__REG DENALI_PI_29
  588. #define LPDDR4__PI_WRLVL_CS_MAP__FLD LPDDR4__DENALI_PI_29__PI_WRLVL_CS_MAP
  589. #define LPDDR4__DENALI_PI_30_READ_MASK 0x0000FF01U
  590. #define LPDDR4__DENALI_PI_30_WRITE_MASK 0x0000FF01U
  591. #define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_MASK 0x00000001U
  592. #define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_SHIFT 0U
  593. #define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_WIDTH 1U
  594. #define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_WOCLR 0U
  595. #define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_WOSET 0U
  596. #define LPDDR4__PI_WRLVL_ERROR_STATUS__REG DENALI_PI_30
  597. #define LPDDR4__PI_WRLVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS
  598. #define LPDDR4__DENALI_PI_30__PI_TDFI_WRLVL_EN_MASK 0x0000FF00U
  599. #define LPDDR4__DENALI_PI_30__PI_TDFI_WRLVL_EN_SHIFT 8U
  600. #define LPDDR4__DENALI_PI_30__PI_TDFI_WRLVL_EN_WIDTH 8U
  601. #define LPDDR4__PI_TDFI_WRLVL_EN__REG DENALI_PI_30
  602. #define LPDDR4__PI_TDFI_WRLVL_EN__FLD LPDDR4__DENALI_PI_30__PI_TDFI_WRLVL_EN
  603. #define LPDDR4__DENALI_PI_31_READ_MASK 0xFFFFFFFFU
  604. #define LPDDR4__DENALI_PI_31_WRITE_MASK 0xFFFFFFFFU
  605. #define LPDDR4__DENALI_PI_31__PI_TDFI_WRLVL_RESP_MASK 0xFFFFFFFFU
  606. #define LPDDR4__DENALI_PI_31__PI_TDFI_WRLVL_RESP_SHIFT 0U
  607. #define LPDDR4__DENALI_PI_31__PI_TDFI_WRLVL_RESP_WIDTH 32U
  608. #define LPDDR4__PI_TDFI_WRLVL_RESP__REG DENALI_PI_31
  609. #define LPDDR4__PI_TDFI_WRLVL_RESP__FLD LPDDR4__DENALI_PI_31__PI_TDFI_WRLVL_RESP
  610. #define LPDDR4__DENALI_PI_32_READ_MASK 0xFFFFFFFFU
  611. #define LPDDR4__DENALI_PI_32_WRITE_MASK 0xFFFFFFFFU
  612. #define LPDDR4__DENALI_PI_32__PI_TDFI_WRLVL_MAX_MASK 0xFFFFFFFFU
  613. #define LPDDR4__DENALI_PI_32__PI_TDFI_WRLVL_MAX_SHIFT 0U
  614. #define LPDDR4__DENALI_PI_32__PI_TDFI_WRLVL_MAX_WIDTH 32U
  615. #define LPDDR4__PI_TDFI_WRLVL_MAX__REG DENALI_PI_32
  616. #define LPDDR4__PI_TDFI_WRLVL_MAX__FLD LPDDR4__DENALI_PI_32__PI_TDFI_WRLVL_MAX
  617. #define LPDDR4__DENALI_PI_33_READ_MASK 0x0F0F0F1FU
  618. #define LPDDR4__DENALI_PI_33_WRITE_MASK 0x0F0F0F1FU
  619. #define LPDDR4__DENALI_PI_33__PI_WRLVL_STROBE_NUM_MASK 0x0000001FU
  620. #define LPDDR4__DENALI_PI_33__PI_WRLVL_STROBE_NUM_SHIFT 0U
  621. #define LPDDR4__DENALI_PI_33__PI_WRLVL_STROBE_NUM_WIDTH 5U
  622. #define LPDDR4__PI_WRLVL_STROBE_NUM__REG DENALI_PI_33
  623. #define LPDDR4__PI_WRLVL_STROBE_NUM__FLD LPDDR4__DENALI_PI_33__PI_WRLVL_STROBE_NUM
  624. #define LPDDR4__DENALI_PI_33__PI_TODTH_WR_MASK 0x00000F00U
  625. #define LPDDR4__DENALI_PI_33__PI_TODTH_WR_SHIFT 8U
  626. #define LPDDR4__DENALI_PI_33__PI_TODTH_WR_WIDTH 4U
  627. #define LPDDR4__PI_TODTH_WR__REG DENALI_PI_33
  628. #define LPDDR4__PI_TODTH_WR__FLD LPDDR4__DENALI_PI_33__PI_TODTH_WR
  629. #define LPDDR4__DENALI_PI_33__PI_TODTH_RD_MASK 0x000F0000U
  630. #define LPDDR4__DENALI_PI_33__PI_TODTH_RD_SHIFT 16U
  631. #define LPDDR4__DENALI_PI_33__PI_TODTH_RD_WIDTH 4U
  632. #define LPDDR4__PI_TODTH_RD__REG DENALI_PI_33
  633. #define LPDDR4__PI_TODTH_RD__FLD LPDDR4__DENALI_PI_33__PI_TODTH_RD
  634. #define LPDDR4__DENALI_PI_33__PI_ODT_VALUE_MASK 0x0F000000U
  635. #define LPDDR4__DENALI_PI_33__PI_ODT_VALUE_SHIFT 24U
  636. #define LPDDR4__DENALI_PI_33__PI_ODT_VALUE_WIDTH 4U
  637. #define LPDDR4__PI_ODT_VALUE__REG DENALI_PI_33
  638. #define LPDDR4__PI_ODT_VALUE__FLD LPDDR4__DENALI_PI_33__PI_ODT_VALUE
  639. #define LPDDR4__DENALI_PI_34_READ_MASK 0x00030000U
  640. #define LPDDR4__DENALI_PI_34_WRITE_MASK 0x00030000U
  641. #define LPDDR4__DENALI_PI_34__PI_RDLVL_REQ_MASK 0x00000001U
  642. #define LPDDR4__DENALI_PI_34__PI_RDLVL_REQ_SHIFT 0U
  643. #define LPDDR4__DENALI_PI_34__PI_RDLVL_REQ_WIDTH 1U
  644. #define LPDDR4__DENALI_PI_34__PI_RDLVL_REQ_WOCLR 0U
  645. #define LPDDR4__DENALI_PI_34__PI_RDLVL_REQ_WOSET 0U
  646. #define LPDDR4__PI_RDLVL_REQ__REG DENALI_PI_34
  647. #define LPDDR4__PI_RDLVL_REQ__FLD LPDDR4__DENALI_PI_34__PI_RDLVL_REQ
  648. #define LPDDR4__DENALI_PI_34__PI_RDLVL_GATE_REQ_MASK 0x00000100U
  649. #define LPDDR4__DENALI_PI_34__PI_RDLVL_GATE_REQ_SHIFT 8U
  650. #define LPDDR4__DENALI_PI_34__PI_RDLVL_GATE_REQ_WIDTH 1U
  651. #define LPDDR4__DENALI_PI_34__PI_RDLVL_GATE_REQ_WOCLR 0U
  652. #define LPDDR4__DENALI_PI_34__PI_RDLVL_GATE_REQ_WOSET 0U
  653. #define LPDDR4__PI_RDLVL_GATE_REQ__REG DENALI_PI_34
  654. #define LPDDR4__PI_RDLVL_GATE_REQ__FLD LPDDR4__DENALI_PI_34__PI_RDLVL_GATE_REQ
  655. #define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_MASK 0x00030000U
  656. #define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_SHIFT 16U
  657. #define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_WIDTH 2U
  658. #define LPDDR4__PI_RDLVL_CS__REG DENALI_PI_34
  659. #define LPDDR4__PI_RDLVL_CS__FLD LPDDR4__DENALI_PI_34__PI_RDLVL_CS
  660. #define LPDDR4__DENALI_PI_35_READ_MASK 0xFFFFFFFFU
  661. #define LPDDR4__DENALI_PI_35_WRITE_MASK 0xFFFFFFFFU
  662. #define LPDDR4__DENALI_PI_35__PI_RDLVL_PAT_0_MASK 0xFFFFFFFFU
  663. #define LPDDR4__DENALI_PI_35__PI_RDLVL_PAT_0_SHIFT 0U
  664. #define LPDDR4__DENALI_PI_35__PI_RDLVL_PAT_0_WIDTH 32U
  665. #define LPDDR4__PI_RDLVL_PAT_0__REG DENALI_PI_35
  666. #define LPDDR4__PI_RDLVL_PAT_0__FLD LPDDR4__DENALI_PI_35__PI_RDLVL_PAT_0
  667. #define LPDDR4__DENALI_PI_36_READ_MASK 0xFFFFFFFFU
  668. #define LPDDR4__DENALI_PI_36_WRITE_MASK 0xFFFFFFFFU
  669. #define LPDDR4__DENALI_PI_36__PI_RDLVL_PAT_1_MASK 0xFFFFFFFFU
  670. #define LPDDR4__DENALI_PI_36__PI_RDLVL_PAT_1_SHIFT 0U
  671. #define LPDDR4__DENALI_PI_36__PI_RDLVL_PAT_1_WIDTH 32U
  672. #define LPDDR4__PI_RDLVL_PAT_1__REG DENALI_PI_36
  673. #define LPDDR4__PI_RDLVL_PAT_1__FLD LPDDR4__DENALI_PI_36__PI_RDLVL_PAT_1
  674. #define LPDDR4__DENALI_PI_37_READ_MASK 0xFFFFFFFFU
  675. #define LPDDR4__DENALI_PI_37_WRITE_MASK 0xFFFFFFFFU
  676. #define LPDDR4__DENALI_PI_37__PI_RDLVL_PAT_2_MASK 0xFFFFFFFFU
  677. #define LPDDR4__DENALI_PI_37__PI_RDLVL_PAT_2_SHIFT 0U
  678. #define LPDDR4__DENALI_PI_37__PI_RDLVL_PAT_2_WIDTH 32U
  679. #define LPDDR4__PI_RDLVL_PAT_2__REG DENALI_PI_37
  680. #define LPDDR4__PI_RDLVL_PAT_2__FLD LPDDR4__DENALI_PI_37__PI_RDLVL_PAT_2
  681. #define LPDDR4__DENALI_PI_38_READ_MASK 0xFFFFFFFFU
  682. #define LPDDR4__DENALI_PI_38_WRITE_MASK 0xFFFFFFFFU
  683. #define LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_3_MASK 0xFFFFFFFFU
  684. #define LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_3_SHIFT 0U
  685. #define LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_3_WIDTH 32U
  686. #define LPDDR4__PI_RDLVL_PAT_3__REG DENALI_PI_38
  687. #define LPDDR4__PI_RDLVL_PAT_3__FLD LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_3
  688. #define LPDDR4__DENALI_PI_39_READ_MASK 0xFFFFFFFFU
  689. #define LPDDR4__DENALI_PI_39_WRITE_MASK 0xFFFFFFFFU
  690. #define LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_4_MASK 0xFFFFFFFFU
  691. #define LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_4_SHIFT 0U
  692. #define LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_4_WIDTH 32U
  693. #define LPDDR4__PI_RDLVL_PAT_4__REG DENALI_PI_39
  694. #define LPDDR4__PI_RDLVL_PAT_4__FLD LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_4
  695. #define LPDDR4__DENALI_PI_40_READ_MASK 0xFFFFFFFFU
  696. #define LPDDR4__DENALI_PI_40_WRITE_MASK 0xFFFFFFFFU
  697. #define LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_5_MASK 0xFFFFFFFFU
  698. #define LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_5_SHIFT 0U
  699. #define LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_5_WIDTH 32U
  700. #define LPDDR4__PI_RDLVL_PAT_5__REG DENALI_PI_40
  701. #define LPDDR4__PI_RDLVL_PAT_5__FLD LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_5
  702. #define LPDDR4__DENALI_PI_41_READ_MASK 0xFFFFFFFFU
  703. #define LPDDR4__DENALI_PI_41_WRITE_MASK 0xFFFFFFFFU
  704. #define LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_6_MASK 0xFFFFFFFFU
  705. #define LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_6_SHIFT 0U
  706. #define LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_6_WIDTH 32U
  707. #define LPDDR4__PI_RDLVL_PAT_6__REG DENALI_PI_41
  708. #define LPDDR4__PI_RDLVL_PAT_6__FLD LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_6
  709. #define LPDDR4__DENALI_PI_42_READ_MASK 0xFFFFFFFFU
  710. #define LPDDR4__DENALI_PI_42_WRITE_MASK 0xFFFFFFFFU
  711. #define LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_7_MASK 0xFFFFFFFFU
  712. #define LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_7_SHIFT 0U
  713. #define LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_7_WIDTH 32U
  714. #define LPDDR4__PI_RDLVL_PAT_7__REG DENALI_PI_42
  715. #define LPDDR4__PI_RDLVL_PAT_7__FLD LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_7
  716. #define LPDDR4__DENALI_PI_43_READ_MASK 0x0101010FU
  717. #define LPDDR4__DENALI_PI_43_WRITE_MASK 0x0101010FU
  718. #define LPDDR4__DENALI_PI_43__PI_RDLVL_SEQ_EN_MASK 0x0000000FU
  719. #define LPDDR4__DENALI_PI_43__PI_RDLVL_SEQ_EN_SHIFT 0U
  720. #define LPDDR4__DENALI_PI_43__PI_RDLVL_SEQ_EN_WIDTH 4U
  721. #define LPDDR4__PI_RDLVL_SEQ_EN__REG DENALI_PI_43
  722. #define LPDDR4__PI_RDLVL_SEQ_EN__FLD LPDDR4__DENALI_PI_43__PI_RDLVL_SEQ_EN
  723. #define LPDDR4__DENALI_PI_43__PI_RDLVL_PERIODIC_MASK 0x00000100U
  724. #define LPDDR4__DENALI_PI_43__PI_RDLVL_PERIODIC_SHIFT 8U
  725. #define LPDDR4__DENALI_PI_43__PI_RDLVL_PERIODIC_WIDTH 1U
  726. #define LPDDR4__DENALI_PI_43__PI_RDLVL_PERIODIC_WOCLR 0U
  727. #define LPDDR4__DENALI_PI_43__PI_RDLVL_PERIODIC_WOSET 0U
  728. #define LPDDR4__PI_RDLVL_PERIODIC__REG DENALI_PI_43
  729. #define LPDDR4__PI_RDLVL_PERIODIC__FLD LPDDR4__DENALI_PI_43__PI_RDLVL_PERIODIC
  730. #define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_MASK 0x00010000U
  731. #define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_SHIFT 16U
  732. #define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_WIDTH 1U
  733. #define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_WOCLR 0U
  734. #define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_WOSET 0U
  735. #define LPDDR4__PI_RDLVL_ON_SREF_EXIT__REG DENALI_PI_43
  736. #define LPDDR4__PI_RDLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT
  737. #define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_MASK 0x01000000U
  738. #define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_SHIFT 24U
  739. #define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_WIDTH 1U
  740. #define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_WOCLR 0U
  741. #define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_WOSET 0U
  742. #define LPDDR4__PI_RDLVL_DISABLE_DFS__REG DENALI_PI_43
  743. #define LPDDR4__PI_RDLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS
  744. #define LPDDR4__DENALI_PI_44_READ_MASK 0x01010101U
  745. #define LPDDR4__DENALI_PI_44_WRITE_MASK 0x01010101U
  746. #define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_PERIODIC_MASK 0x00000001U
  747. #define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_PERIODIC_SHIFT 0U
  748. #define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_PERIODIC_WIDTH 1U
  749. #define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_PERIODIC_WOCLR 0U
  750. #define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_PERIODIC_WOSET 0U
  751. #define LPDDR4__PI_RDLVL_GATE_PERIODIC__REG DENALI_PI_44
  752. #define LPDDR4__PI_RDLVL_GATE_PERIODIC__FLD LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_PERIODIC
  753. #define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_SREF_EXIT_MASK 0x00000100U
  754. #define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_SREF_EXIT_SHIFT 8U
  755. #define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_SREF_EXIT_WIDTH 1U
  756. #define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_SREF_EXIT_WOCLR 0U
  757. #define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_SREF_EXIT_WOSET 0U
  758. #define LPDDR4__PI_RDLVL_GATE_ON_SREF_EXIT__REG DENALI_PI_44
  759. #define LPDDR4__PI_RDLVL_GATE_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_SREF_EXIT
  760. #define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_MASK 0x00010000U
  761. #define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_SHIFT 16U
  762. #define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_WIDTH 1U
  763. #define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_WOCLR 0U
  764. #define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_WOSET 0U
  765. #define LPDDR4__PI_RDLVL_GATE_DISABLE_DFS__REG DENALI_PI_44
  766. #define LPDDR4__PI_RDLVL_GATE_DISABLE_DFS__FLD LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS
  767. #define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_MASK 0x01000000U
  768. #define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_SHIFT 24U
  769. #define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_WIDTH 1U
  770. #define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_WOCLR 0U
  771. #define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_WOSET 0U
  772. #define LPDDR4__PI_RDLVL_ROTATE__REG DENALI_PI_44
  773. #define LPDDR4__PI_RDLVL_ROTATE__FLD LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE
  774. #define LPDDR4__DENALI_PI_45_READ_MASK 0x000F0F01U
  775. #define LPDDR4__DENALI_PI_45_WRITE_MASK 0x000F0F01U
  776. #define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_MASK 0x00000001U
  777. #define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_SHIFT 0U
  778. #define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_WIDTH 1U
  779. #define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_WOCLR 0U
  780. #define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_WOSET 0U
  781. #define LPDDR4__PI_RDLVL_GATE_ROTATE__REG DENALI_PI_45
  782. #define LPDDR4__PI_RDLVL_GATE_ROTATE__FLD LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE
  783. #define LPDDR4__DENALI_PI_45__PI_RDLVL_CS_MAP_MASK 0x00000F00U
  784. #define LPDDR4__DENALI_PI_45__PI_RDLVL_CS_MAP_SHIFT 8U
  785. #define LPDDR4__DENALI_PI_45__PI_RDLVL_CS_MAP_WIDTH 4U
  786. #define LPDDR4__PI_RDLVL_CS_MAP__REG DENALI_PI_45
  787. #define LPDDR4__PI_RDLVL_CS_MAP__FLD LPDDR4__DENALI_PI_45__PI_RDLVL_CS_MAP
  788. #define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_CS_MAP_MASK 0x000F0000U
  789. #define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_CS_MAP_SHIFT 16U
  790. #define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_CS_MAP_WIDTH 4U
  791. #define LPDDR4__PI_RDLVL_GATE_CS_MAP__REG DENALI_PI_45
  792. #define LPDDR4__PI_RDLVL_GATE_CS_MAP__FLD LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_CS_MAP
  793. #define LPDDR4__DENALI_PI_46_READ_MASK 0x000003FFU
  794. #define LPDDR4__DENALI_PI_46_WRITE_MASK 0x000003FFU
  795. #define LPDDR4__DENALI_PI_46__PI_TDFI_RDLVL_RR_MASK 0x000003FFU
  796. #define LPDDR4__DENALI_PI_46__PI_TDFI_RDLVL_RR_SHIFT 0U
  797. #define LPDDR4__DENALI_PI_46__PI_TDFI_RDLVL_RR_WIDTH 10U
  798. #define LPDDR4__PI_TDFI_RDLVL_RR__REG DENALI_PI_46
  799. #define LPDDR4__PI_TDFI_RDLVL_RR__FLD LPDDR4__DENALI_PI_46__PI_TDFI_RDLVL_RR
  800. #define LPDDR4__DENALI_PI_47_READ_MASK 0xFFFFFFFFU
  801. #define LPDDR4__DENALI_PI_47_WRITE_MASK 0xFFFFFFFFU
  802. #define LPDDR4__DENALI_PI_47__PI_TDFI_RDLVL_RESP_MASK 0xFFFFFFFFU
  803. #define LPDDR4__DENALI_PI_47__PI_TDFI_RDLVL_RESP_SHIFT 0U
  804. #define LPDDR4__DENALI_PI_47__PI_TDFI_RDLVL_RESP_WIDTH 32U
  805. #define LPDDR4__PI_TDFI_RDLVL_RESP__REG DENALI_PI_47
  806. #define LPDDR4__PI_TDFI_RDLVL_RESP__FLD LPDDR4__DENALI_PI_47__PI_TDFI_RDLVL_RESP
  807. #define LPDDR4__DENALI_PI_48_READ_MASK 0x0000FF0FU
  808. #define LPDDR4__DENALI_PI_48_WRITE_MASK 0x0000FF0FU
  809. #define LPDDR4__DENALI_PI_48__PI_RDLVL_RESP_MASK_MASK 0x0000000FU
  810. #define LPDDR4__DENALI_PI_48__PI_RDLVL_RESP_MASK_SHIFT 0U
  811. #define LPDDR4__DENALI_PI_48__PI_RDLVL_RESP_MASK_WIDTH 4U
  812. #define LPDDR4__PI_RDLVL_RESP_MASK__REG DENALI_PI_48
  813. #define LPDDR4__PI_RDLVL_RESP_MASK__FLD LPDDR4__DENALI_PI_48__PI_RDLVL_RESP_MASK
  814. #define LPDDR4__DENALI_PI_48__PI_TDFI_RDLVL_EN_MASK 0x0000FF00U
  815. #define LPDDR4__DENALI_PI_48__PI_TDFI_RDLVL_EN_SHIFT 8U
  816. #define LPDDR4__DENALI_PI_48__PI_TDFI_RDLVL_EN_WIDTH 8U
  817. #define LPDDR4__PI_TDFI_RDLVL_EN__REG DENALI_PI_48
  818. #define LPDDR4__PI_TDFI_RDLVL_EN__FLD LPDDR4__DENALI_PI_48__PI_TDFI_RDLVL_EN
  819. #define LPDDR4__DENALI_PI_49_READ_MASK 0xFFFFFFFFU
  820. #define LPDDR4__DENALI_PI_49_WRITE_MASK 0xFFFFFFFFU
  821. #define LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_MAX_MASK 0xFFFFFFFFU
  822. #define LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_MAX_SHIFT 0U
  823. #define LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_MAX_WIDTH 32U
  824. #define LPDDR4__PI_TDFI_RDLVL_MAX__REG DENALI_PI_49
  825. #define LPDDR4__PI_TDFI_RDLVL_MAX__FLD LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_MAX
  826. #define LPDDR4__DENALI_PI_50_READ_MASK 0x00FFFF01U
  827. #define LPDDR4__DENALI_PI_50_WRITE_MASK 0x00FFFF01U
  828. #define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_MASK 0x00000001U
  829. #define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_SHIFT 0U
  830. #define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_WIDTH 1U
  831. #define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_WOCLR 0U
  832. #define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_WOSET 0U
  833. #define LPDDR4__PI_RDLVL_ERROR_STATUS__REG DENALI_PI_50
  834. #define LPDDR4__PI_RDLVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS
  835. #define LPDDR4__DENALI_PI_50__PI_RDLVL_INTERVAL_MASK 0x00FFFF00U
  836. #define LPDDR4__DENALI_PI_50__PI_RDLVL_INTERVAL_SHIFT 8U
  837. #define LPDDR4__DENALI_PI_50__PI_RDLVL_INTERVAL_WIDTH 16U
  838. #define LPDDR4__PI_RDLVL_INTERVAL__REG DENALI_PI_50
  839. #define LPDDR4__PI_RDLVL_INTERVAL__FLD LPDDR4__DENALI_PI_50__PI_RDLVL_INTERVAL
  840. #define LPDDR4__DENALI_PI_51_READ_MASK 0x0F0FFFFFU
  841. #define LPDDR4__DENALI_PI_51_WRITE_MASK 0x0F0FFFFFU
  842. #define LPDDR4__DENALI_PI_51__PI_RDLVL_GATE_INTERVAL_MASK 0x0000FFFFU
  843. #define LPDDR4__DENALI_PI_51__PI_RDLVL_GATE_INTERVAL_SHIFT 0U
  844. #define LPDDR4__DENALI_PI_51__PI_RDLVL_GATE_INTERVAL_WIDTH 16U
  845. #define LPDDR4__PI_RDLVL_GATE_INTERVAL__REG DENALI_PI_51
  846. #define LPDDR4__PI_RDLVL_GATE_INTERVAL__FLD LPDDR4__DENALI_PI_51__PI_RDLVL_GATE_INTERVAL
  847. #define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_START_MASK 0x000F0000U
  848. #define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_START_SHIFT 16U
  849. #define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_START_WIDTH 4U
  850. #define LPDDR4__PI_RDLVL_PATTERN_START__REG DENALI_PI_51
  851. #define LPDDR4__PI_RDLVL_PATTERN_START__FLD LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_START
  852. #define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_NUM_MASK 0x0F000000U
  853. #define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_NUM_SHIFT 24U
  854. #define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_NUM_WIDTH 4U
  855. #define LPDDR4__PI_RDLVL_PATTERN_NUM__REG DENALI_PI_51
  856. #define LPDDR4__PI_RDLVL_PATTERN_NUM__FLD LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_NUM
  857. #define LPDDR4__DENALI_PI_52_READ_MASK 0x01011F1FU
  858. #define LPDDR4__DENALI_PI_52_WRITE_MASK 0x01011F1FU
  859. #define LPDDR4__DENALI_PI_52__PI_RDLVL_STROBE_NUM_MASK 0x0000001FU
  860. #define LPDDR4__DENALI_PI_52__PI_RDLVL_STROBE_NUM_SHIFT 0U
  861. #define LPDDR4__DENALI_PI_52__PI_RDLVL_STROBE_NUM_WIDTH 5U
  862. #define LPDDR4__PI_RDLVL_STROBE_NUM__REG DENALI_PI_52
  863. #define LPDDR4__PI_RDLVL_STROBE_NUM__FLD LPDDR4__DENALI_PI_52__PI_RDLVL_STROBE_NUM
  864. #define LPDDR4__DENALI_PI_52__PI_RDLVL_GATE_STROBE_NUM_MASK 0x00001F00U
  865. #define LPDDR4__DENALI_PI_52__PI_RDLVL_GATE_STROBE_NUM_SHIFT 8U
  866. #define LPDDR4__DENALI_PI_52__PI_RDLVL_GATE_STROBE_NUM_WIDTH 5U
  867. #define LPDDR4__PI_RDLVL_GATE_STROBE_NUM__REG DENALI_PI_52
  868. #define LPDDR4__PI_RDLVL_GATE_STROBE_NUM__FLD LPDDR4__DENALI_PI_52__PI_RDLVL_GATE_STROBE_NUM
  869. #define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_MASK 0x00010000U
  870. #define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_SHIFT 16U
  871. #define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_WIDTH 1U
  872. #define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_WOCLR 0U
  873. #define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_WOSET 0U
  874. #define LPDDR4__PI_RD_PREAMBLE_TRAINING_EN__REG DENALI_PI_52
  875. #define LPDDR4__PI_RD_PREAMBLE_TRAINING_EN__FLD LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN
  876. #define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_MASK 0x01000000U
  877. #define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_SHIFT 24U
  878. #define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_WIDTH 1U
  879. #define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_WOCLR 0U
  880. #define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_WOSET 0U
  881. #define LPDDR4__PI_REG_DIMM_ENABLE__REG DENALI_PI_52
  882. #define LPDDR4__PI_REG_DIMM_ENABLE__FLD LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE
  883. #define LPDDR4__DENALI_PI_53_READ_MASK 0x03007F7FU
  884. #define LPDDR4__DENALI_PI_53_WRITE_MASK 0x03007F7FU
  885. #define LPDDR4__DENALI_PI_53__PI_TDFI_RDDATA_EN_MASK 0x0000007FU
  886. #define LPDDR4__DENALI_PI_53__PI_TDFI_RDDATA_EN_SHIFT 0U
  887. #define LPDDR4__DENALI_PI_53__PI_TDFI_RDDATA_EN_WIDTH 7U
  888. #define LPDDR4__PI_TDFI_RDDATA_EN__REG DENALI_PI_53
  889. #define LPDDR4__PI_TDFI_RDDATA_EN__FLD LPDDR4__DENALI_PI_53__PI_TDFI_RDDATA_EN
  890. #define LPDDR4__DENALI_PI_53__PI_TDFI_PHY_WRLAT_MASK 0x00007F00U
  891. #define LPDDR4__DENALI_PI_53__PI_TDFI_PHY_WRLAT_SHIFT 8U
  892. #define LPDDR4__DENALI_PI_53__PI_TDFI_PHY_WRLAT_WIDTH 7U
  893. #define LPDDR4__PI_TDFI_PHY_WRLAT__REG DENALI_PI_53
  894. #define LPDDR4__PI_TDFI_PHY_WRLAT__FLD LPDDR4__DENALI_PI_53__PI_TDFI_PHY_WRLAT
  895. #define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_MASK 0x00010000U
  896. #define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_SHIFT 16U
  897. #define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_WIDTH 1U
  898. #define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_WOCLR 0U
  899. #define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_WOSET 0U
  900. #define LPDDR4__PI_CALVL_REQ__REG DENALI_PI_53
  901. #define LPDDR4__PI_CALVL_REQ__FLD LPDDR4__DENALI_PI_53__PI_CALVL_REQ
  902. #define LPDDR4__DENALI_PI_53__PI_CALVL_CS_MASK 0x03000000U
  903. #define LPDDR4__DENALI_PI_53__PI_CALVL_CS_SHIFT 24U
  904. #define LPDDR4__DENALI_PI_53__PI_CALVL_CS_WIDTH 2U
  905. #define LPDDR4__PI_CALVL_CS__REG DENALI_PI_53
  906. #define LPDDR4__PI_CALVL_CS__FLD LPDDR4__DENALI_PI_53__PI_CALVL_CS
  907. #define LPDDR4__DENALI_PI_54_READ_MASK 0x01030F01U
  908. #define LPDDR4__DENALI_PI_54_WRITE_MASK 0x01030F01U
  909. #define LPDDR4__DENALI_PI_54__PI_RESERVED3_MASK 0x00000001U
  910. #define LPDDR4__DENALI_PI_54__PI_RESERVED3_SHIFT 0U
  911. #define LPDDR4__DENALI_PI_54__PI_RESERVED3_WIDTH 1U
  912. #define LPDDR4__DENALI_PI_54__PI_RESERVED3_WOCLR 0U
  913. #define LPDDR4__DENALI_PI_54__PI_RESERVED3_WOSET 0U
  914. #define LPDDR4__PI_RESERVED3__REG DENALI_PI_54
  915. #define LPDDR4__PI_RESERVED3__FLD LPDDR4__DENALI_PI_54__PI_RESERVED3
  916. #define LPDDR4__DENALI_PI_54__PI_RESERVED4_MASK 0x00000F00U
  917. #define LPDDR4__DENALI_PI_54__PI_RESERVED4_SHIFT 8U
  918. #define LPDDR4__DENALI_PI_54__PI_RESERVED4_WIDTH 4U
  919. #define LPDDR4__PI_RESERVED4__REG DENALI_PI_54
  920. #define LPDDR4__PI_RESERVED4__FLD LPDDR4__DENALI_PI_54__PI_RESERVED4
  921. #define LPDDR4__DENALI_PI_54__PI_CALVL_SEQ_EN_MASK 0x00030000U
  922. #define LPDDR4__DENALI_PI_54__PI_CALVL_SEQ_EN_SHIFT 16U
  923. #define LPDDR4__DENALI_PI_54__PI_CALVL_SEQ_EN_WIDTH 2U
  924. #define LPDDR4__PI_CALVL_SEQ_EN__REG DENALI_PI_54
  925. #define LPDDR4__PI_CALVL_SEQ_EN__FLD LPDDR4__DENALI_PI_54__PI_CALVL_SEQ_EN
  926. #define LPDDR4__DENALI_PI_54__PI_CALVL_PERIODIC_MASK 0x01000000U
  927. #define LPDDR4__DENALI_PI_54__PI_CALVL_PERIODIC_SHIFT 24U
  928. #define LPDDR4__DENALI_PI_54__PI_CALVL_PERIODIC_WIDTH 1U
  929. #define LPDDR4__DENALI_PI_54__PI_CALVL_PERIODIC_WOCLR 0U
  930. #define LPDDR4__DENALI_PI_54__PI_CALVL_PERIODIC_WOSET 0U
  931. #define LPDDR4__PI_CALVL_PERIODIC__REG DENALI_PI_54
  932. #define LPDDR4__PI_CALVL_PERIODIC__FLD LPDDR4__DENALI_PI_54__PI_CALVL_PERIODIC
  933. #define LPDDR4__DENALI_PI_55_READ_MASK 0x0F010101U
  934. #define LPDDR4__DENALI_PI_55_WRITE_MASK 0x0F010101U
  935. #define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_MASK 0x00000001U
  936. #define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_SHIFT 0U
  937. #define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_WIDTH 1U
  938. #define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_WOCLR 0U
  939. #define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_WOSET 0U
  940. #define LPDDR4__PI_CALVL_ON_SREF_EXIT__REG DENALI_PI_55
  941. #define LPDDR4__PI_CALVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT
  942. #define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_MASK 0x00000100U
  943. #define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_SHIFT 8U
  944. #define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_WIDTH 1U
  945. #define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_WOCLR 0U
  946. #define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_WOSET 0U
  947. #define LPDDR4__PI_CALVL_DISABLE_DFS__REG DENALI_PI_55
  948. #define LPDDR4__PI_CALVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS
  949. #define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_MASK 0x00010000U
  950. #define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_SHIFT 16U
  951. #define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_WIDTH 1U
  952. #define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_WOCLR 0U
  953. #define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_WOSET 0U
  954. #define LPDDR4__PI_CALVL_ROTATE__REG DENALI_PI_55
  955. #define LPDDR4__PI_CALVL_ROTATE__FLD LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE
  956. #define LPDDR4__DENALI_PI_55__PI_CALVL_CS_MAP_MASK 0x0F000000U
  957. #define LPDDR4__DENALI_PI_55__PI_CALVL_CS_MAP_SHIFT 24U
  958. #define LPDDR4__DENALI_PI_55__PI_CALVL_CS_MAP_WIDTH 4U
  959. #define LPDDR4__PI_CALVL_CS_MAP__REG DENALI_PI_55
  960. #define LPDDR4__PI_CALVL_CS_MAP__FLD LPDDR4__DENALI_PI_55__PI_CALVL_CS_MAP
  961. #define LPDDR4__DENALI_PI_56_READ_MASK 0x000000FFU
  962. #define LPDDR4__DENALI_PI_56_WRITE_MASK 0x000000FFU
  963. #define LPDDR4__DENALI_PI_56__PI_TDFI_CALVL_EN_MASK 0x000000FFU
  964. #define LPDDR4__DENALI_PI_56__PI_TDFI_CALVL_EN_SHIFT 0U
  965. #define LPDDR4__DENALI_PI_56__PI_TDFI_CALVL_EN_WIDTH 8U
  966. #define LPDDR4__PI_TDFI_CALVL_EN__REG DENALI_PI_56
  967. #define LPDDR4__PI_TDFI_CALVL_EN__FLD LPDDR4__DENALI_PI_56__PI_TDFI_CALVL_EN
  968. #define LPDDR4__DENALI_PI_57_READ_MASK 0xFFFFFFFFU
  969. #define LPDDR4__DENALI_PI_57_WRITE_MASK 0xFFFFFFFFU
  970. #define LPDDR4__DENALI_PI_57__PI_TDFI_CALVL_RESP_MASK 0xFFFFFFFFU
  971. #define LPDDR4__DENALI_PI_57__PI_TDFI_CALVL_RESP_SHIFT 0U
  972. #define LPDDR4__DENALI_PI_57__PI_TDFI_CALVL_RESP_WIDTH 32U
  973. #define LPDDR4__PI_TDFI_CALVL_RESP__REG DENALI_PI_57
  974. #define LPDDR4__PI_TDFI_CALVL_RESP__FLD LPDDR4__DENALI_PI_57__PI_TDFI_CALVL_RESP
  975. #define LPDDR4__DENALI_PI_58_READ_MASK 0xFFFFFFFFU
  976. #define LPDDR4__DENALI_PI_58_WRITE_MASK 0xFFFFFFFFU
  977. #define LPDDR4__DENALI_PI_58__PI_TDFI_CALVL_MAX_MASK 0xFFFFFFFFU
  978. #define LPDDR4__DENALI_PI_58__PI_TDFI_CALVL_MAX_SHIFT 0U
  979. #define LPDDR4__DENALI_PI_58__PI_TDFI_CALVL_MAX_WIDTH 32U
  980. #define LPDDR4__PI_TDFI_CALVL_MAX__REG DENALI_PI_58
  981. #define LPDDR4__PI_TDFI_CALVL_MAX__FLD LPDDR4__DENALI_PI_58__PI_TDFI_CALVL_MAX
  982. #define LPDDR4__DENALI_PI_59_READ_MASK 0xFFFF0301U
  983. #define LPDDR4__DENALI_PI_59_WRITE_MASK 0xFFFF0301U
  984. #define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_MASK 0x00000001U
  985. #define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_SHIFT 0U
  986. #define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_WIDTH 1U
  987. #define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_WOCLR 0U
  988. #define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_WOSET 0U
  989. #define LPDDR4__PI_CALVL_RESP_MASK__REG DENALI_PI_59
  990. #define LPDDR4__PI_CALVL_RESP_MASK__FLD LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK
  991. #define LPDDR4__DENALI_PI_59__PI_CALVL_ERROR_STATUS_MASK 0x00000300U
  992. #define LPDDR4__DENALI_PI_59__PI_CALVL_ERROR_STATUS_SHIFT 8U
  993. #define LPDDR4__DENALI_PI_59__PI_CALVL_ERROR_STATUS_WIDTH 2U
  994. #define LPDDR4__PI_CALVL_ERROR_STATUS__REG DENALI_PI_59
  995. #define LPDDR4__PI_CALVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_59__PI_CALVL_ERROR_STATUS
  996. #define LPDDR4__DENALI_PI_59__PI_CALVL_INTERVAL_MASK 0xFFFF0000U
  997. #define LPDDR4__DENALI_PI_59__PI_CALVL_INTERVAL_SHIFT 16U
  998. #define LPDDR4__DENALI_PI_59__PI_CALVL_INTERVAL_WIDTH 16U
  999. #define LPDDR4__PI_CALVL_INTERVAL__REG DENALI_PI_59
  1000. #define LPDDR4__PI_CALVL_INTERVAL__FLD LPDDR4__DENALI_PI_59__PI_CALVL_INTERVAL
  1001. #define LPDDR4__DENALI_PI_60_READ_MASK 0x1F1F3F1FU
  1002. #define LPDDR4__DENALI_PI_60_WRITE_MASK 0x1F1F3F1FU
  1003. #define LPDDR4__DENALI_PI_60__PI_TCACKEL_MASK 0x0000001FU
  1004. #define LPDDR4__DENALI_PI_60__PI_TCACKEL_SHIFT 0U
  1005. #define LPDDR4__DENALI_PI_60__PI_TCACKEL_WIDTH 5U
  1006. #define LPDDR4__PI_TCACKEL__REG DENALI_PI_60
  1007. #define LPDDR4__PI_TCACKEL__FLD LPDDR4__DENALI_PI_60__PI_TCACKEL
  1008. #define LPDDR4__DENALI_PI_60__PI_TCAMRD_MASK 0x00003F00U
  1009. #define LPDDR4__DENALI_PI_60__PI_TCAMRD_SHIFT 8U
  1010. #define LPDDR4__DENALI_PI_60__PI_TCAMRD_WIDTH 6U
  1011. #define LPDDR4__PI_TCAMRD__REG DENALI_PI_60
  1012. #define LPDDR4__PI_TCAMRD__FLD LPDDR4__DENALI_PI_60__PI_TCAMRD
  1013. #define LPDDR4__DENALI_PI_60__PI_TCACKEH_MASK 0x001F0000U
  1014. #define LPDDR4__DENALI_PI_60__PI_TCACKEH_SHIFT 16U
  1015. #define LPDDR4__DENALI_PI_60__PI_TCACKEH_WIDTH 5U
  1016. #define LPDDR4__PI_TCACKEH__REG DENALI_PI_60
  1017. #define LPDDR4__PI_TCACKEH__FLD LPDDR4__DENALI_PI_60__PI_TCACKEH
  1018. #define LPDDR4__DENALI_PI_60__PI_TCAEXT_MASK 0x1F000000U
  1019. #define LPDDR4__DENALI_PI_60__PI_TCAEXT_SHIFT 24U
  1020. #define LPDDR4__DENALI_PI_60__PI_TCAEXT_WIDTH 5U
  1021. #define LPDDR4__PI_TCAEXT__REG DENALI_PI_60
  1022. #define LPDDR4__PI_TCAEXT__FLD LPDDR4__DENALI_PI_60__PI_TCAEXT
  1023. #define LPDDR4__DENALI_PI_61_READ_MASK 0xFF0F0F01U
  1024. #define LPDDR4__DENALI_PI_61_WRITE_MASK 0xFF0F0F01U
  1025. #define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_MASK 0x00000001U
  1026. #define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_SHIFT 0U
  1027. #define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_WIDTH 1U
  1028. #define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_WOCLR 0U
  1029. #define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_WOSET 0U
  1030. #define LPDDR4__PI_CA_TRAIN_VREF_EN__REG DENALI_PI_61
  1031. #define LPDDR4__PI_CA_TRAIN_VREF_EN__FLD LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN
  1032. #define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_INITIAL_STEPSIZE_MASK 0x00000F00U
  1033. #define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_INITIAL_STEPSIZE_SHIFT 8U
  1034. #define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_INITIAL_STEPSIZE_WIDTH 4U
  1035. #define LPDDR4__PI_CALVL_VREF_INITIAL_STEPSIZE__REG DENALI_PI_61
  1036. #define LPDDR4__PI_CALVL_VREF_INITIAL_STEPSIZE__FLD LPDDR4__DENALI_PI_61__PI_CALVL_VREF_INITIAL_STEPSIZE
  1037. #define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_NORMAL_STEPSIZE_MASK 0x000F0000U
  1038. #define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_NORMAL_STEPSIZE_SHIFT 16U
  1039. #define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_NORMAL_STEPSIZE_WIDTH 4U
  1040. #define LPDDR4__PI_CALVL_VREF_NORMAL_STEPSIZE__REG DENALI_PI_61
  1041. #define LPDDR4__PI_CALVL_VREF_NORMAL_STEPSIZE__FLD LPDDR4__DENALI_PI_61__PI_CALVL_VREF_NORMAL_STEPSIZE
  1042. #define LPDDR4__DENALI_PI_61__PI_TDFI_INIT_START_MIN_MASK 0xFF000000U
  1043. #define LPDDR4__DENALI_PI_61__PI_TDFI_INIT_START_MIN_SHIFT 24U
  1044. #define LPDDR4__DENALI_PI_61__PI_TDFI_INIT_START_MIN_WIDTH 8U
  1045. #define LPDDR4__PI_TDFI_INIT_START_MIN__REG DENALI_PI_61
  1046. #define LPDDR4__PI_TDFI_INIT_START_MIN__FLD LPDDR4__DENALI_PI_61__PI_TDFI_INIT_START_MIN
  1047. #define LPDDR4__DENALI_PI_62_READ_MASK 0x7F1F0FFFU
  1048. #define LPDDR4__DENALI_PI_62_WRITE_MASK 0x7F1F0FFFU
  1049. #define LPDDR4__DENALI_PI_62__PI_TDFI_INIT_COMPLETE_MIN_MASK 0x000000FFU
  1050. #define LPDDR4__DENALI_PI_62__PI_TDFI_INIT_COMPLETE_MIN_SHIFT 0U
  1051. #define LPDDR4__DENALI_PI_62__PI_TDFI_INIT_COMPLETE_MIN_WIDTH 8U
  1052. #define LPDDR4__PI_TDFI_INIT_COMPLETE_MIN__REG DENALI_PI_62
  1053. #define LPDDR4__PI_TDFI_INIT_COMPLETE_MIN__FLD LPDDR4__DENALI_PI_62__PI_TDFI_INIT_COMPLETE_MIN
  1054. #define LPDDR4__DENALI_PI_62__PI_TCKCKEH_MASK 0x00000F00U
  1055. #define LPDDR4__DENALI_PI_62__PI_TCKCKEH_SHIFT 8U
  1056. #define LPDDR4__DENALI_PI_62__PI_TCKCKEH_WIDTH 4U
  1057. #define LPDDR4__PI_TCKCKEH__REG DENALI_PI_62
  1058. #define LPDDR4__PI_TCKCKEH__FLD LPDDR4__DENALI_PI_62__PI_TCKCKEH
  1059. #define LPDDR4__DENALI_PI_62__PI_CALVL_STROBE_NUM_MASK 0x001F0000U
  1060. #define LPDDR4__DENALI_PI_62__PI_CALVL_STROBE_NUM_SHIFT 16U
  1061. #define LPDDR4__DENALI_PI_62__PI_CALVL_STROBE_NUM_WIDTH 5U
  1062. #define LPDDR4__PI_CALVL_STROBE_NUM__REG DENALI_PI_62
  1063. #define LPDDR4__PI_CALVL_STROBE_NUM__FLD LPDDR4__DENALI_PI_62__PI_CALVL_STROBE_NUM
  1064. #define LPDDR4__DENALI_PI_62__PI_SW_CA_TRAIN_VREF_MASK 0x7F000000U
  1065. #define LPDDR4__DENALI_PI_62__PI_SW_CA_TRAIN_VREF_SHIFT 24U
  1066. #define LPDDR4__DENALI_PI_62__PI_SW_CA_TRAIN_VREF_WIDTH 7U
  1067. #define LPDDR4__PI_SW_CA_TRAIN_VREF__REG DENALI_PI_62
  1068. #define LPDDR4__PI_SW_CA_TRAIN_VREF__FLD LPDDR4__DENALI_PI_62__PI_SW_CA_TRAIN_VREF
  1069. #define LPDDR4__DENALI_PI_63_READ_MASK 0x0101FFFFU
  1070. #define LPDDR4__DENALI_PI_63_WRITE_MASK 0x0101FFFFU
  1071. #define LPDDR4__DENALI_PI_63__PI_CLKDISABLE_2_INIT_START_MASK 0x000000FFU
  1072. #define LPDDR4__DENALI_PI_63__PI_CLKDISABLE_2_INIT_START_SHIFT 0U
  1073. #define LPDDR4__DENALI_PI_63__PI_CLKDISABLE_2_INIT_START_WIDTH 8U
  1074. #define LPDDR4__PI_CLKDISABLE_2_INIT_START__REG DENALI_PI_63
  1075. #define LPDDR4__PI_CLKDISABLE_2_INIT_START__FLD LPDDR4__DENALI_PI_63__PI_CLKDISABLE_2_INIT_START
  1076. #define LPDDR4__DENALI_PI_63__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE_MASK 0x0000FF00U
  1077. #define LPDDR4__DENALI_PI_63__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE_SHIFT 8U
  1078. #define LPDDR4__DENALI_PI_63__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE_WIDTH 8U
  1079. #define LPDDR4__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE__REG DENALI_PI_63
  1080. #define LPDDR4__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE__FLD LPDDR4__DENALI_PI_63__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE
  1081. #define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_MASK 0x00010000U
  1082. #define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_SHIFT 16U
  1083. #define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_WIDTH 1U
  1084. #define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_WOCLR 0U
  1085. #define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_WOSET 0U
  1086. #define LPDDR4__PI_DRAM_CLK_DISABLE_DEASSERT_SEL__REG DENALI_PI_63
  1087. #define LPDDR4__PI_DRAM_CLK_DISABLE_DEASSERT_SEL__FLD LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL
  1088. #define LPDDR4__DENALI_PI_63__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_MASK 0x01000000U
  1089. #define LPDDR4__DENALI_PI_63__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_SHIFT 24U
  1090. #define LPDDR4__DENALI_PI_63__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_WIDTH 1U
  1091. #define LPDDR4__DENALI_PI_63__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_WOCLR 0U
  1092. #define LPDDR4__DENALI_PI_63__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_WOSET 0U
  1093. #define LPDDR4__PI_REFRESH_BETWEEN_SEGMENT_DISABLE__REG DENALI_PI_63
  1094. #define LPDDR4__PI_REFRESH_BETWEEN_SEGMENT_DISABLE__FLD LPDDR4__DENALI_PI_63__PI_REFRESH_BETWEEN_SEGMENT_DISABLE
  1095. #define LPDDR4__DENALI_PI_64_READ_MASK 0x00FFFF01U
  1096. #define LPDDR4__DENALI_PI_64_WRITE_MASK 0x00FFFF01U
  1097. #define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_MASK 0x00000001U
  1098. #define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_SHIFT 0U
  1099. #define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_WIDTH 1U
  1100. #define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_WOCLR 0U
  1101. #define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_WOSET 0U
  1102. #define LPDDR4__PI_MC_DFS_PI_SET_VREF_ENABLE__REG DENALI_PI_64
  1103. #define LPDDR4__PI_MC_DFS_PI_SET_VREF_ENABLE__FLD LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE
  1104. #define LPDDR4__DENALI_PI_64__PI_FSM_ERROR_INFO_MASK_MASK 0x00FFFF00U
  1105. #define LPDDR4__DENALI_PI_64__PI_FSM_ERROR_INFO_MASK_SHIFT 8U
  1106. #define LPDDR4__DENALI_PI_64__PI_FSM_ERROR_INFO_MASK_WIDTH 16U
  1107. #define LPDDR4__PI_FSM_ERROR_INFO_MASK__REG DENALI_PI_64
  1108. #define LPDDR4__PI_FSM_ERROR_INFO_MASK__FLD LPDDR4__DENALI_PI_64__PI_FSM_ERROR_INFO_MASK
  1109. #define LPDDR4__DENALI_PI_65_READ_MASK 0xFFFF0000U
  1110. #define LPDDR4__DENALI_PI_65_WRITE_MASK 0xFFFF0000U
  1111. #define LPDDR4__DENALI_PI_65__PI_SC_FSM_ERROR_INFO_WOCLR_MASK 0x0000FFFFU
  1112. #define LPDDR4__DENALI_PI_65__PI_SC_FSM_ERROR_INFO_WOCLR_SHIFT 0U
  1113. #define LPDDR4__DENALI_PI_65__PI_SC_FSM_ERROR_INFO_WOCLR_WIDTH 16U
  1114. #define LPDDR4__PI_SC_FSM_ERROR_INFO_WOCLR__REG DENALI_PI_65
  1115. #define LPDDR4__PI_SC_FSM_ERROR_INFO_WOCLR__FLD LPDDR4__DENALI_PI_65__PI_SC_FSM_ERROR_INFO_WOCLR
  1116. #define LPDDR4__DENALI_PI_65__PI_FSM_ERROR_INFO_MASK 0xFFFF0000U
  1117. #define LPDDR4__DENALI_PI_65__PI_FSM_ERROR_INFO_SHIFT 16U
  1118. #define LPDDR4__DENALI_PI_65__PI_FSM_ERROR_INFO_WIDTH 16U
  1119. #define LPDDR4__PI_FSM_ERROR_INFO__REG DENALI_PI_65
  1120. #define LPDDR4__PI_FSM_ERROR_INFO__FLD LPDDR4__DENALI_PI_65__PI_FSM_ERROR_INFO
  1121. #define LPDDR4__DENALI_PI_66_READ_MASK 0x010F0701U
  1122. #define LPDDR4__DENALI_PI_66_WRITE_MASK 0x010F0701U
  1123. #define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_EN_MASK 0x00000001U
  1124. #define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_EN_SHIFT 0U
  1125. #define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_EN_WIDTH 1U
  1126. #define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_EN_WOCLR 0U
  1127. #define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_EN_WOSET 0U
  1128. #define LPDDR4__PI_WDQLVL_VREF_EN__REG DENALI_PI_66
  1129. #define LPDDR4__PI_WDQLVL_VREF_EN__FLD LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_EN
  1130. #define LPDDR4__DENALI_PI_66__PI_WDQLVL_BST_NUM_MASK 0x00000700U
  1131. #define LPDDR4__DENALI_PI_66__PI_WDQLVL_BST_NUM_SHIFT 8U
  1132. #define LPDDR4__DENALI_PI_66__PI_WDQLVL_BST_NUM_WIDTH 3U
  1133. #define LPDDR4__PI_WDQLVL_BST_NUM__REG DENALI_PI_66
  1134. #define LPDDR4__PI_WDQLVL_BST_NUM__FLD LPDDR4__DENALI_PI_66__PI_WDQLVL_BST_NUM
  1135. #define LPDDR4__DENALI_PI_66__PI_WDQLVL_RESP_MASK_MASK 0x000F0000U
  1136. #define LPDDR4__DENALI_PI_66__PI_WDQLVL_RESP_MASK_SHIFT 16U
  1137. #define LPDDR4__DENALI_PI_66__PI_WDQLVL_RESP_MASK_WIDTH 4U
  1138. #define LPDDR4__PI_WDQLVL_RESP_MASK__REG DENALI_PI_66
  1139. #define LPDDR4__PI_WDQLVL_RESP_MASK__FLD LPDDR4__DENALI_PI_66__PI_WDQLVL_RESP_MASK
  1140. #define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_MASK 0x01000000U
  1141. #define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_SHIFT 24U
  1142. #define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_WIDTH 1U
  1143. #define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_WOCLR 0U
  1144. #define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_WOSET 0U
  1145. #define LPDDR4__PI_WDQLVL_ROTATE__REG DENALI_PI_66
  1146. #define LPDDR4__PI_WDQLVL_ROTATE__FLD LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE
  1147. #define LPDDR4__DENALI_PI_67_READ_MASK 0x011F1F0FU
  1148. #define LPDDR4__DENALI_PI_67_WRITE_MASK 0x011F1F0FU
  1149. #define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_MAP_MASK 0x0000000FU
  1150. #define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_MAP_SHIFT 0U
  1151. #define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_MAP_WIDTH 4U
  1152. #define LPDDR4__PI_WDQLVL_CS_MAP__REG DENALI_PI_67
  1153. #define LPDDR4__PI_WDQLVL_CS_MAP__FLD LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_MAP
  1154. #define LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_INITIAL_STEPSIZE_MASK 0x00001F00U
  1155. #define LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_INITIAL_STEPSIZE_SHIFT 8U
  1156. #define LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_INITIAL_STEPSIZE_WIDTH 5U
  1157. #define LPDDR4__PI_WDQLVL_VREF_INITIAL_STEPSIZE__REG DENALI_PI_67
  1158. #define LPDDR4__PI_WDQLVL_VREF_INITIAL_STEPSIZE__FLD LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_INITIAL_STEPSIZE
  1159. #define LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_NORMAL_STEPSIZE_MASK 0x001F0000U
  1160. #define LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_NORMAL_STEPSIZE_SHIFT 16U
  1161. #define LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_NORMAL_STEPSIZE_WIDTH 5U
  1162. #define LPDDR4__PI_WDQLVL_VREF_NORMAL_STEPSIZE__REG DENALI_PI_67
  1163. #define LPDDR4__PI_WDQLVL_VREF_NORMAL_STEPSIZE__FLD LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_NORMAL_STEPSIZE
  1164. #define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_MASK 0x01000000U
  1165. #define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_SHIFT 24U
  1166. #define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_WIDTH 1U
  1167. #define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_WOCLR 0U
  1168. #define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_WOSET 0U
  1169. #define LPDDR4__PI_WDQLVL_PERIODIC__REG DENALI_PI_67
  1170. #define LPDDR4__PI_WDQLVL_PERIODIC__FLD LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC
  1171. #define LPDDR4__DENALI_PI_68_READ_MASK 0x00FF0300U
  1172. #define LPDDR4__DENALI_PI_68_WRITE_MASK 0x00FF0300U
  1173. #define LPDDR4__DENALI_PI_68__PI_WDQLVL_REQ_MASK 0x00000001U
  1174. #define LPDDR4__DENALI_PI_68__PI_WDQLVL_REQ_SHIFT 0U
  1175. #define LPDDR4__DENALI_PI_68__PI_WDQLVL_REQ_WIDTH 1U
  1176. #define LPDDR4__DENALI_PI_68__PI_WDQLVL_REQ_WOCLR 0U
  1177. #define LPDDR4__DENALI_PI_68__PI_WDQLVL_REQ_WOSET 0U
  1178. #define LPDDR4__PI_WDQLVL_REQ__REG DENALI_PI_68
  1179. #define LPDDR4__PI_WDQLVL_REQ__FLD LPDDR4__DENALI_PI_68__PI_WDQLVL_REQ
  1180. #define LPDDR4__DENALI_PI_68__PI_WDQLVL_CS_MASK 0x00000300U
  1181. #define LPDDR4__DENALI_PI_68__PI_WDQLVL_CS_SHIFT 8U
  1182. #define LPDDR4__DENALI_PI_68__PI_WDQLVL_CS_WIDTH 2U
  1183. #define LPDDR4__PI_WDQLVL_CS__REG DENALI_PI_68
  1184. #define LPDDR4__PI_WDQLVL_CS__FLD LPDDR4__DENALI_PI_68__PI_WDQLVL_CS
  1185. #define LPDDR4__DENALI_PI_68__PI_TDFI_WDQLVL_EN_MASK 0x00FF0000U
  1186. #define LPDDR4__DENALI_PI_68__PI_TDFI_WDQLVL_EN_SHIFT 16U
  1187. #define LPDDR4__DENALI_PI_68__PI_TDFI_WDQLVL_EN_WIDTH 8U
  1188. #define LPDDR4__PI_TDFI_WDQLVL_EN__REG DENALI_PI_68
  1189. #define LPDDR4__PI_TDFI_WDQLVL_EN__FLD LPDDR4__DENALI_PI_68__PI_TDFI_WDQLVL_EN
  1190. #define LPDDR4__DENALI_PI_69_READ_MASK 0xFFFFFFFFU
  1191. #define LPDDR4__DENALI_PI_69_WRITE_MASK 0xFFFFFFFFU
  1192. #define LPDDR4__DENALI_PI_69__PI_TDFI_WDQLVL_RESP_MASK 0xFFFFFFFFU
  1193. #define LPDDR4__DENALI_PI_69__PI_TDFI_WDQLVL_RESP_SHIFT 0U
  1194. #define LPDDR4__DENALI_PI_69__PI_TDFI_WDQLVL_RESP_WIDTH 32U
  1195. #define LPDDR4__PI_TDFI_WDQLVL_RESP__REG DENALI_PI_69
  1196. #define LPDDR4__PI_TDFI_WDQLVL_RESP__FLD LPDDR4__DENALI_PI_69__PI_TDFI_WDQLVL_RESP
  1197. #define LPDDR4__DENALI_PI_70_READ_MASK 0xFFFFFFFFU
  1198. #define LPDDR4__DENALI_PI_70_WRITE_MASK 0xFFFFFFFFU
  1199. #define LPDDR4__DENALI_PI_70__PI_TDFI_WDQLVL_MAX_MASK 0xFFFFFFFFU
  1200. #define LPDDR4__DENALI_PI_70__PI_TDFI_WDQLVL_MAX_SHIFT 0U
  1201. #define LPDDR4__DENALI_PI_70__PI_TDFI_WDQLVL_MAX_WIDTH 32U
  1202. #define LPDDR4__PI_TDFI_WDQLVL_MAX__REG DENALI_PI_70
  1203. #define LPDDR4__PI_TDFI_WDQLVL_MAX__FLD LPDDR4__DENALI_PI_70__PI_TDFI_WDQLVL_MAX
  1204. #define LPDDR4__DENALI_PI_71_READ_MASK 0x0101FFFFU
  1205. #define LPDDR4__DENALI_PI_71_WRITE_MASK 0x0101FFFFU
  1206. #define LPDDR4__DENALI_PI_71__PI_WDQLVL_INTERVAL_MASK 0x0000FFFFU
  1207. #define LPDDR4__DENALI_PI_71__PI_WDQLVL_INTERVAL_SHIFT 0U
  1208. #define LPDDR4__DENALI_PI_71__PI_WDQLVL_INTERVAL_WIDTH 16U
  1209. #define LPDDR4__PI_WDQLVL_INTERVAL__REG DENALI_PI_71
  1210. #define LPDDR4__PI_WDQLVL_INTERVAL__FLD LPDDR4__DENALI_PI_71__PI_WDQLVL_INTERVAL
  1211. #define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_MASK 0x00010000U
  1212. #define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_SHIFT 16U
  1213. #define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_WIDTH 1U
  1214. #define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_WOCLR 0U
  1215. #define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_WOSET 0U
  1216. #define LPDDR4__PI_WDQLVL_ON_SREF_EXIT__REG DENALI_PI_71
  1217. #define LPDDR4__PI_WDQLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT
  1218. #define LPDDR4__DENALI_PI_71__PI_WDQLVL_DISABLE_DFS_MASK 0x01000000U
  1219. #define LPDDR4__DENALI_PI_71__PI_WDQLVL_DISABLE_DFS_SHIFT 24U
  1220. #define LPDDR4__DENALI_PI_71__PI_WDQLVL_DISABLE_DFS_WIDTH 1U
  1221. #define LPDDR4__DENALI_PI_71__PI_WDQLVL_DISABLE_DFS_WOCLR 0U
  1222. #define LPDDR4__DENALI_PI_71__PI_WDQLVL_DISABLE_DFS_WOSET 0U
  1223. #define LPDDR4__PI_WDQLVL_DISABLE_DFS__REG DENALI_PI_71
  1224. #define LPDDR4__PI_WDQLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_71__PI_WDQLVL_DISABLE_DFS
  1225. #define LPDDR4__DENALI_PI_72_READ_MASK 0x01010103U
  1226. #define LPDDR4__DENALI_PI_72_WRITE_MASK 0x01010103U
  1227. #define LPDDR4__DENALI_PI_72__PI_WDQLVL_ERROR_STATUS_MASK 0x00000003U
  1228. #define LPDDR4__DENALI_PI_72__PI_WDQLVL_ERROR_STATUS_SHIFT 0U
  1229. #define LPDDR4__DENALI_PI_72__PI_WDQLVL_ERROR_STATUS_WIDTH 2U
  1230. #define LPDDR4__PI_WDQLVL_ERROR_STATUS__REG DENALI_PI_72
  1231. #define LPDDR4__PI_WDQLVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_72__PI_WDQLVL_ERROR_STATUS
  1232. #define LPDDR4__DENALI_PI_72__PI_WDQLVL_OSC_EN_MASK 0x00000100U
  1233. #define LPDDR4__DENALI_PI_72__PI_WDQLVL_OSC_EN_SHIFT 8U
  1234. #define LPDDR4__DENALI_PI_72__PI_WDQLVL_OSC_EN_WIDTH 1U
  1235. #define LPDDR4__DENALI_PI_72__PI_WDQLVL_OSC_EN_WOCLR 0U
  1236. #define LPDDR4__DENALI_PI_72__PI_WDQLVL_OSC_EN_WOSET 0U
  1237. #define LPDDR4__PI_WDQLVL_OSC_EN__REG DENALI_PI_72
  1238. #define LPDDR4__PI_WDQLVL_OSC_EN__FLD LPDDR4__DENALI_PI_72__PI_WDQLVL_OSC_EN
  1239. #define LPDDR4__DENALI_PI_72__PI_DQS_OSC_PERIOD_EN_MASK 0x00010000U
  1240. #define LPDDR4__DENALI_PI_72__PI_DQS_OSC_PERIOD_EN_SHIFT 16U
  1241. #define LPDDR4__DENALI_PI_72__PI_DQS_OSC_PERIOD_EN_WIDTH 1U
  1242. #define LPDDR4__DENALI_PI_72__PI_DQS_OSC_PERIOD_EN_WOCLR 0U
  1243. #define LPDDR4__DENALI_PI_72__PI_DQS_OSC_PERIOD_EN_WOSET 0U
  1244. #define LPDDR4__PI_DQS_OSC_PERIOD_EN__REG DENALI_PI_72
  1245. #define LPDDR4__PI_DQS_OSC_PERIOD_EN__FLD LPDDR4__DENALI_PI_72__PI_DQS_OSC_PERIOD_EN
  1246. #define LPDDR4__DENALI_PI_72__PI_PARALLEL_WDQLVL_EN_MASK 0x01000000U
  1247. #define LPDDR4__DENALI_PI_72__PI_PARALLEL_WDQLVL_EN_SHIFT 24U
  1248. #define LPDDR4__DENALI_PI_72__PI_PARALLEL_WDQLVL_EN_WIDTH 1U
  1249. #define LPDDR4__DENALI_PI_72__PI_PARALLEL_WDQLVL_EN_WOCLR 0U
  1250. #define LPDDR4__DENALI_PI_72__PI_PARALLEL_WDQLVL_EN_WOSET 0U
  1251. #define LPDDR4__PI_PARALLEL_WDQLVL_EN__REG DENALI_PI_72
  1252. #define LPDDR4__PI_PARALLEL_WDQLVL_EN__FLD LPDDR4__DENALI_PI_72__PI_PARALLEL_WDQLVL_EN
  1253. #define LPDDR4__DENALI_PI_73_READ_MASK 0x0F1F0703U
  1254. #define LPDDR4__DENALI_PI_73_WRITE_MASK 0x0F1F0703U
  1255. #define LPDDR4__DENALI_PI_73__PI_BANK_DIFF_MASK 0x00000003U
  1256. #define LPDDR4__DENALI_PI_73__PI_BANK_DIFF_SHIFT 0U
  1257. #define LPDDR4__DENALI_PI_73__PI_BANK_DIFF_WIDTH 2U
  1258. #define LPDDR4__PI_BANK_DIFF__REG DENALI_PI_73
  1259. #define LPDDR4__PI_BANK_DIFF__FLD LPDDR4__DENALI_PI_73__PI_BANK_DIFF
  1260. #define LPDDR4__DENALI_PI_73__PI_ROW_DIFF_MASK 0x00000700U
  1261. #define LPDDR4__DENALI_PI_73__PI_ROW_DIFF_SHIFT 8U
  1262. #define LPDDR4__DENALI_PI_73__PI_ROW_DIFF_WIDTH 3U
  1263. #define LPDDR4__PI_ROW_DIFF__REG DENALI_PI_73
  1264. #define LPDDR4__PI_ROW_DIFF__FLD LPDDR4__DENALI_PI_73__PI_ROW_DIFF
  1265. #define LPDDR4__DENALI_PI_73__PI_TCCD_MASK 0x001F0000U
  1266. #define LPDDR4__DENALI_PI_73__PI_TCCD_SHIFT 16U
  1267. #define LPDDR4__DENALI_PI_73__PI_TCCD_WIDTH 5U
  1268. #define LPDDR4__PI_TCCD__REG DENALI_PI_73
  1269. #define LPDDR4__PI_TCCD__FLD LPDDR4__DENALI_PI_73__PI_TCCD
  1270. #define LPDDR4__DENALI_PI_73__PI_RESERVED5_MASK 0x0F000000U
  1271. #define LPDDR4__DENALI_PI_73__PI_RESERVED5_SHIFT 24U
  1272. #define LPDDR4__DENALI_PI_73__PI_RESERVED5_WIDTH 4U
  1273. #define LPDDR4__PI_RESERVED5__REG DENALI_PI_73
  1274. #define LPDDR4__PI_RESERVED5__FLD LPDDR4__DENALI_PI_73__PI_RESERVED5
  1275. #define LPDDR4__DENALI_PI_74_READ_MASK 0x0F0F0F0FU
  1276. #define LPDDR4__DENALI_PI_74_WRITE_MASK 0x0F0F0F0FU
  1277. #define LPDDR4__DENALI_PI_74__PI_RESERVED6_MASK 0x0000000FU
  1278. #define LPDDR4__DENALI_PI_74__PI_RESERVED6_SHIFT 0U
  1279. #define LPDDR4__DENALI_PI_74__PI_RESERVED6_WIDTH 4U
  1280. #define LPDDR4__PI_RESERVED6__REG DENALI_PI_74
  1281. #define LPDDR4__PI_RESERVED6__FLD LPDDR4__DENALI_PI_74__PI_RESERVED6
  1282. #define LPDDR4__DENALI_PI_74__PI_RESERVED7_MASK 0x00000F00U
  1283. #define LPDDR4__DENALI_PI_74__PI_RESERVED7_SHIFT 8U
  1284. #define LPDDR4__DENALI_PI_74__PI_RESERVED7_WIDTH 4U
  1285. #define LPDDR4__PI_RESERVED7__REG DENALI_PI_74
  1286. #define LPDDR4__PI_RESERVED7__FLD LPDDR4__DENALI_PI_74__PI_RESERVED7
  1287. #define LPDDR4__DENALI_PI_74__PI_RESERVED8_MASK 0x000F0000U
  1288. #define LPDDR4__DENALI_PI_74__PI_RESERVED8_SHIFT 16U
  1289. #define LPDDR4__DENALI_PI_74__PI_RESERVED8_WIDTH 4U
  1290. #define LPDDR4__PI_RESERVED8__REG DENALI_PI_74
  1291. #define LPDDR4__PI_RESERVED8__FLD LPDDR4__DENALI_PI_74__PI_RESERVED8
  1292. #define LPDDR4__DENALI_PI_74__PI_RESERVED9_MASK 0x0F000000U
  1293. #define LPDDR4__DENALI_PI_74__PI_RESERVED9_SHIFT 24U
  1294. #define LPDDR4__DENALI_PI_74__PI_RESERVED9_WIDTH 4U
  1295. #define LPDDR4__PI_RESERVED9__REG DENALI_PI_74
  1296. #define LPDDR4__PI_RESERVED9__FLD LPDDR4__DENALI_PI_74__PI_RESERVED9
  1297. #define LPDDR4__DENALI_PI_75_READ_MASK 0x0F0F0F0FU
  1298. #define LPDDR4__DENALI_PI_75_WRITE_MASK 0x0F0F0F0FU
  1299. #define LPDDR4__DENALI_PI_75__PI_RESERVED10_MASK 0x0000000FU
  1300. #define LPDDR4__DENALI_PI_75__PI_RESERVED10_SHIFT 0U
  1301. #define LPDDR4__DENALI_PI_75__PI_RESERVED10_WIDTH 4U
  1302. #define LPDDR4__PI_RESERVED10__REG DENALI_PI_75
  1303. #define LPDDR4__PI_RESERVED10__FLD LPDDR4__DENALI_PI_75__PI_RESERVED10
  1304. #define LPDDR4__DENALI_PI_75__PI_RESERVED11_MASK 0x00000F00U
  1305. #define LPDDR4__DENALI_PI_75__PI_RESERVED11_SHIFT 8U
  1306. #define LPDDR4__DENALI_PI_75__PI_RESERVED11_WIDTH 4U
  1307. #define LPDDR4__PI_RESERVED11__REG DENALI_PI_75
  1308. #define LPDDR4__PI_RESERVED11__FLD LPDDR4__DENALI_PI_75__PI_RESERVED11
  1309. #define LPDDR4__DENALI_PI_75__PI_RESERVED12_MASK 0x000F0000U
  1310. #define LPDDR4__DENALI_PI_75__PI_RESERVED12_SHIFT 16U
  1311. #define LPDDR4__DENALI_PI_75__PI_RESERVED12_WIDTH 4U
  1312. #define LPDDR4__PI_RESERVED12__REG DENALI_PI_75
  1313. #define LPDDR4__PI_RESERVED12__FLD LPDDR4__DENALI_PI_75__PI_RESERVED12
  1314. #define LPDDR4__DENALI_PI_75__PI_RESERVED13_MASK 0x0F000000U
  1315. #define LPDDR4__DENALI_PI_75__PI_RESERVED13_SHIFT 24U
  1316. #define LPDDR4__DENALI_PI_75__PI_RESERVED13_WIDTH 4U
  1317. #define LPDDR4__PI_RESERVED13__REG DENALI_PI_75
  1318. #define LPDDR4__PI_RESERVED13__FLD LPDDR4__DENALI_PI_75__PI_RESERVED13
  1319. #define LPDDR4__DENALI_PI_76_READ_MASK 0x0F0F0F0FU
  1320. #define LPDDR4__DENALI_PI_76_WRITE_MASK 0x0F0F0F0FU
  1321. #define LPDDR4__DENALI_PI_76__PI_RESERVED14_MASK 0x0000000FU
  1322. #define LPDDR4__DENALI_PI_76__PI_RESERVED14_SHIFT 0U
  1323. #define LPDDR4__DENALI_PI_76__PI_RESERVED14_WIDTH 4U
  1324. #define LPDDR4__PI_RESERVED14__REG DENALI_PI_76
  1325. #define LPDDR4__PI_RESERVED14__FLD LPDDR4__DENALI_PI_76__PI_RESERVED14
  1326. #define LPDDR4__DENALI_PI_76__PI_RESERVED15_MASK 0x00000F00U
  1327. #define LPDDR4__DENALI_PI_76__PI_RESERVED15_SHIFT 8U
  1328. #define LPDDR4__DENALI_PI_76__PI_RESERVED15_WIDTH 4U
  1329. #define LPDDR4__PI_RESERVED15__REG DENALI_PI_76
  1330. #define LPDDR4__PI_RESERVED15__FLD LPDDR4__DENALI_PI_76__PI_RESERVED15
  1331. #define LPDDR4__DENALI_PI_76__PI_RESERVED16_MASK 0x000F0000U
  1332. #define LPDDR4__DENALI_PI_76__PI_RESERVED16_SHIFT 16U
  1333. #define LPDDR4__DENALI_PI_76__PI_RESERVED16_WIDTH 4U
  1334. #define LPDDR4__PI_RESERVED16__REG DENALI_PI_76
  1335. #define LPDDR4__PI_RESERVED16__FLD LPDDR4__DENALI_PI_76__PI_RESERVED16
  1336. #define LPDDR4__DENALI_PI_76__PI_RESERVED17_MASK 0x0F000000U
  1337. #define LPDDR4__DENALI_PI_76__PI_RESERVED17_SHIFT 24U
  1338. #define LPDDR4__DENALI_PI_76__PI_RESERVED17_WIDTH 4U
  1339. #define LPDDR4__PI_RESERVED17__REG DENALI_PI_76
  1340. #define LPDDR4__PI_RESERVED17__FLD LPDDR4__DENALI_PI_76__PI_RESERVED17
  1341. #define LPDDR4__DENALI_PI_77_READ_MASK 0x0F0F0F0FU
  1342. #define LPDDR4__DENALI_PI_77_WRITE_MASK 0x0F0F0F0FU
  1343. #define LPDDR4__DENALI_PI_77__PI_RESERVED18_MASK 0x0000000FU
  1344. #define LPDDR4__DENALI_PI_77__PI_RESERVED18_SHIFT 0U
  1345. #define LPDDR4__DENALI_PI_77__PI_RESERVED18_WIDTH 4U
  1346. #define LPDDR4__PI_RESERVED18__REG DENALI_PI_77
  1347. #define LPDDR4__PI_RESERVED18__FLD LPDDR4__DENALI_PI_77__PI_RESERVED18
  1348. #define LPDDR4__DENALI_PI_77__PI_RESERVED19_MASK 0x00000F00U
  1349. #define LPDDR4__DENALI_PI_77__PI_RESERVED19_SHIFT 8U
  1350. #define LPDDR4__DENALI_PI_77__PI_RESERVED19_WIDTH 4U
  1351. #define LPDDR4__PI_RESERVED19__REG DENALI_PI_77
  1352. #define LPDDR4__PI_RESERVED19__FLD LPDDR4__DENALI_PI_77__PI_RESERVED19
  1353. #define LPDDR4__DENALI_PI_77__PI_RESERVED20_MASK 0x000F0000U
  1354. #define LPDDR4__DENALI_PI_77__PI_RESERVED20_SHIFT 16U
  1355. #define LPDDR4__DENALI_PI_77__PI_RESERVED20_WIDTH 4U
  1356. #define LPDDR4__PI_RESERVED20__REG DENALI_PI_77
  1357. #define LPDDR4__PI_RESERVED20__FLD LPDDR4__DENALI_PI_77__PI_RESERVED20
  1358. #define LPDDR4__DENALI_PI_77__PI_RESERVED21_MASK 0x0F000000U
  1359. #define LPDDR4__DENALI_PI_77__PI_RESERVED21_SHIFT 24U
  1360. #define LPDDR4__DENALI_PI_77__PI_RESERVED21_WIDTH 4U
  1361. #define LPDDR4__PI_RESERVED21__REG DENALI_PI_77
  1362. #define LPDDR4__PI_RESERVED21__FLD LPDDR4__DENALI_PI_77__PI_RESERVED21
  1363. #define LPDDR4__DENALI_PI_78_READ_MASK 0x000F0F0FU
  1364. #define LPDDR4__DENALI_PI_78_WRITE_MASK 0x000F0F0FU
  1365. #define LPDDR4__DENALI_PI_78__PI_RESERVED22_MASK 0x0000000FU
  1366. #define LPDDR4__DENALI_PI_78__PI_RESERVED22_SHIFT 0U
  1367. #define LPDDR4__DENALI_PI_78__PI_RESERVED22_WIDTH 4U
  1368. #define LPDDR4__PI_RESERVED22__REG DENALI_PI_78
  1369. #define LPDDR4__PI_RESERVED22__FLD LPDDR4__DENALI_PI_78__PI_RESERVED22
  1370. #define LPDDR4__DENALI_PI_78__PI_RESERVED23_MASK 0x00000F00U
  1371. #define LPDDR4__DENALI_PI_78__PI_RESERVED23_SHIFT 8U
  1372. #define LPDDR4__DENALI_PI_78__PI_RESERVED23_WIDTH 4U
  1373. #define LPDDR4__PI_RESERVED23__REG DENALI_PI_78
  1374. #define LPDDR4__PI_RESERVED23__FLD LPDDR4__DENALI_PI_78__PI_RESERVED23
  1375. #define LPDDR4__DENALI_PI_78__PI_RESERVED24_MASK 0x000F0000U
  1376. #define LPDDR4__DENALI_PI_78__PI_RESERVED24_SHIFT 16U
  1377. #define LPDDR4__DENALI_PI_78__PI_RESERVED24_WIDTH 4U
  1378. #define LPDDR4__PI_RESERVED24__REG DENALI_PI_78
  1379. #define LPDDR4__PI_RESERVED24__FLD LPDDR4__DENALI_PI_78__PI_RESERVED24
  1380. #define LPDDR4__DENALI_PI_79_READ_MASK 0x0FFFFFFFU
  1381. #define LPDDR4__DENALI_PI_79_WRITE_MASK 0x0FFFFFFFU
  1382. #define LPDDR4__DENALI_PI_79__PI_INT_STATUS_MASK 0x0FFFFFFFU
  1383. #define LPDDR4__DENALI_PI_79__PI_INT_STATUS_SHIFT 0U
  1384. #define LPDDR4__DENALI_PI_79__PI_INT_STATUS_WIDTH 28U
  1385. #define LPDDR4__PI_INT_STATUS__REG DENALI_PI_79
  1386. #define LPDDR4__PI_INT_STATUS__FLD LPDDR4__DENALI_PI_79__PI_INT_STATUS
  1387. #define LPDDR4__DENALI_PI_80__PI_INT_ACK_MASK 0x07FFFFFFU
  1388. #define LPDDR4__DENALI_PI_80__PI_INT_ACK_SHIFT 0U
  1389. #define LPDDR4__DENALI_PI_80__PI_INT_ACK_WIDTH 27U
  1390. #define LPDDR4__PI_INT_ACK__REG DENALI_PI_80
  1391. #define LPDDR4__PI_INT_ACK__FLD LPDDR4__DENALI_PI_80__PI_INT_ACK
  1392. #define LPDDR4__DENALI_PI_81_READ_MASK 0x0FFFFFFFU
  1393. #define LPDDR4__DENALI_PI_81_WRITE_MASK 0x0FFFFFFFU
  1394. #define LPDDR4__DENALI_PI_81__PI_INT_MASK_MASK 0x0FFFFFFFU
  1395. #define LPDDR4__DENALI_PI_81__PI_INT_MASK_SHIFT 0U
  1396. #define LPDDR4__DENALI_PI_81__PI_INT_MASK_WIDTH 28U
  1397. #define LPDDR4__PI_INT_MASK__REG DENALI_PI_81
  1398. #define LPDDR4__PI_INT_MASK__FLD LPDDR4__DENALI_PI_81__PI_INT_MASK
  1399. #define LPDDR4__DENALI_PI_82_READ_MASK 0xFFFFFFFFU
  1400. #define LPDDR4__DENALI_PI_82_WRITE_MASK 0xFFFFFFFFU
  1401. #define LPDDR4__DENALI_PI_82__PI_BIST_EXP_DATA_0_MASK 0xFFFFFFFFU
  1402. #define LPDDR4__DENALI_PI_82__PI_BIST_EXP_DATA_0_SHIFT 0U
  1403. #define LPDDR4__DENALI_PI_82__PI_BIST_EXP_DATA_0_WIDTH 32U
  1404. #define LPDDR4__PI_BIST_EXP_DATA_0__REG DENALI_PI_82
  1405. #define LPDDR4__PI_BIST_EXP_DATA_0__FLD LPDDR4__DENALI_PI_82__PI_BIST_EXP_DATA_0
  1406. #define LPDDR4__DENALI_PI_83_READ_MASK 0xFFFFFFFFU
  1407. #define LPDDR4__DENALI_PI_83_WRITE_MASK 0xFFFFFFFFU
  1408. #define LPDDR4__DENALI_PI_83__PI_BIST_EXP_DATA_1_MASK 0xFFFFFFFFU
  1409. #define LPDDR4__DENALI_PI_83__PI_BIST_EXP_DATA_1_SHIFT 0U
  1410. #define LPDDR4__DENALI_PI_83__PI_BIST_EXP_DATA_1_WIDTH 32U
  1411. #define LPDDR4__PI_BIST_EXP_DATA_1__REG DENALI_PI_83
  1412. #define LPDDR4__PI_BIST_EXP_DATA_1__FLD LPDDR4__DENALI_PI_83__PI_BIST_EXP_DATA_1
  1413. #define LPDDR4__DENALI_PI_84_READ_MASK 0xFFFFFFFFU
  1414. #define LPDDR4__DENALI_PI_84_WRITE_MASK 0xFFFFFFFFU
  1415. #define LPDDR4__DENALI_PI_84__PI_BIST_EXP_DATA_2_MASK 0xFFFFFFFFU
  1416. #define LPDDR4__DENALI_PI_84__PI_BIST_EXP_DATA_2_SHIFT 0U
  1417. #define LPDDR4__DENALI_PI_84__PI_BIST_EXP_DATA_2_WIDTH 32U
  1418. #define LPDDR4__PI_BIST_EXP_DATA_2__REG DENALI_PI_84
  1419. #define LPDDR4__PI_BIST_EXP_DATA_2__FLD LPDDR4__DENALI_PI_84__PI_BIST_EXP_DATA_2
  1420. #define LPDDR4__DENALI_PI_85_READ_MASK 0xFFFFFFFFU
  1421. #define LPDDR4__DENALI_PI_85_WRITE_MASK 0xFFFFFFFFU
  1422. #define LPDDR4__DENALI_PI_85__PI_BIST_EXP_DATA_3_MASK 0xFFFFFFFFU
  1423. #define LPDDR4__DENALI_PI_85__PI_BIST_EXP_DATA_3_SHIFT 0U
  1424. #define LPDDR4__DENALI_PI_85__PI_BIST_EXP_DATA_3_WIDTH 32U
  1425. #define LPDDR4__PI_BIST_EXP_DATA_3__REG DENALI_PI_85
  1426. #define LPDDR4__PI_BIST_EXP_DATA_3__FLD LPDDR4__DENALI_PI_85__PI_BIST_EXP_DATA_3
  1427. #define LPDDR4__DENALI_PI_86_READ_MASK 0xFFFFFFFFU
  1428. #define LPDDR4__DENALI_PI_86_WRITE_MASK 0xFFFFFFFFU
  1429. #define LPDDR4__DENALI_PI_86__PI_BIST_FAIL_DATA_0_MASK 0xFFFFFFFFU
  1430. #define LPDDR4__DENALI_PI_86__PI_BIST_FAIL_DATA_0_SHIFT 0U
  1431. #define LPDDR4__DENALI_PI_86__PI_BIST_FAIL_DATA_0_WIDTH 32U
  1432. #define LPDDR4__PI_BIST_FAIL_DATA_0__REG DENALI_PI_86
  1433. #define LPDDR4__PI_BIST_FAIL_DATA_0__FLD LPDDR4__DENALI_PI_86__PI_BIST_FAIL_DATA_0
  1434. #define LPDDR4__DENALI_PI_87_READ_MASK 0xFFFFFFFFU
  1435. #define LPDDR4__DENALI_PI_87_WRITE_MASK 0xFFFFFFFFU
  1436. #define LPDDR4__DENALI_PI_87__PI_BIST_FAIL_DATA_1_MASK 0xFFFFFFFFU
  1437. #define LPDDR4__DENALI_PI_87__PI_BIST_FAIL_DATA_1_SHIFT 0U
  1438. #define LPDDR4__DENALI_PI_87__PI_BIST_FAIL_DATA_1_WIDTH 32U
  1439. #define LPDDR4__PI_BIST_FAIL_DATA_1__REG DENALI_PI_87
  1440. #define LPDDR4__PI_BIST_FAIL_DATA_1__FLD LPDDR4__DENALI_PI_87__PI_BIST_FAIL_DATA_1
  1441. #define LPDDR4__DENALI_PI_88_READ_MASK 0xFFFFFFFFU
  1442. #define LPDDR4__DENALI_PI_88_WRITE_MASK 0xFFFFFFFFU
  1443. #define LPDDR4__DENALI_PI_88__PI_BIST_FAIL_DATA_2_MASK 0xFFFFFFFFU
  1444. #define LPDDR4__DENALI_PI_88__PI_BIST_FAIL_DATA_2_SHIFT 0U
  1445. #define LPDDR4__DENALI_PI_88__PI_BIST_FAIL_DATA_2_WIDTH 32U
  1446. #define LPDDR4__PI_BIST_FAIL_DATA_2__REG DENALI_PI_88
  1447. #define LPDDR4__PI_BIST_FAIL_DATA_2__FLD LPDDR4__DENALI_PI_88__PI_BIST_FAIL_DATA_2
  1448. #define LPDDR4__DENALI_PI_89_READ_MASK 0xFFFFFFFFU
  1449. #define LPDDR4__DENALI_PI_89_WRITE_MASK 0xFFFFFFFFU
  1450. #define LPDDR4__DENALI_PI_89__PI_BIST_FAIL_DATA_3_MASK 0xFFFFFFFFU
  1451. #define LPDDR4__DENALI_PI_89__PI_BIST_FAIL_DATA_3_SHIFT 0U
  1452. #define LPDDR4__DENALI_PI_89__PI_BIST_FAIL_DATA_3_WIDTH 32U
  1453. #define LPDDR4__PI_BIST_FAIL_DATA_3__REG DENALI_PI_89
  1454. #define LPDDR4__PI_BIST_FAIL_DATA_3__FLD LPDDR4__DENALI_PI_89__PI_BIST_FAIL_DATA_3
  1455. #define LPDDR4__DENALI_PI_90_READ_MASK 0xFFFFFFFFU
  1456. #define LPDDR4__DENALI_PI_90_WRITE_MASK 0xFFFFFFFFU
  1457. #define LPDDR4__DENALI_PI_90__PI_BIST_FAIL_ADDR_0_MASK 0xFFFFFFFFU
  1458. #define LPDDR4__DENALI_PI_90__PI_BIST_FAIL_ADDR_0_SHIFT 0U
  1459. #define LPDDR4__DENALI_PI_90__PI_BIST_FAIL_ADDR_0_WIDTH 32U
  1460. #define LPDDR4__PI_BIST_FAIL_ADDR_0__REG DENALI_PI_90
  1461. #define LPDDR4__PI_BIST_FAIL_ADDR_0__FLD LPDDR4__DENALI_PI_90__PI_BIST_FAIL_ADDR_0
  1462. #define LPDDR4__DENALI_PI_91_READ_MASK 0x011F1F07U
  1463. #define LPDDR4__DENALI_PI_91_WRITE_MASK 0x011F1F07U
  1464. #define LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1_MASK 0x00000007U
  1465. #define LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1_SHIFT 0U
  1466. #define LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1_WIDTH 3U
  1467. #define LPDDR4__PI_BIST_FAIL_ADDR_1__REG DENALI_PI_91
  1468. #define LPDDR4__PI_BIST_FAIL_ADDR_1__FLD LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1
  1469. #define LPDDR4__DENALI_PI_91__PI_BSTLEN_MASK 0x00001F00U
  1470. #define LPDDR4__DENALI_PI_91__PI_BSTLEN_SHIFT 8U
  1471. #define LPDDR4__DENALI_PI_91__PI_BSTLEN_WIDTH 5U
  1472. #define LPDDR4__PI_BSTLEN__REG DENALI_PI_91
  1473. #define LPDDR4__PI_BSTLEN__FLD LPDDR4__DENALI_PI_91__PI_BSTLEN
  1474. #define LPDDR4__DENALI_PI_91__PI_LONG_COUNT_MASK_MASK 0x001F0000U
  1475. #define LPDDR4__DENALI_PI_91__PI_LONG_COUNT_MASK_SHIFT 16U
  1476. #define LPDDR4__DENALI_PI_91__PI_LONG_COUNT_MASK_WIDTH 5U
  1477. #define LPDDR4__PI_LONG_COUNT_MASK__REG DENALI_PI_91
  1478. #define LPDDR4__PI_LONG_COUNT_MASK__FLD LPDDR4__DENALI_PI_91__PI_LONG_COUNT_MASK
  1479. #define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_MASK 0x01000000U
  1480. #define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_SHIFT 24U
  1481. #define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_WIDTH 1U
  1482. #define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_WOCLR 0U
  1483. #define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_WOSET 0U
  1484. #define LPDDR4__PI_CMD_SWAP_EN__REG DENALI_PI_91
  1485. #define LPDDR4__PI_CMD_SWAP_EN__FLD LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN
  1486. #define LPDDR4__DENALI_PI_92_READ_MASK 0x03030301U
  1487. #define LPDDR4__DENALI_PI_92_WRITE_MASK 0x03030301U
  1488. #define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_EN_MASK 0x00000001U
  1489. #define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_EN_SHIFT 0U
  1490. #define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_EN_WIDTH 1U
  1491. #define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_EN_WOCLR 0U
  1492. #define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_EN_WOSET 0U
  1493. #define LPDDR4__PI_DATA_BYTE_SWAP_EN__REG DENALI_PI_92
  1494. #define LPDDR4__PI_DATA_BYTE_SWAP_EN__FLD LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_EN
  1495. #define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE0_MASK 0x00000300U
  1496. #define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE0_SHIFT 8U
  1497. #define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE0_WIDTH 2U
  1498. #define LPDDR4__PI_DATA_BYTE_SWAP_SLICE0__REG DENALI_PI_92
  1499. #define LPDDR4__PI_DATA_BYTE_SWAP_SLICE0__FLD LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE0
  1500. #define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE1_MASK 0x00030000U
  1501. #define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE1_SHIFT 16U
  1502. #define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE1_WIDTH 2U
  1503. #define LPDDR4__PI_DATA_BYTE_SWAP_SLICE1__REG DENALI_PI_92
  1504. #define LPDDR4__PI_DATA_BYTE_SWAP_SLICE1__FLD LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE1
  1505. #define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE2_MASK 0x03000000U
  1506. #define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE2_SHIFT 24U
  1507. #define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE2_WIDTH 2U
  1508. #define LPDDR4__PI_DATA_BYTE_SWAP_SLICE2__REG DENALI_PI_92
  1509. #define LPDDR4__PI_DATA_BYTE_SWAP_SLICE2__FLD LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE2
  1510. #define LPDDR4__DENALI_PI_93_READ_MASK 0x03FF0103U
  1511. #define LPDDR4__DENALI_PI_93_WRITE_MASK 0x03FF0103U
  1512. #define LPDDR4__DENALI_PI_93__PI_DATA_BYTE_SWAP_SLICE3_MASK 0x00000003U
  1513. #define LPDDR4__DENALI_PI_93__PI_DATA_BYTE_SWAP_SLICE3_SHIFT 0U
  1514. #define LPDDR4__DENALI_PI_93__PI_DATA_BYTE_SWAP_SLICE3_WIDTH 2U
  1515. #define LPDDR4__PI_DATA_BYTE_SWAP_SLICE3__REG DENALI_PI_93
  1516. #define LPDDR4__PI_DATA_BYTE_SWAP_SLICE3__FLD LPDDR4__DENALI_PI_93__PI_DATA_BYTE_SWAP_SLICE3
  1517. #define LPDDR4__DENALI_PI_93__PI_CTRLUPD_REQ_PER_AREF_EN_MASK 0x00000100U
  1518. #define LPDDR4__DENALI_PI_93__PI_CTRLUPD_REQ_PER_AREF_EN_SHIFT 8U
  1519. #define LPDDR4__DENALI_PI_93__PI_CTRLUPD_REQ_PER_AREF_EN_WIDTH 1U
  1520. #define LPDDR4__DENALI_PI_93__PI_CTRLUPD_REQ_PER_AREF_EN_WOCLR 0U
  1521. #define LPDDR4__DENALI_PI_93__PI_CTRLUPD_REQ_PER_AREF_EN_WOSET 0U
  1522. #define LPDDR4__PI_CTRLUPD_REQ_PER_AREF_EN__REG DENALI_PI_93
  1523. #define LPDDR4__PI_CTRLUPD_REQ_PER_AREF_EN__FLD LPDDR4__DENALI_PI_93__PI_CTRLUPD_REQ_PER_AREF_EN
  1524. #define LPDDR4__DENALI_PI_93__PI_TDFI_CTRLUPD_MIN_MASK 0x00FF0000U
  1525. #define LPDDR4__DENALI_PI_93__PI_TDFI_CTRLUPD_MIN_SHIFT 16U
  1526. #define LPDDR4__DENALI_PI_93__PI_TDFI_CTRLUPD_MIN_WIDTH 8U
  1527. #define LPDDR4__PI_TDFI_CTRLUPD_MIN__REG DENALI_PI_93
  1528. #define LPDDR4__PI_TDFI_CTRLUPD_MIN__FLD LPDDR4__DENALI_PI_93__PI_TDFI_CTRLUPD_MIN
  1529. #define LPDDR4__DENALI_PI_93__PI_UPDATE_ERROR_STATUS_MASK 0x03000000U
  1530. #define LPDDR4__DENALI_PI_93__PI_UPDATE_ERROR_STATUS_SHIFT 24U
  1531. #define LPDDR4__DENALI_PI_93__PI_UPDATE_ERROR_STATUS_WIDTH 2U
  1532. #define LPDDR4__PI_UPDATE_ERROR_STATUS__REG DENALI_PI_93
  1533. #define LPDDR4__PI_UPDATE_ERROR_STATUS__FLD LPDDR4__DENALI_PI_93__PI_UPDATE_ERROR_STATUS
  1534. #define LPDDR4__DENALI_PI_94_READ_MASK 0x013F0301U
  1535. #define LPDDR4__DENALI_PI_94_WRITE_MASK 0x013F0301U
  1536. #define LPDDR4__DENALI_PI_94__PI_BIST_GO_MASK 0x00000001U
  1537. #define LPDDR4__DENALI_PI_94__PI_BIST_GO_SHIFT 0U
  1538. #define LPDDR4__DENALI_PI_94__PI_BIST_GO_WIDTH 1U
  1539. #define LPDDR4__DENALI_PI_94__PI_BIST_GO_WOCLR 0U
  1540. #define LPDDR4__DENALI_PI_94__PI_BIST_GO_WOSET 0U
  1541. #define LPDDR4__PI_BIST_GO__REG DENALI_PI_94
  1542. #define LPDDR4__PI_BIST_GO__FLD LPDDR4__DENALI_PI_94__PI_BIST_GO
  1543. #define LPDDR4__DENALI_PI_94__PI_BIST_RESULT_MASK 0x00000300U
  1544. #define LPDDR4__DENALI_PI_94__PI_BIST_RESULT_SHIFT 8U
  1545. #define LPDDR4__DENALI_PI_94__PI_BIST_RESULT_WIDTH 2U
  1546. #define LPDDR4__PI_BIST_RESULT__REG DENALI_PI_94
  1547. #define LPDDR4__PI_BIST_RESULT__FLD LPDDR4__DENALI_PI_94__PI_BIST_RESULT
  1548. #define LPDDR4__DENALI_PI_94__PI_ADDR_SPACE_MASK 0x003F0000U
  1549. #define LPDDR4__DENALI_PI_94__PI_ADDR_SPACE_SHIFT 16U
  1550. #define LPDDR4__DENALI_PI_94__PI_ADDR_SPACE_WIDTH 6U
  1551. #define LPDDR4__PI_ADDR_SPACE__REG DENALI_PI_94
  1552. #define LPDDR4__PI_ADDR_SPACE__FLD LPDDR4__DENALI_PI_94__PI_ADDR_SPACE
  1553. #define LPDDR4__DENALI_PI_94__PI_BIST_DATA_CHECK_MASK 0x01000000U
  1554. #define LPDDR4__DENALI_PI_94__PI_BIST_DATA_CHECK_SHIFT 24U
  1555. #define LPDDR4__DENALI_PI_94__PI_BIST_DATA_CHECK_WIDTH 1U
  1556. #define LPDDR4__DENALI_PI_94__PI_BIST_DATA_CHECK_WOCLR 0U
  1557. #define LPDDR4__DENALI_PI_94__PI_BIST_DATA_CHECK_WOSET 0U
  1558. #define LPDDR4__PI_BIST_DATA_CHECK__REG DENALI_PI_94
  1559. #define LPDDR4__PI_BIST_DATA_CHECK__FLD LPDDR4__DENALI_PI_94__PI_BIST_DATA_CHECK
  1560. #define LPDDR4__DENALI_PI_95_READ_MASK 0x00000001U
  1561. #define LPDDR4__DENALI_PI_95_WRITE_MASK 0x00000001U
  1562. #define LPDDR4__DENALI_PI_95__PI_BIST_ADDR_CHECK_MASK 0x00000001U
  1563. #define LPDDR4__DENALI_PI_95__PI_BIST_ADDR_CHECK_SHIFT 0U
  1564. #define LPDDR4__DENALI_PI_95__PI_BIST_ADDR_CHECK_WIDTH 1U
  1565. #define LPDDR4__DENALI_PI_95__PI_BIST_ADDR_CHECK_WOCLR 0U
  1566. #define LPDDR4__DENALI_PI_95__PI_BIST_ADDR_CHECK_WOSET 0U
  1567. #define LPDDR4__PI_BIST_ADDR_CHECK__REG DENALI_PI_95
  1568. #define LPDDR4__PI_BIST_ADDR_CHECK__FLD LPDDR4__DENALI_PI_95__PI_BIST_ADDR_CHECK
  1569. #define LPDDR4__DENALI_PI_96_READ_MASK 0xFFFFFFFFU
  1570. #define LPDDR4__DENALI_PI_96_WRITE_MASK 0xFFFFFFFFU
  1571. #define LPDDR4__DENALI_PI_96__PI_BIST_START_ADDRESS_0_MASK 0xFFFFFFFFU
  1572. #define LPDDR4__DENALI_PI_96__PI_BIST_START_ADDRESS_0_SHIFT 0U
  1573. #define LPDDR4__DENALI_PI_96__PI_BIST_START_ADDRESS_0_WIDTH 32U
  1574. #define LPDDR4__PI_BIST_START_ADDRESS_0__REG DENALI_PI_96
  1575. #define LPDDR4__PI_BIST_START_ADDRESS_0__FLD LPDDR4__DENALI_PI_96__PI_BIST_START_ADDRESS_0
  1576. #define LPDDR4__DENALI_PI_97_READ_MASK 0x0000FF07U
  1577. #define LPDDR4__DENALI_PI_97_WRITE_MASK 0x0000FF07U
  1578. #define LPDDR4__DENALI_PI_97__PI_BIST_START_ADDRESS_1_MASK 0x00000007U
  1579. #define LPDDR4__DENALI_PI_97__PI_BIST_START_ADDRESS_1_SHIFT 0U
  1580. #define LPDDR4__DENALI_PI_97__PI_BIST_START_ADDRESS_1_WIDTH 3U
  1581. #define LPDDR4__PI_BIST_START_ADDRESS_1__REG DENALI_PI_97
  1582. #define LPDDR4__PI_BIST_START_ADDRESS_1__FLD LPDDR4__DENALI_PI_97__PI_BIST_START_ADDRESS_1
  1583. #define LPDDR4__DENALI_PI_97__PI_MBIST_INIT_PATTERN_MASK 0x0000FF00U
  1584. #define LPDDR4__DENALI_PI_97__PI_MBIST_INIT_PATTERN_SHIFT 8U
  1585. #define LPDDR4__DENALI_PI_97__PI_MBIST_INIT_PATTERN_WIDTH 8U
  1586. #define LPDDR4__PI_MBIST_INIT_PATTERN__REG DENALI_PI_97
  1587. #define LPDDR4__PI_MBIST_INIT_PATTERN__FLD LPDDR4__DENALI_PI_97__PI_MBIST_INIT_PATTERN
  1588. #define LPDDR4__DENALI_PI_98_READ_MASK 0xFFFFFFFFU
  1589. #define LPDDR4__DENALI_PI_98_WRITE_MASK 0xFFFFFFFFU
  1590. #define LPDDR4__DENALI_PI_98__PI_BIST_DATA_MASK_0_MASK 0xFFFFFFFFU
  1591. #define LPDDR4__DENALI_PI_98__PI_BIST_DATA_MASK_0_SHIFT 0U
  1592. #define LPDDR4__DENALI_PI_98__PI_BIST_DATA_MASK_0_WIDTH 32U
  1593. #define LPDDR4__PI_BIST_DATA_MASK_0__REG DENALI_PI_98
  1594. #define LPDDR4__PI_BIST_DATA_MASK_0__FLD LPDDR4__DENALI_PI_98__PI_BIST_DATA_MASK_0
  1595. #define LPDDR4__DENALI_PI_99_READ_MASK 0xFFFFFFFFU
  1596. #define LPDDR4__DENALI_PI_99_WRITE_MASK 0xFFFFFFFFU
  1597. #define LPDDR4__DENALI_PI_99__PI_BIST_DATA_MASK_1_MASK 0xFFFFFFFFU
  1598. #define LPDDR4__DENALI_PI_99__PI_BIST_DATA_MASK_1_SHIFT 0U
  1599. #define LPDDR4__DENALI_PI_99__PI_BIST_DATA_MASK_1_WIDTH 32U
  1600. #define LPDDR4__PI_BIST_DATA_MASK_1__REG DENALI_PI_99
  1601. #define LPDDR4__PI_BIST_DATA_MASK_1__FLD LPDDR4__DENALI_PI_99__PI_BIST_DATA_MASK_1
  1602. #define LPDDR4__DENALI_PI_100_READ_MASK 0x0FFF0FFFU
  1603. #define LPDDR4__DENALI_PI_100_WRITE_MASK 0x0FFF0FFFU
  1604. #define LPDDR4__DENALI_PI_100__PI_BIST_ERR_COUNT_MASK 0x00000FFFU
  1605. #define LPDDR4__DENALI_PI_100__PI_BIST_ERR_COUNT_SHIFT 0U
  1606. #define LPDDR4__DENALI_PI_100__PI_BIST_ERR_COUNT_WIDTH 12U
  1607. #define LPDDR4__PI_BIST_ERR_COUNT__REG DENALI_PI_100
  1608. #define LPDDR4__PI_BIST_ERR_COUNT__FLD LPDDR4__DENALI_PI_100__PI_BIST_ERR_COUNT
  1609. #define LPDDR4__DENALI_PI_100__PI_BIST_ERR_STOP_MASK 0x0FFF0000U
  1610. #define LPDDR4__DENALI_PI_100__PI_BIST_ERR_STOP_SHIFT 16U
  1611. #define LPDDR4__DENALI_PI_100__PI_BIST_ERR_STOP_WIDTH 12U
  1612. #define LPDDR4__PI_BIST_ERR_STOP__REG DENALI_PI_100
  1613. #define LPDDR4__PI_BIST_ERR_STOP__FLD LPDDR4__DENALI_PI_100__PI_BIST_ERR_STOP
  1614. #define LPDDR4__DENALI_PI_101_READ_MASK 0xFFFFFFFFU
  1615. #define LPDDR4__DENALI_PI_101_WRITE_MASK 0xFFFFFFFFU
  1616. #define LPDDR4__DENALI_PI_101__PI_BIST_ADDR_MASK_0_0_MASK 0xFFFFFFFFU
  1617. #define LPDDR4__DENALI_PI_101__PI_BIST_ADDR_MASK_0_0_SHIFT 0U
  1618. #define LPDDR4__DENALI_PI_101__PI_BIST_ADDR_MASK_0_0_WIDTH 32U
  1619. #define LPDDR4__PI_BIST_ADDR_MASK_0_0__REG DENALI_PI_101
  1620. #define LPDDR4__PI_BIST_ADDR_MASK_0_0__FLD LPDDR4__DENALI_PI_101__PI_BIST_ADDR_MASK_0_0
  1621. #define LPDDR4__DENALI_PI_102_READ_MASK 0x0000000FU
  1622. #define LPDDR4__DENALI_PI_102_WRITE_MASK 0x0000000FU
  1623. #define LPDDR4__DENALI_PI_102__PI_BIST_ADDR_MASK_0_1_MASK 0x0000000FU
  1624. #define LPDDR4__DENALI_PI_102__PI_BIST_ADDR_MASK_0_1_SHIFT 0U
  1625. #define LPDDR4__DENALI_PI_102__PI_BIST_ADDR_MASK_0_1_WIDTH 4U
  1626. #define LPDDR4__PI_BIST_ADDR_MASK_0_1__REG DENALI_PI_102
  1627. #define LPDDR4__PI_BIST_ADDR_MASK_0_1__FLD LPDDR4__DENALI_PI_102__PI_BIST_ADDR_MASK_0_1
  1628. #define LPDDR4__DENALI_PI_103_READ_MASK 0xFFFFFFFFU
  1629. #define LPDDR4__DENALI_PI_103_WRITE_MASK 0xFFFFFFFFU
  1630. #define LPDDR4__DENALI_PI_103__PI_BIST_ADDR_MASK_1_0_MASK 0xFFFFFFFFU
  1631. #define LPDDR4__DENALI_PI_103__PI_BIST_ADDR_MASK_1_0_SHIFT 0U
  1632. #define LPDDR4__DENALI_PI_103__PI_BIST_ADDR_MASK_1_0_WIDTH 32U
  1633. #define LPDDR4__PI_BIST_ADDR_MASK_1_0__REG DENALI_PI_103
  1634. #define LPDDR4__PI_BIST_ADDR_MASK_1_0__FLD LPDDR4__DENALI_PI_103__PI_BIST_ADDR_MASK_1_0
  1635. #define LPDDR4__DENALI_PI_104_READ_MASK 0x0000000FU
  1636. #define LPDDR4__DENALI_PI_104_WRITE_MASK 0x0000000FU
  1637. #define LPDDR4__DENALI_PI_104__PI_BIST_ADDR_MASK_1_1_MASK 0x0000000FU
  1638. #define LPDDR4__DENALI_PI_104__PI_BIST_ADDR_MASK_1_1_SHIFT 0U
  1639. #define LPDDR4__DENALI_PI_104__PI_BIST_ADDR_MASK_1_1_WIDTH 4U
  1640. #define LPDDR4__PI_BIST_ADDR_MASK_1_1__REG DENALI_PI_104
  1641. #define LPDDR4__PI_BIST_ADDR_MASK_1_1__FLD LPDDR4__DENALI_PI_104__PI_BIST_ADDR_MASK_1_1
  1642. #define LPDDR4__DENALI_PI_105_READ_MASK 0xFFFFFFFFU
  1643. #define LPDDR4__DENALI_PI_105_WRITE_MASK 0xFFFFFFFFU
  1644. #define LPDDR4__DENALI_PI_105__PI_BIST_ADDR_MASK_2_0_MASK 0xFFFFFFFFU
  1645. #define LPDDR4__DENALI_PI_105__PI_BIST_ADDR_MASK_2_0_SHIFT 0U
  1646. #define LPDDR4__DENALI_PI_105__PI_BIST_ADDR_MASK_2_0_WIDTH 32U
  1647. #define LPDDR4__PI_BIST_ADDR_MASK_2_0__REG DENALI_PI_105
  1648. #define LPDDR4__PI_BIST_ADDR_MASK_2_0__FLD LPDDR4__DENALI_PI_105__PI_BIST_ADDR_MASK_2_0
  1649. #define LPDDR4__DENALI_PI_106_READ_MASK 0x0000000FU
  1650. #define LPDDR4__DENALI_PI_106_WRITE_MASK 0x0000000FU
  1651. #define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_MASK_2_1_MASK 0x0000000FU
  1652. #define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_MASK_2_1_SHIFT 0U
  1653. #define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_MASK_2_1_WIDTH 4U
  1654. #define LPDDR4__PI_BIST_ADDR_MASK_2_1__REG DENALI_PI_106
  1655. #define LPDDR4__PI_BIST_ADDR_MASK_2_1__FLD LPDDR4__DENALI_PI_106__PI_BIST_ADDR_MASK_2_1
  1656. #define LPDDR4__DENALI_PI_107_READ_MASK 0xFFFFFFFFU
  1657. #define LPDDR4__DENALI_PI_107_WRITE_MASK 0xFFFFFFFFU
  1658. #define LPDDR4__DENALI_PI_107__PI_BIST_ADDR_MASK_3_0_MASK 0xFFFFFFFFU
  1659. #define LPDDR4__DENALI_PI_107__PI_BIST_ADDR_MASK_3_0_SHIFT 0U
  1660. #define LPDDR4__DENALI_PI_107__PI_BIST_ADDR_MASK_3_0_WIDTH 32U
  1661. #define LPDDR4__PI_BIST_ADDR_MASK_3_0__REG DENALI_PI_107
  1662. #define LPDDR4__PI_BIST_ADDR_MASK_3_0__FLD LPDDR4__DENALI_PI_107__PI_BIST_ADDR_MASK_3_0
  1663. #define LPDDR4__DENALI_PI_108_READ_MASK 0x0000000FU
  1664. #define LPDDR4__DENALI_PI_108_WRITE_MASK 0x0000000FU
  1665. #define LPDDR4__DENALI_PI_108__PI_BIST_ADDR_MASK_3_1_MASK 0x0000000FU
  1666. #define LPDDR4__DENALI_PI_108__PI_BIST_ADDR_MASK_3_1_SHIFT 0U
  1667. #define LPDDR4__DENALI_PI_108__PI_BIST_ADDR_MASK_3_1_WIDTH 4U
  1668. #define LPDDR4__PI_BIST_ADDR_MASK_3_1__REG DENALI_PI_108
  1669. #define LPDDR4__PI_BIST_ADDR_MASK_3_1__FLD LPDDR4__DENALI_PI_108__PI_BIST_ADDR_MASK_3_1
  1670. #define LPDDR4__DENALI_PI_109_READ_MASK 0xFFFFFFFFU
  1671. #define LPDDR4__DENALI_PI_109_WRITE_MASK 0xFFFFFFFFU
  1672. #define LPDDR4__DENALI_PI_109__PI_BIST_ADDR_MASK_4_0_MASK 0xFFFFFFFFU
  1673. #define LPDDR4__DENALI_PI_109__PI_BIST_ADDR_MASK_4_0_SHIFT 0U
  1674. #define LPDDR4__DENALI_PI_109__PI_BIST_ADDR_MASK_4_0_WIDTH 32U
  1675. #define LPDDR4__PI_BIST_ADDR_MASK_4_0__REG DENALI_PI_109
  1676. #define LPDDR4__PI_BIST_ADDR_MASK_4_0__FLD LPDDR4__DENALI_PI_109__PI_BIST_ADDR_MASK_4_0
  1677. #define LPDDR4__DENALI_PI_110_READ_MASK 0x0000000FU
  1678. #define LPDDR4__DENALI_PI_110_WRITE_MASK 0x0000000FU
  1679. #define LPDDR4__DENALI_PI_110__PI_BIST_ADDR_MASK_4_1_MASK 0x0000000FU
  1680. #define LPDDR4__DENALI_PI_110__PI_BIST_ADDR_MASK_4_1_SHIFT 0U
  1681. #define LPDDR4__DENALI_PI_110__PI_BIST_ADDR_MASK_4_1_WIDTH 4U
  1682. #define LPDDR4__PI_BIST_ADDR_MASK_4_1__REG DENALI_PI_110
  1683. #define LPDDR4__PI_BIST_ADDR_MASK_4_1__FLD LPDDR4__DENALI_PI_110__PI_BIST_ADDR_MASK_4_1
  1684. #define LPDDR4__DENALI_PI_111_READ_MASK 0xFFFFFFFFU
  1685. #define LPDDR4__DENALI_PI_111_WRITE_MASK 0xFFFFFFFFU
  1686. #define LPDDR4__DENALI_PI_111__PI_BIST_ADDR_MASK_5_0_MASK 0xFFFFFFFFU
  1687. #define LPDDR4__DENALI_PI_111__PI_BIST_ADDR_MASK_5_0_SHIFT 0U
  1688. #define LPDDR4__DENALI_PI_111__PI_BIST_ADDR_MASK_5_0_WIDTH 32U
  1689. #define LPDDR4__PI_BIST_ADDR_MASK_5_0__REG DENALI_PI_111
  1690. #define LPDDR4__PI_BIST_ADDR_MASK_5_0__FLD LPDDR4__DENALI_PI_111__PI_BIST_ADDR_MASK_5_0
  1691. #define LPDDR4__DENALI_PI_112_READ_MASK 0x0000000FU
  1692. #define LPDDR4__DENALI_PI_112_WRITE_MASK 0x0000000FU
  1693. #define LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_5_1_MASK 0x0000000FU
  1694. #define LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_5_1_SHIFT 0U
  1695. #define LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_5_1_WIDTH 4U
  1696. #define LPDDR4__PI_BIST_ADDR_MASK_5_1__REG DENALI_PI_112
  1697. #define LPDDR4__PI_BIST_ADDR_MASK_5_1__FLD LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_5_1
  1698. #define LPDDR4__DENALI_PI_113_READ_MASK 0xFFFFFFFFU
  1699. #define LPDDR4__DENALI_PI_113_WRITE_MASK 0xFFFFFFFFU
  1700. #define LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_6_0_MASK 0xFFFFFFFFU
  1701. #define LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_6_0_SHIFT 0U
  1702. #define LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_6_0_WIDTH 32U
  1703. #define LPDDR4__PI_BIST_ADDR_MASK_6_0__REG DENALI_PI_113
  1704. #define LPDDR4__PI_BIST_ADDR_MASK_6_0__FLD LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_6_0
  1705. #define LPDDR4__DENALI_PI_114_READ_MASK 0x0000000FU
  1706. #define LPDDR4__DENALI_PI_114_WRITE_MASK 0x0000000FU
  1707. #define LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_6_1_MASK 0x0000000FU
  1708. #define LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_6_1_SHIFT 0U
  1709. #define LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_6_1_WIDTH 4U
  1710. #define LPDDR4__PI_BIST_ADDR_MASK_6_1__REG DENALI_PI_114
  1711. #define LPDDR4__PI_BIST_ADDR_MASK_6_1__FLD LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_6_1
  1712. #define LPDDR4__DENALI_PI_115_READ_MASK 0xFFFFFFFFU
  1713. #define LPDDR4__DENALI_PI_115_WRITE_MASK 0xFFFFFFFFU
  1714. #define LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_7_0_MASK 0xFFFFFFFFU
  1715. #define LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_7_0_SHIFT 0U
  1716. #define LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_7_0_WIDTH 32U
  1717. #define LPDDR4__PI_BIST_ADDR_MASK_7_0__REG DENALI_PI_115
  1718. #define LPDDR4__PI_BIST_ADDR_MASK_7_0__FLD LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_7_0
  1719. #define LPDDR4__DENALI_PI_116_READ_MASK 0x0000000FU
  1720. #define LPDDR4__DENALI_PI_116_WRITE_MASK 0x0000000FU
  1721. #define LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_7_1_MASK 0x0000000FU
  1722. #define LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_7_1_SHIFT 0U
  1723. #define LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_7_1_WIDTH 4U
  1724. #define LPDDR4__PI_BIST_ADDR_MASK_7_1__REG DENALI_PI_116
  1725. #define LPDDR4__PI_BIST_ADDR_MASK_7_1__FLD LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_7_1
  1726. #define LPDDR4__DENALI_PI_117_READ_MASK 0xFFFFFFFFU
  1727. #define LPDDR4__DENALI_PI_117_WRITE_MASK 0xFFFFFFFFU
  1728. #define LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_8_0_MASK 0xFFFFFFFFU
  1729. #define LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_8_0_SHIFT 0U
  1730. #define LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_8_0_WIDTH 32U
  1731. #define LPDDR4__PI_BIST_ADDR_MASK_8_0__REG DENALI_PI_117
  1732. #define LPDDR4__PI_BIST_ADDR_MASK_8_0__FLD LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_8_0
  1733. #define LPDDR4__DENALI_PI_118_READ_MASK 0x0000000FU
  1734. #define LPDDR4__DENALI_PI_118_WRITE_MASK 0x0000000FU
  1735. #define LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_8_1_MASK 0x0000000FU
  1736. #define LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_8_1_SHIFT 0U
  1737. #define LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_8_1_WIDTH 4U
  1738. #define LPDDR4__PI_BIST_ADDR_MASK_8_1__REG DENALI_PI_118
  1739. #define LPDDR4__PI_BIST_ADDR_MASK_8_1__FLD LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_8_1
  1740. #define LPDDR4__DENALI_PI_119_READ_MASK 0xFFFFFFFFU
  1741. #define LPDDR4__DENALI_PI_119_WRITE_MASK 0xFFFFFFFFU
  1742. #define LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_9_0_MASK 0xFFFFFFFFU
  1743. #define LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_9_0_SHIFT 0U
  1744. #define LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_9_0_WIDTH 32U
  1745. #define LPDDR4__PI_BIST_ADDR_MASK_9_0__REG DENALI_PI_119
  1746. #define LPDDR4__PI_BIST_ADDR_MASK_9_0__FLD LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_9_0
  1747. #define LPDDR4__DENALI_PI_120_READ_MASK 0x0303070FU
  1748. #define LPDDR4__DENALI_PI_120_WRITE_MASK 0x0303070FU
  1749. #define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_9_1_MASK 0x0000000FU
  1750. #define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_9_1_SHIFT 0U
  1751. #define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_9_1_WIDTH 4U
  1752. #define LPDDR4__PI_BIST_ADDR_MASK_9_1__REG DENALI_PI_120
  1753. #define LPDDR4__PI_BIST_ADDR_MASK_9_1__FLD LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_9_1
  1754. #define LPDDR4__DENALI_PI_120__PI_BIST_MODE_MASK 0x00000700U
  1755. #define LPDDR4__DENALI_PI_120__PI_BIST_MODE_SHIFT 8U
  1756. #define LPDDR4__DENALI_PI_120__PI_BIST_MODE_WIDTH 3U
  1757. #define LPDDR4__PI_BIST_MODE__REG DENALI_PI_120
  1758. #define LPDDR4__PI_BIST_MODE__FLD LPDDR4__DENALI_PI_120__PI_BIST_MODE
  1759. #define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MODE_MASK 0x00030000U
  1760. #define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MODE_SHIFT 16U
  1761. #define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MODE_WIDTH 2U
  1762. #define LPDDR4__PI_BIST_ADDR_MODE__REG DENALI_PI_120
  1763. #define LPDDR4__PI_BIST_ADDR_MODE__FLD LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MODE
  1764. #define LPDDR4__DENALI_PI_120__PI_BIST_PAT_MODE_MASK 0x03000000U
  1765. #define LPDDR4__DENALI_PI_120__PI_BIST_PAT_MODE_SHIFT 24U
  1766. #define LPDDR4__DENALI_PI_120__PI_BIST_PAT_MODE_WIDTH 2U
  1767. #define LPDDR4__PI_BIST_PAT_MODE__REG DENALI_PI_120
  1768. #define LPDDR4__PI_BIST_PAT_MODE__FLD LPDDR4__DENALI_PI_120__PI_BIST_PAT_MODE
  1769. #define LPDDR4__DENALI_PI_121_READ_MASK 0xFFFFFFFFU
  1770. #define LPDDR4__DENALI_PI_121_WRITE_MASK 0xFFFFFFFFU
  1771. #define LPDDR4__DENALI_PI_121__PI_BIST_USER_PAT_0_MASK 0xFFFFFFFFU
  1772. #define LPDDR4__DENALI_PI_121__PI_BIST_USER_PAT_0_SHIFT 0U
  1773. #define LPDDR4__DENALI_PI_121__PI_BIST_USER_PAT_0_WIDTH 32U
  1774. #define LPDDR4__PI_BIST_USER_PAT_0__REG DENALI_PI_121
  1775. #define LPDDR4__PI_BIST_USER_PAT_0__FLD LPDDR4__DENALI_PI_121__PI_BIST_USER_PAT_0
  1776. #define LPDDR4__DENALI_PI_122_READ_MASK 0xFFFFFFFFU
  1777. #define LPDDR4__DENALI_PI_122_WRITE_MASK 0xFFFFFFFFU
  1778. #define LPDDR4__DENALI_PI_122__PI_BIST_USER_PAT_1_MASK 0xFFFFFFFFU
  1779. #define LPDDR4__DENALI_PI_122__PI_BIST_USER_PAT_1_SHIFT 0U
  1780. #define LPDDR4__DENALI_PI_122__PI_BIST_USER_PAT_1_WIDTH 32U
  1781. #define LPDDR4__PI_BIST_USER_PAT_1__REG DENALI_PI_122
  1782. #define LPDDR4__PI_BIST_USER_PAT_1__FLD LPDDR4__DENALI_PI_122__PI_BIST_USER_PAT_1
  1783. #define LPDDR4__DENALI_PI_123_READ_MASK 0xFFFFFFFFU
  1784. #define LPDDR4__DENALI_PI_123_WRITE_MASK 0xFFFFFFFFU
  1785. #define LPDDR4__DENALI_PI_123__PI_BIST_USER_PAT_2_MASK 0xFFFFFFFFU
  1786. #define LPDDR4__DENALI_PI_123__PI_BIST_USER_PAT_2_SHIFT 0U
  1787. #define LPDDR4__DENALI_PI_123__PI_BIST_USER_PAT_2_WIDTH 32U
  1788. #define LPDDR4__PI_BIST_USER_PAT_2__REG DENALI_PI_123
  1789. #define LPDDR4__PI_BIST_USER_PAT_2__FLD LPDDR4__DENALI_PI_123__PI_BIST_USER_PAT_2
  1790. #define LPDDR4__DENALI_PI_124_READ_MASK 0xFFFFFFFFU
  1791. #define LPDDR4__DENALI_PI_124_WRITE_MASK 0xFFFFFFFFU
  1792. #define LPDDR4__DENALI_PI_124__PI_BIST_USER_PAT_3_MASK 0xFFFFFFFFU
  1793. #define LPDDR4__DENALI_PI_124__PI_BIST_USER_PAT_3_SHIFT 0U
  1794. #define LPDDR4__DENALI_PI_124__PI_BIST_USER_PAT_3_WIDTH 32U
  1795. #define LPDDR4__PI_BIST_USER_PAT_3__REG DENALI_PI_124
  1796. #define LPDDR4__PI_BIST_USER_PAT_3__FLD LPDDR4__DENALI_PI_124__PI_BIST_USER_PAT_3
  1797. #define LPDDR4__DENALI_PI_125_READ_MASK 0x0000000FU
  1798. #define LPDDR4__DENALI_PI_125_WRITE_MASK 0x0000000FU
  1799. #define LPDDR4__DENALI_PI_125__PI_BIST_PAT_NUM_MASK 0x0000000FU
  1800. #define LPDDR4__DENALI_PI_125__PI_BIST_PAT_NUM_SHIFT 0U
  1801. #define LPDDR4__DENALI_PI_125__PI_BIST_PAT_NUM_WIDTH 4U
  1802. #define LPDDR4__PI_BIST_PAT_NUM__REG DENALI_PI_125
  1803. #define LPDDR4__PI_BIST_PAT_NUM__FLD LPDDR4__DENALI_PI_125__PI_BIST_PAT_NUM
  1804. #define LPDDR4__DENALI_PI_126_READ_MASK 0x3FFFFFFFU
  1805. #define LPDDR4__DENALI_PI_126_WRITE_MASK 0x3FFFFFFFU
  1806. #define LPDDR4__DENALI_PI_126__PI_BIST_STAGE_0_MASK 0x3FFFFFFFU
  1807. #define LPDDR4__DENALI_PI_126__PI_BIST_STAGE_0_SHIFT 0U
  1808. #define LPDDR4__DENALI_PI_126__PI_BIST_STAGE_0_WIDTH 30U
  1809. #define LPDDR4__PI_BIST_STAGE_0__REG DENALI_PI_126
  1810. #define LPDDR4__PI_BIST_STAGE_0__FLD LPDDR4__DENALI_PI_126__PI_BIST_STAGE_0
  1811. #define LPDDR4__DENALI_PI_127_READ_MASK 0x3FFFFFFFU
  1812. #define LPDDR4__DENALI_PI_127_WRITE_MASK 0x3FFFFFFFU
  1813. #define LPDDR4__DENALI_PI_127__PI_BIST_STAGE_1_MASK 0x3FFFFFFFU
  1814. #define LPDDR4__DENALI_PI_127__PI_BIST_STAGE_1_SHIFT 0U
  1815. #define LPDDR4__DENALI_PI_127__PI_BIST_STAGE_1_WIDTH 30U
  1816. #define LPDDR4__PI_BIST_STAGE_1__REG DENALI_PI_127
  1817. #define LPDDR4__PI_BIST_STAGE_1__FLD LPDDR4__DENALI_PI_127__PI_BIST_STAGE_1
  1818. #define LPDDR4__DENALI_PI_128_READ_MASK 0x3FFFFFFFU
  1819. #define LPDDR4__DENALI_PI_128_WRITE_MASK 0x3FFFFFFFU
  1820. #define LPDDR4__DENALI_PI_128__PI_BIST_STAGE_2_MASK 0x3FFFFFFFU
  1821. #define LPDDR4__DENALI_PI_128__PI_BIST_STAGE_2_SHIFT 0U
  1822. #define LPDDR4__DENALI_PI_128__PI_BIST_STAGE_2_WIDTH 30U
  1823. #define LPDDR4__PI_BIST_STAGE_2__REG DENALI_PI_128
  1824. #define LPDDR4__PI_BIST_STAGE_2__FLD LPDDR4__DENALI_PI_128__PI_BIST_STAGE_2
  1825. #define LPDDR4__DENALI_PI_129_READ_MASK 0x3FFFFFFFU
  1826. #define LPDDR4__DENALI_PI_129_WRITE_MASK 0x3FFFFFFFU
  1827. #define LPDDR4__DENALI_PI_129__PI_BIST_STAGE_3_MASK 0x3FFFFFFFU
  1828. #define LPDDR4__DENALI_PI_129__PI_BIST_STAGE_3_SHIFT 0U
  1829. #define LPDDR4__DENALI_PI_129__PI_BIST_STAGE_3_WIDTH 30U
  1830. #define LPDDR4__PI_BIST_STAGE_3__REG DENALI_PI_129
  1831. #define LPDDR4__PI_BIST_STAGE_3__FLD LPDDR4__DENALI_PI_129__PI_BIST_STAGE_3
  1832. #define LPDDR4__DENALI_PI_130_READ_MASK 0x3FFFFFFFU
  1833. #define LPDDR4__DENALI_PI_130_WRITE_MASK 0x3FFFFFFFU
  1834. #define LPDDR4__DENALI_PI_130__PI_BIST_STAGE_4_MASK 0x3FFFFFFFU
  1835. #define LPDDR4__DENALI_PI_130__PI_BIST_STAGE_4_SHIFT 0U
  1836. #define LPDDR4__DENALI_PI_130__PI_BIST_STAGE_4_WIDTH 30U
  1837. #define LPDDR4__PI_BIST_STAGE_4__REG DENALI_PI_130
  1838. #define LPDDR4__PI_BIST_STAGE_4__FLD LPDDR4__DENALI_PI_130__PI_BIST_STAGE_4
  1839. #define LPDDR4__DENALI_PI_131_READ_MASK 0x3FFFFFFFU
  1840. #define LPDDR4__DENALI_PI_131_WRITE_MASK 0x3FFFFFFFU
  1841. #define LPDDR4__DENALI_PI_131__PI_BIST_STAGE_5_MASK 0x3FFFFFFFU
  1842. #define LPDDR4__DENALI_PI_131__PI_BIST_STAGE_5_SHIFT 0U
  1843. #define LPDDR4__DENALI_PI_131__PI_BIST_STAGE_5_WIDTH 30U
  1844. #define LPDDR4__PI_BIST_STAGE_5__REG DENALI_PI_131
  1845. #define LPDDR4__PI_BIST_STAGE_5__FLD LPDDR4__DENALI_PI_131__PI_BIST_STAGE_5
  1846. #define LPDDR4__DENALI_PI_132_READ_MASK 0x3FFFFFFFU
  1847. #define LPDDR4__DENALI_PI_132_WRITE_MASK 0x3FFFFFFFU
  1848. #define LPDDR4__DENALI_PI_132__PI_BIST_STAGE_6_MASK 0x3FFFFFFFU
  1849. #define LPDDR4__DENALI_PI_132__PI_BIST_STAGE_6_SHIFT 0U
  1850. #define LPDDR4__DENALI_PI_132__PI_BIST_STAGE_6_WIDTH 30U
  1851. #define LPDDR4__PI_BIST_STAGE_6__REG DENALI_PI_132
  1852. #define LPDDR4__PI_BIST_STAGE_6__FLD LPDDR4__DENALI_PI_132__PI_BIST_STAGE_6
  1853. #define LPDDR4__DENALI_PI_133_READ_MASK 0x3FFFFFFFU
  1854. #define LPDDR4__DENALI_PI_133_WRITE_MASK 0x3FFFFFFFU
  1855. #define LPDDR4__DENALI_PI_133__PI_BIST_STAGE_7_MASK 0x3FFFFFFFU
  1856. #define LPDDR4__DENALI_PI_133__PI_BIST_STAGE_7_SHIFT 0U
  1857. #define LPDDR4__DENALI_PI_133__PI_BIST_STAGE_7_WIDTH 30U
  1858. #define LPDDR4__PI_BIST_STAGE_7__REG DENALI_PI_133
  1859. #define LPDDR4__PI_BIST_STAGE_7__FLD LPDDR4__DENALI_PI_133__PI_BIST_STAGE_7
  1860. #define LPDDR4__DENALI_PI_134_READ_MASK 0x0101010FU
  1861. #define LPDDR4__DENALI_PI_134_WRITE_MASK 0x0101010FU
  1862. #define LPDDR4__DENALI_PI_134__PI_COL_DIFF_MASK 0x0000000FU
  1863. #define LPDDR4__DENALI_PI_134__PI_COL_DIFF_SHIFT 0U
  1864. #define LPDDR4__DENALI_PI_134__PI_COL_DIFF_WIDTH 4U
  1865. #define LPDDR4__PI_COL_DIFF__REG DENALI_PI_134
  1866. #define LPDDR4__PI_COL_DIFF__FLD LPDDR4__DENALI_PI_134__PI_COL_DIFF
  1867. #define LPDDR4__DENALI_PI_134__PI_SELF_REFRESH_EN_MASK 0x00000100U
  1868. #define LPDDR4__DENALI_PI_134__PI_SELF_REFRESH_EN_SHIFT 8U
  1869. #define LPDDR4__DENALI_PI_134__PI_SELF_REFRESH_EN_WIDTH 1U
  1870. #define LPDDR4__DENALI_PI_134__PI_SELF_REFRESH_EN_WOCLR 0U
  1871. #define LPDDR4__DENALI_PI_134__PI_SELF_REFRESH_EN_WOSET 0U
  1872. #define LPDDR4__PI_SELF_REFRESH_EN__REG DENALI_PI_134
  1873. #define LPDDR4__PI_SELF_REFRESH_EN__FLD LPDDR4__DENALI_PI_134__PI_SELF_REFRESH_EN
  1874. #define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_MASK 0x00010000U
  1875. #define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_SHIFT 16U
  1876. #define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_WIDTH 1U
  1877. #define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_WOCLR 0U
  1878. #define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_WOSET 0U
  1879. #define LPDDR4__PI_PWRUP_SREFRESH_EXIT__REG DENALI_PI_134
  1880. #define LPDDR4__PI_PWRUP_SREFRESH_EXIT__FLD LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT
  1881. #define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_MASK 0x01000000U
  1882. #define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_SHIFT 24U
  1883. #define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_WIDTH 1U
  1884. #define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_WOCLR 0U
  1885. #define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_WOSET 0U
  1886. #define LPDDR4__PI_SREFRESH_EXIT_NO_REFRESH__REG DENALI_PI_134
  1887. #define LPDDR4__PI_SREFRESH_EXIT_NO_REFRESH__FLD LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH
  1888. #define LPDDR4__DENALI_PI_135_READ_MASK 0x01010100U
  1889. #define LPDDR4__DENALI_PI_135_WRITE_MASK 0x01010100U
  1890. #define LPDDR4__DENALI_PI_135__PI_SREF_ENTRY_REQ_MASK 0x00000001U
  1891. #define LPDDR4__DENALI_PI_135__PI_SREF_ENTRY_REQ_SHIFT 0U
  1892. #define LPDDR4__DENALI_PI_135__PI_SREF_ENTRY_REQ_WIDTH 1U
  1893. #define LPDDR4__DENALI_PI_135__PI_SREF_ENTRY_REQ_WOCLR 0U
  1894. #define LPDDR4__DENALI_PI_135__PI_SREF_ENTRY_REQ_WOSET 0U
  1895. #define LPDDR4__PI_SREF_ENTRY_REQ__REG DENALI_PI_135
  1896. #define LPDDR4__PI_SREF_ENTRY_REQ__FLD LPDDR4__DENALI_PI_135__PI_SREF_ENTRY_REQ
  1897. #define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_MASK 0x00000100U
  1898. #define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_SHIFT 8U
  1899. #define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_WIDTH 1U
  1900. #define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_WOCLR 0U
  1901. #define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_WOSET 0U
  1902. #define LPDDR4__PI_NO_MRW_BT_INIT__REG DENALI_PI_135
  1903. #define LPDDR4__PI_NO_MRW_BT_INIT__FLD LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT
  1904. #define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_MASK 0x00010000U
  1905. #define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_SHIFT 16U
  1906. #define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_WIDTH 1U
  1907. #define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_WOCLR 0U
  1908. #define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_WOSET 0U
  1909. #define LPDDR4__PI_NO_MRW_INIT__REG DENALI_PI_135
  1910. #define LPDDR4__PI_NO_MRW_INIT__FLD LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT
  1911. #define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_MASK 0x01000000U
  1912. #define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_SHIFT 24U
  1913. #define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_WIDTH 1U
  1914. #define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_WOCLR 0U
  1915. #define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_WOSET 0U
  1916. #define LPDDR4__PI_NO_PHY_IND_TRAIN_INIT__REG DENALI_PI_135
  1917. #define LPDDR4__PI_NO_PHY_IND_TRAIN_INIT__FLD LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT
  1918. #define LPDDR4__DENALI_PI_136_READ_MASK 0x00000001U
  1919. #define LPDDR4__DENALI_PI_136_WRITE_MASK 0x00000001U
  1920. #define LPDDR4__DENALI_PI_136__PI_NO_AUTO_MRR_INIT_MASK 0x00000001U
  1921. #define LPDDR4__DENALI_PI_136__PI_NO_AUTO_MRR_INIT_SHIFT 0U
  1922. #define LPDDR4__DENALI_PI_136__PI_NO_AUTO_MRR_INIT_WIDTH 1U
  1923. #define LPDDR4__DENALI_PI_136__PI_NO_AUTO_MRR_INIT_WOCLR 0U
  1924. #define LPDDR4__DENALI_PI_136__PI_NO_AUTO_MRR_INIT_WOSET 0U
  1925. #define LPDDR4__PI_NO_AUTO_MRR_INIT__REG DENALI_PI_136
  1926. #define LPDDR4__PI_NO_AUTO_MRR_INIT__FLD LPDDR4__DENALI_PI_136__PI_NO_AUTO_MRR_INIT
  1927. #define LPDDR4__DENALI_PI_137_READ_MASK 0xFFFFFFFFU
  1928. #define LPDDR4__DENALI_PI_137_WRITE_MASK 0xFFFFFFFFU
  1929. #define LPDDR4__DENALI_PI_137__PI_TRST_PWRON_MASK 0xFFFFFFFFU
  1930. #define LPDDR4__DENALI_PI_137__PI_TRST_PWRON_SHIFT 0U
  1931. #define LPDDR4__DENALI_PI_137__PI_TRST_PWRON_WIDTH 32U
  1932. #define LPDDR4__PI_TRST_PWRON__REG DENALI_PI_137
  1933. #define LPDDR4__PI_TRST_PWRON__FLD LPDDR4__DENALI_PI_137__PI_TRST_PWRON
  1934. #define LPDDR4__DENALI_PI_138_READ_MASK 0xFFFFFFFFU
  1935. #define LPDDR4__DENALI_PI_138_WRITE_MASK 0xFFFFFFFFU
  1936. #define LPDDR4__DENALI_PI_138__PI_CKE_INACTIVE_MASK 0xFFFFFFFFU
  1937. #define LPDDR4__DENALI_PI_138__PI_CKE_INACTIVE_SHIFT 0U
  1938. #define LPDDR4__DENALI_PI_138__PI_CKE_INACTIVE_WIDTH 32U
  1939. #define LPDDR4__PI_CKE_INACTIVE__REG DENALI_PI_138
  1940. #define LPDDR4__PI_CKE_INACTIVE__FLD LPDDR4__DENALI_PI_138__PI_CKE_INACTIVE
  1941. #define LPDDR4__DENALI_PI_139_READ_MASK 0xFFFF0101U
  1942. #define LPDDR4__DENALI_PI_139_WRITE_MASK 0xFFFF0101U
  1943. #define LPDDR4__DENALI_PI_139__PI_DLL_RST_MASK 0x00000001U
  1944. #define LPDDR4__DENALI_PI_139__PI_DLL_RST_SHIFT 0U
  1945. #define LPDDR4__DENALI_PI_139__PI_DLL_RST_WIDTH 1U
  1946. #define LPDDR4__DENALI_PI_139__PI_DLL_RST_WOCLR 0U
  1947. #define LPDDR4__DENALI_PI_139__PI_DLL_RST_WOSET 0U
  1948. #define LPDDR4__PI_DLL_RST__REG DENALI_PI_139
  1949. #define LPDDR4__PI_DLL_RST__FLD LPDDR4__DENALI_PI_139__PI_DLL_RST
  1950. #define LPDDR4__DENALI_PI_139__PI_DRAM_INIT_EN_MASK 0x00000100U
  1951. #define LPDDR4__DENALI_PI_139__PI_DRAM_INIT_EN_SHIFT 8U
  1952. #define LPDDR4__DENALI_PI_139__PI_DRAM_INIT_EN_WIDTH 1U
  1953. #define LPDDR4__DENALI_PI_139__PI_DRAM_INIT_EN_WOCLR 0U
  1954. #define LPDDR4__DENALI_PI_139__PI_DRAM_INIT_EN_WOSET 0U
  1955. #define LPDDR4__PI_DRAM_INIT_EN__REG DENALI_PI_139
  1956. #define LPDDR4__PI_DRAM_INIT_EN__FLD LPDDR4__DENALI_PI_139__PI_DRAM_INIT_EN
  1957. #define LPDDR4__DENALI_PI_139__PI_DLL_RST_DELAY_MASK 0xFFFF0000U
  1958. #define LPDDR4__DENALI_PI_139__PI_DLL_RST_DELAY_SHIFT 16U
  1959. #define LPDDR4__DENALI_PI_139__PI_DLL_RST_DELAY_WIDTH 16U
  1960. #define LPDDR4__PI_DLL_RST_DELAY__REG DENALI_PI_139
  1961. #define LPDDR4__PI_DLL_RST_DELAY__FLD LPDDR4__DENALI_PI_139__PI_DLL_RST_DELAY
  1962. #define LPDDR4__DENALI_PI_140_READ_MASK 0x000000FFU
  1963. #define LPDDR4__DENALI_PI_140_WRITE_MASK 0x000000FFU
  1964. #define LPDDR4__DENALI_PI_140__PI_DLL_RST_ADJ_DLY_MASK 0x000000FFU
  1965. #define LPDDR4__DENALI_PI_140__PI_DLL_RST_ADJ_DLY_SHIFT 0U
  1966. #define LPDDR4__DENALI_PI_140__PI_DLL_RST_ADJ_DLY_WIDTH 8U
  1967. #define LPDDR4__PI_DLL_RST_ADJ_DLY__REG DENALI_PI_140
  1968. #define LPDDR4__PI_DLL_RST_ADJ_DLY__FLD LPDDR4__DENALI_PI_140__PI_DLL_RST_ADJ_DLY
  1969. #define LPDDR4__DENALI_PI_141_READ_MASK 0x03FFFFFFU
  1970. #define LPDDR4__DENALI_PI_141_WRITE_MASK 0x03FFFFFFU
  1971. #define LPDDR4__DENALI_PI_141__PI_WRITE_MODEREG_MASK 0x03FFFFFFU
  1972. #define LPDDR4__DENALI_PI_141__PI_WRITE_MODEREG_SHIFT 0U
  1973. #define LPDDR4__DENALI_PI_141__PI_WRITE_MODEREG_WIDTH 26U
  1974. #define LPDDR4__PI_WRITE_MODEREG__REG DENALI_PI_141
  1975. #define LPDDR4__PI_WRITE_MODEREG__FLD LPDDR4__DENALI_PI_141__PI_WRITE_MODEREG
  1976. #define LPDDR4__DENALI_PI_142_READ_MASK 0x01FFFFFFU
  1977. #define LPDDR4__DENALI_PI_142_WRITE_MASK 0x01FFFFFFU
  1978. #define LPDDR4__DENALI_PI_142__PI_MRW_STATUS_MASK 0x000000FFU
  1979. #define LPDDR4__DENALI_PI_142__PI_MRW_STATUS_SHIFT 0U
  1980. #define LPDDR4__DENALI_PI_142__PI_MRW_STATUS_WIDTH 8U
  1981. #define LPDDR4__PI_MRW_STATUS__REG DENALI_PI_142
  1982. #define LPDDR4__PI_MRW_STATUS__FLD LPDDR4__DENALI_PI_142__PI_MRW_STATUS
  1983. #define LPDDR4__DENALI_PI_142__PI_READ_MODEREG_MASK 0x01FFFF00U
  1984. #define LPDDR4__DENALI_PI_142__PI_READ_MODEREG_SHIFT 8U
  1985. #define LPDDR4__DENALI_PI_142__PI_READ_MODEREG_WIDTH 17U
  1986. #define LPDDR4__PI_READ_MODEREG__REG DENALI_PI_142
  1987. #define LPDDR4__PI_READ_MODEREG__FLD LPDDR4__DENALI_PI_142__PI_READ_MODEREG
  1988. #define LPDDR4__DENALI_PI_143_READ_MASK 0x01FFFFFFU
  1989. #define LPDDR4__DENALI_PI_143_WRITE_MASK 0x01FFFFFFU
  1990. #define LPDDR4__DENALI_PI_143__PI_PERIPHERAL_MRR_DATA_0_MASK 0x00FFFFFFU
  1991. #define LPDDR4__DENALI_PI_143__PI_PERIPHERAL_MRR_DATA_0_SHIFT 0U
  1992. #define LPDDR4__DENALI_PI_143__PI_PERIPHERAL_MRR_DATA_0_WIDTH 24U
  1993. #define LPDDR4__PI_PERIPHERAL_MRR_DATA_0__REG DENALI_PI_143
  1994. #define LPDDR4__PI_PERIPHERAL_MRR_DATA_0__FLD LPDDR4__DENALI_PI_143__PI_PERIPHERAL_MRR_DATA_0
  1995. #define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_MASK 0x01000000U
  1996. #define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_SHIFT 24U
  1997. #define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_WIDTH 1U
  1998. #define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_WOCLR 0U
  1999. #define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_WOSET 0U
  2000. #define LPDDR4__PI_NO_ZQ_INIT__REG DENALI_PI_143
  2001. #define LPDDR4__PI_NO_ZQ_INIT__FLD LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT
  2002. #define LPDDR4__DENALI_PI_144_READ_MASK 0x0101000FU
  2003. #define LPDDR4__DENALI_PI_144_WRITE_MASK 0x0101000FU
  2004. #define LPDDR4__DENALI_PI_144__PI_RESERVED25_MASK 0x0000000FU
  2005. #define LPDDR4__DENALI_PI_144__PI_RESERVED25_SHIFT 0U
  2006. #define LPDDR4__DENALI_PI_144__PI_RESERVED25_WIDTH 4U
  2007. #define LPDDR4__PI_RESERVED25__REG DENALI_PI_144
  2008. #define LPDDR4__PI_RESERVED25__FLD LPDDR4__DENALI_PI_144__PI_RESERVED25
  2009. #define LPDDR4__DENALI_PI_144__PI_RESERVED26_MASK 0x00000F00U
  2010. #define LPDDR4__DENALI_PI_144__PI_RESERVED26_SHIFT 8U
  2011. #define LPDDR4__DENALI_PI_144__PI_RESERVED26_WIDTH 4U
  2012. #define LPDDR4__PI_RESERVED26__REG DENALI_PI_144
  2013. #define LPDDR4__PI_RESERVED26__FLD LPDDR4__DENALI_PI_144__PI_RESERVED26
  2014. #define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_MASK 0x00010000U
  2015. #define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_SHIFT 16U
  2016. #define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_WIDTH 1U
  2017. #define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_WOCLR 0U
  2018. #define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_WOSET 0U
  2019. #define LPDDR4__PI_ZQ_REQ_PENDING__REG DENALI_PI_144
  2020. #define LPDDR4__PI_ZQ_REQ_PENDING__FLD LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING
  2021. #define LPDDR4__DENALI_PI_144__PI_RESERVED27_MASK 0x01000000U
  2022. #define LPDDR4__DENALI_PI_144__PI_RESERVED27_SHIFT 24U
  2023. #define LPDDR4__DENALI_PI_144__PI_RESERVED27_WIDTH 1U
  2024. #define LPDDR4__DENALI_PI_144__PI_RESERVED27_WOCLR 0U
  2025. #define LPDDR4__DENALI_PI_144__PI_RESERVED27_WOSET 0U
  2026. #define LPDDR4__PI_RESERVED27__REG DENALI_PI_144
  2027. #define LPDDR4__PI_RESERVED27__FLD LPDDR4__DENALI_PI_144__PI_RESERVED27
  2028. #define LPDDR4__DENALI_PI_145_READ_MASK 0xFF010F07U
  2029. #define LPDDR4__DENALI_PI_145_WRITE_MASK 0xFF010F07U
  2030. #define LPDDR4__DENALI_PI_145__PI_RESERVED28_MASK 0x00000007U
  2031. #define LPDDR4__DENALI_PI_145__PI_RESERVED28_SHIFT 0U
  2032. #define LPDDR4__DENALI_PI_145__PI_RESERVED28_WIDTH 3U
  2033. #define LPDDR4__PI_RESERVED28__REG DENALI_PI_145
  2034. #define LPDDR4__PI_RESERVED28__FLD LPDDR4__DENALI_PI_145__PI_RESERVED28
  2035. #define LPDDR4__DENALI_PI_145__PI_MONITOR_SRC_SEL_0_MASK 0x00000F00U
  2036. #define LPDDR4__DENALI_PI_145__PI_MONITOR_SRC_SEL_0_SHIFT 8U
  2037. #define LPDDR4__DENALI_PI_145__PI_MONITOR_SRC_SEL_0_WIDTH 4U
  2038. #define LPDDR4__PI_MONITOR_SRC_SEL_0__REG DENALI_PI_145
  2039. #define LPDDR4__PI_MONITOR_SRC_SEL_0__FLD LPDDR4__DENALI_PI_145__PI_MONITOR_SRC_SEL_0
  2040. #define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_MASK 0x00010000U
  2041. #define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_SHIFT 16U
  2042. #define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_WIDTH 1U
  2043. #define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_WOCLR 0U
  2044. #define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_WOSET 0U
  2045. #define LPDDR4__PI_MONITOR_CAP_SEL_0__REG DENALI_PI_145
  2046. #define LPDDR4__PI_MONITOR_CAP_SEL_0__FLD LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0
  2047. #define LPDDR4__DENALI_PI_145__PI_MONITOR_0_MASK 0xFF000000U
  2048. #define LPDDR4__DENALI_PI_145__PI_MONITOR_0_SHIFT 24U
  2049. #define LPDDR4__DENALI_PI_145__PI_MONITOR_0_WIDTH 8U
  2050. #define LPDDR4__PI_MONITOR_0__REG DENALI_PI_145
  2051. #define LPDDR4__PI_MONITOR_0__FLD LPDDR4__DENALI_PI_145__PI_MONITOR_0
  2052. #define LPDDR4__DENALI_PI_146_READ_MASK 0x0FFF010FU
  2053. #define LPDDR4__DENALI_PI_146_WRITE_MASK 0x0FFF010FU
  2054. #define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_1_MASK 0x0000000FU
  2055. #define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_1_SHIFT 0U
  2056. #define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_1_WIDTH 4U
  2057. #define LPDDR4__PI_MONITOR_SRC_SEL_1__REG DENALI_PI_146
  2058. #define LPDDR4__PI_MONITOR_SRC_SEL_1__FLD LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_1
  2059. #define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_MASK 0x00000100U
  2060. #define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_SHIFT 8U
  2061. #define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_WIDTH 1U
  2062. #define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_WOCLR 0U
  2063. #define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_WOSET 0U
  2064. #define LPDDR4__PI_MONITOR_CAP_SEL_1__REG DENALI_PI_146
  2065. #define LPDDR4__PI_MONITOR_CAP_SEL_1__FLD LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1
  2066. #define LPDDR4__DENALI_PI_146__PI_MONITOR_1_MASK 0x00FF0000U
  2067. #define LPDDR4__DENALI_PI_146__PI_MONITOR_1_SHIFT 16U
  2068. #define LPDDR4__DENALI_PI_146__PI_MONITOR_1_WIDTH 8U
  2069. #define LPDDR4__PI_MONITOR_1__REG DENALI_PI_146
  2070. #define LPDDR4__PI_MONITOR_1__FLD LPDDR4__DENALI_PI_146__PI_MONITOR_1
  2071. #define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_2_MASK 0x0F000000U
  2072. #define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_2_SHIFT 24U
  2073. #define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_2_WIDTH 4U
  2074. #define LPDDR4__PI_MONITOR_SRC_SEL_2__REG DENALI_PI_146
  2075. #define LPDDR4__PI_MONITOR_SRC_SEL_2__FLD LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_2
  2076. #define LPDDR4__DENALI_PI_147_READ_MASK 0x010FFF01U
  2077. #define LPDDR4__DENALI_PI_147_WRITE_MASK 0x010FFF01U
  2078. #define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_MASK 0x00000001U
  2079. #define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_SHIFT 0U
  2080. #define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_WIDTH 1U
  2081. #define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_WOCLR 0U
  2082. #define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_WOSET 0U
  2083. #define LPDDR4__PI_MONITOR_CAP_SEL_2__REG DENALI_PI_147
  2084. #define LPDDR4__PI_MONITOR_CAP_SEL_2__FLD LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2
  2085. #define LPDDR4__DENALI_PI_147__PI_MONITOR_2_MASK 0x0000FF00U
  2086. #define LPDDR4__DENALI_PI_147__PI_MONITOR_2_SHIFT 8U
  2087. #define LPDDR4__DENALI_PI_147__PI_MONITOR_2_WIDTH 8U
  2088. #define LPDDR4__PI_MONITOR_2__REG DENALI_PI_147
  2089. #define LPDDR4__PI_MONITOR_2__FLD LPDDR4__DENALI_PI_147__PI_MONITOR_2
  2090. #define LPDDR4__DENALI_PI_147__PI_MONITOR_SRC_SEL_3_MASK 0x000F0000U
  2091. #define LPDDR4__DENALI_PI_147__PI_MONITOR_SRC_SEL_3_SHIFT 16U
  2092. #define LPDDR4__DENALI_PI_147__PI_MONITOR_SRC_SEL_3_WIDTH 4U
  2093. #define LPDDR4__PI_MONITOR_SRC_SEL_3__REG DENALI_PI_147
  2094. #define LPDDR4__PI_MONITOR_SRC_SEL_3__FLD LPDDR4__DENALI_PI_147__PI_MONITOR_SRC_SEL_3
  2095. #define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_MASK 0x01000000U
  2096. #define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_SHIFT 24U
  2097. #define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_WIDTH 1U
  2098. #define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_WOCLR 0U
  2099. #define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_WOSET 0U
  2100. #define LPDDR4__PI_MONITOR_CAP_SEL_3__REG DENALI_PI_147
  2101. #define LPDDR4__PI_MONITOR_CAP_SEL_3__FLD LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3
  2102. #define LPDDR4__DENALI_PI_148_READ_MASK 0xFF010FFFU
  2103. #define LPDDR4__DENALI_PI_148_WRITE_MASK 0xFF010FFFU
  2104. #define LPDDR4__DENALI_PI_148__PI_MONITOR_3_MASK 0x000000FFU
  2105. #define LPDDR4__DENALI_PI_148__PI_MONITOR_3_SHIFT 0U
  2106. #define LPDDR4__DENALI_PI_148__PI_MONITOR_3_WIDTH 8U
  2107. #define LPDDR4__PI_MONITOR_3__REG DENALI_PI_148
  2108. #define LPDDR4__PI_MONITOR_3__FLD LPDDR4__DENALI_PI_148__PI_MONITOR_3
  2109. #define LPDDR4__DENALI_PI_148__PI_MONITOR_SRC_SEL_4_MASK 0x00000F00U
  2110. #define LPDDR4__DENALI_PI_148__PI_MONITOR_SRC_SEL_4_SHIFT 8U
  2111. #define LPDDR4__DENALI_PI_148__PI_MONITOR_SRC_SEL_4_WIDTH 4U
  2112. #define LPDDR4__PI_MONITOR_SRC_SEL_4__REG DENALI_PI_148
  2113. #define LPDDR4__PI_MONITOR_SRC_SEL_4__FLD LPDDR4__DENALI_PI_148__PI_MONITOR_SRC_SEL_4
  2114. #define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_MASK 0x00010000U
  2115. #define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_SHIFT 16U
  2116. #define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_WIDTH 1U
  2117. #define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_WOCLR 0U
  2118. #define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_WOSET 0U
  2119. #define LPDDR4__PI_MONITOR_CAP_SEL_4__REG DENALI_PI_148
  2120. #define LPDDR4__PI_MONITOR_CAP_SEL_4__FLD LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4
  2121. #define LPDDR4__DENALI_PI_148__PI_MONITOR_4_MASK 0xFF000000U
  2122. #define LPDDR4__DENALI_PI_148__PI_MONITOR_4_SHIFT 24U
  2123. #define LPDDR4__DENALI_PI_148__PI_MONITOR_4_WIDTH 8U
  2124. #define LPDDR4__PI_MONITOR_4__REG DENALI_PI_148
  2125. #define LPDDR4__PI_MONITOR_4__FLD LPDDR4__DENALI_PI_148__PI_MONITOR_4
  2126. #define LPDDR4__DENALI_PI_149_READ_MASK 0x0FFF010FU
  2127. #define LPDDR4__DENALI_PI_149_WRITE_MASK 0x0FFF010FU
  2128. #define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_5_MASK 0x0000000FU
  2129. #define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_5_SHIFT 0U
  2130. #define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_5_WIDTH 4U
  2131. #define LPDDR4__PI_MONITOR_SRC_SEL_5__REG DENALI_PI_149
  2132. #define LPDDR4__PI_MONITOR_SRC_SEL_5__FLD LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_5
  2133. #define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_MASK 0x00000100U
  2134. #define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_SHIFT 8U
  2135. #define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_WIDTH 1U
  2136. #define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_WOCLR 0U
  2137. #define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_WOSET 0U
  2138. #define LPDDR4__PI_MONITOR_CAP_SEL_5__REG DENALI_PI_149
  2139. #define LPDDR4__PI_MONITOR_CAP_SEL_5__FLD LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5
  2140. #define LPDDR4__DENALI_PI_149__PI_MONITOR_5_MASK 0x00FF0000U
  2141. #define LPDDR4__DENALI_PI_149__PI_MONITOR_5_SHIFT 16U
  2142. #define LPDDR4__DENALI_PI_149__PI_MONITOR_5_WIDTH 8U
  2143. #define LPDDR4__PI_MONITOR_5__REG DENALI_PI_149
  2144. #define LPDDR4__PI_MONITOR_5__FLD LPDDR4__DENALI_PI_149__PI_MONITOR_5
  2145. #define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_6_MASK 0x0F000000U
  2146. #define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_6_SHIFT 24U
  2147. #define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_6_WIDTH 4U
  2148. #define LPDDR4__PI_MONITOR_SRC_SEL_6__REG DENALI_PI_149
  2149. #define LPDDR4__PI_MONITOR_SRC_SEL_6__FLD LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_6
  2150. #define LPDDR4__DENALI_PI_150_READ_MASK 0x010FFF01U
  2151. #define LPDDR4__DENALI_PI_150_WRITE_MASK 0x010FFF01U
  2152. #define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_MASK 0x00000001U
  2153. #define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_SHIFT 0U
  2154. #define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_WIDTH 1U
  2155. #define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_WOCLR 0U
  2156. #define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_WOSET 0U
  2157. #define LPDDR4__PI_MONITOR_CAP_SEL_6__REG DENALI_PI_150
  2158. #define LPDDR4__PI_MONITOR_CAP_SEL_6__FLD LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6
  2159. #define LPDDR4__DENALI_PI_150__PI_MONITOR_6_MASK 0x0000FF00U
  2160. #define LPDDR4__DENALI_PI_150__PI_MONITOR_6_SHIFT 8U
  2161. #define LPDDR4__DENALI_PI_150__PI_MONITOR_6_WIDTH 8U
  2162. #define LPDDR4__PI_MONITOR_6__REG DENALI_PI_150
  2163. #define LPDDR4__PI_MONITOR_6__FLD LPDDR4__DENALI_PI_150__PI_MONITOR_6
  2164. #define LPDDR4__DENALI_PI_150__PI_MONITOR_SRC_SEL_7_MASK 0x000F0000U
  2165. #define LPDDR4__DENALI_PI_150__PI_MONITOR_SRC_SEL_7_SHIFT 16U
  2166. #define LPDDR4__DENALI_PI_150__PI_MONITOR_SRC_SEL_7_WIDTH 4U
  2167. #define LPDDR4__PI_MONITOR_SRC_SEL_7__REG DENALI_PI_150
  2168. #define LPDDR4__PI_MONITOR_SRC_SEL_7__FLD LPDDR4__DENALI_PI_150__PI_MONITOR_SRC_SEL_7
  2169. #define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_MASK 0x01000000U
  2170. #define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_SHIFT 24U
  2171. #define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_WIDTH 1U
  2172. #define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_WOCLR 0U
  2173. #define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_WOSET 0U
  2174. #define LPDDR4__PI_MONITOR_CAP_SEL_7__REG DENALI_PI_150
  2175. #define LPDDR4__PI_MONITOR_CAP_SEL_7__FLD LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7
  2176. #define LPDDR4__DENALI_PI_151_READ_MASK 0x000000FFU
  2177. #define LPDDR4__DENALI_PI_151_WRITE_MASK 0x000000FFU
  2178. #define LPDDR4__DENALI_PI_151__PI_MONITOR_7_MASK 0x000000FFU
  2179. #define LPDDR4__DENALI_PI_151__PI_MONITOR_7_SHIFT 0U
  2180. #define LPDDR4__DENALI_PI_151__PI_MONITOR_7_WIDTH 8U
  2181. #define LPDDR4__PI_MONITOR_7__REG DENALI_PI_151
  2182. #define LPDDR4__PI_MONITOR_7__FLD LPDDR4__DENALI_PI_151__PI_MONITOR_7
  2183. #define LPDDR4__DENALI_PI_152__PI_MONITOR_STROBE_MASK 0x000000FFU
  2184. #define LPDDR4__DENALI_PI_152__PI_MONITOR_STROBE_SHIFT 0U
  2185. #define LPDDR4__DENALI_PI_152__PI_MONITOR_STROBE_WIDTH 8U
  2186. #define LPDDR4__PI_MONITOR_STROBE__REG DENALI_PI_152
  2187. #define LPDDR4__PI_MONITOR_STROBE__FLD LPDDR4__DENALI_PI_152__PI_MONITOR_STROBE
  2188. #define LPDDR4__DENALI_PI_153_READ_MASK 0x011F1F01U
  2189. #define LPDDR4__DENALI_PI_153_WRITE_MASK 0x011F1F01U
  2190. #define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_MASK 0x00000001U
  2191. #define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_SHIFT 0U
  2192. #define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_WIDTH 1U
  2193. #define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_WOCLR 0U
  2194. #define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_WOSET 0U
  2195. #define LPDDR4__PI_DLL_LOCK__REG DENALI_PI_153
  2196. #define LPDDR4__PI_DLL_LOCK__FLD LPDDR4__DENALI_PI_153__PI_DLL_LOCK
  2197. #define LPDDR4__DENALI_PI_153__PI_FREQ_NUMBER_STATUS_MASK 0x00001F00U
  2198. #define LPDDR4__DENALI_PI_153__PI_FREQ_NUMBER_STATUS_SHIFT 8U
  2199. #define LPDDR4__DENALI_PI_153__PI_FREQ_NUMBER_STATUS_WIDTH 5U
  2200. #define LPDDR4__PI_FREQ_NUMBER_STATUS__REG DENALI_PI_153
  2201. #define LPDDR4__PI_FREQ_NUMBER_STATUS__FLD LPDDR4__DENALI_PI_153__PI_FREQ_NUMBER_STATUS
  2202. #define LPDDR4__DENALI_PI_153__PI_FREQ_RETENTION_NUM_MASK 0x001F0000U
  2203. #define LPDDR4__DENALI_PI_153__PI_FREQ_RETENTION_NUM_SHIFT 16U
  2204. #define LPDDR4__DENALI_PI_153__PI_FREQ_RETENTION_NUM_WIDTH 5U
  2205. #define LPDDR4__PI_FREQ_RETENTION_NUM__REG DENALI_PI_153
  2206. #define LPDDR4__PI_FREQ_RETENTION_NUM__FLD LPDDR4__DENALI_PI_153__PI_FREQ_RETENTION_NUM
  2207. #define LPDDR4__DENALI_PI_153__PI_RESERVED29_MASK 0x01000000U
  2208. #define LPDDR4__DENALI_PI_153__PI_RESERVED29_SHIFT 24U
  2209. #define LPDDR4__DENALI_PI_153__PI_RESERVED29_WIDTH 1U
  2210. #define LPDDR4__DENALI_PI_153__PI_RESERVED29_WOCLR 0U
  2211. #define LPDDR4__DENALI_PI_153__PI_RESERVED29_WOSET 0U
  2212. #define LPDDR4__PI_RESERVED29__REG DENALI_PI_153
  2213. #define LPDDR4__PI_RESERVED29__FLD LPDDR4__DENALI_PI_153__PI_RESERVED29
  2214. #define LPDDR4__DENALI_PI_154_READ_MASK 0x01010103U
  2215. #define LPDDR4__DENALI_PI_154_WRITE_MASK 0x01010103U
  2216. #define LPDDR4__DENALI_PI_154__PI_PHYMSTR_TYPE_MASK 0x00000003U
  2217. #define LPDDR4__DENALI_PI_154__PI_PHYMSTR_TYPE_SHIFT 0U
  2218. #define LPDDR4__DENALI_PI_154__PI_PHYMSTR_TYPE_WIDTH 2U
  2219. #define LPDDR4__PI_PHYMSTR_TYPE__REG DENALI_PI_154
  2220. #define LPDDR4__PI_PHYMSTR_TYPE__FLD LPDDR4__DENALI_PI_154__PI_PHYMSTR_TYPE
  2221. #define LPDDR4__DENALI_PI_154__PI_RESERVED30_MASK 0x00000100U
  2222. #define LPDDR4__DENALI_PI_154__PI_RESERVED30_SHIFT 8U
  2223. #define LPDDR4__DENALI_PI_154__PI_RESERVED30_WIDTH 1U
  2224. #define LPDDR4__DENALI_PI_154__PI_RESERVED30_WOCLR 0U
  2225. #define LPDDR4__DENALI_PI_154__PI_RESERVED30_WOSET 0U
  2226. #define LPDDR4__PI_RESERVED30__REG DENALI_PI_154
  2227. #define LPDDR4__PI_RESERVED30__FLD LPDDR4__DENALI_PI_154__PI_RESERVED30
  2228. #define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_MASK 0x00010000U
  2229. #define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_SHIFT 16U
  2230. #define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_WIDTH 1U
  2231. #define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_WOCLR 0U
  2232. #define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_WOSET 0U
  2233. #define LPDDR4__PI_POWER_REDUC_EN__REG DENALI_PI_154
  2234. #define LPDDR4__PI_POWER_REDUC_EN__FLD LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN
  2235. #define LPDDR4__DENALI_PI_154__PI_RESERVED31_MASK 0x01000000U
  2236. #define LPDDR4__DENALI_PI_154__PI_RESERVED31_SHIFT 24U
  2237. #define LPDDR4__DENALI_PI_154__PI_RESERVED31_WIDTH 1U
  2238. #define LPDDR4__DENALI_PI_154__PI_RESERVED31_WOCLR 0U
  2239. #define LPDDR4__DENALI_PI_154__PI_RESERVED31_WOSET 0U
  2240. #define LPDDR4__PI_RESERVED31__REG DENALI_PI_154
  2241. #define LPDDR4__PI_RESERVED31__FLD LPDDR4__DENALI_PI_154__PI_RESERVED31
  2242. #define LPDDR4__DENALI_PI_155_READ_MASK 0x01010101U
  2243. #define LPDDR4__DENALI_PI_155_WRITE_MASK 0x01010101U
  2244. #define LPDDR4__DENALI_PI_155__PI_RESERVED32_MASK 0x00000001U
  2245. #define LPDDR4__DENALI_PI_155__PI_RESERVED32_SHIFT 0U
  2246. #define LPDDR4__DENALI_PI_155__PI_RESERVED32_WIDTH 1U
  2247. #define LPDDR4__DENALI_PI_155__PI_RESERVED32_WOCLR 0U
  2248. #define LPDDR4__DENALI_PI_155__PI_RESERVED32_WOSET 0U
  2249. #define LPDDR4__PI_RESERVED32__REG DENALI_PI_155
  2250. #define LPDDR4__PI_RESERVED32__FLD LPDDR4__DENALI_PI_155__PI_RESERVED32
  2251. #define LPDDR4__DENALI_PI_155__PI_RESERVED33_MASK 0x00000100U
  2252. #define LPDDR4__DENALI_PI_155__PI_RESERVED33_SHIFT 8U
  2253. #define LPDDR4__DENALI_PI_155__PI_RESERVED33_WIDTH 1U
  2254. #define LPDDR4__DENALI_PI_155__PI_RESERVED33_WOCLR 0U
  2255. #define LPDDR4__DENALI_PI_155__PI_RESERVED33_WOSET 0U
  2256. #define LPDDR4__PI_RESERVED33__REG DENALI_PI_155
  2257. #define LPDDR4__PI_RESERVED33__FLD LPDDR4__DENALI_PI_155__PI_RESERVED33
  2258. #define LPDDR4__DENALI_PI_155__PI_RESERVED34_MASK 0x00010000U
  2259. #define LPDDR4__DENALI_PI_155__PI_RESERVED34_SHIFT 16U
  2260. #define LPDDR4__DENALI_PI_155__PI_RESERVED34_WIDTH 1U
  2261. #define LPDDR4__DENALI_PI_155__PI_RESERVED34_WOCLR 0U
  2262. #define LPDDR4__DENALI_PI_155__PI_RESERVED34_WOSET 0U
  2263. #define LPDDR4__PI_RESERVED34__REG DENALI_PI_155
  2264. #define LPDDR4__PI_RESERVED34__FLD LPDDR4__DENALI_PI_155__PI_RESERVED34
  2265. #define LPDDR4__DENALI_PI_155__PI_RESERVED35_MASK 0x01000000U
  2266. #define LPDDR4__DENALI_PI_155__PI_RESERVED35_SHIFT 24U
  2267. #define LPDDR4__DENALI_PI_155__PI_RESERVED35_WIDTH 1U
  2268. #define LPDDR4__DENALI_PI_155__PI_RESERVED35_WOCLR 0U
  2269. #define LPDDR4__DENALI_PI_155__PI_RESERVED35_WOSET 0U
  2270. #define LPDDR4__PI_RESERVED35__REG DENALI_PI_155
  2271. #define LPDDR4__PI_RESERVED35__FLD LPDDR4__DENALI_PI_155__PI_RESERVED35
  2272. #define LPDDR4__DENALI_PI_156_READ_MASK 0x01010101U
  2273. #define LPDDR4__DENALI_PI_156_WRITE_MASK 0x01010101U
  2274. #define LPDDR4__DENALI_PI_156__PI_RESERVED36_MASK 0x00000001U
  2275. #define LPDDR4__DENALI_PI_156__PI_RESERVED36_SHIFT 0U
  2276. #define LPDDR4__DENALI_PI_156__PI_RESERVED36_WIDTH 1U
  2277. #define LPDDR4__DENALI_PI_156__PI_RESERVED36_WOCLR 0U
  2278. #define LPDDR4__DENALI_PI_156__PI_RESERVED36_WOSET 0U
  2279. #define LPDDR4__PI_RESERVED36__REG DENALI_PI_156
  2280. #define LPDDR4__PI_RESERVED36__FLD LPDDR4__DENALI_PI_156__PI_RESERVED36
  2281. #define LPDDR4__DENALI_PI_156__PI_RESERVED37_MASK 0x00000100U
  2282. #define LPDDR4__DENALI_PI_156__PI_RESERVED37_SHIFT 8U
  2283. #define LPDDR4__DENALI_PI_156__PI_RESERVED37_WIDTH 1U
  2284. #define LPDDR4__DENALI_PI_156__PI_RESERVED37_WOCLR 0U
  2285. #define LPDDR4__DENALI_PI_156__PI_RESERVED37_WOSET 0U
  2286. #define LPDDR4__PI_RESERVED37__REG DENALI_PI_156
  2287. #define LPDDR4__PI_RESERVED37__FLD LPDDR4__DENALI_PI_156__PI_RESERVED37
  2288. #define LPDDR4__DENALI_PI_156__PI_RESERVED38_MASK 0x00010000U
  2289. #define LPDDR4__DENALI_PI_156__PI_RESERVED38_SHIFT 16U
  2290. #define LPDDR4__DENALI_PI_156__PI_RESERVED38_WIDTH 1U
  2291. #define LPDDR4__DENALI_PI_156__PI_RESERVED38_WOCLR 0U
  2292. #define LPDDR4__DENALI_PI_156__PI_RESERVED38_WOSET 0U
  2293. #define LPDDR4__PI_RESERVED38__REG DENALI_PI_156
  2294. #define LPDDR4__PI_RESERVED38__FLD LPDDR4__DENALI_PI_156__PI_RESERVED38
  2295. #define LPDDR4__DENALI_PI_156__PI_RESERVED39_MASK 0x01000000U
  2296. #define LPDDR4__DENALI_PI_156__PI_RESERVED39_SHIFT 24U
  2297. #define LPDDR4__DENALI_PI_156__PI_RESERVED39_WIDTH 1U
  2298. #define LPDDR4__DENALI_PI_156__PI_RESERVED39_WOCLR 0U
  2299. #define LPDDR4__DENALI_PI_156__PI_RESERVED39_WOSET 0U
  2300. #define LPDDR4__PI_RESERVED39__REG DENALI_PI_156
  2301. #define LPDDR4__PI_RESERVED39__FLD LPDDR4__DENALI_PI_156__PI_RESERVED39
  2302. #define LPDDR4__DENALI_PI_157_READ_MASK 0x01010101U
  2303. #define LPDDR4__DENALI_PI_157_WRITE_MASK 0x01010101U
  2304. #define LPDDR4__DENALI_PI_157__PI_RESERVED40_MASK 0x00000001U
  2305. #define LPDDR4__DENALI_PI_157__PI_RESERVED40_SHIFT 0U
  2306. #define LPDDR4__DENALI_PI_157__PI_RESERVED40_WIDTH 1U
  2307. #define LPDDR4__DENALI_PI_157__PI_RESERVED40_WOCLR 0U
  2308. #define LPDDR4__DENALI_PI_157__PI_RESERVED40_WOSET 0U
  2309. #define LPDDR4__PI_RESERVED40__REG DENALI_PI_157
  2310. #define LPDDR4__PI_RESERVED40__FLD LPDDR4__DENALI_PI_157__PI_RESERVED40
  2311. #define LPDDR4__DENALI_PI_157__PI_RESERVED41_MASK 0x00000100U
  2312. #define LPDDR4__DENALI_PI_157__PI_RESERVED41_SHIFT 8U
  2313. #define LPDDR4__DENALI_PI_157__PI_RESERVED41_WIDTH 1U
  2314. #define LPDDR4__DENALI_PI_157__PI_RESERVED41_WOCLR 0U
  2315. #define LPDDR4__DENALI_PI_157__PI_RESERVED41_WOSET 0U
  2316. #define LPDDR4__PI_RESERVED41__REG DENALI_PI_157
  2317. #define LPDDR4__PI_RESERVED41__FLD LPDDR4__DENALI_PI_157__PI_RESERVED41
  2318. #define LPDDR4__DENALI_PI_157__PI_RESERVED42_MASK 0x00010000U
  2319. #define LPDDR4__DENALI_PI_157__PI_RESERVED42_SHIFT 16U
  2320. #define LPDDR4__DENALI_PI_157__PI_RESERVED42_WIDTH 1U
  2321. #define LPDDR4__DENALI_PI_157__PI_RESERVED42_WOCLR 0U
  2322. #define LPDDR4__DENALI_PI_157__PI_RESERVED42_WOSET 0U
  2323. #define LPDDR4__PI_RESERVED42__REG DENALI_PI_157
  2324. #define LPDDR4__PI_RESERVED42__FLD LPDDR4__DENALI_PI_157__PI_RESERVED42
  2325. #define LPDDR4__DENALI_PI_157__PI_RESERVED43_MASK 0x01000000U
  2326. #define LPDDR4__DENALI_PI_157__PI_RESERVED43_SHIFT 24U
  2327. #define LPDDR4__DENALI_PI_157__PI_RESERVED43_WIDTH 1U
  2328. #define LPDDR4__DENALI_PI_157__PI_RESERVED43_WOCLR 0U
  2329. #define LPDDR4__DENALI_PI_157__PI_RESERVED43_WOSET 0U
  2330. #define LPDDR4__PI_RESERVED43__REG DENALI_PI_157
  2331. #define LPDDR4__PI_RESERVED43__FLD LPDDR4__DENALI_PI_157__PI_RESERVED43
  2332. #define LPDDR4__DENALI_PI_158_READ_MASK 0x01010101U
  2333. #define LPDDR4__DENALI_PI_158_WRITE_MASK 0x01010101U
  2334. #define LPDDR4__DENALI_PI_158__PI_RESERVED44_MASK 0x00000001U
  2335. #define LPDDR4__DENALI_PI_158__PI_RESERVED44_SHIFT 0U
  2336. #define LPDDR4__DENALI_PI_158__PI_RESERVED44_WIDTH 1U
  2337. #define LPDDR4__DENALI_PI_158__PI_RESERVED44_WOCLR 0U
  2338. #define LPDDR4__DENALI_PI_158__PI_RESERVED44_WOSET 0U
  2339. #define LPDDR4__PI_RESERVED44__REG DENALI_PI_158
  2340. #define LPDDR4__PI_RESERVED44__FLD LPDDR4__DENALI_PI_158__PI_RESERVED44
  2341. #define LPDDR4__DENALI_PI_158__PI_RESERVED45_MASK 0x00000100U
  2342. #define LPDDR4__DENALI_PI_158__PI_RESERVED45_SHIFT 8U
  2343. #define LPDDR4__DENALI_PI_158__PI_RESERVED45_WIDTH 1U
  2344. #define LPDDR4__DENALI_PI_158__PI_RESERVED45_WOCLR 0U
  2345. #define LPDDR4__DENALI_PI_158__PI_RESERVED45_WOSET 0U
  2346. #define LPDDR4__PI_RESERVED45__REG DENALI_PI_158
  2347. #define LPDDR4__PI_RESERVED45__FLD LPDDR4__DENALI_PI_158__PI_RESERVED45
  2348. #define LPDDR4__DENALI_PI_158__PI_RESERVED46_MASK 0x00010000U
  2349. #define LPDDR4__DENALI_PI_158__PI_RESERVED46_SHIFT 16U
  2350. #define LPDDR4__DENALI_PI_158__PI_RESERVED46_WIDTH 1U
  2351. #define LPDDR4__DENALI_PI_158__PI_RESERVED46_WOCLR 0U
  2352. #define LPDDR4__DENALI_PI_158__PI_RESERVED46_WOSET 0U
  2353. #define LPDDR4__PI_RESERVED46__REG DENALI_PI_158
  2354. #define LPDDR4__PI_RESERVED46__FLD LPDDR4__DENALI_PI_158__PI_RESERVED46
  2355. #define LPDDR4__DENALI_PI_158__PI_RESERVED47_MASK 0x01000000U
  2356. #define LPDDR4__DENALI_PI_158__PI_RESERVED47_SHIFT 24U
  2357. #define LPDDR4__DENALI_PI_158__PI_RESERVED47_WIDTH 1U
  2358. #define LPDDR4__DENALI_PI_158__PI_RESERVED47_WOCLR 0U
  2359. #define LPDDR4__DENALI_PI_158__PI_RESERVED47_WOSET 0U
  2360. #define LPDDR4__PI_RESERVED47__REG DENALI_PI_158
  2361. #define LPDDR4__PI_RESERVED47__FLD LPDDR4__DENALI_PI_158__PI_RESERVED47
  2362. #define LPDDR4__DENALI_PI_159_READ_MASK 0x0001FFFFU
  2363. #define LPDDR4__DENALI_PI_159_WRITE_MASK 0x0001FFFFU
  2364. #define LPDDR4__DENALI_PI_159__PI_WRLVL_MAX_STROBE_PEND_MASK 0x000000FFU
  2365. #define LPDDR4__DENALI_PI_159__PI_WRLVL_MAX_STROBE_PEND_SHIFT 0U
  2366. #define LPDDR4__DENALI_PI_159__PI_WRLVL_MAX_STROBE_PEND_WIDTH 8U
  2367. #define LPDDR4__PI_WRLVL_MAX_STROBE_PEND__REG DENALI_PI_159
  2368. #define LPDDR4__PI_WRLVL_MAX_STROBE_PEND__FLD LPDDR4__DENALI_PI_159__PI_WRLVL_MAX_STROBE_PEND
  2369. #define LPDDR4__DENALI_PI_159__PI_TREFBW_THR_MASK 0x0001FF00U
  2370. #define LPDDR4__DENALI_PI_159__PI_TREFBW_THR_SHIFT 8U
  2371. #define LPDDR4__DENALI_PI_159__PI_TREFBW_THR_WIDTH 9U
  2372. #define LPDDR4__PI_TREFBW_THR__REG DENALI_PI_159
  2373. #define LPDDR4__PI_TREFBW_THR__FLD LPDDR4__DENALI_PI_159__PI_TREFBW_THR
  2374. #define LPDDR4__DENALI_PI_160_READ_MASK 0x0000001FU
  2375. #define LPDDR4__DENALI_PI_160_WRITE_MASK 0x0000001FU
  2376. #define LPDDR4__DENALI_PI_160__PI_FREQ_CHANGE_REG_COPY_MASK 0x0000001FU
  2377. #define LPDDR4__DENALI_PI_160__PI_FREQ_CHANGE_REG_COPY_SHIFT 0U
  2378. #define LPDDR4__DENALI_PI_160__PI_FREQ_CHANGE_REG_COPY_WIDTH 5U
  2379. #define LPDDR4__PI_FREQ_CHANGE_REG_COPY__REG DENALI_PI_160
  2380. #define LPDDR4__PI_FREQ_CHANGE_REG_COPY__FLD LPDDR4__DENALI_PI_160__PI_FREQ_CHANGE_REG_COPY
  2381. #define LPDDR4__DENALI_PI_161_READ_MASK 0x0F011F01U
  2382. #define LPDDR4__DENALI_PI_161_WRITE_MASK 0x0F011F01U
  2383. #define LPDDR4__DENALI_PI_161__PI_FREQ_SEL_FROM_REGIF_MASK 0x00000001U
  2384. #define LPDDR4__DENALI_PI_161__PI_FREQ_SEL_FROM_REGIF_SHIFT 0U
  2385. #define LPDDR4__DENALI_PI_161__PI_FREQ_SEL_FROM_REGIF_WIDTH 1U
  2386. #define LPDDR4__DENALI_PI_161__PI_FREQ_SEL_FROM_REGIF_WOCLR 0U
  2387. #define LPDDR4__DENALI_PI_161__PI_FREQ_SEL_FROM_REGIF_WOSET 0U
  2388. #define LPDDR4__PI_FREQ_SEL_FROM_REGIF__REG DENALI_PI_161
  2389. #define LPDDR4__PI_FREQ_SEL_FROM_REGIF__FLD LPDDR4__DENALI_PI_161__PI_FREQ_SEL_FROM_REGIF
  2390. #define LPDDR4__DENALI_PI_161__PI_RESERVED48_MASK 0x00001F00U
  2391. #define LPDDR4__DENALI_PI_161__PI_RESERVED48_SHIFT 8U
  2392. #define LPDDR4__DENALI_PI_161__PI_RESERVED48_WIDTH 5U
  2393. #define LPDDR4__PI_RESERVED48__REG DENALI_PI_161
  2394. #define LPDDR4__PI_RESERVED48__FLD LPDDR4__DENALI_PI_161__PI_RESERVED48
  2395. #define LPDDR4__DENALI_PI_161__PI_PARALLEL_CALVL_EN_MASK 0x00010000U
  2396. #define LPDDR4__DENALI_PI_161__PI_PARALLEL_CALVL_EN_SHIFT 16U
  2397. #define LPDDR4__DENALI_PI_161__PI_PARALLEL_CALVL_EN_WIDTH 1U
  2398. #define LPDDR4__DENALI_PI_161__PI_PARALLEL_CALVL_EN_WOCLR 0U
  2399. #define LPDDR4__DENALI_PI_161__PI_PARALLEL_CALVL_EN_WOSET 0U
  2400. #define LPDDR4__PI_PARALLEL_CALVL_EN__REG DENALI_PI_161
  2401. #define LPDDR4__PI_PARALLEL_CALVL_EN__FLD LPDDR4__DENALI_PI_161__PI_PARALLEL_CALVL_EN
  2402. #define LPDDR4__DENALI_PI_161__PI_CATR_MASK 0x0F000000U
  2403. #define LPDDR4__DENALI_PI_161__PI_CATR_SHIFT 24U
  2404. #define LPDDR4__DENALI_PI_161__PI_CATR_WIDTH 4U
  2405. #define LPDDR4__PI_CATR__REG DENALI_PI_161
  2406. #define LPDDR4__PI_CATR__FLD LPDDR4__DENALI_PI_161__PI_CATR
  2407. #define LPDDR4__DENALI_PI_162_READ_MASK 0x01010101U
  2408. #define LPDDR4__DENALI_PI_162_WRITE_MASK 0x01010101U
  2409. #define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_MASK 0x00000001U
  2410. #define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_SHIFT 0U
  2411. #define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_WIDTH 1U
  2412. #define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_WOCLR 0U
  2413. #define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_WOSET 0U
  2414. #define LPDDR4__PI_NO_CATR_READ__REG DENALI_PI_162
  2415. #define LPDDR4__PI_NO_CATR_READ__FLD LPDDR4__DENALI_PI_162__PI_NO_CATR_READ
  2416. #define LPDDR4__DENALI_PI_162__PI_MASK_INIT_COMPLETE_MASK 0x00000100U
  2417. #define LPDDR4__DENALI_PI_162__PI_MASK_INIT_COMPLETE_SHIFT 8U
  2418. #define LPDDR4__DENALI_PI_162__PI_MASK_INIT_COMPLETE_WIDTH 1U
  2419. #define LPDDR4__DENALI_PI_162__PI_MASK_INIT_COMPLETE_WOCLR 0U
  2420. #define LPDDR4__DENALI_PI_162__PI_MASK_INIT_COMPLETE_WOSET 0U
  2421. #define LPDDR4__PI_MASK_INIT_COMPLETE__REG DENALI_PI_162
  2422. #define LPDDR4__PI_MASK_INIT_COMPLETE__FLD LPDDR4__DENALI_PI_162__PI_MASK_INIT_COMPLETE
  2423. #define LPDDR4__DENALI_PI_162__PI_DISCONNECT_MC_MASK 0x00010000U
  2424. #define LPDDR4__DENALI_PI_162__PI_DISCONNECT_MC_SHIFT 16U
  2425. #define LPDDR4__DENALI_PI_162__PI_DISCONNECT_MC_WIDTH 1U
  2426. #define LPDDR4__DENALI_PI_162__PI_DISCONNECT_MC_WOCLR 0U
  2427. #define LPDDR4__DENALI_PI_162__PI_DISCONNECT_MC_WOSET 0U
  2428. #define LPDDR4__PI_DISCONNECT_MC__REG DENALI_PI_162
  2429. #define LPDDR4__PI_DISCONNECT_MC__FLD LPDDR4__DENALI_PI_162__PI_DISCONNECT_MC
  2430. #define LPDDR4__DENALI_PI_162__PI_NOTCARE_MC_INIT_START_MASK 0x01000000U
  2431. #define LPDDR4__DENALI_PI_162__PI_NOTCARE_MC_INIT_START_SHIFT 24U
  2432. #define LPDDR4__DENALI_PI_162__PI_NOTCARE_MC_INIT_START_WIDTH 1U
  2433. #define LPDDR4__DENALI_PI_162__PI_NOTCARE_MC_INIT_START_WOCLR 0U
  2434. #define LPDDR4__DENALI_PI_162__PI_NOTCARE_MC_INIT_START_WOSET 0U
  2435. #define LPDDR4__PI_NOTCARE_MC_INIT_START__REG DENALI_PI_162
  2436. #define LPDDR4__PI_NOTCARE_MC_INIT_START__FLD LPDDR4__DENALI_PI_162__PI_NOTCARE_MC_INIT_START
  2437. #define LPDDR4__DENALI_PI_163_READ_MASK 0xFFFFFF01U
  2438. #define LPDDR4__DENALI_PI_163_WRITE_MASK 0xFFFFFF01U
  2439. #define LPDDR4__DENALI_PI_163__PI_TRACE_MC_MR13_MASK 0x00000001U
  2440. #define LPDDR4__DENALI_PI_163__PI_TRACE_MC_MR13_SHIFT 0U
  2441. #define LPDDR4__DENALI_PI_163__PI_TRACE_MC_MR13_WIDTH 1U
  2442. #define LPDDR4__DENALI_PI_163__PI_TRACE_MC_MR13_WOCLR 0U
  2443. #define LPDDR4__DENALI_PI_163__PI_TRACE_MC_MR13_WOSET 0U
  2444. #define LPDDR4__PI_TRACE_MC_MR13__REG DENALI_PI_163
  2445. #define LPDDR4__PI_TRACE_MC_MR13__FLD LPDDR4__DENALI_PI_163__PI_TRACE_MC_MR13
  2446. #define LPDDR4__DENALI_PI_163__PI_TSDO_F0_MASK 0x0000FF00U
  2447. #define LPDDR4__DENALI_PI_163__PI_TSDO_F0_SHIFT 8U
  2448. #define LPDDR4__DENALI_PI_163__PI_TSDO_F0_WIDTH 8U
  2449. #define LPDDR4__PI_TSDO_F0__REG DENALI_PI_163
  2450. #define LPDDR4__PI_TSDO_F0__FLD LPDDR4__DENALI_PI_163__PI_TSDO_F0
  2451. #define LPDDR4__DENALI_PI_163__PI_TSDO_F1_MASK 0x00FF0000U
  2452. #define LPDDR4__DENALI_PI_163__PI_TSDO_F1_SHIFT 16U
  2453. #define LPDDR4__DENALI_PI_163__PI_TSDO_F1_WIDTH 8U
  2454. #define LPDDR4__PI_TSDO_F1__REG DENALI_PI_163
  2455. #define LPDDR4__PI_TSDO_F1__FLD LPDDR4__DENALI_PI_163__PI_TSDO_F1
  2456. #define LPDDR4__DENALI_PI_163__PI_TSDO_F2_MASK 0xFF000000U
  2457. #define LPDDR4__DENALI_PI_163__PI_TSDO_F2_SHIFT 24U
  2458. #define LPDDR4__DENALI_PI_163__PI_TSDO_F2_WIDTH 8U
  2459. #define LPDDR4__PI_TSDO_F2__REG DENALI_PI_163
  2460. #define LPDDR4__PI_TSDO_F2__FLD LPDDR4__DENALI_PI_163__PI_TSDO_F2
  2461. #define LPDDR4__DENALI_PI_164_READ_MASK 0x000000FFU
  2462. #define LPDDR4__DENALI_PI_164_WRITE_MASK 0x000000FFU
  2463. #define LPDDR4__DENALI_PI_164__PI_TDELAY_RDWR_2_BUS_IDLE_F0_MASK 0x000000FFU
  2464. #define LPDDR4__DENALI_PI_164__PI_TDELAY_RDWR_2_BUS_IDLE_F0_SHIFT 0U
  2465. #define LPDDR4__DENALI_PI_164__PI_TDELAY_RDWR_2_BUS_IDLE_F0_WIDTH 8U
  2466. #define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F0__REG DENALI_PI_164
  2467. #define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F0__FLD LPDDR4__DENALI_PI_164__PI_TDELAY_RDWR_2_BUS_IDLE_F0
  2468. #define LPDDR4__DENALI_PI_165_READ_MASK 0x000000FFU
  2469. #define LPDDR4__DENALI_PI_165_WRITE_MASK 0x000000FFU
  2470. #define LPDDR4__DENALI_PI_165__PI_TDELAY_RDWR_2_BUS_IDLE_F1_MASK 0x000000FFU
  2471. #define LPDDR4__DENALI_PI_165__PI_TDELAY_RDWR_2_BUS_IDLE_F1_SHIFT 0U
  2472. #define LPDDR4__DENALI_PI_165__PI_TDELAY_RDWR_2_BUS_IDLE_F1_WIDTH 8U
  2473. #define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F1__REG DENALI_PI_165
  2474. #define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F1__FLD LPDDR4__DENALI_PI_165__PI_TDELAY_RDWR_2_BUS_IDLE_F1
  2475. #define LPDDR4__DENALI_PI_166_READ_MASK 0x000FFFFFU
  2476. #define LPDDR4__DENALI_PI_166_WRITE_MASK 0x000FFFFFU
  2477. #define LPDDR4__DENALI_PI_166__PI_TDELAY_RDWR_2_BUS_IDLE_F2_MASK 0x000000FFU
  2478. #define LPDDR4__DENALI_PI_166__PI_TDELAY_RDWR_2_BUS_IDLE_F2_SHIFT 0U
  2479. #define LPDDR4__DENALI_PI_166__PI_TDELAY_RDWR_2_BUS_IDLE_F2_WIDTH 8U
  2480. #define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F2__REG DENALI_PI_166
  2481. #define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F2__FLD LPDDR4__DENALI_PI_166__PI_TDELAY_RDWR_2_BUS_IDLE_F2
  2482. #define LPDDR4__DENALI_PI_166__PI_ZQINIT_F0_MASK 0x000FFF00U
  2483. #define LPDDR4__DENALI_PI_166__PI_ZQINIT_F0_SHIFT 8U
  2484. #define LPDDR4__DENALI_PI_166__PI_ZQINIT_F0_WIDTH 12U
  2485. #define LPDDR4__PI_ZQINIT_F0__REG DENALI_PI_166
  2486. #define LPDDR4__PI_ZQINIT_F0__FLD LPDDR4__DENALI_PI_166__PI_ZQINIT_F0
  2487. #define LPDDR4__DENALI_PI_167_READ_MASK 0x0FFF0FFFU
  2488. #define LPDDR4__DENALI_PI_167_WRITE_MASK 0x0FFF0FFFU
  2489. #define LPDDR4__DENALI_PI_167__PI_ZQINIT_F1_MASK 0x00000FFFU
  2490. #define LPDDR4__DENALI_PI_167__PI_ZQINIT_F1_SHIFT 0U
  2491. #define LPDDR4__DENALI_PI_167__PI_ZQINIT_F1_WIDTH 12U
  2492. #define LPDDR4__PI_ZQINIT_F1__REG DENALI_PI_167
  2493. #define LPDDR4__PI_ZQINIT_F1__FLD LPDDR4__DENALI_PI_167__PI_ZQINIT_F1
  2494. #define LPDDR4__DENALI_PI_167__PI_ZQINIT_F2_MASK 0x0FFF0000U
  2495. #define LPDDR4__DENALI_PI_167__PI_ZQINIT_F2_SHIFT 16U
  2496. #define LPDDR4__DENALI_PI_167__PI_ZQINIT_F2_WIDTH 12U
  2497. #define LPDDR4__PI_ZQINIT_F2__REG DENALI_PI_167
  2498. #define LPDDR4__PI_ZQINIT_F2__FLD LPDDR4__DENALI_PI_167__PI_ZQINIT_F2
  2499. #define LPDDR4__DENALI_PI_168_READ_MASK 0x7F7F7F7FU
  2500. #define LPDDR4__DENALI_PI_168_WRITE_MASK 0x7F7F7F7FU
  2501. #define LPDDR4__DENALI_PI_168__PI_WRLAT_F0_MASK 0x0000007FU
  2502. #define LPDDR4__DENALI_PI_168__PI_WRLAT_F0_SHIFT 0U
  2503. #define LPDDR4__DENALI_PI_168__PI_WRLAT_F0_WIDTH 7U
  2504. #define LPDDR4__PI_WRLAT_F0__REG DENALI_PI_168
  2505. #define LPDDR4__PI_WRLAT_F0__FLD LPDDR4__DENALI_PI_168__PI_WRLAT_F0
  2506. #define LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F0_MASK 0x00007F00U
  2507. #define LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F0_SHIFT 8U
  2508. #define LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F0_WIDTH 7U
  2509. #define LPDDR4__PI_CASLAT_LIN_F0__REG DENALI_PI_168
  2510. #define LPDDR4__PI_CASLAT_LIN_F0__FLD LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F0
  2511. #define LPDDR4__DENALI_PI_168__PI_WRLAT_F1_MASK 0x007F0000U
  2512. #define LPDDR4__DENALI_PI_168__PI_WRLAT_F1_SHIFT 16U
  2513. #define LPDDR4__DENALI_PI_168__PI_WRLAT_F1_WIDTH 7U
  2514. #define LPDDR4__PI_WRLAT_F1__REG DENALI_PI_168
  2515. #define LPDDR4__PI_WRLAT_F1__FLD LPDDR4__DENALI_PI_168__PI_WRLAT_F1
  2516. #define LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F1_MASK 0x7F000000U
  2517. #define LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F1_SHIFT 24U
  2518. #define LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F1_WIDTH 7U
  2519. #define LPDDR4__PI_CASLAT_LIN_F1__REG DENALI_PI_168
  2520. #define LPDDR4__PI_CASLAT_LIN_F1__FLD LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F1
  2521. #define LPDDR4__DENALI_PI_169_READ_MASK 0x03FF7F7FU
  2522. #define LPDDR4__DENALI_PI_169_WRITE_MASK 0x03FF7F7FU
  2523. #define LPDDR4__DENALI_PI_169__PI_WRLAT_F2_MASK 0x0000007FU
  2524. #define LPDDR4__DENALI_PI_169__PI_WRLAT_F2_SHIFT 0U
  2525. #define LPDDR4__DENALI_PI_169__PI_WRLAT_F2_WIDTH 7U
  2526. #define LPDDR4__PI_WRLAT_F2__REG DENALI_PI_169
  2527. #define LPDDR4__PI_WRLAT_F2__FLD LPDDR4__DENALI_PI_169__PI_WRLAT_F2
  2528. #define LPDDR4__DENALI_PI_169__PI_CASLAT_LIN_F2_MASK 0x00007F00U
  2529. #define LPDDR4__DENALI_PI_169__PI_CASLAT_LIN_F2_SHIFT 8U
  2530. #define LPDDR4__DENALI_PI_169__PI_CASLAT_LIN_F2_WIDTH 7U
  2531. #define LPDDR4__PI_CASLAT_LIN_F2__REG DENALI_PI_169
  2532. #define LPDDR4__PI_CASLAT_LIN_F2__FLD LPDDR4__DENALI_PI_169__PI_CASLAT_LIN_F2
  2533. #define LPDDR4__DENALI_PI_169__PI_TRFC_F0_MASK 0x03FF0000U
  2534. #define LPDDR4__DENALI_PI_169__PI_TRFC_F0_SHIFT 16U
  2535. #define LPDDR4__DENALI_PI_169__PI_TRFC_F0_WIDTH 10U
  2536. #define LPDDR4__PI_TRFC_F0__REG DENALI_PI_169
  2537. #define LPDDR4__PI_TRFC_F0__FLD LPDDR4__DENALI_PI_169__PI_TRFC_F0
  2538. #define LPDDR4__DENALI_PI_170_READ_MASK 0x000FFFFFU
  2539. #define LPDDR4__DENALI_PI_170_WRITE_MASK 0x000FFFFFU
  2540. #define LPDDR4__DENALI_PI_170__PI_TREF_F0_MASK 0x000FFFFFU
  2541. #define LPDDR4__DENALI_PI_170__PI_TREF_F0_SHIFT 0U
  2542. #define LPDDR4__DENALI_PI_170__PI_TREF_F0_WIDTH 20U
  2543. #define LPDDR4__PI_TREF_F0__REG DENALI_PI_170
  2544. #define LPDDR4__PI_TREF_F0__FLD LPDDR4__DENALI_PI_170__PI_TREF_F0
  2545. #define LPDDR4__DENALI_PI_171_READ_MASK 0x000003FFU
  2546. #define LPDDR4__DENALI_PI_171_WRITE_MASK 0x000003FFU
  2547. #define LPDDR4__DENALI_PI_171__PI_TRFC_F1_MASK 0x000003FFU
  2548. #define LPDDR4__DENALI_PI_171__PI_TRFC_F1_SHIFT 0U
  2549. #define LPDDR4__DENALI_PI_171__PI_TRFC_F1_WIDTH 10U
  2550. #define LPDDR4__PI_TRFC_F1__REG DENALI_PI_171
  2551. #define LPDDR4__PI_TRFC_F1__FLD LPDDR4__DENALI_PI_171__PI_TRFC_F1
  2552. #define LPDDR4__DENALI_PI_172_READ_MASK 0x000FFFFFU
  2553. #define LPDDR4__DENALI_PI_172_WRITE_MASK 0x000FFFFFU
  2554. #define LPDDR4__DENALI_PI_172__PI_TREF_F1_MASK 0x000FFFFFU
  2555. #define LPDDR4__DENALI_PI_172__PI_TREF_F1_SHIFT 0U
  2556. #define LPDDR4__DENALI_PI_172__PI_TREF_F1_WIDTH 20U
  2557. #define LPDDR4__PI_TREF_F1__REG DENALI_PI_172
  2558. #define LPDDR4__PI_TREF_F1__FLD LPDDR4__DENALI_PI_172__PI_TREF_F1
  2559. #define LPDDR4__DENALI_PI_173_READ_MASK 0x000003FFU
  2560. #define LPDDR4__DENALI_PI_173_WRITE_MASK 0x000003FFU
  2561. #define LPDDR4__DENALI_PI_173__PI_TRFC_F2_MASK 0x000003FFU
  2562. #define LPDDR4__DENALI_PI_173__PI_TRFC_F2_SHIFT 0U
  2563. #define LPDDR4__DENALI_PI_173__PI_TRFC_F2_WIDTH 10U
  2564. #define LPDDR4__PI_TRFC_F2__REG DENALI_PI_173
  2565. #define LPDDR4__PI_TRFC_F2__FLD LPDDR4__DENALI_PI_173__PI_TRFC_F2
  2566. #define LPDDR4__DENALI_PI_174_READ_MASK 0x0F0FFFFFU
  2567. #define LPDDR4__DENALI_PI_174_WRITE_MASK 0x0F0FFFFFU
  2568. #define LPDDR4__DENALI_PI_174__PI_TREF_F2_MASK 0x000FFFFFU
  2569. #define LPDDR4__DENALI_PI_174__PI_TREF_F2_SHIFT 0U
  2570. #define LPDDR4__DENALI_PI_174__PI_TREF_F2_WIDTH 20U
  2571. #define LPDDR4__PI_TREF_F2__REG DENALI_PI_174
  2572. #define LPDDR4__PI_TREF_F2__FLD LPDDR4__DENALI_PI_174__PI_TREF_F2
  2573. #define LPDDR4__DENALI_PI_174__PI_TDFI_CTRL_DELAY_F0_MASK 0x0F000000U
  2574. #define LPDDR4__DENALI_PI_174__PI_TDFI_CTRL_DELAY_F0_SHIFT 24U
  2575. #define LPDDR4__DENALI_PI_174__PI_TDFI_CTRL_DELAY_F0_WIDTH 4U
  2576. #define LPDDR4__PI_TDFI_CTRL_DELAY_F0__REG DENALI_PI_174
  2577. #define LPDDR4__PI_TDFI_CTRL_DELAY_F0__FLD LPDDR4__DENALI_PI_174__PI_TDFI_CTRL_DELAY_F0
  2578. #define LPDDR4__DENALI_PI_175_READ_MASK 0x03030F0FU
  2579. #define LPDDR4__DENALI_PI_175_WRITE_MASK 0x03030F0FU
  2580. #define LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F1_MASK 0x0000000FU
  2581. #define LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F1_SHIFT 0U
  2582. #define LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F1_WIDTH 4U
  2583. #define LPDDR4__PI_TDFI_CTRL_DELAY_F1__REG DENALI_PI_175
  2584. #define LPDDR4__PI_TDFI_CTRL_DELAY_F1__FLD LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F1
  2585. #define LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F2_MASK 0x00000F00U
  2586. #define LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F2_SHIFT 8U
  2587. #define LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F2_WIDTH 4U
  2588. #define LPDDR4__PI_TDFI_CTRL_DELAY_F2__REG DENALI_PI_175
  2589. #define LPDDR4__PI_TDFI_CTRL_DELAY_F2__FLD LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F2
  2590. #define LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F0_MASK 0x00030000U
  2591. #define LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F0_SHIFT 16U
  2592. #define LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F0_WIDTH 2U
  2593. #define LPDDR4__PI_WRLVL_EN_F0__REG DENALI_PI_175
  2594. #define LPDDR4__PI_WRLVL_EN_F0__FLD LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F0
  2595. #define LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F1_MASK 0x03000000U
  2596. #define LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F1_SHIFT 24U
  2597. #define LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F1_WIDTH 2U
  2598. #define LPDDR4__PI_WRLVL_EN_F1__REG DENALI_PI_175
  2599. #define LPDDR4__PI_WRLVL_EN_F1__FLD LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F1
  2600. #define LPDDR4__DENALI_PI_176_READ_MASK 0x0003FF03U
  2601. #define LPDDR4__DENALI_PI_176_WRITE_MASK 0x0003FF03U
  2602. #define LPDDR4__DENALI_PI_176__PI_WRLVL_EN_F2_MASK 0x00000003U
  2603. #define LPDDR4__DENALI_PI_176__PI_WRLVL_EN_F2_SHIFT 0U
  2604. #define LPDDR4__DENALI_PI_176__PI_WRLVL_EN_F2_WIDTH 2U
  2605. #define LPDDR4__PI_WRLVL_EN_F2__REG DENALI_PI_176
  2606. #define LPDDR4__PI_WRLVL_EN_F2__FLD LPDDR4__DENALI_PI_176__PI_WRLVL_EN_F2
  2607. #define LPDDR4__DENALI_PI_176__PI_TDFI_WRLVL_WW_F0_MASK 0x0003FF00U
  2608. #define LPDDR4__DENALI_PI_176__PI_TDFI_WRLVL_WW_F0_SHIFT 8U
  2609. #define LPDDR4__DENALI_PI_176__PI_TDFI_WRLVL_WW_F0_WIDTH 10U
  2610. #define LPDDR4__PI_TDFI_WRLVL_WW_F0__REG DENALI_PI_176
  2611. #define LPDDR4__PI_TDFI_WRLVL_WW_F0__FLD LPDDR4__DENALI_PI_176__PI_TDFI_WRLVL_WW_F0
  2612. #define LPDDR4__DENALI_PI_177_READ_MASK 0x03FF03FFU
  2613. #define LPDDR4__DENALI_PI_177_WRITE_MASK 0x03FF03FFU
  2614. #define LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F1_MASK 0x000003FFU
  2615. #define LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F1_SHIFT 0U
  2616. #define LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F1_WIDTH 10U
  2617. #define LPDDR4__PI_TDFI_WRLVL_WW_F1__REG DENALI_PI_177
  2618. #define LPDDR4__PI_TDFI_WRLVL_WW_F1__FLD LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F1
  2619. #define LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F2_MASK 0x03FF0000U
  2620. #define LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F2_SHIFT 16U
  2621. #define LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F2_WIDTH 10U
  2622. #define LPDDR4__PI_TDFI_WRLVL_WW_F2__REG DENALI_PI_177
  2623. #define LPDDR4__PI_TDFI_WRLVL_WW_F2__FLD LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F2
  2624. #define LPDDR4__DENALI_PI_178_READ_MASK 0x01FF01FFU
  2625. #define LPDDR4__DENALI_PI_178_WRITE_MASK 0x01FF01FFU
  2626. #define LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F0_MASK 0x000000FFU
  2627. #define LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F0_SHIFT 0U
  2628. #define LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F0_WIDTH 8U
  2629. #define LPDDR4__PI_TODTL_2CMD_F0__REG DENALI_PI_178
  2630. #define LPDDR4__PI_TODTL_2CMD_F0__FLD LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F0
  2631. #define LPDDR4__DENALI_PI_178__PI_ODT_EN_F0_MASK 0x00000100U
  2632. #define LPDDR4__DENALI_PI_178__PI_ODT_EN_F0_SHIFT 8U
  2633. #define LPDDR4__DENALI_PI_178__PI_ODT_EN_F0_WIDTH 1U
  2634. #define LPDDR4__DENALI_PI_178__PI_ODT_EN_F0_WOCLR 0U
  2635. #define LPDDR4__DENALI_PI_178__PI_ODT_EN_F0_WOSET 0U
  2636. #define LPDDR4__PI_ODT_EN_F0__REG DENALI_PI_178
  2637. #define LPDDR4__PI_ODT_EN_F0__FLD LPDDR4__DENALI_PI_178__PI_ODT_EN_F0
  2638. #define LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F1_MASK 0x00FF0000U
  2639. #define LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F1_SHIFT 16U
  2640. #define LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F1_WIDTH 8U
  2641. #define LPDDR4__PI_TODTL_2CMD_F1__REG DENALI_PI_178
  2642. #define LPDDR4__PI_TODTL_2CMD_F1__FLD LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F1
  2643. #define LPDDR4__DENALI_PI_178__PI_ODT_EN_F1_MASK 0x01000000U
  2644. #define LPDDR4__DENALI_PI_178__PI_ODT_EN_F1_SHIFT 24U
  2645. #define LPDDR4__DENALI_PI_178__PI_ODT_EN_F1_WIDTH 1U
  2646. #define LPDDR4__DENALI_PI_178__PI_ODT_EN_F1_WOCLR 0U
  2647. #define LPDDR4__DENALI_PI_178__PI_ODT_EN_F1_WOSET 0U
  2648. #define LPDDR4__PI_ODT_EN_F1__REG DENALI_PI_178
  2649. #define LPDDR4__PI_ODT_EN_F1__FLD LPDDR4__DENALI_PI_178__PI_ODT_EN_F1
  2650. #define LPDDR4__DENALI_PI_179_READ_MASK 0x0F0F01FFU
  2651. #define LPDDR4__DENALI_PI_179_WRITE_MASK 0x0F0F01FFU
  2652. #define LPDDR4__DENALI_PI_179__PI_TODTL_2CMD_F2_MASK 0x000000FFU
  2653. #define LPDDR4__DENALI_PI_179__PI_TODTL_2CMD_F2_SHIFT 0U
  2654. #define LPDDR4__DENALI_PI_179__PI_TODTL_2CMD_F2_WIDTH 8U
  2655. #define LPDDR4__PI_TODTL_2CMD_F2__REG DENALI_PI_179
  2656. #define LPDDR4__PI_TODTL_2CMD_F2__FLD LPDDR4__DENALI_PI_179__PI_TODTL_2CMD_F2
  2657. #define LPDDR4__DENALI_PI_179__PI_ODT_EN_F2_MASK 0x00000100U
  2658. #define LPDDR4__DENALI_PI_179__PI_ODT_EN_F2_SHIFT 8U
  2659. #define LPDDR4__DENALI_PI_179__PI_ODT_EN_F2_WIDTH 1U
  2660. #define LPDDR4__DENALI_PI_179__PI_ODT_EN_F2_WOCLR 0U
  2661. #define LPDDR4__DENALI_PI_179__PI_ODT_EN_F2_WOSET 0U
  2662. #define LPDDR4__PI_ODT_EN_F2__REG DENALI_PI_179
  2663. #define LPDDR4__PI_ODT_EN_F2__FLD LPDDR4__DENALI_PI_179__PI_ODT_EN_F2
  2664. #define LPDDR4__DENALI_PI_179__PI_ODTLON_F0_MASK 0x000F0000U
  2665. #define LPDDR4__DENALI_PI_179__PI_ODTLON_F0_SHIFT 16U
  2666. #define LPDDR4__DENALI_PI_179__PI_ODTLON_F0_WIDTH 4U
  2667. #define LPDDR4__PI_ODTLON_F0__REG DENALI_PI_179
  2668. #define LPDDR4__PI_ODTLON_F0__FLD LPDDR4__DENALI_PI_179__PI_ODTLON_F0
  2669. #define LPDDR4__DENALI_PI_179__PI_TODTON_MIN_F0_MASK 0x0F000000U
  2670. #define LPDDR4__DENALI_PI_179__PI_TODTON_MIN_F0_SHIFT 24U
  2671. #define LPDDR4__DENALI_PI_179__PI_TODTON_MIN_F0_WIDTH 4U
  2672. #define LPDDR4__PI_TODTON_MIN_F0__REG DENALI_PI_179
  2673. #define LPDDR4__PI_TODTON_MIN_F0__FLD LPDDR4__DENALI_PI_179__PI_TODTON_MIN_F0
  2674. #define LPDDR4__DENALI_PI_180_READ_MASK 0x0F0F0F0FU
  2675. #define LPDDR4__DENALI_PI_180_WRITE_MASK 0x0F0F0F0FU
  2676. #define LPDDR4__DENALI_PI_180__PI_ODTLON_F1_MASK 0x0000000FU
  2677. #define LPDDR4__DENALI_PI_180__PI_ODTLON_F1_SHIFT 0U
  2678. #define LPDDR4__DENALI_PI_180__PI_ODTLON_F1_WIDTH 4U
  2679. #define LPDDR4__PI_ODTLON_F1__REG DENALI_PI_180
  2680. #define LPDDR4__PI_ODTLON_F1__FLD LPDDR4__DENALI_PI_180__PI_ODTLON_F1
  2681. #define LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F1_MASK 0x00000F00U
  2682. #define LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F1_SHIFT 8U
  2683. #define LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F1_WIDTH 4U
  2684. #define LPDDR4__PI_TODTON_MIN_F1__REG DENALI_PI_180
  2685. #define LPDDR4__PI_TODTON_MIN_F1__FLD LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F1
  2686. #define LPDDR4__DENALI_PI_180__PI_ODTLON_F2_MASK 0x000F0000U
  2687. #define LPDDR4__DENALI_PI_180__PI_ODTLON_F2_SHIFT 16U
  2688. #define LPDDR4__DENALI_PI_180__PI_ODTLON_F2_WIDTH 4U
  2689. #define LPDDR4__PI_ODTLON_F2__REG DENALI_PI_180
  2690. #define LPDDR4__PI_ODTLON_F2__FLD LPDDR4__DENALI_PI_180__PI_ODTLON_F2
  2691. #define LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F2_MASK 0x0F000000U
  2692. #define LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F2_SHIFT 24U
  2693. #define LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F2_WIDTH 4U
  2694. #define LPDDR4__PI_TODTON_MIN_F2__REG DENALI_PI_180
  2695. #define LPDDR4__PI_TODTON_MIN_F2__FLD LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F2
  2696. #define LPDDR4__DENALI_PI_181_READ_MASK 0x03030303U
  2697. #define LPDDR4__DENALI_PI_181_WRITE_MASK 0x03030303U
  2698. #define LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F0_MASK 0x00000003U
  2699. #define LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F0_SHIFT 0U
  2700. #define LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F0_WIDTH 2U
  2701. #define LPDDR4__PI_RDLVL_EN_F0__REG DENALI_PI_181
  2702. #define LPDDR4__PI_RDLVL_EN_F0__FLD LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F0
  2703. #define LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F0_MASK 0x00000300U
  2704. #define LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F0_SHIFT 8U
  2705. #define LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F0_WIDTH 2U
  2706. #define LPDDR4__PI_RDLVL_GATE_EN_F0__REG DENALI_PI_181
  2707. #define LPDDR4__PI_RDLVL_GATE_EN_F0__FLD LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F0
  2708. #define LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F1_MASK 0x00030000U
  2709. #define LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F1_SHIFT 16U
  2710. #define LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F1_WIDTH 2U
  2711. #define LPDDR4__PI_RDLVL_EN_F1__REG DENALI_PI_181
  2712. #define LPDDR4__PI_RDLVL_EN_F1__FLD LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F1
  2713. #define LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F1_MASK 0x03000000U
  2714. #define LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F1_SHIFT 24U
  2715. #define LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F1_WIDTH 2U
  2716. #define LPDDR4__PI_RDLVL_GATE_EN_F1__REG DENALI_PI_181
  2717. #define LPDDR4__PI_RDLVL_GATE_EN_F1__FLD LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F1
  2718. #define LPDDR4__DENALI_PI_182_READ_MASK 0x03030303U
  2719. #define LPDDR4__DENALI_PI_182_WRITE_MASK 0x03030303U
  2720. #define LPDDR4__DENALI_PI_182__PI_RDLVL_EN_F2_MASK 0x00000003U
  2721. #define LPDDR4__DENALI_PI_182__PI_RDLVL_EN_F2_SHIFT 0U
  2722. #define LPDDR4__DENALI_PI_182__PI_RDLVL_EN_F2_WIDTH 2U
  2723. #define LPDDR4__PI_RDLVL_EN_F2__REG DENALI_PI_182
  2724. #define LPDDR4__PI_RDLVL_EN_F2__FLD LPDDR4__DENALI_PI_182__PI_RDLVL_EN_F2
  2725. #define LPDDR4__DENALI_PI_182__PI_RDLVL_GATE_EN_F2_MASK 0x00000300U
  2726. #define LPDDR4__DENALI_PI_182__PI_RDLVL_GATE_EN_F2_SHIFT 8U
  2727. #define LPDDR4__DENALI_PI_182__PI_RDLVL_GATE_EN_F2_WIDTH 2U
  2728. #define LPDDR4__PI_RDLVL_GATE_EN_F2__REG DENALI_PI_182
  2729. #define LPDDR4__PI_RDLVL_GATE_EN_F2__FLD LPDDR4__DENALI_PI_182__PI_RDLVL_GATE_EN_F2
  2730. #define LPDDR4__DENALI_PI_182__PI_RDLVL_PAT0_EN_F0_MASK 0x00030000U
  2731. #define LPDDR4__DENALI_PI_182__PI_RDLVL_PAT0_EN_F0_SHIFT 16U
  2732. #define LPDDR4__DENALI_PI_182__PI_RDLVL_PAT0_EN_F0_WIDTH 2U
  2733. #define LPDDR4__PI_RDLVL_PAT0_EN_F0__REG DENALI_PI_182
  2734. #define LPDDR4__PI_RDLVL_PAT0_EN_F0__FLD LPDDR4__DENALI_PI_182__PI_RDLVL_PAT0_EN_F0
  2735. #define LPDDR4__DENALI_PI_182__PI_RDLVL_RXCAL_EN_F0_MASK 0x03000000U
  2736. #define LPDDR4__DENALI_PI_182__PI_RDLVL_RXCAL_EN_F0_SHIFT 24U
  2737. #define LPDDR4__DENALI_PI_182__PI_RDLVL_RXCAL_EN_F0_WIDTH 2U
  2738. #define LPDDR4__PI_RDLVL_RXCAL_EN_F0__REG DENALI_PI_182
  2739. #define LPDDR4__PI_RDLVL_RXCAL_EN_F0__FLD LPDDR4__DENALI_PI_182__PI_RDLVL_RXCAL_EN_F0
  2740. #define LPDDR4__DENALI_PI_183_READ_MASK 0x03030303U
  2741. #define LPDDR4__DENALI_PI_183_WRITE_MASK 0x03030303U
  2742. #define LPDDR4__DENALI_PI_183__PI_RDLVL_DFE_EN_F0_MASK 0x00000003U
  2743. #define LPDDR4__DENALI_PI_183__PI_RDLVL_DFE_EN_F0_SHIFT 0U
  2744. #define LPDDR4__DENALI_PI_183__PI_RDLVL_DFE_EN_F0_WIDTH 2U
  2745. #define LPDDR4__PI_RDLVL_DFE_EN_F0__REG DENALI_PI_183
  2746. #define LPDDR4__PI_RDLVL_DFE_EN_F0__FLD LPDDR4__DENALI_PI_183__PI_RDLVL_DFE_EN_F0
  2747. #define LPDDR4__DENALI_PI_183__PI_RDLVL_MULTI_EN_F0_MASK 0x00000300U
  2748. #define LPDDR4__DENALI_PI_183__PI_RDLVL_MULTI_EN_F0_SHIFT 8U
  2749. #define LPDDR4__DENALI_PI_183__PI_RDLVL_MULTI_EN_F0_WIDTH 2U
  2750. #define LPDDR4__PI_RDLVL_MULTI_EN_F0__REG DENALI_PI_183
  2751. #define LPDDR4__PI_RDLVL_MULTI_EN_F0__FLD LPDDR4__DENALI_PI_183__PI_RDLVL_MULTI_EN_F0
  2752. #define LPDDR4__DENALI_PI_183__PI_RDLVL_PAT0_EN_F1_MASK 0x00030000U
  2753. #define LPDDR4__DENALI_PI_183__PI_RDLVL_PAT0_EN_F1_SHIFT 16U
  2754. #define LPDDR4__DENALI_PI_183__PI_RDLVL_PAT0_EN_F1_WIDTH 2U
  2755. #define LPDDR4__PI_RDLVL_PAT0_EN_F1__REG DENALI_PI_183
  2756. #define LPDDR4__PI_RDLVL_PAT0_EN_F1__FLD LPDDR4__DENALI_PI_183__PI_RDLVL_PAT0_EN_F1
  2757. #define LPDDR4__DENALI_PI_183__PI_RDLVL_RXCAL_EN_F1_MASK 0x03000000U
  2758. #define LPDDR4__DENALI_PI_183__PI_RDLVL_RXCAL_EN_F1_SHIFT 24U
  2759. #define LPDDR4__DENALI_PI_183__PI_RDLVL_RXCAL_EN_F1_WIDTH 2U
  2760. #define LPDDR4__PI_RDLVL_RXCAL_EN_F1__REG DENALI_PI_183
  2761. #define LPDDR4__PI_RDLVL_RXCAL_EN_F1__FLD LPDDR4__DENALI_PI_183__PI_RDLVL_RXCAL_EN_F1
  2762. #define LPDDR4__DENALI_PI_184_READ_MASK 0x03030303U
  2763. #define LPDDR4__DENALI_PI_184_WRITE_MASK 0x03030303U
  2764. #define LPDDR4__DENALI_PI_184__PI_RDLVL_DFE_EN_F1_MASK 0x00000003U
  2765. #define LPDDR4__DENALI_PI_184__PI_RDLVL_DFE_EN_F1_SHIFT 0U
  2766. #define LPDDR4__DENALI_PI_184__PI_RDLVL_DFE_EN_F1_WIDTH 2U
  2767. #define LPDDR4__PI_RDLVL_DFE_EN_F1__REG DENALI_PI_184
  2768. #define LPDDR4__PI_RDLVL_DFE_EN_F1__FLD LPDDR4__DENALI_PI_184__PI_RDLVL_DFE_EN_F1
  2769. #define LPDDR4__DENALI_PI_184__PI_RDLVL_MULTI_EN_F1_MASK 0x00000300U
  2770. #define LPDDR4__DENALI_PI_184__PI_RDLVL_MULTI_EN_F1_SHIFT 8U
  2771. #define LPDDR4__DENALI_PI_184__PI_RDLVL_MULTI_EN_F1_WIDTH 2U
  2772. #define LPDDR4__PI_RDLVL_MULTI_EN_F1__REG DENALI_PI_184
  2773. #define LPDDR4__PI_RDLVL_MULTI_EN_F1__FLD LPDDR4__DENALI_PI_184__PI_RDLVL_MULTI_EN_F1
  2774. #define LPDDR4__DENALI_PI_184__PI_RDLVL_PAT0_EN_F2_MASK 0x00030000U
  2775. #define LPDDR4__DENALI_PI_184__PI_RDLVL_PAT0_EN_F2_SHIFT 16U
  2776. #define LPDDR4__DENALI_PI_184__PI_RDLVL_PAT0_EN_F2_WIDTH 2U
  2777. #define LPDDR4__PI_RDLVL_PAT0_EN_F2__REG DENALI_PI_184
  2778. #define LPDDR4__PI_RDLVL_PAT0_EN_F2__FLD LPDDR4__DENALI_PI_184__PI_RDLVL_PAT0_EN_F2
  2779. #define LPDDR4__DENALI_PI_184__PI_RDLVL_RXCAL_EN_F2_MASK 0x03000000U
  2780. #define LPDDR4__DENALI_PI_184__PI_RDLVL_RXCAL_EN_F2_SHIFT 24U
  2781. #define LPDDR4__DENALI_PI_184__PI_RDLVL_RXCAL_EN_F2_WIDTH 2U
  2782. #define LPDDR4__PI_RDLVL_RXCAL_EN_F2__REG DENALI_PI_184
  2783. #define LPDDR4__PI_RDLVL_RXCAL_EN_F2__FLD LPDDR4__DENALI_PI_184__PI_RDLVL_RXCAL_EN_F2
  2784. #define LPDDR4__DENALI_PI_185_READ_MASK 0x7F7F0303U
  2785. #define LPDDR4__DENALI_PI_185_WRITE_MASK 0x7F7F0303U
  2786. #define LPDDR4__DENALI_PI_185__PI_RDLVL_DFE_EN_F2_MASK 0x00000003U
  2787. #define LPDDR4__DENALI_PI_185__PI_RDLVL_DFE_EN_F2_SHIFT 0U
  2788. #define LPDDR4__DENALI_PI_185__PI_RDLVL_DFE_EN_F2_WIDTH 2U
  2789. #define LPDDR4__PI_RDLVL_DFE_EN_F2__REG DENALI_PI_185
  2790. #define LPDDR4__PI_RDLVL_DFE_EN_F2__FLD LPDDR4__DENALI_PI_185__PI_RDLVL_DFE_EN_F2
  2791. #define LPDDR4__DENALI_PI_185__PI_RDLVL_MULTI_EN_F2_MASK 0x00000300U
  2792. #define LPDDR4__DENALI_PI_185__PI_RDLVL_MULTI_EN_F2_SHIFT 8U
  2793. #define LPDDR4__DENALI_PI_185__PI_RDLVL_MULTI_EN_F2_WIDTH 2U
  2794. #define LPDDR4__PI_RDLVL_MULTI_EN_F2__REG DENALI_PI_185
  2795. #define LPDDR4__PI_RDLVL_MULTI_EN_F2__FLD LPDDR4__DENALI_PI_185__PI_RDLVL_MULTI_EN_F2
  2796. #define LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F0_MASK 0x007F0000U
  2797. #define LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F0_SHIFT 16U
  2798. #define LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F0_WIDTH 7U
  2799. #define LPDDR4__PI_RDLAT_ADJ_F0__REG DENALI_PI_185
  2800. #define LPDDR4__PI_RDLAT_ADJ_F0__FLD LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F0
  2801. #define LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F1_MASK 0x7F000000U
  2802. #define LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F1_SHIFT 24U
  2803. #define LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F1_WIDTH 7U
  2804. #define LPDDR4__PI_RDLAT_ADJ_F1__REG DENALI_PI_185
  2805. #define LPDDR4__PI_RDLAT_ADJ_F1__FLD LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F1
  2806. #define LPDDR4__DENALI_PI_186_READ_MASK 0x7F7F7F7FU
  2807. #define LPDDR4__DENALI_PI_186_WRITE_MASK 0x7F7F7F7FU
  2808. #define LPDDR4__DENALI_PI_186__PI_RDLAT_ADJ_F2_MASK 0x0000007FU
  2809. #define LPDDR4__DENALI_PI_186__PI_RDLAT_ADJ_F2_SHIFT 0U
  2810. #define LPDDR4__DENALI_PI_186__PI_RDLAT_ADJ_F2_WIDTH 7U
  2811. #define LPDDR4__PI_RDLAT_ADJ_F2__REG DENALI_PI_186
  2812. #define LPDDR4__PI_RDLAT_ADJ_F2__FLD LPDDR4__DENALI_PI_186__PI_RDLAT_ADJ_F2
  2813. #define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F0_MASK 0x00007F00U
  2814. #define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F0_SHIFT 8U
  2815. #define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F0_WIDTH 7U
  2816. #define LPDDR4__PI_WRLAT_ADJ_F0__REG DENALI_PI_186
  2817. #define LPDDR4__PI_WRLAT_ADJ_F0__FLD LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F0
  2818. #define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F1_MASK 0x007F0000U
  2819. #define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F1_SHIFT 16U
  2820. #define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F1_WIDTH 7U
  2821. #define LPDDR4__PI_WRLAT_ADJ_F1__REG DENALI_PI_186
  2822. #define LPDDR4__PI_WRLAT_ADJ_F1__FLD LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F1
  2823. #define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F2_MASK 0x7F000000U
  2824. #define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F2_SHIFT 24U
  2825. #define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F2_WIDTH 7U
  2826. #define LPDDR4__PI_WRLAT_ADJ_F2__REG DENALI_PI_186
  2827. #define LPDDR4__PI_WRLAT_ADJ_F2__FLD LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F2
  2828. #define LPDDR4__DENALI_PI_187_READ_MASK 0x00070707U
  2829. #define LPDDR4__DENALI_PI_187_WRITE_MASK 0x00070707U
  2830. #define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F0_MASK 0x00000007U
  2831. #define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F0_SHIFT 0U
  2832. #define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F0_WIDTH 3U
  2833. #define LPDDR4__PI_TDFI_PHY_WRDATA_F0__REG DENALI_PI_187
  2834. #define LPDDR4__PI_TDFI_PHY_WRDATA_F0__FLD LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F0
  2835. #define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F1_MASK 0x00000700U
  2836. #define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F1_SHIFT 8U
  2837. #define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F1_WIDTH 3U
  2838. #define LPDDR4__PI_TDFI_PHY_WRDATA_F1__REG DENALI_PI_187
  2839. #define LPDDR4__PI_TDFI_PHY_WRDATA_F1__FLD LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F1
  2840. #define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F2_MASK 0x00070000U
  2841. #define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F2_SHIFT 16U
  2842. #define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F2_WIDTH 3U
  2843. #define LPDDR4__PI_TDFI_PHY_WRDATA_F2__REG DENALI_PI_187
  2844. #define LPDDR4__PI_TDFI_PHY_WRDATA_F2__FLD LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F2
  2845. #define LPDDR4__DENALI_PI_188_READ_MASK 0x03FF03FFU
  2846. #define LPDDR4__DENALI_PI_188_WRITE_MASK 0x03FF03FFU
  2847. #define LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CC_F0_MASK 0x000003FFU
  2848. #define LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CC_F0_SHIFT 0U
  2849. #define LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CC_F0_WIDTH 10U
  2850. #define LPDDR4__PI_TDFI_CALVL_CC_F0__REG DENALI_PI_188
  2851. #define LPDDR4__PI_TDFI_CALVL_CC_F0__FLD LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CC_F0
  2852. #define LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CAPTURE_F0_MASK 0x03FF0000U
  2853. #define LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CAPTURE_F0_SHIFT 16U
  2854. #define LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CAPTURE_F0_WIDTH 10U
  2855. #define LPDDR4__PI_TDFI_CALVL_CAPTURE_F0__REG DENALI_PI_188
  2856. #define LPDDR4__PI_TDFI_CALVL_CAPTURE_F0__FLD LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CAPTURE_F0
  2857. #define LPDDR4__DENALI_PI_189_READ_MASK 0x03FF03FFU
  2858. #define LPDDR4__DENALI_PI_189_WRITE_MASK 0x03FF03FFU
  2859. #define LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CC_F1_MASK 0x000003FFU
  2860. #define LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CC_F1_SHIFT 0U
  2861. #define LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CC_F1_WIDTH 10U
  2862. #define LPDDR4__PI_TDFI_CALVL_CC_F1__REG DENALI_PI_189
  2863. #define LPDDR4__PI_TDFI_CALVL_CC_F1__FLD LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CC_F1
  2864. #define LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CAPTURE_F1_MASK 0x03FF0000U
  2865. #define LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CAPTURE_F1_SHIFT 16U
  2866. #define LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CAPTURE_F1_WIDTH 10U
  2867. #define LPDDR4__PI_TDFI_CALVL_CAPTURE_F1__REG DENALI_PI_189
  2868. #define LPDDR4__PI_TDFI_CALVL_CAPTURE_F1__FLD LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CAPTURE_F1
  2869. #define LPDDR4__DENALI_PI_190_READ_MASK 0x03FF03FFU
  2870. #define LPDDR4__DENALI_PI_190_WRITE_MASK 0x03FF03FFU
  2871. #define LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CC_F2_MASK 0x000003FFU
  2872. #define LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CC_F2_SHIFT 0U
  2873. #define LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CC_F2_WIDTH 10U
  2874. #define LPDDR4__PI_TDFI_CALVL_CC_F2__REG DENALI_PI_190
  2875. #define LPDDR4__PI_TDFI_CALVL_CC_F2__FLD LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CC_F2
  2876. #define LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CAPTURE_F2_MASK 0x03FF0000U
  2877. #define LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CAPTURE_F2_SHIFT 16U
  2878. #define LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CAPTURE_F2_WIDTH 10U
  2879. #define LPDDR4__PI_TDFI_CALVL_CAPTURE_F2__REG DENALI_PI_190
  2880. #define LPDDR4__PI_TDFI_CALVL_CAPTURE_F2__FLD LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CAPTURE_F2
  2881. #define LPDDR4__DENALI_PI_191_READ_MASK 0x1F030303U
  2882. #define LPDDR4__DENALI_PI_191_WRITE_MASK 0x1F030303U
  2883. #define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F0_MASK 0x00000003U
  2884. #define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F0_SHIFT 0U
  2885. #define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F0_WIDTH 2U
  2886. #define LPDDR4__PI_CALVL_EN_F0__REG DENALI_PI_191
  2887. #define LPDDR4__PI_CALVL_EN_F0__FLD LPDDR4__DENALI_PI_191__PI_CALVL_EN_F0
  2888. #define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F1_MASK 0x00000300U
  2889. #define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F1_SHIFT 8U
  2890. #define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F1_WIDTH 2U
  2891. #define LPDDR4__PI_CALVL_EN_F1__REG DENALI_PI_191
  2892. #define LPDDR4__PI_CALVL_EN_F1__FLD LPDDR4__DENALI_PI_191__PI_CALVL_EN_F1
  2893. #define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F2_MASK 0x00030000U
  2894. #define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F2_SHIFT 16U
  2895. #define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F2_WIDTH 2U
  2896. #define LPDDR4__PI_CALVL_EN_F2__REG DENALI_PI_191
  2897. #define LPDDR4__PI_CALVL_EN_F2__FLD LPDDR4__DENALI_PI_191__PI_CALVL_EN_F2
  2898. #define LPDDR4__DENALI_PI_191__PI_TMRZ_F0_MASK 0x1F000000U
  2899. #define LPDDR4__DENALI_PI_191__PI_TMRZ_F0_SHIFT 24U
  2900. #define LPDDR4__DENALI_PI_191__PI_TMRZ_F0_WIDTH 5U
  2901. #define LPDDR4__PI_TMRZ_F0__REG DENALI_PI_191
  2902. #define LPDDR4__PI_TMRZ_F0__FLD LPDDR4__DENALI_PI_191__PI_TMRZ_F0
  2903. #define LPDDR4__DENALI_PI_192_READ_MASK 0x001F3FFFU
  2904. #define LPDDR4__DENALI_PI_192_WRITE_MASK 0x001F3FFFU
  2905. #define LPDDR4__DENALI_PI_192__PI_TCAENT_F0_MASK 0x00003FFFU
  2906. #define LPDDR4__DENALI_PI_192__PI_TCAENT_F0_SHIFT 0U
  2907. #define LPDDR4__DENALI_PI_192__PI_TCAENT_F0_WIDTH 14U
  2908. #define LPDDR4__PI_TCAENT_F0__REG DENALI_PI_192
  2909. #define LPDDR4__PI_TCAENT_F0__FLD LPDDR4__DENALI_PI_192__PI_TCAENT_F0
  2910. #define LPDDR4__DENALI_PI_192__PI_TMRZ_F1_MASK 0x001F0000U
  2911. #define LPDDR4__DENALI_PI_192__PI_TMRZ_F1_SHIFT 16U
  2912. #define LPDDR4__DENALI_PI_192__PI_TMRZ_F1_WIDTH 5U
  2913. #define LPDDR4__PI_TMRZ_F1__REG DENALI_PI_192
  2914. #define LPDDR4__PI_TMRZ_F1__FLD LPDDR4__DENALI_PI_192__PI_TMRZ_F1
  2915. #define LPDDR4__DENALI_PI_193_READ_MASK 0x001F3FFFU
  2916. #define LPDDR4__DENALI_PI_193_WRITE_MASK 0x001F3FFFU
  2917. #define LPDDR4__DENALI_PI_193__PI_TCAENT_F1_MASK 0x00003FFFU
  2918. #define LPDDR4__DENALI_PI_193__PI_TCAENT_F1_SHIFT 0U
  2919. #define LPDDR4__DENALI_PI_193__PI_TCAENT_F1_WIDTH 14U
  2920. #define LPDDR4__PI_TCAENT_F1__REG DENALI_PI_193
  2921. #define LPDDR4__PI_TCAENT_F1__FLD LPDDR4__DENALI_PI_193__PI_TCAENT_F1
  2922. #define LPDDR4__DENALI_PI_193__PI_TMRZ_F2_MASK 0x001F0000U
  2923. #define LPDDR4__DENALI_PI_193__PI_TMRZ_F2_SHIFT 16U
  2924. #define LPDDR4__DENALI_PI_193__PI_TMRZ_F2_WIDTH 5U
  2925. #define LPDDR4__PI_TMRZ_F2__REG DENALI_PI_193
  2926. #define LPDDR4__PI_TMRZ_F2__FLD LPDDR4__DENALI_PI_193__PI_TMRZ_F2
  2927. #define LPDDR4__DENALI_PI_194_READ_MASK 0x1F1F3FFFU
  2928. #define LPDDR4__DENALI_PI_194_WRITE_MASK 0x1F1F3FFFU
  2929. #define LPDDR4__DENALI_PI_194__PI_TCAENT_F2_MASK 0x00003FFFU
  2930. #define LPDDR4__DENALI_PI_194__PI_TCAENT_F2_SHIFT 0U
  2931. #define LPDDR4__DENALI_PI_194__PI_TCAENT_F2_WIDTH 14U
  2932. #define LPDDR4__PI_TCAENT_F2__REG DENALI_PI_194
  2933. #define LPDDR4__PI_TCAENT_F2__FLD LPDDR4__DENALI_PI_194__PI_TCAENT_F2
  2934. #define LPDDR4__DENALI_PI_194__PI_TDFI_CACSCA_F0_MASK 0x001F0000U
  2935. #define LPDDR4__DENALI_PI_194__PI_TDFI_CACSCA_F0_SHIFT 16U
  2936. #define LPDDR4__DENALI_PI_194__PI_TDFI_CACSCA_F0_WIDTH 5U
  2937. #define LPDDR4__PI_TDFI_CACSCA_F0__REG DENALI_PI_194
  2938. #define LPDDR4__PI_TDFI_CACSCA_F0__FLD LPDDR4__DENALI_PI_194__PI_TDFI_CACSCA_F0
  2939. #define LPDDR4__DENALI_PI_194__PI_TDFI_CASEL_F0_MASK 0x1F000000U
  2940. #define LPDDR4__DENALI_PI_194__PI_TDFI_CASEL_F0_SHIFT 24U
  2941. #define LPDDR4__DENALI_PI_194__PI_TDFI_CASEL_F0_WIDTH 5U
  2942. #define LPDDR4__PI_TDFI_CASEL_F0__REG DENALI_PI_194
  2943. #define LPDDR4__PI_TDFI_CASEL_F0__FLD LPDDR4__DENALI_PI_194__PI_TDFI_CASEL_F0
  2944. #define LPDDR4__DENALI_PI_195_READ_MASK 0x03FF03FFU
  2945. #define LPDDR4__DENALI_PI_195_WRITE_MASK 0x03FF03FFU
  2946. #define LPDDR4__DENALI_PI_195__PI_TVREF_SHORT_F0_MASK 0x000003FFU
  2947. #define LPDDR4__DENALI_PI_195__PI_TVREF_SHORT_F0_SHIFT 0U
  2948. #define LPDDR4__DENALI_PI_195__PI_TVREF_SHORT_F0_WIDTH 10U
  2949. #define LPDDR4__PI_TVREF_SHORT_F0__REG DENALI_PI_195
  2950. #define LPDDR4__PI_TVREF_SHORT_F0__FLD LPDDR4__DENALI_PI_195__PI_TVREF_SHORT_F0
  2951. #define LPDDR4__DENALI_PI_195__PI_TVREF_LONG_F0_MASK 0x03FF0000U
  2952. #define LPDDR4__DENALI_PI_195__PI_TVREF_LONG_F0_SHIFT 16U
  2953. #define LPDDR4__DENALI_PI_195__PI_TVREF_LONG_F0_WIDTH 10U
  2954. #define LPDDR4__PI_TVREF_LONG_F0__REG DENALI_PI_195
  2955. #define LPDDR4__PI_TVREF_LONG_F0__FLD LPDDR4__DENALI_PI_195__PI_TVREF_LONG_F0
  2956. #define LPDDR4__DENALI_PI_196_READ_MASK 0x03FF1F1FU
  2957. #define LPDDR4__DENALI_PI_196_WRITE_MASK 0x03FF1F1FU
  2958. #define LPDDR4__DENALI_PI_196__PI_TDFI_CACSCA_F1_MASK 0x0000001FU
  2959. #define LPDDR4__DENALI_PI_196__PI_TDFI_CACSCA_F1_SHIFT 0U
  2960. #define LPDDR4__DENALI_PI_196__PI_TDFI_CACSCA_F1_WIDTH 5U
  2961. #define LPDDR4__PI_TDFI_CACSCA_F1__REG DENALI_PI_196
  2962. #define LPDDR4__PI_TDFI_CACSCA_F1__FLD LPDDR4__DENALI_PI_196__PI_TDFI_CACSCA_F1
  2963. #define LPDDR4__DENALI_PI_196__PI_TDFI_CASEL_F1_MASK 0x00001F00U
  2964. #define LPDDR4__DENALI_PI_196__PI_TDFI_CASEL_F1_SHIFT 8U
  2965. #define LPDDR4__DENALI_PI_196__PI_TDFI_CASEL_F1_WIDTH 5U
  2966. #define LPDDR4__PI_TDFI_CASEL_F1__REG DENALI_PI_196
  2967. #define LPDDR4__PI_TDFI_CASEL_F1__FLD LPDDR4__DENALI_PI_196__PI_TDFI_CASEL_F1
  2968. #define LPDDR4__DENALI_PI_196__PI_TVREF_SHORT_F1_MASK 0x03FF0000U
  2969. #define LPDDR4__DENALI_PI_196__PI_TVREF_SHORT_F1_SHIFT 16U
  2970. #define LPDDR4__DENALI_PI_196__PI_TVREF_SHORT_F1_WIDTH 10U
  2971. #define LPDDR4__PI_TVREF_SHORT_F1__REG DENALI_PI_196
  2972. #define LPDDR4__PI_TVREF_SHORT_F1__FLD LPDDR4__DENALI_PI_196__PI_TVREF_SHORT_F1
  2973. #define LPDDR4__DENALI_PI_197_READ_MASK 0x1F1F03FFU
  2974. #define LPDDR4__DENALI_PI_197_WRITE_MASK 0x1F1F03FFU
  2975. #define LPDDR4__DENALI_PI_197__PI_TVREF_LONG_F1_MASK 0x000003FFU
  2976. #define LPDDR4__DENALI_PI_197__PI_TVREF_LONG_F1_SHIFT 0U
  2977. #define LPDDR4__DENALI_PI_197__PI_TVREF_LONG_F1_WIDTH 10U
  2978. #define LPDDR4__PI_TVREF_LONG_F1__REG DENALI_PI_197
  2979. #define LPDDR4__PI_TVREF_LONG_F1__FLD LPDDR4__DENALI_PI_197__PI_TVREF_LONG_F1
  2980. #define LPDDR4__DENALI_PI_197__PI_TDFI_CACSCA_F2_MASK 0x001F0000U
  2981. #define LPDDR4__DENALI_PI_197__PI_TDFI_CACSCA_F2_SHIFT 16U
  2982. #define LPDDR4__DENALI_PI_197__PI_TDFI_CACSCA_F2_WIDTH 5U
  2983. #define LPDDR4__PI_TDFI_CACSCA_F2__REG DENALI_PI_197
  2984. #define LPDDR4__PI_TDFI_CACSCA_F2__FLD LPDDR4__DENALI_PI_197__PI_TDFI_CACSCA_F2
  2985. #define LPDDR4__DENALI_PI_197__PI_TDFI_CASEL_F2_MASK 0x1F000000U
  2986. #define LPDDR4__DENALI_PI_197__PI_TDFI_CASEL_F2_SHIFT 24U
  2987. #define LPDDR4__DENALI_PI_197__PI_TDFI_CASEL_F2_WIDTH 5U
  2988. #define LPDDR4__PI_TDFI_CASEL_F2__REG DENALI_PI_197
  2989. #define LPDDR4__PI_TDFI_CASEL_F2__FLD LPDDR4__DENALI_PI_197__PI_TDFI_CASEL_F2
  2990. #define LPDDR4__DENALI_PI_198_READ_MASK 0x03FF03FFU
  2991. #define LPDDR4__DENALI_PI_198_WRITE_MASK 0x03FF03FFU
  2992. #define LPDDR4__DENALI_PI_198__PI_TVREF_SHORT_F2_MASK 0x000003FFU
  2993. #define LPDDR4__DENALI_PI_198__PI_TVREF_SHORT_F2_SHIFT 0U
  2994. #define LPDDR4__DENALI_PI_198__PI_TVREF_SHORT_F2_WIDTH 10U
  2995. #define LPDDR4__PI_TVREF_SHORT_F2__REG DENALI_PI_198
  2996. #define LPDDR4__PI_TVREF_SHORT_F2__FLD LPDDR4__DENALI_PI_198__PI_TVREF_SHORT_F2
  2997. #define LPDDR4__DENALI_PI_198__PI_TVREF_LONG_F2_MASK 0x03FF0000U
  2998. #define LPDDR4__DENALI_PI_198__PI_TVREF_LONG_F2_SHIFT 16U
  2999. #define LPDDR4__DENALI_PI_198__PI_TVREF_LONG_F2_WIDTH 10U
  3000. #define LPDDR4__PI_TVREF_LONG_F2__REG DENALI_PI_198
  3001. #define LPDDR4__PI_TVREF_LONG_F2__FLD LPDDR4__DENALI_PI_198__PI_TVREF_LONG_F2
  3002. #define LPDDR4__DENALI_PI_199_READ_MASK 0x7F7F7F7FU
  3003. #define LPDDR4__DENALI_PI_199_WRITE_MASK 0x7F7F7F7FU
  3004. #define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F0_MASK 0x0000007FU
  3005. #define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F0_SHIFT 0U
  3006. #define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F0_WIDTH 7U
  3007. #define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F0__REG DENALI_PI_199
  3008. #define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F0__FLD LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F0
  3009. #define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F0_MASK 0x00007F00U
  3010. #define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F0_SHIFT 8U
  3011. #define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F0_WIDTH 7U
  3012. #define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F0__REG DENALI_PI_199
  3013. #define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F0__FLD LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F0
  3014. #define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F1_MASK 0x007F0000U
  3015. #define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F1_SHIFT 16U
  3016. #define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F1_WIDTH 7U
  3017. #define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F1__REG DENALI_PI_199
  3018. #define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F1__FLD LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F1
  3019. #define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F1_MASK 0x7F000000U
  3020. #define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F1_SHIFT 24U
  3021. #define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F1_WIDTH 7U
  3022. #define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F1__REG DENALI_PI_199
  3023. #define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F1__FLD LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F1
  3024. #define LPDDR4__DENALI_PI_200_READ_MASK 0x0F0F7F7FU
  3025. #define LPDDR4__DENALI_PI_200_WRITE_MASK 0x0F0F7F7FU
  3026. #define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_START_POINT_F2_MASK 0x0000007FU
  3027. #define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_START_POINT_F2_SHIFT 0U
  3028. #define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_START_POINT_F2_WIDTH 7U
  3029. #define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F2__REG DENALI_PI_200
  3030. #define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F2__FLD LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_START_POINT_F2
  3031. #define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_STOP_POINT_F2_MASK 0x00007F00U
  3032. #define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_STOP_POINT_F2_SHIFT 8U
  3033. #define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_STOP_POINT_F2_WIDTH 7U
  3034. #define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F2__REG DENALI_PI_200
  3035. #define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F2__FLD LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_STOP_POINT_F2
  3036. #define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F0_MASK 0x000F0000U
  3037. #define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F0_SHIFT 16U
  3038. #define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F0_WIDTH 4U
  3039. #define LPDDR4__PI_CALVL_VREF_DELTA_F0__REG DENALI_PI_200
  3040. #define LPDDR4__PI_CALVL_VREF_DELTA_F0__FLD LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F0
  3041. #define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F1_MASK 0x0F000000U
  3042. #define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F1_SHIFT 24U
  3043. #define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F1_WIDTH 4U
  3044. #define LPDDR4__PI_CALVL_VREF_DELTA_F1__REG DENALI_PI_200
  3045. #define LPDDR4__PI_CALVL_VREF_DELTA_F1__FLD LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F1
  3046. #define LPDDR4__DENALI_PI_201_READ_MASK 0xFF1F0F0FU
  3047. #define LPDDR4__DENALI_PI_201_WRITE_MASK 0xFF1F0F0FU
  3048. #define LPDDR4__DENALI_PI_201__PI_CALVL_VREF_DELTA_F2_MASK 0x0000000FU
  3049. #define LPDDR4__DENALI_PI_201__PI_CALVL_VREF_DELTA_F2_SHIFT 0U
  3050. #define LPDDR4__DENALI_PI_201__PI_CALVL_VREF_DELTA_F2_WIDTH 4U
  3051. #define LPDDR4__PI_CALVL_VREF_DELTA_F2__REG DENALI_PI_201
  3052. #define LPDDR4__PI_CALVL_VREF_DELTA_F2__FLD LPDDR4__DENALI_PI_201__PI_CALVL_VREF_DELTA_F2
  3053. #define LPDDR4__DENALI_PI_201__PI_TDFI_CALVL_STROBE_F0_MASK 0x00000F00U
  3054. #define LPDDR4__DENALI_PI_201__PI_TDFI_CALVL_STROBE_F0_SHIFT 8U
  3055. #define LPDDR4__DENALI_PI_201__PI_TDFI_CALVL_STROBE_F0_WIDTH 4U
  3056. #define LPDDR4__PI_TDFI_CALVL_STROBE_F0__REG DENALI_PI_201
  3057. #define LPDDR4__PI_TDFI_CALVL_STROBE_F0__FLD LPDDR4__DENALI_PI_201__PI_TDFI_CALVL_STROBE_F0
  3058. #define LPDDR4__DENALI_PI_201__PI_TXP_F0_MASK 0x001F0000U
  3059. #define LPDDR4__DENALI_PI_201__PI_TXP_F0_SHIFT 16U
  3060. #define LPDDR4__DENALI_PI_201__PI_TXP_F0_WIDTH 5U
  3061. #define LPDDR4__PI_TXP_F0__REG DENALI_PI_201
  3062. #define LPDDR4__PI_TXP_F0__FLD LPDDR4__DENALI_PI_201__PI_TXP_F0
  3063. #define LPDDR4__DENALI_PI_201__PI_TMRWCKEL_F0_MASK 0xFF000000U
  3064. #define LPDDR4__DENALI_PI_201__PI_TMRWCKEL_F0_SHIFT 24U
  3065. #define LPDDR4__DENALI_PI_201__PI_TMRWCKEL_F0_WIDTH 8U
  3066. #define LPDDR4__PI_TMRWCKEL_F0__REG DENALI_PI_201
  3067. #define LPDDR4__PI_TMRWCKEL_F0__FLD LPDDR4__DENALI_PI_201__PI_TMRWCKEL_F0
  3068. #define LPDDR4__DENALI_PI_202_READ_MASK 0xFF1F0F1FU
  3069. #define LPDDR4__DENALI_PI_202_WRITE_MASK 0xFF1F0F1FU
  3070. #define LPDDR4__DENALI_PI_202__PI_TCKELCK_F0_MASK 0x0000001FU
  3071. #define LPDDR4__DENALI_PI_202__PI_TCKELCK_F0_SHIFT 0U
  3072. #define LPDDR4__DENALI_PI_202__PI_TCKELCK_F0_WIDTH 5U
  3073. #define LPDDR4__PI_TCKELCK_F0__REG DENALI_PI_202
  3074. #define LPDDR4__PI_TCKELCK_F0__FLD LPDDR4__DENALI_PI_202__PI_TCKELCK_F0
  3075. #define LPDDR4__DENALI_PI_202__PI_TDFI_CALVL_STROBE_F1_MASK 0x00000F00U
  3076. #define LPDDR4__DENALI_PI_202__PI_TDFI_CALVL_STROBE_F1_SHIFT 8U
  3077. #define LPDDR4__DENALI_PI_202__PI_TDFI_CALVL_STROBE_F1_WIDTH 4U
  3078. #define LPDDR4__PI_TDFI_CALVL_STROBE_F1__REG DENALI_PI_202
  3079. #define LPDDR4__PI_TDFI_CALVL_STROBE_F1__FLD LPDDR4__DENALI_PI_202__PI_TDFI_CALVL_STROBE_F1
  3080. #define LPDDR4__DENALI_PI_202__PI_TXP_F1_MASK 0x001F0000U
  3081. #define LPDDR4__DENALI_PI_202__PI_TXP_F1_SHIFT 16U
  3082. #define LPDDR4__DENALI_PI_202__PI_TXP_F1_WIDTH 5U
  3083. #define LPDDR4__PI_TXP_F1__REG DENALI_PI_202
  3084. #define LPDDR4__PI_TXP_F1__FLD LPDDR4__DENALI_PI_202__PI_TXP_F1
  3085. #define LPDDR4__DENALI_PI_202__PI_TMRWCKEL_F1_MASK 0xFF000000U
  3086. #define LPDDR4__DENALI_PI_202__PI_TMRWCKEL_F1_SHIFT 24U
  3087. #define LPDDR4__DENALI_PI_202__PI_TMRWCKEL_F1_WIDTH 8U
  3088. #define LPDDR4__PI_TMRWCKEL_F1__REG DENALI_PI_202
  3089. #define LPDDR4__PI_TMRWCKEL_F1__FLD LPDDR4__DENALI_PI_202__PI_TMRWCKEL_F1
  3090. #define LPDDR4__DENALI_PI_203_READ_MASK 0xFF1F0F1FU
  3091. #define LPDDR4__DENALI_PI_203_WRITE_MASK 0xFF1F0F1FU
  3092. #define LPDDR4__DENALI_PI_203__PI_TCKELCK_F1_MASK 0x0000001FU
  3093. #define LPDDR4__DENALI_PI_203__PI_TCKELCK_F1_SHIFT 0U
  3094. #define LPDDR4__DENALI_PI_203__PI_TCKELCK_F1_WIDTH 5U
  3095. #define LPDDR4__PI_TCKELCK_F1__REG DENALI_PI_203
  3096. #define LPDDR4__PI_TCKELCK_F1__FLD LPDDR4__DENALI_PI_203__PI_TCKELCK_F1
  3097. #define LPDDR4__DENALI_PI_203__PI_TDFI_CALVL_STROBE_F2_MASK 0x00000F00U
  3098. #define LPDDR4__DENALI_PI_203__PI_TDFI_CALVL_STROBE_F2_SHIFT 8U
  3099. #define LPDDR4__DENALI_PI_203__PI_TDFI_CALVL_STROBE_F2_WIDTH 4U
  3100. #define LPDDR4__PI_TDFI_CALVL_STROBE_F2__REG DENALI_PI_203
  3101. #define LPDDR4__PI_TDFI_CALVL_STROBE_F2__FLD LPDDR4__DENALI_PI_203__PI_TDFI_CALVL_STROBE_F2
  3102. #define LPDDR4__DENALI_PI_203__PI_TXP_F2_MASK 0x001F0000U
  3103. #define LPDDR4__DENALI_PI_203__PI_TXP_F2_SHIFT 16U
  3104. #define LPDDR4__DENALI_PI_203__PI_TXP_F2_WIDTH 5U
  3105. #define LPDDR4__PI_TXP_F2__REG DENALI_PI_203
  3106. #define LPDDR4__PI_TXP_F2__FLD LPDDR4__DENALI_PI_203__PI_TXP_F2
  3107. #define LPDDR4__DENALI_PI_203__PI_TMRWCKEL_F2_MASK 0xFF000000U
  3108. #define LPDDR4__DENALI_PI_203__PI_TMRWCKEL_F2_SHIFT 24U
  3109. #define LPDDR4__DENALI_PI_203__PI_TMRWCKEL_F2_WIDTH 8U
  3110. #define LPDDR4__PI_TMRWCKEL_F2__REG DENALI_PI_203
  3111. #define LPDDR4__PI_TMRWCKEL_F2__FLD LPDDR4__DENALI_PI_203__PI_TMRWCKEL_F2
  3112. #define LPDDR4__DENALI_PI_204_READ_MASK 0x0003FF1FU
  3113. #define LPDDR4__DENALI_PI_204_WRITE_MASK 0x0003FF1FU
  3114. #define LPDDR4__DENALI_PI_204__PI_TCKELCK_F2_MASK 0x0000001FU
  3115. #define LPDDR4__DENALI_PI_204__PI_TCKELCK_F2_SHIFT 0U
  3116. #define LPDDR4__DENALI_PI_204__PI_TCKELCK_F2_WIDTH 5U
  3117. #define LPDDR4__PI_TCKELCK_F2__REG DENALI_PI_204
  3118. #define LPDDR4__PI_TCKELCK_F2__FLD LPDDR4__DENALI_PI_204__PI_TCKELCK_F2
  3119. #define LPDDR4__DENALI_PI_204__PI_TDFI_INIT_START_F0_MASK 0x0003FF00U
  3120. #define LPDDR4__DENALI_PI_204__PI_TDFI_INIT_START_F0_SHIFT 8U
  3121. #define LPDDR4__DENALI_PI_204__PI_TDFI_INIT_START_F0_WIDTH 10U
  3122. #define LPDDR4__PI_TDFI_INIT_START_F0__REG DENALI_PI_204
  3123. #define LPDDR4__PI_TDFI_INIT_START_F0__FLD LPDDR4__DENALI_PI_204__PI_TDFI_INIT_START_F0
  3124. #define LPDDR4__DENALI_PI_205_READ_MASK 0x03FFFFFFU
  3125. #define LPDDR4__DENALI_PI_205_WRITE_MASK 0x03FFFFFFU
  3126. #define LPDDR4__DENALI_PI_205__PI_TDFI_INIT_COMPLETE_F0_MASK 0x0000FFFFU
  3127. #define LPDDR4__DENALI_PI_205__PI_TDFI_INIT_COMPLETE_F0_SHIFT 0U
  3128. #define LPDDR4__DENALI_PI_205__PI_TDFI_INIT_COMPLETE_F0_WIDTH 16U
  3129. #define LPDDR4__PI_TDFI_INIT_COMPLETE_F0__REG DENALI_PI_205
  3130. #define LPDDR4__PI_TDFI_INIT_COMPLETE_F0__FLD LPDDR4__DENALI_PI_205__PI_TDFI_INIT_COMPLETE_F0
  3131. #define LPDDR4__DENALI_PI_205__PI_TDFI_INIT_START_F1_MASK 0x03FF0000U
  3132. #define LPDDR4__DENALI_PI_205__PI_TDFI_INIT_START_F1_SHIFT 16U
  3133. #define LPDDR4__DENALI_PI_205__PI_TDFI_INIT_START_F1_WIDTH 10U
  3134. #define LPDDR4__PI_TDFI_INIT_START_F1__REG DENALI_PI_205
  3135. #define LPDDR4__PI_TDFI_INIT_START_F1__FLD LPDDR4__DENALI_PI_205__PI_TDFI_INIT_START_F1
  3136. #define LPDDR4__DENALI_PI_206_READ_MASK 0x03FFFFFFU
  3137. #define LPDDR4__DENALI_PI_206_WRITE_MASK 0x03FFFFFFU
  3138. #define LPDDR4__DENALI_PI_206__PI_TDFI_INIT_COMPLETE_F1_MASK 0x0000FFFFU
  3139. #define LPDDR4__DENALI_PI_206__PI_TDFI_INIT_COMPLETE_F1_SHIFT 0U
  3140. #define LPDDR4__DENALI_PI_206__PI_TDFI_INIT_COMPLETE_F1_WIDTH 16U
  3141. #define LPDDR4__PI_TDFI_INIT_COMPLETE_F1__REG DENALI_PI_206
  3142. #define LPDDR4__PI_TDFI_INIT_COMPLETE_F1__FLD LPDDR4__DENALI_PI_206__PI_TDFI_INIT_COMPLETE_F1
  3143. #define LPDDR4__DENALI_PI_206__PI_TDFI_INIT_START_F2_MASK 0x03FF0000U
  3144. #define LPDDR4__DENALI_PI_206__PI_TDFI_INIT_START_F2_SHIFT 16U
  3145. #define LPDDR4__DENALI_PI_206__PI_TDFI_INIT_START_F2_WIDTH 10U
  3146. #define LPDDR4__PI_TDFI_INIT_START_F2__REG DENALI_PI_206
  3147. #define LPDDR4__PI_TDFI_INIT_START_F2__FLD LPDDR4__DENALI_PI_206__PI_TDFI_INIT_START_F2
  3148. #define LPDDR4__DENALI_PI_207_READ_MASK 0x003FFFFFU
  3149. #define LPDDR4__DENALI_PI_207_WRITE_MASK 0x003FFFFFU
  3150. #define LPDDR4__DENALI_PI_207__PI_TDFI_INIT_COMPLETE_F2_MASK 0x0000FFFFU
  3151. #define LPDDR4__DENALI_PI_207__PI_TDFI_INIT_COMPLETE_F2_SHIFT 0U
  3152. #define LPDDR4__DENALI_PI_207__PI_TDFI_INIT_COMPLETE_F2_WIDTH 16U
  3153. #define LPDDR4__PI_TDFI_INIT_COMPLETE_F2__REG DENALI_PI_207
  3154. #define LPDDR4__PI_TDFI_INIT_COMPLETE_F2__FLD LPDDR4__DENALI_PI_207__PI_TDFI_INIT_COMPLETE_F2
  3155. #define LPDDR4__DENALI_PI_207__PI_TCKEHDQS_F0_MASK 0x003F0000U
  3156. #define LPDDR4__DENALI_PI_207__PI_TCKEHDQS_F0_SHIFT 16U
  3157. #define LPDDR4__DENALI_PI_207__PI_TCKEHDQS_F0_WIDTH 6U
  3158. #define LPDDR4__PI_TCKEHDQS_F0__REG DENALI_PI_207
  3159. #define LPDDR4__PI_TCKEHDQS_F0__FLD LPDDR4__DENALI_PI_207__PI_TCKEHDQS_F0
  3160. #define LPDDR4__DENALI_PI_208_READ_MASK 0x003F03FFU
  3161. #define LPDDR4__DENALI_PI_208_WRITE_MASK 0x003F03FFU
  3162. #define LPDDR4__DENALI_PI_208__PI_TFC_F0_MASK 0x000003FFU
  3163. #define LPDDR4__DENALI_PI_208__PI_TFC_F0_SHIFT 0U
  3164. #define LPDDR4__DENALI_PI_208__PI_TFC_F0_WIDTH 10U
  3165. #define LPDDR4__PI_TFC_F0__REG DENALI_PI_208
  3166. #define LPDDR4__PI_TFC_F0__FLD LPDDR4__DENALI_PI_208__PI_TFC_F0
  3167. #define LPDDR4__DENALI_PI_208__PI_TCKEHDQS_F1_MASK 0x003F0000U
  3168. #define LPDDR4__DENALI_PI_208__PI_TCKEHDQS_F1_SHIFT 16U
  3169. #define LPDDR4__DENALI_PI_208__PI_TCKEHDQS_F1_WIDTH 6U
  3170. #define LPDDR4__PI_TCKEHDQS_F1__REG DENALI_PI_208
  3171. #define LPDDR4__PI_TCKEHDQS_F1__FLD LPDDR4__DENALI_PI_208__PI_TCKEHDQS_F1
  3172. #define LPDDR4__DENALI_PI_209_READ_MASK 0x003F03FFU
  3173. #define LPDDR4__DENALI_PI_209_WRITE_MASK 0x003F03FFU
  3174. #define LPDDR4__DENALI_PI_209__PI_TFC_F1_MASK 0x000003FFU
  3175. #define LPDDR4__DENALI_PI_209__PI_TFC_F1_SHIFT 0U
  3176. #define LPDDR4__DENALI_PI_209__PI_TFC_F1_WIDTH 10U
  3177. #define LPDDR4__PI_TFC_F1__REG DENALI_PI_209
  3178. #define LPDDR4__PI_TFC_F1__FLD LPDDR4__DENALI_PI_209__PI_TFC_F1
  3179. #define LPDDR4__DENALI_PI_209__PI_TCKEHDQS_F2_MASK 0x003F0000U
  3180. #define LPDDR4__DENALI_PI_209__PI_TCKEHDQS_F2_SHIFT 16U
  3181. #define LPDDR4__DENALI_PI_209__PI_TCKEHDQS_F2_WIDTH 6U
  3182. #define LPDDR4__PI_TCKEHDQS_F2__REG DENALI_PI_209
  3183. #define LPDDR4__PI_TCKEHDQS_F2__FLD LPDDR4__DENALI_PI_209__PI_TCKEHDQS_F2
  3184. #define LPDDR4__DENALI_PI_210_READ_MASK 0x03FF03FFU
  3185. #define LPDDR4__DENALI_PI_210_WRITE_MASK 0x03FF03FFU
  3186. #define LPDDR4__DENALI_PI_210__PI_TFC_F2_MASK 0x000003FFU
  3187. #define LPDDR4__DENALI_PI_210__PI_TFC_F2_SHIFT 0U
  3188. #define LPDDR4__DENALI_PI_210__PI_TFC_F2_WIDTH 10U
  3189. #define LPDDR4__PI_TFC_F2__REG DENALI_PI_210
  3190. #define LPDDR4__PI_TFC_F2__FLD LPDDR4__DENALI_PI_210__PI_TFC_F2
  3191. #define LPDDR4__DENALI_PI_210__PI_TDFI_WDQLVL_WR_F0_MASK 0x03FF0000U
  3192. #define LPDDR4__DENALI_PI_210__PI_TDFI_WDQLVL_WR_F0_SHIFT 16U
  3193. #define LPDDR4__DENALI_PI_210__PI_TDFI_WDQLVL_WR_F0_WIDTH 10U
  3194. #define LPDDR4__PI_TDFI_WDQLVL_WR_F0__REG DENALI_PI_210
  3195. #define LPDDR4__PI_TDFI_WDQLVL_WR_F0__FLD LPDDR4__DENALI_PI_210__PI_TDFI_WDQLVL_WR_F0
  3196. #define LPDDR4__DENALI_PI_211_READ_MASK 0x7F7F03FFU
  3197. #define LPDDR4__DENALI_PI_211_WRITE_MASK 0x7F7F03FFU
  3198. #define LPDDR4__DENALI_PI_211__PI_TDFI_WDQLVL_RW_F0_MASK 0x000003FFU
  3199. #define LPDDR4__DENALI_PI_211__PI_TDFI_WDQLVL_RW_F0_SHIFT 0U
  3200. #define LPDDR4__DENALI_PI_211__PI_TDFI_WDQLVL_RW_F0_WIDTH 10U
  3201. #define LPDDR4__PI_TDFI_WDQLVL_RW_F0__REG DENALI_PI_211
  3202. #define LPDDR4__PI_TDFI_WDQLVL_RW_F0__FLD LPDDR4__DENALI_PI_211__PI_TDFI_WDQLVL_RW_F0
  3203. #define LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_START_POINT_F0_MASK 0x007F0000U
  3204. #define LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_START_POINT_F0_SHIFT 16U
  3205. #define LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_START_POINT_F0_WIDTH 7U
  3206. #define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F0__REG DENALI_PI_211
  3207. #define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F0__FLD LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_START_POINT_F0
  3208. #define LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0_MASK 0x7F000000U
  3209. #define LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0_SHIFT 24U
  3210. #define LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0_WIDTH 7U
  3211. #define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0__REG DENALI_PI_211
  3212. #define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0__FLD LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0
  3213. #define LPDDR4__DENALI_PI_212_READ_MASK 0x0003030FU
  3214. #define LPDDR4__DENALI_PI_212_WRITE_MASK 0x0003030FU
  3215. #define LPDDR4__DENALI_PI_212__PI_WDQLVL_VREF_DELTA_F0_MASK 0x0000000FU
  3216. #define LPDDR4__DENALI_PI_212__PI_WDQLVL_VREF_DELTA_F0_SHIFT 0U
  3217. #define LPDDR4__DENALI_PI_212__PI_WDQLVL_VREF_DELTA_F0_WIDTH 4U
  3218. #define LPDDR4__PI_WDQLVL_VREF_DELTA_F0__REG DENALI_PI_212
  3219. #define LPDDR4__PI_WDQLVL_VREF_DELTA_F0__FLD LPDDR4__DENALI_PI_212__PI_WDQLVL_VREF_DELTA_F0
  3220. #define LPDDR4__DENALI_PI_212__PI_WDQLVL_EN_F0_MASK 0x00000300U
  3221. #define LPDDR4__DENALI_PI_212__PI_WDQLVL_EN_F0_SHIFT 8U
  3222. #define LPDDR4__DENALI_PI_212__PI_WDQLVL_EN_F0_WIDTH 2U
  3223. #define LPDDR4__PI_WDQLVL_EN_F0__REG DENALI_PI_212
  3224. #define LPDDR4__PI_WDQLVL_EN_F0__FLD LPDDR4__DENALI_PI_212__PI_WDQLVL_EN_F0
  3225. #define LPDDR4__DENALI_PI_212__PI_NTP_TRAIN_EN_F0_MASK 0x00030000U
  3226. #define LPDDR4__DENALI_PI_212__PI_NTP_TRAIN_EN_F0_SHIFT 16U
  3227. #define LPDDR4__DENALI_PI_212__PI_NTP_TRAIN_EN_F0_WIDTH 2U
  3228. #define LPDDR4__PI_NTP_TRAIN_EN_F0__REG DENALI_PI_212
  3229. #define LPDDR4__PI_NTP_TRAIN_EN_F0__FLD LPDDR4__DENALI_PI_212__PI_NTP_TRAIN_EN_F0
  3230. #define LPDDR4__DENALI_PI_213_READ_MASK 0x03FF03FFU
  3231. #define LPDDR4__DENALI_PI_213_WRITE_MASK 0x03FF03FFU
  3232. #define LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_WR_F1_MASK 0x000003FFU
  3233. #define LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_WR_F1_SHIFT 0U
  3234. #define LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_WR_F1_WIDTH 10U
  3235. #define LPDDR4__PI_TDFI_WDQLVL_WR_F1__REG DENALI_PI_213
  3236. #define LPDDR4__PI_TDFI_WDQLVL_WR_F1__FLD LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_WR_F1
  3237. #define LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_RW_F1_MASK 0x03FF0000U
  3238. #define LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_RW_F1_SHIFT 16U
  3239. #define LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_RW_F1_WIDTH 10U
  3240. #define LPDDR4__PI_TDFI_WDQLVL_RW_F1__REG DENALI_PI_213
  3241. #define LPDDR4__PI_TDFI_WDQLVL_RW_F1__FLD LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_RW_F1
  3242. #define LPDDR4__DENALI_PI_214_READ_MASK 0x030F7F7FU
  3243. #define LPDDR4__DENALI_PI_214_WRITE_MASK 0x030F7F7FU
  3244. #define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_START_POINT_F1_MASK 0x0000007FU
  3245. #define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_START_POINT_F1_SHIFT 0U
  3246. #define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_START_POINT_F1_WIDTH 7U
  3247. #define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F1__REG DENALI_PI_214
  3248. #define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F1__FLD LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_START_POINT_F1
  3249. #define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1_MASK 0x00007F00U
  3250. #define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1_SHIFT 8U
  3251. #define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1_WIDTH 7U
  3252. #define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1__REG DENALI_PI_214
  3253. #define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1__FLD LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1
  3254. #define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_DELTA_F1_MASK 0x000F0000U
  3255. #define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_DELTA_F1_SHIFT 16U
  3256. #define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_DELTA_F1_WIDTH 4U
  3257. #define LPDDR4__PI_WDQLVL_VREF_DELTA_F1__REG DENALI_PI_214
  3258. #define LPDDR4__PI_WDQLVL_VREF_DELTA_F1__FLD LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_DELTA_F1
  3259. #define LPDDR4__DENALI_PI_214__PI_WDQLVL_EN_F1_MASK 0x03000000U
  3260. #define LPDDR4__DENALI_PI_214__PI_WDQLVL_EN_F1_SHIFT 24U
  3261. #define LPDDR4__DENALI_PI_214__PI_WDQLVL_EN_F1_WIDTH 2U
  3262. #define LPDDR4__PI_WDQLVL_EN_F1__REG DENALI_PI_214
  3263. #define LPDDR4__PI_WDQLVL_EN_F1__FLD LPDDR4__DENALI_PI_214__PI_WDQLVL_EN_F1
  3264. #define LPDDR4__DENALI_PI_215_READ_MASK 0x0003FF03U
  3265. #define LPDDR4__DENALI_PI_215_WRITE_MASK 0x0003FF03U
  3266. #define LPDDR4__DENALI_PI_215__PI_NTP_TRAIN_EN_F1_MASK 0x00000003U
  3267. #define LPDDR4__DENALI_PI_215__PI_NTP_TRAIN_EN_F1_SHIFT 0U
  3268. #define LPDDR4__DENALI_PI_215__PI_NTP_TRAIN_EN_F1_WIDTH 2U
  3269. #define LPDDR4__PI_NTP_TRAIN_EN_F1__REG DENALI_PI_215
  3270. #define LPDDR4__PI_NTP_TRAIN_EN_F1__FLD LPDDR4__DENALI_PI_215__PI_NTP_TRAIN_EN_F1
  3271. #define LPDDR4__DENALI_PI_215__PI_TDFI_WDQLVL_WR_F2_MASK 0x0003FF00U
  3272. #define LPDDR4__DENALI_PI_215__PI_TDFI_WDQLVL_WR_F2_SHIFT 8U
  3273. #define LPDDR4__DENALI_PI_215__PI_TDFI_WDQLVL_WR_F2_WIDTH 10U
  3274. #define LPDDR4__PI_TDFI_WDQLVL_WR_F2__REG DENALI_PI_215
  3275. #define LPDDR4__PI_TDFI_WDQLVL_WR_F2__FLD LPDDR4__DENALI_PI_215__PI_TDFI_WDQLVL_WR_F2
  3276. #define LPDDR4__DENALI_PI_216_READ_MASK 0x7F7F03FFU
  3277. #define LPDDR4__DENALI_PI_216_WRITE_MASK 0x7F7F03FFU
  3278. #define LPDDR4__DENALI_PI_216__PI_TDFI_WDQLVL_RW_F2_MASK 0x000003FFU
  3279. #define LPDDR4__DENALI_PI_216__PI_TDFI_WDQLVL_RW_F2_SHIFT 0U
  3280. #define LPDDR4__DENALI_PI_216__PI_TDFI_WDQLVL_RW_F2_WIDTH 10U
  3281. #define LPDDR4__PI_TDFI_WDQLVL_RW_F2__REG DENALI_PI_216
  3282. #define LPDDR4__PI_TDFI_WDQLVL_RW_F2__FLD LPDDR4__DENALI_PI_216__PI_TDFI_WDQLVL_RW_F2
  3283. #define LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_START_POINT_F2_MASK 0x007F0000U
  3284. #define LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_START_POINT_F2_SHIFT 16U
  3285. #define LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_START_POINT_F2_WIDTH 7U
  3286. #define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F2__REG DENALI_PI_216
  3287. #define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F2__FLD LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_START_POINT_F2
  3288. #define LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2_MASK 0x7F000000U
  3289. #define LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2_SHIFT 24U
  3290. #define LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2_WIDTH 7U
  3291. #define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2__REG DENALI_PI_216
  3292. #define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2__FLD LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2
  3293. #define LPDDR4__DENALI_PI_217_READ_MASK 0xFF03030FU
  3294. #define LPDDR4__DENALI_PI_217_WRITE_MASK 0xFF03030FU
  3295. #define LPDDR4__DENALI_PI_217__PI_WDQLVL_VREF_DELTA_F2_MASK 0x0000000FU
  3296. #define LPDDR4__DENALI_PI_217__PI_WDQLVL_VREF_DELTA_F2_SHIFT 0U
  3297. #define LPDDR4__DENALI_PI_217__PI_WDQLVL_VREF_DELTA_F2_WIDTH 4U
  3298. #define LPDDR4__PI_WDQLVL_VREF_DELTA_F2__REG DENALI_PI_217
  3299. #define LPDDR4__PI_WDQLVL_VREF_DELTA_F2__FLD LPDDR4__DENALI_PI_217__PI_WDQLVL_VREF_DELTA_F2
  3300. #define LPDDR4__DENALI_PI_217__PI_WDQLVL_EN_F2_MASK 0x00000300U
  3301. #define LPDDR4__DENALI_PI_217__PI_WDQLVL_EN_F2_SHIFT 8U
  3302. #define LPDDR4__DENALI_PI_217__PI_WDQLVL_EN_F2_WIDTH 2U
  3303. #define LPDDR4__PI_WDQLVL_EN_F2__REG DENALI_PI_217
  3304. #define LPDDR4__PI_WDQLVL_EN_F2__FLD LPDDR4__DENALI_PI_217__PI_WDQLVL_EN_F2
  3305. #define LPDDR4__DENALI_PI_217__PI_NTP_TRAIN_EN_F2_MASK 0x00030000U
  3306. #define LPDDR4__DENALI_PI_217__PI_NTP_TRAIN_EN_F2_SHIFT 16U
  3307. #define LPDDR4__DENALI_PI_217__PI_NTP_TRAIN_EN_F2_WIDTH 2U
  3308. #define LPDDR4__PI_NTP_TRAIN_EN_F2__REG DENALI_PI_217
  3309. #define LPDDR4__PI_NTP_TRAIN_EN_F2__FLD LPDDR4__DENALI_PI_217__PI_NTP_TRAIN_EN_F2
  3310. #define LPDDR4__DENALI_PI_217__PI_TRTP_F0_MASK 0xFF000000U
  3311. #define LPDDR4__DENALI_PI_217__PI_TRTP_F0_SHIFT 24U
  3312. #define LPDDR4__DENALI_PI_217__PI_TRTP_F0_WIDTH 8U
  3313. #define LPDDR4__PI_TRTP_F0__REG DENALI_PI_217
  3314. #define LPDDR4__PI_TRTP_F0__FLD LPDDR4__DENALI_PI_217__PI_TRTP_F0
  3315. #define LPDDR4__DENALI_PI_218_READ_MASK 0xFF3FFFFFU
  3316. #define LPDDR4__DENALI_PI_218_WRITE_MASK 0xFF3FFFFFU
  3317. #define LPDDR4__DENALI_PI_218__PI_TRP_F0_MASK 0x000000FFU
  3318. #define LPDDR4__DENALI_PI_218__PI_TRP_F0_SHIFT 0U
  3319. #define LPDDR4__DENALI_PI_218__PI_TRP_F0_WIDTH 8U
  3320. #define LPDDR4__PI_TRP_F0__REG DENALI_PI_218
  3321. #define LPDDR4__PI_TRP_F0__FLD LPDDR4__DENALI_PI_218__PI_TRP_F0
  3322. #define LPDDR4__DENALI_PI_218__PI_TRCD_F0_MASK 0x0000FF00U
  3323. #define LPDDR4__DENALI_PI_218__PI_TRCD_F0_SHIFT 8U
  3324. #define LPDDR4__DENALI_PI_218__PI_TRCD_F0_WIDTH 8U
  3325. #define LPDDR4__PI_TRCD_F0__REG DENALI_PI_218
  3326. #define LPDDR4__PI_TRCD_F0__FLD LPDDR4__DENALI_PI_218__PI_TRCD_F0
  3327. #define LPDDR4__DENALI_PI_218__PI_TWTR_F0_MASK 0x003F0000U
  3328. #define LPDDR4__DENALI_PI_218__PI_TWTR_F0_SHIFT 16U
  3329. #define LPDDR4__DENALI_PI_218__PI_TWTR_F0_WIDTH 6U
  3330. #define LPDDR4__PI_TWTR_F0__REG DENALI_PI_218
  3331. #define LPDDR4__PI_TWTR_F0__FLD LPDDR4__DENALI_PI_218__PI_TWTR_F0
  3332. #define LPDDR4__DENALI_PI_218__PI_TWR_F0_MASK 0xFF000000U
  3333. #define LPDDR4__DENALI_PI_218__PI_TWR_F0_SHIFT 24U
  3334. #define LPDDR4__DENALI_PI_218__PI_TWR_F0_WIDTH 8U
  3335. #define LPDDR4__PI_TWR_F0__REG DENALI_PI_218
  3336. #define LPDDR4__PI_TWR_F0__FLD LPDDR4__DENALI_PI_218__PI_TWR_F0
  3337. #define LPDDR4__DENALI_PI_219_READ_MASK 0xFF01FFFFU
  3338. #define LPDDR4__DENALI_PI_219_WRITE_MASK 0xFF01FFFFU
  3339. #define LPDDR4__DENALI_PI_219__PI_TRAS_MAX_F0_MASK 0x0001FFFFU
  3340. #define LPDDR4__DENALI_PI_219__PI_TRAS_MAX_F0_SHIFT 0U
  3341. #define LPDDR4__DENALI_PI_219__PI_TRAS_MAX_F0_WIDTH 17U
  3342. #define LPDDR4__PI_TRAS_MAX_F0__REG DENALI_PI_219
  3343. #define LPDDR4__PI_TRAS_MAX_F0__FLD LPDDR4__DENALI_PI_219__PI_TRAS_MAX_F0
  3344. #define LPDDR4__DENALI_PI_219__PI_TRAS_MIN_F0_MASK 0xFF000000U
  3345. #define LPDDR4__DENALI_PI_219__PI_TRAS_MIN_F0_SHIFT 24U
  3346. #define LPDDR4__DENALI_PI_219__PI_TRAS_MIN_F0_WIDTH 8U
  3347. #define LPDDR4__PI_TRAS_MIN_F0__REG DENALI_PI_219
  3348. #define LPDDR4__PI_TRAS_MIN_F0__FLD LPDDR4__DENALI_PI_219__PI_TRAS_MIN_F0
  3349. #define LPDDR4__DENALI_PI_220_READ_MASK 0xFFFF3F0FU
  3350. #define LPDDR4__DENALI_PI_220_WRITE_MASK 0xFFFF3F0FU
  3351. #define LPDDR4__DENALI_PI_220__PI_TDQSCK_MAX_F0_MASK 0x0000000FU
  3352. #define LPDDR4__DENALI_PI_220__PI_TDQSCK_MAX_F0_SHIFT 0U
  3353. #define LPDDR4__DENALI_PI_220__PI_TDQSCK_MAX_F0_WIDTH 4U
  3354. #define LPDDR4__PI_TDQSCK_MAX_F0__REG DENALI_PI_220
  3355. #define LPDDR4__PI_TDQSCK_MAX_F0__FLD LPDDR4__DENALI_PI_220__PI_TDQSCK_MAX_F0
  3356. #define LPDDR4__DENALI_PI_220__PI_TCCDMW_F0_MASK 0x00003F00U
  3357. #define LPDDR4__DENALI_PI_220__PI_TCCDMW_F0_SHIFT 8U
  3358. #define LPDDR4__DENALI_PI_220__PI_TCCDMW_F0_WIDTH 6U
  3359. #define LPDDR4__PI_TCCDMW_F0__REG DENALI_PI_220
  3360. #define LPDDR4__PI_TCCDMW_F0__FLD LPDDR4__DENALI_PI_220__PI_TCCDMW_F0
  3361. #define LPDDR4__DENALI_PI_220__PI_TSR_F0_MASK 0x00FF0000U
  3362. #define LPDDR4__DENALI_PI_220__PI_TSR_F0_SHIFT 16U
  3363. #define LPDDR4__DENALI_PI_220__PI_TSR_F0_WIDTH 8U
  3364. #define LPDDR4__PI_TSR_F0__REG DENALI_PI_220
  3365. #define LPDDR4__PI_TSR_F0__FLD LPDDR4__DENALI_PI_220__PI_TSR_F0
  3366. #define LPDDR4__DENALI_PI_220__PI_TMRD_F0_MASK 0xFF000000U
  3367. #define LPDDR4__DENALI_PI_220__PI_TMRD_F0_SHIFT 24U
  3368. #define LPDDR4__DENALI_PI_220__PI_TMRD_F0_WIDTH 8U
  3369. #define LPDDR4__PI_TMRD_F0__REG DENALI_PI_220
  3370. #define LPDDR4__PI_TMRD_F0__FLD LPDDR4__DENALI_PI_220__PI_TMRD_F0
  3371. #define LPDDR4__DENALI_PI_221_READ_MASK 0xFFFFFFFFU
  3372. #define LPDDR4__DENALI_PI_221_WRITE_MASK 0xFFFFFFFFU
  3373. #define LPDDR4__DENALI_PI_221__PI_TMRW_F0_MASK 0x000000FFU
  3374. #define LPDDR4__DENALI_PI_221__PI_TMRW_F0_SHIFT 0U
  3375. #define LPDDR4__DENALI_PI_221__PI_TMRW_F0_WIDTH 8U
  3376. #define LPDDR4__PI_TMRW_F0__REG DENALI_PI_221
  3377. #define LPDDR4__PI_TMRW_F0__FLD LPDDR4__DENALI_PI_221__PI_TMRW_F0
  3378. #define LPDDR4__DENALI_PI_221__PI_TRTP_F1_MASK 0x0000FF00U
  3379. #define LPDDR4__DENALI_PI_221__PI_TRTP_F1_SHIFT 8U
  3380. #define LPDDR4__DENALI_PI_221__PI_TRTP_F1_WIDTH 8U
  3381. #define LPDDR4__PI_TRTP_F1__REG DENALI_PI_221
  3382. #define LPDDR4__PI_TRTP_F1__FLD LPDDR4__DENALI_PI_221__PI_TRTP_F1
  3383. #define LPDDR4__DENALI_PI_221__PI_TRP_F1_MASK 0x00FF0000U
  3384. #define LPDDR4__DENALI_PI_221__PI_TRP_F1_SHIFT 16U
  3385. #define LPDDR4__DENALI_PI_221__PI_TRP_F1_WIDTH 8U
  3386. #define LPDDR4__PI_TRP_F1__REG DENALI_PI_221
  3387. #define LPDDR4__PI_TRP_F1__FLD LPDDR4__DENALI_PI_221__PI_TRP_F1
  3388. #define LPDDR4__DENALI_PI_221__PI_TRCD_F1_MASK 0xFF000000U
  3389. #define LPDDR4__DENALI_PI_221__PI_TRCD_F1_SHIFT 24U
  3390. #define LPDDR4__DENALI_PI_221__PI_TRCD_F1_WIDTH 8U
  3391. #define LPDDR4__PI_TRCD_F1__REG DENALI_PI_221
  3392. #define LPDDR4__PI_TRCD_F1__FLD LPDDR4__DENALI_PI_221__PI_TRCD_F1
  3393. #define LPDDR4__DENALI_PI_222_READ_MASK 0x0000FF3FU
  3394. #define LPDDR4__DENALI_PI_222_WRITE_MASK 0x0000FF3FU
  3395. #define LPDDR4__DENALI_PI_222__PI_TWTR_F1_MASK 0x0000003FU
  3396. #define LPDDR4__DENALI_PI_222__PI_TWTR_F1_SHIFT 0U
  3397. #define LPDDR4__DENALI_PI_222__PI_TWTR_F1_WIDTH 6U
  3398. #define LPDDR4__PI_TWTR_F1__REG DENALI_PI_222
  3399. #define LPDDR4__PI_TWTR_F1__FLD LPDDR4__DENALI_PI_222__PI_TWTR_F1
  3400. #define LPDDR4__DENALI_PI_222__PI_TWR_F1_MASK 0x0000FF00U
  3401. #define LPDDR4__DENALI_PI_222__PI_TWR_F1_SHIFT 8U
  3402. #define LPDDR4__DENALI_PI_222__PI_TWR_F1_WIDTH 8U
  3403. #define LPDDR4__PI_TWR_F1__REG DENALI_PI_222
  3404. #define LPDDR4__PI_TWR_F1__FLD LPDDR4__DENALI_PI_222__PI_TWR_F1
  3405. #define LPDDR4__DENALI_PI_223_READ_MASK 0xFF01FFFFU
  3406. #define LPDDR4__DENALI_PI_223_WRITE_MASK 0xFF01FFFFU
  3407. #define LPDDR4__DENALI_PI_223__PI_TRAS_MAX_F1_MASK 0x0001FFFFU
  3408. #define LPDDR4__DENALI_PI_223__PI_TRAS_MAX_F1_SHIFT 0U
  3409. #define LPDDR4__DENALI_PI_223__PI_TRAS_MAX_F1_WIDTH 17U
  3410. #define LPDDR4__PI_TRAS_MAX_F1__REG DENALI_PI_223
  3411. #define LPDDR4__PI_TRAS_MAX_F1__FLD LPDDR4__DENALI_PI_223__PI_TRAS_MAX_F1
  3412. #define LPDDR4__DENALI_PI_223__PI_TRAS_MIN_F1_MASK 0xFF000000U
  3413. #define LPDDR4__DENALI_PI_223__PI_TRAS_MIN_F1_SHIFT 24U
  3414. #define LPDDR4__DENALI_PI_223__PI_TRAS_MIN_F1_WIDTH 8U
  3415. #define LPDDR4__PI_TRAS_MIN_F1__REG DENALI_PI_223
  3416. #define LPDDR4__PI_TRAS_MIN_F1__FLD LPDDR4__DENALI_PI_223__PI_TRAS_MIN_F1
  3417. #define LPDDR4__DENALI_PI_224_READ_MASK 0xFFFF3F0FU
  3418. #define LPDDR4__DENALI_PI_224_WRITE_MASK 0xFFFF3F0FU
  3419. #define LPDDR4__DENALI_PI_224__PI_TDQSCK_MAX_F1_MASK 0x0000000FU
  3420. #define LPDDR4__DENALI_PI_224__PI_TDQSCK_MAX_F1_SHIFT 0U
  3421. #define LPDDR4__DENALI_PI_224__PI_TDQSCK_MAX_F1_WIDTH 4U
  3422. #define LPDDR4__PI_TDQSCK_MAX_F1__REG DENALI_PI_224
  3423. #define LPDDR4__PI_TDQSCK_MAX_F1__FLD LPDDR4__DENALI_PI_224__PI_TDQSCK_MAX_F1
  3424. #define LPDDR4__DENALI_PI_224__PI_TCCDMW_F1_MASK 0x00003F00U
  3425. #define LPDDR4__DENALI_PI_224__PI_TCCDMW_F1_SHIFT 8U
  3426. #define LPDDR4__DENALI_PI_224__PI_TCCDMW_F1_WIDTH 6U
  3427. #define LPDDR4__PI_TCCDMW_F1__REG DENALI_PI_224
  3428. #define LPDDR4__PI_TCCDMW_F1__FLD LPDDR4__DENALI_PI_224__PI_TCCDMW_F1
  3429. #define LPDDR4__DENALI_PI_224__PI_TSR_F1_MASK 0x00FF0000U
  3430. #define LPDDR4__DENALI_PI_224__PI_TSR_F1_SHIFT 16U
  3431. #define LPDDR4__DENALI_PI_224__PI_TSR_F1_WIDTH 8U
  3432. #define LPDDR4__PI_TSR_F1__REG DENALI_PI_224
  3433. #define LPDDR4__PI_TSR_F1__FLD LPDDR4__DENALI_PI_224__PI_TSR_F1
  3434. #define LPDDR4__DENALI_PI_224__PI_TMRD_F1_MASK 0xFF000000U
  3435. #define LPDDR4__DENALI_PI_224__PI_TMRD_F1_SHIFT 24U
  3436. #define LPDDR4__DENALI_PI_224__PI_TMRD_F1_WIDTH 8U
  3437. #define LPDDR4__PI_TMRD_F1__REG DENALI_PI_224
  3438. #define LPDDR4__PI_TMRD_F1__FLD LPDDR4__DENALI_PI_224__PI_TMRD_F1
  3439. #define LPDDR4__DENALI_PI_225_READ_MASK 0xFFFFFFFFU
  3440. #define LPDDR4__DENALI_PI_225_WRITE_MASK 0xFFFFFFFFU
  3441. #define LPDDR4__DENALI_PI_225__PI_TMRW_F1_MASK 0x000000FFU
  3442. #define LPDDR4__DENALI_PI_225__PI_TMRW_F1_SHIFT 0U
  3443. #define LPDDR4__DENALI_PI_225__PI_TMRW_F1_WIDTH 8U
  3444. #define LPDDR4__PI_TMRW_F1__REG DENALI_PI_225
  3445. #define LPDDR4__PI_TMRW_F1__FLD LPDDR4__DENALI_PI_225__PI_TMRW_F1
  3446. #define LPDDR4__DENALI_PI_225__PI_TRTP_F2_MASK 0x0000FF00U
  3447. #define LPDDR4__DENALI_PI_225__PI_TRTP_F2_SHIFT 8U
  3448. #define LPDDR4__DENALI_PI_225__PI_TRTP_F2_WIDTH 8U
  3449. #define LPDDR4__PI_TRTP_F2__REG DENALI_PI_225
  3450. #define LPDDR4__PI_TRTP_F2__FLD LPDDR4__DENALI_PI_225__PI_TRTP_F2
  3451. #define LPDDR4__DENALI_PI_225__PI_TRP_F2_MASK 0x00FF0000U
  3452. #define LPDDR4__DENALI_PI_225__PI_TRP_F2_SHIFT 16U
  3453. #define LPDDR4__DENALI_PI_225__PI_TRP_F2_WIDTH 8U
  3454. #define LPDDR4__PI_TRP_F2__REG DENALI_PI_225
  3455. #define LPDDR4__PI_TRP_F2__FLD LPDDR4__DENALI_PI_225__PI_TRP_F2
  3456. #define LPDDR4__DENALI_PI_225__PI_TRCD_F2_MASK 0xFF000000U
  3457. #define LPDDR4__DENALI_PI_225__PI_TRCD_F2_SHIFT 24U
  3458. #define LPDDR4__DENALI_PI_225__PI_TRCD_F2_WIDTH 8U
  3459. #define LPDDR4__PI_TRCD_F2__REG DENALI_PI_225
  3460. #define LPDDR4__PI_TRCD_F2__FLD LPDDR4__DENALI_PI_225__PI_TRCD_F2
  3461. #define LPDDR4__DENALI_PI_226_READ_MASK 0x0000FF3FU
  3462. #define LPDDR4__DENALI_PI_226_WRITE_MASK 0x0000FF3FU
  3463. #define LPDDR4__DENALI_PI_226__PI_TWTR_F2_MASK 0x0000003FU
  3464. #define LPDDR4__DENALI_PI_226__PI_TWTR_F2_SHIFT 0U
  3465. #define LPDDR4__DENALI_PI_226__PI_TWTR_F2_WIDTH 6U
  3466. #define LPDDR4__PI_TWTR_F2__REG DENALI_PI_226
  3467. #define LPDDR4__PI_TWTR_F2__FLD LPDDR4__DENALI_PI_226__PI_TWTR_F2
  3468. #define LPDDR4__DENALI_PI_226__PI_TWR_F2_MASK 0x0000FF00U
  3469. #define LPDDR4__DENALI_PI_226__PI_TWR_F2_SHIFT 8U
  3470. #define LPDDR4__DENALI_PI_226__PI_TWR_F2_WIDTH 8U
  3471. #define LPDDR4__PI_TWR_F2__REG DENALI_PI_226
  3472. #define LPDDR4__PI_TWR_F2__FLD LPDDR4__DENALI_PI_226__PI_TWR_F2
  3473. #define LPDDR4__DENALI_PI_227_READ_MASK 0xFF01FFFFU
  3474. #define LPDDR4__DENALI_PI_227_WRITE_MASK 0xFF01FFFFU
  3475. #define LPDDR4__DENALI_PI_227__PI_TRAS_MAX_F2_MASK 0x0001FFFFU
  3476. #define LPDDR4__DENALI_PI_227__PI_TRAS_MAX_F2_SHIFT 0U
  3477. #define LPDDR4__DENALI_PI_227__PI_TRAS_MAX_F2_WIDTH 17U
  3478. #define LPDDR4__PI_TRAS_MAX_F2__REG DENALI_PI_227
  3479. #define LPDDR4__PI_TRAS_MAX_F2__FLD LPDDR4__DENALI_PI_227__PI_TRAS_MAX_F2
  3480. #define LPDDR4__DENALI_PI_227__PI_TRAS_MIN_F2_MASK 0xFF000000U
  3481. #define LPDDR4__DENALI_PI_227__PI_TRAS_MIN_F2_SHIFT 24U
  3482. #define LPDDR4__DENALI_PI_227__PI_TRAS_MIN_F2_WIDTH 8U
  3483. #define LPDDR4__PI_TRAS_MIN_F2__REG DENALI_PI_227
  3484. #define LPDDR4__PI_TRAS_MIN_F2__FLD LPDDR4__DENALI_PI_227__PI_TRAS_MIN_F2
  3485. #define LPDDR4__DENALI_PI_228_READ_MASK 0xFFFF3F0FU
  3486. #define LPDDR4__DENALI_PI_228_WRITE_MASK 0xFFFF3F0FU
  3487. #define LPDDR4__DENALI_PI_228__PI_TDQSCK_MAX_F2_MASK 0x0000000FU
  3488. #define LPDDR4__DENALI_PI_228__PI_TDQSCK_MAX_F2_SHIFT 0U
  3489. #define LPDDR4__DENALI_PI_228__PI_TDQSCK_MAX_F2_WIDTH 4U
  3490. #define LPDDR4__PI_TDQSCK_MAX_F2__REG DENALI_PI_228
  3491. #define LPDDR4__PI_TDQSCK_MAX_F2__FLD LPDDR4__DENALI_PI_228__PI_TDQSCK_MAX_F2
  3492. #define LPDDR4__DENALI_PI_228__PI_TCCDMW_F2_MASK 0x00003F00U
  3493. #define LPDDR4__DENALI_PI_228__PI_TCCDMW_F2_SHIFT 8U
  3494. #define LPDDR4__DENALI_PI_228__PI_TCCDMW_F2_WIDTH 6U
  3495. #define LPDDR4__PI_TCCDMW_F2__REG DENALI_PI_228
  3496. #define LPDDR4__PI_TCCDMW_F2__FLD LPDDR4__DENALI_PI_228__PI_TCCDMW_F2
  3497. #define LPDDR4__DENALI_PI_228__PI_TSR_F2_MASK 0x00FF0000U
  3498. #define LPDDR4__DENALI_PI_228__PI_TSR_F2_SHIFT 16U
  3499. #define LPDDR4__DENALI_PI_228__PI_TSR_F2_WIDTH 8U
  3500. #define LPDDR4__PI_TSR_F2__REG DENALI_PI_228
  3501. #define LPDDR4__PI_TSR_F2__FLD LPDDR4__DENALI_PI_228__PI_TSR_F2
  3502. #define LPDDR4__DENALI_PI_228__PI_TMRD_F2_MASK 0xFF000000U
  3503. #define LPDDR4__DENALI_PI_228__PI_TMRD_F2_SHIFT 24U
  3504. #define LPDDR4__DENALI_PI_228__PI_TMRD_F2_WIDTH 8U
  3505. #define LPDDR4__PI_TMRD_F2__REG DENALI_PI_228
  3506. #define LPDDR4__PI_TMRD_F2__FLD LPDDR4__DENALI_PI_228__PI_TMRD_F2
  3507. #define LPDDR4__DENALI_PI_229_READ_MASK 0x1FFFFFFFU
  3508. #define LPDDR4__DENALI_PI_229_WRITE_MASK 0x1FFFFFFFU
  3509. #define LPDDR4__DENALI_PI_229__PI_TMRW_F2_MASK 0x000000FFU
  3510. #define LPDDR4__DENALI_PI_229__PI_TMRW_F2_SHIFT 0U
  3511. #define LPDDR4__DENALI_PI_229__PI_TMRW_F2_WIDTH 8U
  3512. #define LPDDR4__PI_TMRW_F2__REG DENALI_PI_229
  3513. #define LPDDR4__PI_TMRW_F2__FLD LPDDR4__DENALI_PI_229__PI_TMRW_F2
  3514. #define LPDDR4__DENALI_PI_229__PI_TDFI_CTRLUPD_MAX_F0_MASK 0x1FFFFF00U
  3515. #define LPDDR4__DENALI_PI_229__PI_TDFI_CTRLUPD_MAX_F0_SHIFT 8U
  3516. #define LPDDR4__DENALI_PI_229__PI_TDFI_CTRLUPD_MAX_F0_WIDTH 21U
  3517. #define LPDDR4__PI_TDFI_CTRLUPD_MAX_F0__REG DENALI_PI_229
  3518. #define LPDDR4__PI_TDFI_CTRLUPD_MAX_F0__FLD LPDDR4__DENALI_PI_229__PI_TDFI_CTRLUPD_MAX_F0
  3519. #define LPDDR4__DENALI_PI_230_READ_MASK 0xFFFFFFFFU
  3520. #define LPDDR4__DENALI_PI_230_WRITE_MASK 0xFFFFFFFFU
  3521. #define LPDDR4__DENALI_PI_230__PI_TDFI_CTRLUPD_INTERVAL_F0_MASK 0xFFFFFFFFU
  3522. #define LPDDR4__DENALI_PI_230__PI_TDFI_CTRLUPD_INTERVAL_F0_SHIFT 0U
  3523. #define LPDDR4__DENALI_PI_230__PI_TDFI_CTRLUPD_INTERVAL_F0_WIDTH 32U
  3524. #define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F0__REG DENALI_PI_230
  3525. #define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F0__FLD LPDDR4__DENALI_PI_230__PI_TDFI_CTRLUPD_INTERVAL_F0
  3526. #define LPDDR4__DENALI_PI_231_READ_MASK 0x001FFFFFU
  3527. #define LPDDR4__DENALI_PI_231_WRITE_MASK 0x001FFFFFU
  3528. #define LPDDR4__DENALI_PI_231__PI_TDFI_CTRLUPD_MAX_F1_MASK 0x001FFFFFU
  3529. #define LPDDR4__DENALI_PI_231__PI_TDFI_CTRLUPD_MAX_F1_SHIFT 0U
  3530. #define LPDDR4__DENALI_PI_231__PI_TDFI_CTRLUPD_MAX_F1_WIDTH 21U
  3531. #define LPDDR4__PI_TDFI_CTRLUPD_MAX_F1__REG DENALI_PI_231
  3532. #define LPDDR4__PI_TDFI_CTRLUPD_MAX_F1__FLD LPDDR4__DENALI_PI_231__PI_TDFI_CTRLUPD_MAX_F1
  3533. #define LPDDR4__DENALI_PI_232_READ_MASK 0xFFFFFFFFU
  3534. #define LPDDR4__DENALI_PI_232_WRITE_MASK 0xFFFFFFFFU
  3535. #define LPDDR4__DENALI_PI_232__PI_TDFI_CTRLUPD_INTERVAL_F1_MASK 0xFFFFFFFFU
  3536. #define LPDDR4__DENALI_PI_232__PI_TDFI_CTRLUPD_INTERVAL_F1_SHIFT 0U
  3537. #define LPDDR4__DENALI_PI_232__PI_TDFI_CTRLUPD_INTERVAL_F1_WIDTH 32U
  3538. #define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F1__REG DENALI_PI_232
  3539. #define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F1__FLD LPDDR4__DENALI_PI_232__PI_TDFI_CTRLUPD_INTERVAL_F1
  3540. #define LPDDR4__DENALI_PI_233_READ_MASK 0x001FFFFFU
  3541. #define LPDDR4__DENALI_PI_233_WRITE_MASK 0x001FFFFFU
  3542. #define LPDDR4__DENALI_PI_233__PI_TDFI_CTRLUPD_MAX_F2_MASK 0x001FFFFFU
  3543. #define LPDDR4__DENALI_PI_233__PI_TDFI_CTRLUPD_MAX_F2_SHIFT 0U
  3544. #define LPDDR4__DENALI_PI_233__PI_TDFI_CTRLUPD_MAX_F2_WIDTH 21U
  3545. #define LPDDR4__PI_TDFI_CTRLUPD_MAX_F2__REG DENALI_PI_233
  3546. #define LPDDR4__PI_TDFI_CTRLUPD_MAX_F2__FLD LPDDR4__DENALI_PI_233__PI_TDFI_CTRLUPD_MAX_F2
  3547. #define LPDDR4__DENALI_PI_234_READ_MASK 0xFFFFFFFFU
  3548. #define LPDDR4__DENALI_PI_234_WRITE_MASK 0xFFFFFFFFU
  3549. #define LPDDR4__DENALI_PI_234__PI_TDFI_CTRLUPD_INTERVAL_F2_MASK 0xFFFFFFFFU
  3550. #define LPDDR4__DENALI_PI_234__PI_TDFI_CTRLUPD_INTERVAL_F2_SHIFT 0U
  3551. #define LPDDR4__DENALI_PI_234__PI_TDFI_CTRLUPD_INTERVAL_F2_WIDTH 32U
  3552. #define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F2__REG DENALI_PI_234
  3553. #define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F2__FLD LPDDR4__DENALI_PI_234__PI_TDFI_CTRLUPD_INTERVAL_F2
  3554. #define LPDDR4__DENALI_PI_235_READ_MASK 0xFFFFFFFFU
  3555. #define LPDDR4__DENALI_PI_235_WRITE_MASK 0xFFFFFFFFU
  3556. #define LPDDR4__DENALI_PI_235__PI_TXSR_F0_MASK 0x0000FFFFU
  3557. #define LPDDR4__DENALI_PI_235__PI_TXSR_F0_SHIFT 0U
  3558. #define LPDDR4__DENALI_PI_235__PI_TXSR_F0_WIDTH 16U
  3559. #define LPDDR4__PI_TXSR_F0__REG DENALI_PI_235
  3560. #define LPDDR4__PI_TXSR_F0__FLD LPDDR4__DENALI_PI_235__PI_TXSR_F0
  3561. #define LPDDR4__DENALI_PI_235__PI_TXSR_F1_MASK 0xFFFF0000U
  3562. #define LPDDR4__DENALI_PI_235__PI_TXSR_F1_SHIFT 16U
  3563. #define LPDDR4__DENALI_PI_235__PI_TXSR_F1_WIDTH 16U
  3564. #define LPDDR4__PI_TXSR_F1__REG DENALI_PI_235
  3565. #define LPDDR4__PI_TXSR_F1__FLD LPDDR4__DENALI_PI_235__PI_TXSR_F1
  3566. #define LPDDR4__DENALI_PI_236_READ_MASK 0x3F3FFFFFU
  3567. #define LPDDR4__DENALI_PI_236_WRITE_MASK 0x3F3FFFFFU
  3568. #define LPDDR4__DENALI_PI_236__PI_TXSR_F2_MASK 0x0000FFFFU
  3569. #define LPDDR4__DENALI_PI_236__PI_TXSR_F2_SHIFT 0U
  3570. #define LPDDR4__DENALI_PI_236__PI_TXSR_F2_WIDTH 16U
  3571. #define LPDDR4__PI_TXSR_F2__REG DENALI_PI_236
  3572. #define LPDDR4__PI_TXSR_F2__FLD LPDDR4__DENALI_PI_236__PI_TXSR_F2
  3573. #define LPDDR4__DENALI_PI_236__PI_TEXCKE_F0_MASK 0x003F0000U
  3574. #define LPDDR4__DENALI_PI_236__PI_TEXCKE_F0_SHIFT 16U
  3575. #define LPDDR4__DENALI_PI_236__PI_TEXCKE_F0_WIDTH 6U
  3576. #define LPDDR4__PI_TEXCKE_F0__REG DENALI_PI_236
  3577. #define LPDDR4__PI_TEXCKE_F0__FLD LPDDR4__DENALI_PI_236__PI_TEXCKE_F0
  3578. #define LPDDR4__DENALI_PI_236__PI_TEXCKE_F1_MASK 0x3F000000U
  3579. #define LPDDR4__DENALI_PI_236__PI_TEXCKE_F1_SHIFT 24U
  3580. #define LPDDR4__DENALI_PI_236__PI_TEXCKE_F1_WIDTH 6U
  3581. #define LPDDR4__PI_TEXCKE_F1__REG DENALI_PI_236
  3582. #define LPDDR4__PI_TEXCKE_F1__FLD LPDDR4__DENALI_PI_236__PI_TEXCKE_F1
  3583. #define LPDDR4__DENALI_PI_237_READ_MASK 0xFFFFFF3FU
  3584. #define LPDDR4__DENALI_PI_237_WRITE_MASK 0xFFFFFF3FU
  3585. #define LPDDR4__DENALI_PI_237__PI_TEXCKE_F2_MASK 0x0000003FU
  3586. #define LPDDR4__DENALI_PI_237__PI_TEXCKE_F2_SHIFT 0U
  3587. #define LPDDR4__DENALI_PI_237__PI_TEXCKE_F2_WIDTH 6U
  3588. #define LPDDR4__PI_TEXCKE_F2__REG DENALI_PI_237
  3589. #define LPDDR4__PI_TEXCKE_F2__FLD LPDDR4__DENALI_PI_237__PI_TEXCKE_F2
  3590. #define LPDDR4__DENALI_PI_237__PI_TINIT_F0_MASK 0xFFFFFF00U
  3591. #define LPDDR4__DENALI_PI_237__PI_TINIT_F0_SHIFT 8U
  3592. #define LPDDR4__DENALI_PI_237__PI_TINIT_F0_WIDTH 24U
  3593. #define LPDDR4__PI_TINIT_F0__REG DENALI_PI_237
  3594. #define LPDDR4__PI_TINIT_F0__FLD LPDDR4__DENALI_PI_237__PI_TINIT_F0
  3595. #define LPDDR4__DENALI_PI_238_READ_MASK 0x00FFFFFFU
  3596. #define LPDDR4__DENALI_PI_238_WRITE_MASK 0x00FFFFFFU
  3597. #define LPDDR4__DENALI_PI_238__PI_TINIT3_F0_MASK 0x00FFFFFFU
  3598. #define LPDDR4__DENALI_PI_238__PI_TINIT3_F0_SHIFT 0U
  3599. #define LPDDR4__DENALI_PI_238__PI_TINIT3_F0_WIDTH 24U
  3600. #define LPDDR4__PI_TINIT3_F0__REG DENALI_PI_238
  3601. #define LPDDR4__PI_TINIT3_F0__FLD LPDDR4__DENALI_PI_238__PI_TINIT3_F0
  3602. #define LPDDR4__DENALI_PI_239_READ_MASK 0x00FFFFFFU
  3603. #define LPDDR4__DENALI_PI_239_WRITE_MASK 0x00FFFFFFU
  3604. #define LPDDR4__DENALI_PI_239__PI_TINIT4_F0_MASK 0x00FFFFFFU
  3605. #define LPDDR4__DENALI_PI_239__PI_TINIT4_F0_SHIFT 0U
  3606. #define LPDDR4__DENALI_PI_239__PI_TINIT4_F0_WIDTH 24U
  3607. #define LPDDR4__PI_TINIT4_F0__REG DENALI_PI_239
  3608. #define LPDDR4__PI_TINIT4_F0__FLD LPDDR4__DENALI_PI_239__PI_TINIT4_F0
  3609. #define LPDDR4__DENALI_PI_240_READ_MASK 0x00FFFFFFU
  3610. #define LPDDR4__DENALI_PI_240_WRITE_MASK 0x00FFFFFFU
  3611. #define LPDDR4__DENALI_PI_240__PI_TINIT5_F0_MASK 0x00FFFFFFU
  3612. #define LPDDR4__DENALI_PI_240__PI_TINIT5_F0_SHIFT 0U
  3613. #define LPDDR4__DENALI_PI_240__PI_TINIT5_F0_WIDTH 24U
  3614. #define LPDDR4__PI_TINIT5_F0__REG DENALI_PI_240
  3615. #define LPDDR4__PI_TINIT5_F0__FLD LPDDR4__DENALI_PI_240__PI_TINIT5_F0
  3616. #define LPDDR4__DENALI_PI_241_READ_MASK 0x0000FFFFU
  3617. #define LPDDR4__DENALI_PI_241_WRITE_MASK 0x0000FFFFU
  3618. #define LPDDR4__DENALI_PI_241__PI_TXSNR_F0_MASK 0x0000FFFFU
  3619. #define LPDDR4__DENALI_PI_241__PI_TXSNR_F0_SHIFT 0U
  3620. #define LPDDR4__DENALI_PI_241__PI_TXSNR_F0_WIDTH 16U
  3621. #define LPDDR4__PI_TXSNR_F0__REG DENALI_PI_241
  3622. #define LPDDR4__PI_TXSNR_F0__FLD LPDDR4__DENALI_PI_241__PI_TXSNR_F0
  3623. #define LPDDR4__DENALI_PI_242_READ_MASK 0x00FFFFFFU
  3624. #define LPDDR4__DENALI_PI_242_WRITE_MASK 0x00FFFFFFU
  3625. #define LPDDR4__DENALI_PI_242__PI_TINIT_F1_MASK 0x00FFFFFFU
  3626. #define LPDDR4__DENALI_PI_242__PI_TINIT_F1_SHIFT 0U
  3627. #define LPDDR4__DENALI_PI_242__PI_TINIT_F1_WIDTH 24U
  3628. #define LPDDR4__PI_TINIT_F1__REG DENALI_PI_242
  3629. #define LPDDR4__PI_TINIT_F1__FLD LPDDR4__DENALI_PI_242__PI_TINIT_F1
  3630. #define LPDDR4__DENALI_PI_243_READ_MASK 0x00FFFFFFU
  3631. #define LPDDR4__DENALI_PI_243_WRITE_MASK 0x00FFFFFFU
  3632. #define LPDDR4__DENALI_PI_243__PI_TINIT3_F1_MASK 0x00FFFFFFU
  3633. #define LPDDR4__DENALI_PI_243__PI_TINIT3_F1_SHIFT 0U
  3634. #define LPDDR4__DENALI_PI_243__PI_TINIT3_F1_WIDTH 24U
  3635. #define LPDDR4__PI_TINIT3_F1__REG DENALI_PI_243
  3636. #define LPDDR4__PI_TINIT3_F1__FLD LPDDR4__DENALI_PI_243__PI_TINIT3_F1
  3637. #define LPDDR4__DENALI_PI_244_READ_MASK 0x00FFFFFFU
  3638. #define LPDDR4__DENALI_PI_244_WRITE_MASK 0x00FFFFFFU
  3639. #define LPDDR4__DENALI_PI_244__PI_TINIT4_F1_MASK 0x00FFFFFFU
  3640. #define LPDDR4__DENALI_PI_244__PI_TINIT4_F1_SHIFT 0U
  3641. #define LPDDR4__DENALI_PI_244__PI_TINIT4_F1_WIDTH 24U
  3642. #define LPDDR4__PI_TINIT4_F1__REG DENALI_PI_244
  3643. #define LPDDR4__PI_TINIT4_F1__FLD LPDDR4__DENALI_PI_244__PI_TINIT4_F1
  3644. #define LPDDR4__DENALI_PI_245_READ_MASK 0x00FFFFFFU
  3645. #define LPDDR4__DENALI_PI_245_WRITE_MASK 0x00FFFFFFU
  3646. #define LPDDR4__DENALI_PI_245__PI_TINIT5_F1_MASK 0x00FFFFFFU
  3647. #define LPDDR4__DENALI_PI_245__PI_TINIT5_F1_SHIFT 0U
  3648. #define LPDDR4__DENALI_PI_245__PI_TINIT5_F1_WIDTH 24U
  3649. #define LPDDR4__PI_TINIT5_F1__REG DENALI_PI_245
  3650. #define LPDDR4__PI_TINIT5_F1__FLD LPDDR4__DENALI_PI_245__PI_TINIT5_F1
  3651. #define LPDDR4__DENALI_PI_246_READ_MASK 0x0000FFFFU
  3652. #define LPDDR4__DENALI_PI_246_WRITE_MASK 0x0000FFFFU
  3653. #define LPDDR4__DENALI_PI_246__PI_TXSNR_F1_MASK 0x0000FFFFU
  3654. #define LPDDR4__DENALI_PI_246__PI_TXSNR_F1_SHIFT 0U
  3655. #define LPDDR4__DENALI_PI_246__PI_TXSNR_F1_WIDTH 16U
  3656. #define LPDDR4__PI_TXSNR_F1__REG DENALI_PI_246
  3657. #define LPDDR4__PI_TXSNR_F1__FLD LPDDR4__DENALI_PI_246__PI_TXSNR_F1
  3658. #define LPDDR4__DENALI_PI_247_READ_MASK 0x00FFFFFFU
  3659. #define LPDDR4__DENALI_PI_247_WRITE_MASK 0x00FFFFFFU
  3660. #define LPDDR4__DENALI_PI_247__PI_TINIT_F2_MASK 0x00FFFFFFU
  3661. #define LPDDR4__DENALI_PI_247__PI_TINIT_F2_SHIFT 0U
  3662. #define LPDDR4__DENALI_PI_247__PI_TINIT_F2_WIDTH 24U
  3663. #define LPDDR4__PI_TINIT_F2__REG DENALI_PI_247
  3664. #define LPDDR4__PI_TINIT_F2__FLD LPDDR4__DENALI_PI_247__PI_TINIT_F2
  3665. #define LPDDR4__DENALI_PI_248_READ_MASK 0x00FFFFFFU
  3666. #define LPDDR4__DENALI_PI_248_WRITE_MASK 0x00FFFFFFU
  3667. #define LPDDR4__DENALI_PI_248__PI_TINIT3_F2_MASK 0x00FFFFFFU
  3668. #define LPDDR4__DENALI_PI_248__PI_TINIT3_F2_SHIFT 0U
  3669. #define LPDDR4__DENALI_PI_248__PI_TINIT3_F2_WIDTH 24U
  3670. #define LPDDR4__PI_TINIT3_F2__REG DENALI_PI_248
  3671. #define LPDDR4__PI_TINIT3_F2__FLD LPDDR4__DENALI_PI_248__PI_TINIT3_F2
  3672. #define LPDDR4__DENALI_PI_249_READ_MASK 0x00FFFFFFU
  3673. #define LPDDR4__DENALI_PI_249_WRITE_MASK 0x00FFFFFFU
  3674. #define LPDDR4__DENALI_PI_249__PI_TINIT4_F2_MASK 0x00FFFFFFU
  3675. #define LPDDR4__DENALI_PI_249__PI_TINIT4_F2_SHIFT 0U
  3676. #define LPDDR4__DENALI_PI_249__PI_TINIT4_F2_WIDTH 24U
  3677. #define LPDDR4__PI_TINIT4_F2__REG DENALI_PI_249
  3678. #define LPDDR4__PI_TINIT4_F2__FLD LPDDR4__DENALI_PI_249__PI_TINIT4_F2
  3679. #define LPDDR4__DENALI_PI_250_READ_MASK 0x00FFFFFFU
  3680. #define LPDDR4__DENALI_PI_250_WRITE_MASK 0x00FFFFFFU
  3681. #define LPDDR4__DENALI_PI_250__PI_TINIT5_F2_MASK 0x00FFFFFFU
  3682. #define LPDDR4__DENALI_PI_250__PI_TINIT5_F2_SHIFT 0U
  3683. #define LPDDR4__DENALI_PI_250__PI_TINIT5_F2_WIDTH 24U
  3684. #define LPDDR4__PI_TINIT5_F2__REG DENALI_PI_250
  3685. #define LPDDR4__PI_TINIT5_F2__FLD LPDDR4__DENALI_PI_250__PI_TINIT5_F2
  3686. #define LPDDR4__DENALI_PI_251_READ_MASK 0x0FFFFFFFU
  3687. #define LPDDR4__DENALI_PI_251_WRITE_MASK 0x0FFFFFFFU
  3688. #define LPDDR4__DENALI_PI_251__PI_TXSNR_F2_MASK 0x0000FFFFU
  3689. #define LPDDR4__DENALI_PI_251__PI_TXSNR_F2_SHIFT 0U
  3690. #define LPDDR4__DENALI_PI_251__PI_TXSNR_F2_WIDTH 16U
  3691. #define LPDDR4__PI_TXSNR_F2__REG DENALI_PI_251
  3692. #define LPDDR4__PI_TXSNR_F2__FLD LPDDR4__DENALI_PI_251__PI_TXSNR_F2
  3693. #define LPDDR4__DENALI_PI_251__PI_RESERVED49_MASK 0x0FFF0000U
  3694. #define LPDDR4__DENALI_PI_251__PI_RESERVED49_SHIFT 16U
  3695. #define LPDDR4__DENALI_PI_251__PI_RESERVED49_WIDTH 12U
  3696. #define LPDDR4__PI_RESERVED49__REG DENALI_PI_251
  3697. #define LPDDR4__PI_RESERVED49__FLD LPDDR4__DENALI_PI_251__PI_RESERVED49
  3698. #define LPDDR4__DENALI_PI_252_READ_MASK 0x0FFF0FFFU
  3699. #define LPDDR4__DENALI_PI_252_WRITE_MASK 0x0FFF0FFFU
  3700. #define LPDDR4__DENALI_PI_252__PI_RESERVED50_MASK 0x00000FFFU
  3701. #define LPDDR4__DENALI_PI_252__PI_RESERVED50_SHIFT 0U
  3702. #define LPDDR4__DENALI_PI_252__PI_RESERVED50_WIDTH 12U
  3703. #define LPDDR4__PI_RESERVED50__REG DENALI_PI_252
  3704. #define LPDDR4__PI_RESERVED50__FLD LPDDR4__DENALI_PI_252__PI_RESERVED50
  3705. #define LPDDR4__DENALI_PI_252__PI_TZQCAL_F0_MASK 0x0FFF0000U
  3706. #define LPDDR4__DENALI_PI_252__PI_TZQCAL_F0_SHIFT 16U
  3707. #define LPDDR4__DENALI_PI_252__PI_TZQCAL_F0_WIDTH 12U
  3708. #define LPDDR4__PI_TZQCAL_F0__REG DENALI_PI_252
  3709. #define LPDDR4__PI_TZQCAL_F0__FLD LPDDR4__DENALI_PI_252__PI_TZQCAL_F0
  3710. #define LPDDR4__DENALI_PI_253_READ_MASK 0x000FFF7FU
  3711. #define LPDDR4__DENALI_PI_253_WRITE_MASK 0x000FFF7FU
  3712. #define LPDDR4__DENALI_PI_253__PI_TZQLAT_F0_MASK 0x0000007FU
  3713. #define LPDDR4__DENALI_PI_253__PI_TZQLAT_F0_SHIFT 0U
  3714. #define LPDDR4__DENALI_PI_253__PI_TZQLAT_F0_WIDTH 7U
  3715. #define LPDDR4__PI_TZQLAT_F0__REG DENALI_PI_253
  3716. #define LPDDR4__PI_TZQLAT_F0__FLD LPDDR4__DENALI_PI_253__PI_TZQLAT_F0
  3717. #define LPDDR4__DENALI_PI_253__PI_RESERVED51_MASK 0x000FFF00U
  3718. #define LPDDR4__DENALI_PI_253__PI_RESERVED51_SHIFT 8U
  3719. #define LPDDR4__DENALI_PI_253__PI_RESERVED51_WIDTH 12U
  3720. #define LPDDR4__PI_RESERVED51__REG DENALI_PI_253
  3721. #define LPDDR4__PI_RESERVED51__FLD LPDDR4__DENALI_PI_253__PI_RESERVED51
  3722. #define LPDDR4__DENALI_PI_254_READ_MASK 0x0FFF0FFFU
  3723. #define LPDDR4__DENALI_PI_254_WRITE_MASK 0x0FFF0FFFU
  3724. #define LPDDR4__DENALI_PI_254__PI_RESERVED52_MASK 0x00000FFFU
  3725. #define LPDDR4__DENALI_PI_254__PI_RESERVED52_SHIFT 0U
  3726. #define LPDDR4__DENALI_PI_254__PI_RESERVED52_WIDTH 12U
  3727. #define LPDDR4__PI_RESERVED52__REG DENALI_PI_254
  3728. #define LPDDR4__PI_RESERVED52__FLD LPDDR4__DENALI_PI_254__PI_RESERVED52
  3729. #define LPDDR4__DENALI_PI_254__PI_TZQCAL_F1_MASK 0x0FFF0000U
  3730. #define LPDDR4__DENALI_PI_254__PI_TZQCAL_F1_SHIFT 16U
  3731. #define LPDDR4__DENALI_PI_254__PI_TZQCAL_F1_WIDTH 12U
  3732. #define LPDDR4__PI_TZQCAL_F1__REG DENALI_PI_254
  3733. #define LPDDR4__PI_TZQCAL_F1__FLD LPDDR4__DENALI_PI_254__PI_TZQCAL_F1
  3734. #define LPDDR4__DENALI_PI_255_READ_MASK 0x000FFF7FU
  3735. #define LPDDR4__DENALI_PI_255_WRITE_MASK 0x000FFF7FU
  3736. #define LPDDR4__DENALI_PI_255__PI_TZQLAT_F1_MASK 0x0000007FU
  3737. #define LPDDR4__DENALI_PI_255__PI_TZQLAT_F1_SHIFT 0U
  3738. #define LPDDR4__DENALI_PI_255__PI_TZQLAT_F1_WIDTH 7U
  3739. #define LPDDR4__PI_TZQLAT_F1__REG DENALI_PI_255
  3740. #define LPDDR4__PI_TZQLAT_F1__FLD LPDDR4__DENALI_PI_255__PI_TZQLAT_F1
  3741. #define LPDDR4__DENALI_PI_255__PI_RESERVED53_MASK 0x000FFF00U
  3742. #define LPDDR4__DENALI_PI_255__PI_RESERVED53_SHIFT 8U
  3743. #define LPDDR4__DENALI_PI_255__PI_RESERVED53_WIDTH 12U
  3744. #define LPDDR4__PI_RESERVED53__REG DENALI_PI_255
  3745. #define LPDDR4__PI_RESERVED53__FLD LPDDR4__DENALI_PI_255__PI_RESERVED53
  3746. #define LPDDR4__DENALI_PI_256_READ_MASK 0x0FFF0FFFU
  3747. #define LPDDR4__DENALI_PI_256_WRITE_MASK 0x0FFF0FFFU
  3748. #define LPDDR4__DENALI_PI_256__PI_RESERVED54_MASK 0x00000FFFU
  3749. #define LPDDR4__DENALI_PI_256__PI_RESERVED54_SHIFT 0U
  3750. #define LPDDR4__DENALI_PI_256__PI_RESERVED54_WIDTH 12U
  3751. #define LPDDR4__PI_RESERVED54__REG DENALI_PI_256
  3752. #define LPDDR4__PI_RESERVED54__FLD LPDDR4__DENALI_PI_256__PI_RESERVED54
  3753. #define LPDDR4__DENALI_PI_256__PI_TZQCAL_F2_MASK 0x0FFF0000U
  3754. #define LPDDR4__DENALI_PI_256__PI_TZQCAL_F2_SHIFT 16U
  3755. #define LPDDR4__DENALI_PI_256__PI_TZQCAL_F2_WIDTH 12U
  3756. #define LPDDR4__PI_TZQCAL_F2__REG DENALI_PI_256
  3757. #define LPDDR4__PI_TZQCAL_F2__FLD LPDDR4__DENALI_PI_256__PI_TZQCAL_F2
  3758. #define LPDDR4__DENALI_PI_257_READ_MASK 0x000FFF7FU
  3759. #define LPDDR4__DENALI_PI_257_WRITE_MASK 0x000FFF7FU
  3760. #define LPDDR4__DENALI_PI_257__PI_TZQLAT_F2_MASK 0x0000007FU
  3761. #define LPDDR4__DENALI_PI_257__PI_TZQLAT_F2_SHIFT 0U
  3762. #define LPDDR4__DENALI_PI_257__PI_TZQLAT_F2_WIDTH 7U
  3763. #define LPDDR4__PI_TZQLAT_F2__REG DENALI_PI_257
  3764. #define LPDDR4__PI_TZQLAT_F2__FLD LPDDR4__DENALI_PI_257__PI_TZQLAT_F2
  3765. #define LPDDR4__DENALI_PI_257__PI_RESERVED55_MASK 0x000FFF00U
  3766. #define LPDDR4__DENALI_PI_257__PI_RESERVED55_SHIFT 8U
  3767. #define LPDDR4__DENALI_PI_257__PI_RESERVED55_WIDTH 12U
  3768. #define LPDDR4__PI_RESERVED55__REG DENALI_PI_257
  3769. #define LPDDR4__PI_RESERVED55__FLD LPDDR4__DENALI_PI_257__PI_RESERVED55
  3770. #define LPDDR4__DENALI_PI_258_READ_MASK 0x0FFF0FFFU
  3771. #define LPDDR4__DENALI_PI_258_WRITE_MASK 0x0FFF0FFFU
  3772. #define LPDDR4__DENALI_PI_258__PI_RESERVED56_MASK 0x00000FFFU
  3773. #define LPDDR4__DENALI_PI_258__PI_RESERVED56_SHIFT 0U
  3774. #define LPDDR4__DENALI_PI_258__PI_RESERVED56_WIDTH 12U
  3775. #define LPDDR4__PI_RESERVED56__REG DENALI_PI_258
  3776. #define LPDDR4__PI_RESERVED56__FLD LPDDR4__DENALI_PI_258__PI_RESERVED56
  3777. #define LPDDR4__DENALI_PI_258__PI_RESERVED57_MASK 0x0FFF0000U
  3778. #define LPDDR4__DENALI_PI_258__PI_RESERVED57_SHIFT 16U
  3779. #define LPDDR4__DENALI_PI_258__PI_RESERVED57_WIDTH 12U
  3780. #define LPDDR4__PI_RESERVED57__REG DENALI_PI_258
  3781. #define LPDDR4__PI_RESERVED57__FLD LPDDR4__DENALI_PI_258__PI_RESERVED57
  3782. #define LPDDR4__DENALI_PI_259_READ_MASK 0xFF0F0F0FU
  3783. #define LPDDR4__DENALI_PI_259_WRITE_MASK 0xFF0F0F0FU
  3784. #define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F0_MASK 0x0000000FU
  3785. #define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F0_SHIFT 0U
  3786. #define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F0_WIDTH 4U
  3787. #define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F0__REG DENALI_PI_259
  3788. #define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F0__FLD LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F0
  3789. #define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F1_MASK 0x00000F00U
  3790. #define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F1_SHIFT 8U
  3791. #define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F1_WIDTH 4U
  3792. #define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F1__REG DENALI_PI_259
  3793. #define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F1__FLD LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F1
  3794. #define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F2_MASK 0x000F0000U
  3795. #define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F2_SHIFT 16U
  3796. #define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F2_WIDTH 4U
  3797. #define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F2__REG DENALI_PI_259
  3798. #define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F2__FLD LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F2
  3799. #define LPDDR4__DENALI_PI_259__PI_MR13_DATA_0_MASK 0xFF000000U
  3800. #define LPDDR4__DENALI_PI_259__PI_MR13_DATA_0_SHIFT 24U
  3801. #define LPDDR4__DENALI_PI_259__PI_MR13_DATA_0_WIDTH 8U
  3802. #define LPDDR4__PI_MR13_DATA_0__REG DENALI_PI_259
  3803. #define LPDDR4__PI_MR13_DATA_0__FLD LPDDR4__DENALI_PI_259__PI_MR13_DATA_0
  3804. #define LPDDR4__DENALI_PI_260_READ_MASK 0xFFFFFFFFU
  3805. #define LPDDR4__DENALI_PI_260_WRITE_MASK 0xFFFFFFFFU
  3806. #define LPDDR4__DENALI_PI_260__PI_MR15_DATA_0_MASK 0x000000FFU
  3807. #define LPDDR4__DENALI_PI_260__PI_MR15_DATA_0_SHIFT 0U
  3808. #define LPDDR4__DENALI_PI_260__PI_MR15_DATA_0_WIDTH 8U
  3809. #define LPDDR4__PI_MR15_DATA_0__REG DENALI_PI_260
  3810. #define LPDDR4__PI_MR15_DATA_0__FLD LPDDR4__DENALI_PI_260__PI_MR15_DATA_0
  3811. #define LPDDR4__DENALI_PI_260__PI_MR16_DATA_0_MASK 0x0000FF00U
  3812. #define LPDDR4__DENALI_PI_260__PI_MR16_DATA_0_SHIFT 8U
  3813. #define LPDDR4__DENALI_PI_260__PI_MR16_DATA_0_WIDTH 8U
  3814. #define LPDDR4__PI_MR16_DATA_0__REG DENALI_PI_260
  3815. #define LPDDR4__PI_MR16_DATA_0__FLD LPDDR4__DENALI_PI_260__PI_MR16_DATA_0
  3816. #define LPDDR4__DENALI_PI_260__PI_MR17_DATA_0_MASK 0x00FF0000U
  3817. #define LPDDR4__DENALI_PI_260__PI_MR17_DATA_0_SHIFT 16U
  3818. #define LPDDR4__DENALI_PI_260__PI_MR17_DATA_0_WIDTH 8U
  3819. #define LPDDR4__PI_MR17_DATA_0__REG DENALI_PI_260
  3820. #define LPDDR4__PI_MR17_DATA_0__FLD LPDDR4__DENALI_PI_260__PI_MR17_DATA_0
  3821. #define LPDDR4__DENALI_PI_260__PI_MR20_DATA_0_MASK 0xFF000000U
  3822. #define LPDDR4__DENALI_PI_260__PI_MR20_DATA_0_SHIFT 24U
  3823. #define LPDDR4__DENALI_PI_260__PI_MR20_DATA_0_WIDTH 8U
  3824. #define LPDDR4__PI_MR20_DATA_0__REG DENALI_PI_260
  3825. #define LPDDR4__PI_MR20_DATA_0__FLD LPDDR4__DENALI_PI_260__PI_MR20_DATA_0
  3826. #define LPDDR4__DENALI_PI_261_READ_MASK 0xFFFFFFFFU
  3827. #define LPDDR4__DENALI_PI_261_WRITE_MASK 0xFFFFFFFFU
  3828. #define LPDDR4__DENALI_PI_261__PI_MR32_DATA_0_MASK 0x000000FFU
  3829. #define LPDDR4__DENALI_PI_261__PI_MR32_DATA_0_SHIFT 0U
  3830. #define LPDDR4__DENALI_PI_261__PI_MR32_DATA_0_WIDTH 8U
  3831. #define LPDDR4__PI_MR32_DATA_0__REG DENALI_PI_261
  3832. #define LPDDR4__PI_MR32_DATA_0__FLD LPDDR4__DENALI_PI_261__PI_MR32_DATA_0
  3833. #define LPDDR4__DENALI_PI_261__PI_MR40_DATA_0_MASK 0x0000FF00U
  3834. #define LPDDR4__DENALI_PI_261__PI_MR40_DATA_0_SHIFT 8U
  3835. #define LPDDR4__DENALI_PI_261__PI_MR40_DATA_0_WIDTH 8U
  3836. #define LPDDR4__PI_MR40_DATA_0__REG DENALI_PI_261
  3837. #define LPDDR4__PI_MR40_DATA_0__FLD LPDDR4__DENALI_PI_261__PI_MR40_DATA_0
  3838. #define LPDDR4__DENALI_PI_261__PI_MR13_DATA_1_MASK 0x00FF0000U
  3839. #define LPDDR4__DENALI_PI_261__PI_MR13_DATA_1_SHIFT 16U
  3840. #define LPDDR4__DENALI_PI_261__PI_MR13_DATA_1_WIDTH 8U
  3841. #define LPDDR4__PI_MR13_DATA_1__REG DENALI_PI_261
  3842. #define LPDDR4__PI_MR13_DATA_1__FLD LPDDR4__DENALI_PI_261__PI_MR13_DATA_1
  3843. #define LPDDR4__DENALI_PI_261__PI_MR15_DATA_1_MASK 0xFF000000U
  3844. #define LPDDR4__DENALI_PI_261__PI_MR15_DATA_1_SHIFT 24U
  3845. #define LPDDR4__DENALI_PI_261__PI_MR15_DATA_1_WIDTH 8U
  3846. #define LPDDR4__PI_MR15_DATA_1__REG DENALI_PI_261
  3847. #define LPDDR4__PI_MR15_DATA_1__FLD LPDDR4__DENALI_PI_261__PI_MR15_DATA_1
  3848. #define LPDDR4__DENALI_PI_262_READ_MASK 0xFFFFFFFFU
  3849. #define LPDDR4__DENALI_PI_262_WRITE_MASK 0xFFFFFFFFU
  3850. #define LPDDR4__DENALI_PI_262__PI_MR16_DATA_1_MASK 0x000000FFU
  3851. #define LPDDR4__DENALI_PI_262__PI_MR16_DATA_1_SHIFT 0U
  3852. #define LPDDR4__DENALI_PI_262__PI_MR16_DATA_1_WIDTH 8U
  3853. #define LPDDR4__PI_MR16_DATA_1__REG DENALI_PI_262
  3854. #define LPDDR4__PI_MR16_DATA_1__FLD LPDDR4__DENALI_PI_262__PI_MR16_DATA_1
  3855. #define LPDDR4__DENALI_PI_262__PI_MR17_DATA_1_MASK 0x0000FF00U
  3856. #define LPDDR4__DENALI_PI_262__PI_MR17_DATA_1_SHIFT 8U
  3857. #define LPDDR4__DENALI_PI_262__PI_MR17_DATA_1_WIDTH 8U
  3858. #define LPDDR4__PI_MR17_DATA_1__REG DENALI_PI_262
  3859. #define LPDDR4__PI_MR17_DATA_1__FLD LPDDR4__DENALI_PI_262__PI_MR17_DATA_1
  3860. #define LPDDR4__DENALI_PI_262__PI_MR20_DATA_1_MASK 0x00FF0000U
  3861. #define LPDDR4__DENALI_PI_262__PI_MR20_DATA_1_SHIFT 16U
  3862. #define LPDDR4__DENALI_PI_262__PI_MR20_DATA_1_WIDTH 8U
  3863. #define LPDDR4__PI_MR20_DATA_1__REG DENALI_PI_262
  3864. #define LPDDR4__PI_MR20_DATA_1__FLD LPDDR4__DENALI_PI_262__PI_MR20_DATA_1
  3865. #define LPDDR4__DENALI_PI_262__PI_MR32_DATA_1_MASK 0xFF000000U
  3866. #define LPDDR4__DENALI_PI_262__PI_MR32_DATA_1_SHIFT 24U
  3867. #define LPDDR4__DENALI_PI_262__PI_MR32_DATA_1_WIDTH 8U
  3868. #define LPDDR4__PI_MR32_DATA_1__REG DENALI_PI_262
  3869. #define LPDDR4__PI_MR32_DATA_1__FLD LPDDR4__DENALI_PI_262__PI_MR32_DATA_1
  3870. #define LPDDR4__DENALI_PI_263_READ_MASK 0xFFFFFFFFU
  3871. #define LPDDR4__DENALI_PI_263_WRITE_MASK 0xFFFFFFFFU
  3872. #define LPDDR4__DENALI_PI_263__PI_MR40_DATA_1_MASK 0x000000FFU
  3873. #define LPDDR4__DENALI_PI_263__PI_MR40_DATA_1_SHIFT 0U
  3874. #define LPDDR4__DENALI_PI_263__PI_MR40_DATA_1_WIDTH 8U
  3875. #define LPDDR4__PI_MR40_DATA_1__REG DENALI_PI_263
  3876. #define LPDDR4__PI_MR40_DATA_1__FLD LPDDR4__DENALI_PI_263__PI_MR40_DATA_1
  3877. #define LPDDR4__DENALI_PI_263__PI_MR13_DATA_2_MASK 0x0000FF00U
  3878. #define LPDDR4__DENALI_PI_263__PI_MR13_DATA_2_SHIFT 8U
  3879. #define LPDDR4__DENALI_PI_263__PI_MR13_DATA_2_WIDTH 8U
  3880. #define LPDDR4__PI_MR13_DATA_2__REG DENALI_PI_263
  3881. #define LPDDR4__PI_MR13_DATA_2__FLD LPDDR4__DENALI_PI_263__PI_MR13_DATA_2
  3882. #define LPDDR4__DENALI_PI_263__PI_MR15_DATA_2_MASK 0x00FF0000U
  3883. #define LPDDR4__DENALI_PI_263__PI_MR15_DATA_2_SHIFT 16U
  3884. #define LPDDR4__DENALI_PI_263__PI_MR15_DATA_2_WIDTH 8U
  3885. #define LPDDR4__PI_MR15_DATA_2__REG DENALI_PI_263
  3886. #define LPDDR4__PI_MR15_DATA_2__FLD LPDDR4__DENALI_PI_263__PI_MR15_DATA_2
  3887. #define LPDDR4__DENALI_PI_263__PI_MR16_DATA_2_MASK 0xFF000000U
  3888. #define LPDDR4__DENALI_PI_263__PI_MR16_DATA_2_SHIFT 24U
  3889. #define LPDDR4__DENALI_PI_263__PI_MR16_DATA_2_WIDTH 8U
  3890. #define LPDDR4__PI_MR16_DATA_2__REG DENALI_PI_263
  3891. #define LPDDR4__PI_MR16_DATA_2__FLD LPDDR4__DENALI_PI_263__PI_MR16_DATA_2
  3892. #define LPDDR4__DENALI_PI_264_READ_MASK 0xFFFFFFFFU
  3893. #define LPDDR4__DENALI_PI_264_WRITE_MASK 0xFFFFFFFFU
  3894. #define LPDDR4__DENALI_PI_264__PI_MR17_DATA_2_MASK 0x000000FFU
  3895. #define LPDDR4__DENALI_PI_264__PI_MR17_DATA_2_SHIFT 0U
  3896. #define LPDDR4__DENALI_PI_264__PI_MR17_DATA_2_WIDTH 8U
  3897. #define LPDDR4__PI_MR17_DATA_2__REG DENALI_PI_264
  3898. #define LPDDR4__PI_MR17_DATA_2__FLD LPDDR4__DENALI_PI_264__PI_MR17_DATA_2
  3899. #define LPDDR4__DENALI_PI_264__PI_MR20_DATA_2_MASK 0x0000FF00U
  3900. #define LPDDR4__DENALI_PI_264__PI_MR20_DATA_2_SHIFT 8U
  3901. #define LPDDR4__DENALI_PI_264__PI_MR20_DATA_2_WIDTH 8U
  3902. #define LPDDR4__PI_MR20_DATA_2__REG DENALI_PI_264
  3903. #define LPDDR4__PI_MR20_DATA_2__FLD LPDDR4__DENALI_PI_264__PI_MR20_DATA_2
  3904. #define LPDDR4__DENALI_PI_264__PI_MR32_DATA_2_MASK 0x00FF0000U
  3905. #define LPDDR4__DENALI_PI_264__PI_MR32_DATA_2_SHIFT 16U
  3906. #define LPDDR4__DENALI_PI_264__PI_MR32_DATA_2_WIDTH 8U
  3907. #define LPDDR4__PI_MR32_DATA_2__REG DENALI_PI_264
  3908. #define LPDDR4__PI_MR32_DATA_2__FLD LPDDR4__DENALI_PI_264__PI_MR32_DATA_2
  3909. #define LPDDR4__DENALI_PI_264__PI_MR40_DATA_2_MASK 0xFF000000U
  3910. #define LPDDR4__DENALI_PI_264__PI_MR40_DATA_2_SHIFT 24U
  3911. #define LPDDR4__DENALI_PI_264__PI_MR40_DATA_2_WIDTH 8U
  3912. #define LPDDR4__PI_MR40_DATA_2__REG DENALI_PI_264
  3913. #define LPDDR4__PI_MR40_DATA_2__FLD LPDDR4__DENALI_PI_264__PI_MR40_DATA_2
  3914. #define LPDDR4__DENALI_PI_265_READ_MASK 0xFFFFFFFFU
  3915. #define LPDDR4__DENALI_PI_265_WRITE_MASK 0xFFFFFFFFU
  3916. #define LPDDR4__DENALI_PI_265__PI_MR13_DATA_3_MASK 0x000000FFU
  3917. #define LPDDR4__DENALI_PI_265__PI_MR13_DATA_3_SHIFT 0U
  3918. #define LPDDR4__DENALI_PI_265__PI_MR13_DATA_3_WIDTH 8U
  3919. #define LPDDR4__PI_MR13_DATA_3__REG DENALI_PI_265
  3920. #define LPDDR4__PI_MR13_DATA_3__FLD LPDDR4__DENALI_PI_265__PI_MR13_DATA_3
  3921. #define LPDDR4__DENALI_PI_265__PI_MR15_DATA_3_MASK 0x0000FF00U
  3922. #define LPDDR4__DENALI_PI_265__PI_MR15_DATA_3_SHIFT 8U
  3923. #define LPDDR4__DENALI_PI_265__PI_MR15_DATA_3_WIDTH 8U
  3924. #define LPDDR4__PI_MR15_DATA_3__REG DENALI_PI_265
  3925. #define LPDDR4__PI_MR15_DATA_3__FLD LPDDR4__DENALI_PI_265__PI_MR15_DATA_3
  3926. #define LPDDR4__DENALI_PI_265__PI_MR16_DATA_3_MASK 0x00FF0000U
  3927. #define LPDDR4__DENALI_PI_265__PI_MR16_DATA_3_SHIFT 16U
  3928. #define LPDDR4__DENALI_PI_265__PI_MR16_DATA_3_WIDTH 8U
  3929. #define LPDDR4__PI_MR16_DATA_3__REG DENALI_PI_265
  3930. #define LPDDR4__PI_MR16_DATA_3__FLD LPDDR4__DENALI_PI_265__PI_MR16_DATA_3
  3931. #define LPDDR4__DENALI_PI_265__PI_MR17_DATA_3_MASK 0xFF000000U
  3932. #define LPDDR4__DENALI_PI_265__PI_MR17_DATA_3_SHIFT 24U
  3933. #define LPDDR4__DENALI_PI_265__PI_MR17_DATA_3_WIDTH 8U
  3934. #define LPDDR4__PI_MR17_DATA_3__REG DENALI_PI_265
  3935. #define LPDDR4__PI_MR17_DATA_3__FLD LPDDR4__DENALI_PI_265__PI_MR17_DATA_3
  3936. #define LPDDR4__DENALI_PI_266_READ_MASK 0x0FFFFFFFU
  3937. #define LPDDR4__DENALI_PI_266_WRITE_MASK 0x0FFFFFFFU
  3938. #define LPDDR4__DENALI_PI_266__PI_MR20_DATA_3_MASK 0x000000FFU
  3939. #define LPDDR4__DENALI_PI_266__PI_MR20_DATA_3_SHIFT 0U
  3940. #define LPDDR4__DENALI_PI_266__PI_MR20_DATA_3_WIDTH 8U
  3941. #define LPDDR4__PI_MR20_DATA_3__REG DENALI_PI_266
  3942. #define LPDDR4__PI_MR20_DATA_3__FLD LPDDR4__DENALI_PI_266__PI_MR20_DATA_3
  3943. #define LPDDR4__DENALI_PI_266__PI_MR32_DATA_3_MASK 0x0000FF00U
  3944. #define LPDDR4__DENALI_PI_266__PI_MR32_DATA_3_SHIFT 8U
  3945. #define LPDDR4__DENALI_PI_266__PI_MR32_DATA_3_WIDTH 8U
  3946. #define LPDDR4__PI_MR32_DATA_3__REG DENALI_PI_266
  3947. #define LPDDR4__PI_MR32_DATA_3__FLD LPDDR4__DENALI_PI_266__PI_MR32_DATA_3
  3948. #define LPDDR4__DENALI_PI_266__PI_MR40_DATA_3_MASK 0x00FF0000U
  3949. #define LPDDR4__DENALI_PI_266__PI_MR40_DATA_3_SHIFT 16U
  3950. #define LPDDR4__DENALI_PI_266__PI_MR40_DATA_3_WIDTH 8U
  3951. #define LPDDR4__PI_MR40_DATA_3__REG DENALI_PI_266
  3952. #define LPDDR4__PI_MR40_DATA_3__FLD LPDDR4__DENALI_PI_266__PI_MR40_DATA_3
  3953. #define LPDDR4__DENALI_PI_266__PI_CKE_MUX_0_MASK 0x0F000000U
  3954. #define LPDDR4__DENALI_PI_266__PI_CKE_MUX_0_SHIFT 24U
  3955. #define LPDDR4__DENALI_PI_266__PI_CKE_MUX_0_WIDTH 4U
  3956. #define LPDDR4__PI_CKE_MUX_0__REG DENALI_PI_266
  3957. #define LPDDR4__PI_CKE_MUX_0__FLD LPDDR4__DENALI_PI_266__PI_CKE_MUX_0
  3958. #define LPDDR4__DENALI_PI_267_READ_MASK 0x0F0F0F0FU
  3959. #define LPDDR4__DENALI_PI_267_WRITE_MASK 0x0F0F0F0FU
  3960. #define LPDDR4__DENALI_PI_267__PI_CKE_MUX_1_MASK 0x0000000FU
  3961. #define LPDDR4__DENALI_PI_267__PI_CKE_MUX_1_SHIFT 0U
  3962. #define LPDDR4__DENALI_PI_267__PI_CKE_MUX_1_WIDTH 4U
  3963. #define LPDDR4__PI_CKE_MUX_1__REG DENALI_PI_267
  3964. #define LPDDR4__PI_CKE_MUX_1__FLD LPDDR4__DENALI_PI_267__PI_CKE_MUX_1
  3965. #define LPDDR4__DENALI_PI_267__PI_CKE_MUX_2_MASK 0x00000F00U
  3966. #define LPDDR4__DENALI_PI_267__PI_CKE_MUX_2_SHIFT 8U
  3967. #define LPDDR4__DENALI_PI_267__PI_CKE_MUX_2_WIDTH 4U
  3968. #define LPDDR4__PI_CKE_MUX_2__REG DENALI_PI_267
  3969. #define LPDDR4__PI_CKE_MUX_2__FLD LPDDR4__DENALI_PI_267__PI_CKE_MUX_2
  3970. #define LPDDR4__DENALI_PI_267__PI_CKE_MUX_3_MASK 0x000F0000U
  3971. #define LPDDR4__DENALI_PI_267__PI_CKE_MUX_3_SHIFT 16U
  3972. #define LPDDR4__DENALI_PI_267__PI_CKE_MUX_3_WIDTH 4U
  3973. #define LPDDR4__PI_CKE_MUX_3__REG DENALI_PI_267
  3974. #define LPDDR4__PI_CKE_MUX_3__FLD LPDDR4__DENALI_PI_267__PI_CKE_MUX_3
  3975. #define LPDDR4__DENALI_PI_267__PI_CS_MUX_0_MASK 0x0F000000U
  3976. #define LPDDR4__DENALI_PI_267__PI_CS_MUX_0_SHIFT 24U
  3977. #define LPDDR4__DENALI_PI_267__PI_CS_MUX_0_WIDTH 4U
  3978. #define LPDDR4__PI_CS_MUX_0__REG DENALI_PI_267
  3979. #define LPDDR4__PI_CS_MUX_0__FLD LPDDR4__DENALI_PI_267__PI_CS_MUX_0
  3980. #define LPDDR4__DENALI_PI_268_READ_MASK 0x0F0F0F0FU
  3981. #define LPDDR4__DENALI_PI_268_WRITE_MASK 0x0F0F0F0FU
  3982. #define LPDDR4__DENALI_PI_268__PI_CS_MUX_1_MASK 0x0000000FU
  3983. #define LPDDR4__DENALI_PI_268__PI_CS_MUX_1_SHIFT 0U
  3984. #define LPDDR4__DENALI_PI_268__PI_CS_MUX_1_WIDTH 4U
  3985. #define LPDDR4__PI_CS_MUX_1__REG DENALI_PI_268
  3986. #define LPDDR4__PI_CS_MUX_1__FLD LPDDR4__DENALI_PI_268__PI_CS_MUX_1
  3987. #define LPDDR4__DENALI_PI_268__PI_CS_MUX_2_MASK 0x00000F00U
  3988. #define LPDDR4__DENALI_PI_268__PI_CS_MUX_2_SHIFT 8U
  3989. #define LPDDR4__DENALI_PI_268__PI_CS_MUX_2_WIDTH 4U
  3990. #define LPDDR4__PI_CS_MUX_2__REG DENALI_PI_268
  3991. #define LPDDR4__PI_CS_MUX_2__FLD LPDDR4__DENALI_PI_268__PI_CS_MUX_2
  3992. #define LPDDR4__DENALI_PI_268__PI_CS_MUX_3_MASK 0x000F0000U
  3993. #define LPDDR4__DENALI_PI_268__PI_CS_MUX_3_SHIFT 16U
  3994. #define LPDDR4__DENALI_PI_268__PI_CS_MUX_3_WIDTH 4U
  3995. #define LPDDR4__PI_CS_MUX_3__REG DENALI_PI_268
  3996. #define LPDDR4__PI_CS_MUX_3__FLD LPDDR4__DENALI_PI_268__PI_CS_MUX_3
  3997. #define LPDDR4__DENALI_PI_268__PI_RESET_N_MUX_0_MASK 0x0F000000U
  3998. #define LPDDR4__DENALI_PI_268__PI_RESET_N_MUX_0_SHIFT 24U
  3999. #define LPDDR4__DENALI_PI_268__PI_RESET_N_MUX_0_WIDTH 4U
  4000. #define LPDDR4__PI_RESET_N_MUX_0__REG DENALI_PI_268
  4001. #define LPDDR4__PI_RESET_N_MUX_0__FLD LPDDR4__DENALI_PI_268__PI_RESET_N_MUX_0
  4002. #define LPDDR4__DENALI_PI_269_READ_MASK 0xFF0F0F0FU
  4003. #define LPDDR4__DENALI_PI_269_WRITE_MASK 0xFF0F0F0FU
  4004. #define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_1_MASK 0x0000000FU
  4005. #define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_1_SHIFT 0U
  4006. #define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_1_WIDTH 4U
  4007. #define LPDDR4__PI_RESET_N_MUX_1__REG DENALI_PI_269
  4008. #define LPDDR4__PI_RESET_N_MUX_1__FLD LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_1
  4009. #define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_2_MASK 0x00000F00U
  4010. #define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_2_SHIFT 8U
  4011. #define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_2_WIDTH 4U
  4012. #define LPDDR4__PI_RESET_N_MUX_2__REG DENALI_PI_269
  4013. #define LPDDR4__PI_RESET_N_MUX_2__FLD LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_2
  4014. #define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_3_MASK 0x000F0000U
  4015. #define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_3_SHIFT 16U
  4016. #define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_3_WIDTH 4U
  4017. #define LPDDR4__PI_RESET_N_MUX_3__REG DENALI_PI_269
  4018. #define LPDDR4__PI_RESET_N_MUX_3__FLD LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_3
  4019. #define LPDDR4__DENALI_PI_269__PI_MRSINGLE_DATA_0_MASK 0xFF000000U
  4020. #define LPDDR4__DENALI_PI_269__PI_MRSINGLE_DATA_0_SHIFT 24U
  4021. #define LPDDR4__DENALI_PI_269__PI_MRSINGLE_DATA_0_WIDTH 8U
  4022. #define LPDDR4__PI_MRSINGLE_DATA_0__REG DENALI_PI_269
  4023. #define LPDDR4__PI_MRSINGLE_DATA_0__FLD LPDDR4__DENALI_PI_269__PI_MRSINGLE_DATA_0
  4024. #define LPDDR4__DENALI_PI_270_READ_MASK 0x0FFFFFFFU
  4025. #define LPDDR4__DENALI_PI_270_WRITE_MASK 0x0FFFFFFFU
  4026. #define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_1_MASK 0x000000FFU
  4027. #define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_1_SHIFT 0U
  4028. #define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_1_WIDTH 8U
  4029. #define LPDDR4__PI_MRSINGLE_DATA_1__REG DENALI_PI_270
  4030. #define LPDDR4__PI_MRSINGLE_DATA_1__FLD LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_1
  4031. #define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_2_MASK 0x0000FF00U
  4032. #define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_2_SHIFT 8U
  4033. #define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_2_WIDTH 8U
  4034. #define LPDDR4__PI_MRSINGLE_DATA_2__REG DENALI_PI_270
  4035. #define LPDDR4__PI_MRSINGLE_DATA_2__FLD LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_2
  4036. #define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_3_MASK 0x00FF0000U
  4037. #define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_3_SHIFT 16U
  4038. #define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_3_WIDTH 8U
  4039. #define LPDDR4__PI_MRSINGLE_DATA_3__REG DENALI_PI_270
  4040. #define LPDDR4__PI_MRSINGLE_DATA_3__FLD LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_3
  4041. #define LPDDR4__DENALI_PI_270__PI_ZQ_CAL_START_MAP_0_MASK 0x0F000000U
  4042. #define LPDDR4__DENALI_PI_270__PI_ZQ_CAL_START_MAP_0_SHIFT 24U
  4043. #define LPDDR4__DENALI_PI_270__PI_ZQ_CAL_START_MAP_0_WIDTH 4U
  4044. #define LPDDR4__PI_ZQ_CAL_START_MAP_0__REG DENALI_PI_270
  4045. #define LPDDR4__PI_ZQ_CAL_START_MAP_0__FLD LPDDR4__DENALI_PI_270__PI_ZQ_CAL_START_MAP_0
  4046. #define LPDDR4__DENALI_PI_271_READ_MASK 0x0F0F0F0FU
  4047. #define LPDDR4__DENALI_PI_271_WRITE_MASK 0x0F0F0F0FU
  4048. #define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_0_MASK 0x0000000FU
  4049. #define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_0_SHIFT 0U
  4050. #define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_0_WIDTH 4U
  4051. #define LPDDR4__PI_ZQ_CAL_LATCH_MAP_0__REG DENALI_PI_271
  4052. #define LPDDR4__PI_ZQ_CAL_LATCH_MAP_0__FLD LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_0
  4053. #define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_1_MASK 0x00000F00U
  4054. #define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_1_SHIFT 8U
  4055. #define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_1_WIDTH 4U
  4056. #define LPDDR4__PI_ZQ_CAL_START_MAP_1__REG DENALI_PI_271
  4057. #define LPDDR4__PI_ZQ_CAL_START_MAP_1__FLD LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_1
  4058. #define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_1_MASK 0x000F0000U
  4059. #define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_1_SHIFT 16U
  4060. #define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_1_WIDTH 4U
  4061. #define LPDDR4__PI_ZQ_CAL_LATCH_MAP_1__REG DENALI_PI_271
  4062. #define LPDDR4__PI_ZQ_CAL_LATCH_MAP_1__FLD LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_1
  4063. #define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_2_MASK 0x0F000000U
  4064. #define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_2_SHIFT 24U
  4065. #define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_2_WIDTH 4U
  4066. #define LPDDR4__PI_ZQ_CAL_START_MAP_2__REG DENALI_PI_271
  4067. #define LPDDR4__PI_ZQ_CAL_START_MAP_2__FLD LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_2
  4068. #define LPDDR4__DENALI_PI_272_READ_MASK 0x000F0F0FU
  4069. #define LPDDR4__DENALI_PI_272_WRITE_MASK 0x000F0F0FU
  4070. #define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_2_MASK 0x0000000FU
  4071. #define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_2_SHIFT 0U
  4072. #define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_2_WIDTH 4U
  4073. #define LPDDR4__PI_ZQ_CAL_LATCH_MAP_2__REG DENALI_PI_272
  4074. #define LPDDR4__PI_ZQ_CAL_LATCH_MAP_2__FLD LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_2
  4075. #define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_START_MAP_3_MASK 0x00000F00U
  4076. #define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_START_MAP_3_SHIFT 8U
  4077. #define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_START_MAP_3_WIDTH 4U
  4078. #define LPDDR4__PI_ZQ_CAL_START_MAP_3__REG DENALI_PI_272
  4079. #define LPDDR4__PI_ZQ_CAL_START_MAP_3__FLD LPDDR4__DENALI_PI_272__PI_ZQ_CAL_START_MAP_3
  4080. #define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_3_MASK 0x000F0000U
  4081. #define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_3_SHIFT 16U
  4082. #define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_3_WIDTH 4U
  4083. #define LPDDR4__PI_ZQ_CAL_LATCH_MAP_3__REG DENALI_PI_272
  4084. #define LPDDR4__PI_ZQ_CAL_LATCH_MAP_3__FLD LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_3
  4085. #define LPDDR4__DENALI_PI_273_READ_MASK 0xFFFFFFFFU
  4086. #define LPDDR4__DENALI_PI_273_WRITE_MASK 0xFFFFFFFFU
  4087. #define LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_0_0_MASK 0x0000FFFFU
  4088. #define LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_0_0_SHIFT 0U
  4089. #define LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_0_0_WIDTH 16U
  4090. #define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_0__REG DENALI_PI_273
  4091. #define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_0__FLD LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_0_0
  4092. #define LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_1_0_MASK 0xFFFF0000U
  4093. #define LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_1_0_SHIFT 16U
  4094. #define LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_1_0_WIDTH 16U
  4095. #define LPDDR4__PI_DQS_OSC_BASE_VALUE_1_0__REG DENALI_PI_273
  4096. #define LPDDR4__PI_DQS_OSC_BASE_VALUE_1_0__FLD LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_1_0
  4097. #define LPDDR4__DENALI_PI_274_READ_MASK 0xFFFFFFFFU
  4098. #define LPDDR4__DENALI_PI_274_WRITE_MASK 0xFFFFFFFFU
  4099. #define LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_0_1_MASK 0x0000FFFFU
  4100. #define LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_0_1_SHIFT 0U
  4101. #define LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_0_1_WIDTH 16U
  4102. #define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_1__REG DENALI_PI_274
  4103. #define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_1__FLD LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_0_1
  4104. #define LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_1_1_MASK 0xFFFF0000U
  4105. #define LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_1_1_SHIFT 16U
  4106. #define LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_1_1_WIDTH 16U
  4107. #define LPDDR4__PI_DQS_OSC_BASE_VALUE_1_1__REG DENALI_PI_274
  4108. #define LPDDR4__PI_DQS_OSC_BASE_VALUE_1_1__FLD LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_1_1
  4109. #define LPDDR4__DENALI_PI_275_READ_MASK 0xFFFFFFFFU
  4110. #define LPDDR4__DENALI_PI_275_WRITE_MASK 0xFFFFFFFFU
  4111. #define LPDDR4__DENALI_PI_275__PI_MR1_DATA_F0_0_MASK 0x000000FFU
  4112. #define LPDDR4__DENALI_PI_275__PI_MR1_DATA_F0_0_SHIFT 0U
  4113. #define LPDDR4__DENALI_PI_275__PI_MR1_DATA_F0_0_WIDTH 8U
  4114. #define LPDDR4__PI_MR1_DATA_F0_0__REG DENALI_PI_275
  4115. #define LPDDR4__PI_MR1_DATA_F0_0__FLD LPDDR4__DENALI_PI_275__PI_MR1_DATA_F0_0
  4116. #define LPDDR4__DENALI_PI_275__PI_MR2_DATA_F0_0_MASK 0x0000FF00U
  4117. #define LPDDR4__DENALI_PI_275__PI_MR2_DATA_F0_0_SHIFT 8U
  4118. #define LPDDR4__DENALI_PI_275__PI_MR2_DATA_F0_0_WIDTH 8U
  4119. #define LPDDR4__PI_MR2_DATA_F0_0__REG DENALI_PI_275
  4120. #define LPDDR4__PI_MR2_DATA_F0_0__FLD LPDDR4__DENALI_PI_275__PI_MR2_DATA_F0_0
  4121. #define LPDDR4__DENALI_PI_275__PI_MR3_DATA_F0_0_MASK 0x00FF0000U
  4122. #define LPDDR4__DENALI_PI_275__PI_MR3_DATA_F0_0_SHIFT 16U
  4123. #define LPDDR4__DENALI_PI_275__PI_MR3_DATA_F0_0_WIDTH 8U
  4124. #define LPDDR4__PI_MR3_DATA_F0_0__REG DENALI_PI_275
  4125. #define LPDDR4__PI_MR3_DATA_F0_0__FLD LPDDR4__DENALI_PI_275__PI_MR3_DATA_F0_0
  4126. #define LPDDR4__DENALI_PI_275__PI_MR11_DATA_F0_0_MASK 0xFF000000U
  4127. #define LPDDR4__DENALI_PI_275__PI_MR11_DATA_F0_0_SHIFT 24U
  4128. #define LPDDR4__DENALI_PI_275__PI_MR11_DATA_F0_0_WIDTH 8U
  4129. #define LPDDR4__PI_MR11_DATA_F0_0__REG DENALI_PI_275
  4130. #define LPDDR4__PI_MR11_DATA_F0_0__FLD LPDDR4__DENALI_PI_275__PI_MR11_DATA_F0_0
  4131. #define LPDDR4__DENALI_PI_276_READ_MASK 0xFFFFFFFFU
  4132. #define LPDDR4__DENALI_PI_276_WRITE_MASK 0xFFFFFFFFU
  4133. #define LPDDR4__DENALI_PI_276__PI_MR12_DATA_F0_0_MASK 0x000000FFU
  4134. #define LPDDR4__DENALI_PI_276__PI_MR12_DATA_F0_0_SHIFT 0U
  4135. #define LPDDR4__DENALI_PI_276__PI_MR12_DATA_F0_0_WIDTH 8U
  4136. #define LPDDR4__PI_MR12_DATA_F0_0__REG DENALI_PI_276
  4137. #define LPDDR4__PI_MR12_DATA_F0_0__FLD LPDDR4__DENALI_PI_276__PI_MR12_DATA_F0_0
  4138. #define LPDDR4__DENALI_PI_276__PI_MR14_DATA_F0_0_MASK 0x0000FF00U
  4139. #define LPDDR4__DENALI_PI_276__PI_MR14_DATA_F0_0_SHIFT 8U
  4140. #define LPDDR4__DENALI_PI_276__PI_MR14_DATA_F0_0_WIDTH 8U
  4141. #define LPDDR4__PI_MR14_DATA_F0_0__REG DENALI_PI_276
  4142. #define LPDDR4__PI_MR14_DATA_F0_0__FLD LPDDR4__DENALI_PI_276__PI_MR14_DATA_F0_0
  4143. #define LPDDR4__DENALI_PI_276__PI_MR22_DATA_F0_0_MASK 0x00FF0000U
  4144. #define LPDDR4__DENALI_PI_276__PI_MR22_DATA_F0_0_SHIFT 16U
  4145. #define LPDDR4__DENALI_PI_276__PI_MR22_DATA_F0_0_WIDTH 8U
  4146. #define LPDDR4__PI_MR22_DATA_F0_0__REG DENALI_PI_276
  4147. #define LPDDR4__PI_MR22_DATA_F0_0__FLD LPDDR4__DENALI_PI_276__PI_MR22_DATA_F0_0
  4148. #define LPDDR4__DENALI_PI_276__PI_MR23_DATA_F0_0_MASK 0xFF000000U
  4149. #define LPDDR4__DENALI_PI_276__PI_MR23_DATA_F0_0_SHIFT 24U
  4150. #define LPDDR4__DENALI_PI_276__PI_MR23_DATA_F0_0_WIDTH 8U
  4151. #define LPDDR4__PI_MR23_DATA_F0_0__REG DENALI_PI_276
  4152. #define LPDDR4__PI_MR23_DATA_F0_0__FLD LPDDR4__DENALI_PI_276__PI_MR23_DATA_F0_0
  4153. #define LPDDR4__DENALI_PI_277_READ_MASK 0xFFFFFFFFU
  4154. #define LPDDR4__DENALI_PI_277_WRITE_MASK 0xFFFFFFFFU
  4155. #define LPDDR4__DENALI_PI_277__PI_MR1_DATA_F1_0_MASK 0x000000FFU
  4156. #define LPDDR4__DENALI_PI_277__PI_MR1_DATA_F1_0_SHIFT 0U
  4157. #define LPDDR4__DENALI_PI_277__PI_MR1_DATA_F1_0_WIDTH 8U
  4158. #define LPDDR4__PI_MR1_DATA_F1_0__REG DENALI_PI_277
  4159. #define LPDDR4__PI_MR1_DATA_F1_0__FLD LPDDR4__DENALI_PI_277__PI_MR1_DATA_F1_0
  4160. #define LPDDR4__DENALI_PI_277__PI_MR2_DATA_F1_0_MASK 0x0000FF00U
  4161. #define LPDDR4__DENALI_PI_277__PI_MR2_DATA_F1_0_SHIFT 8U
  4162. #define LPDDR4__DENALI_PI_277__PI_MR2_DATA_F1_0_WIDTH 8U
  4163. #define LPDDR4__PI_MR2_DATA_F1_0__REG DENALI_PI_277
  4164. #define LPDDR4__PI_MR2_DATA_F1_0__FLD LPDDR4__DENALI_PI_277__PI_MR2_DATA_F1_0
  4165. #define LPDDR4__DENALI_PI_277__PI_MR3_DATA_F1_0_MASK 0x00FF0000U
  4166. #define LPDDR4__DENALI_PI_277__PI_MR3_DATA_F1_0_SHIFT 16U
  4167. #define LPDDR4__DENALI_PI_277__PI_MR3_DATA_F1_0_WIDTH 8U
  4168. #define LPDDR4__PI_MR3_DATA_F1_0__REG DENALI_PI_277
  4169. #define LPDDR4__PI_MR3_DATA_F1_0__FLD LPDDR4__DENALI_PI_277__PI_MR3_DATA_F1_0
  4170. #define LPDDR4__DENALI_PI_277__PI_MR11_DATA_F1_0_MASK 0xFF000000U
  4171. #define LPDDR4__DENALI_PI_277__PI_MR11_DATA_F1_0_SHIFT 24U
  4172. #define LPDDR4__DENALI_PI_277__PI_MR11_DATA_F1_0_WIDTH 8U
  4173. #define LPDDR4__PI_MR11_DATA_F1_0__REG DENALI_PI_277
  4174. #define LPDDR4__PI_MR11_DATA_F1_0__FLD LPDDR4__DENALI_PI_277__PI_MR11_DATA_F1_0
  4175. #define LPDDR4__DENALI_PI_278_READ_MASK 0xFFFFFFFFU
  4176. #define LPDDR4__DENALI_PI_278_WRITE_MASK 0xFFFFFFFFU
  4177. #define LPDDR4__DENALI_PI_278__PI_MR12_DATA_F1_0_MASK 0x000000FFU
  4178. #define LPDDR4__DENALI_PI_278__PI_MR12_DATA_F1_0_SHIFT 0U
  4179. #define LPDDR4__DENALI_PI_278__PI_MR12_DATA_F1_0_WIDTH 8U
  4180. #define LPDDR4__PI_MR12_DATA_F1_0__REG DENALI_PI_278
  4181. #define LPDDR4__PI_MR12_DATA_F1_0__FLD LPDDR4__DENALI_PI_278__PI_MR12_DATA_F1_0
  4182. #define LPDDR4__DENALI_PI_278__PI_MR14_DATA_F1_0_MASK 0x0000FF00U
  4183. #define LPDDR4__DENALI_PI_278__PI_MR14_DATA_F1_0_SHIFT 8U
  4184. #define LPDDR4__DENALI_PI_278__PI_MR14_DATA_F1_0_WIDTH 8U
  4185. #define LPDDR4__PI_MR14_DATA_F1_0__REG DENALI_PI_278
  4186. #define LPDDR4__PI_MR14_DATA_F1_0__FLD LPDDR4__DENALI_PI_278__PI_MR14_DATA_F1_0
  4187. #define LPDDR4__DENALI_PI_278__PI_MR22_DATA_F1_0_MASK 0x00FF0000U
  4188. #define LPDDR4__DENALI_PI_278__PI_MR22_DATA_F1_0_SHIFT 16U
  4189. #define LPDDR4__DENALI_PI_278__PI_MR22_DATA_F1_0_WIDTH 8U
  4190. #define LPDDR4__PI_MR22_DATA_F1_0__REG DENALI_PI_278
  4191. #define LPDDR4__PI_MR22_DATA_F1_0__FLD LPDDR4__DENALI_PI_278__PI_MR22_DATA_F1_0
  4192. #define LPDDR4__DENALI_PI_278__PI_MR23_DATA_F1_0_MASK 0xFF000000U
  4193. #define LPDDR4__DENALI_PI_278__PI_MR23_DATA_F1_0_SHIFT 24U
  4194. #define LPDDR4__DENALI_PI_278__PI_MR23_DATA_F1_0_WIDTH 8U
  4195. #define LPDDR4__PI_MR23_DATA_F1_0__REG DENALI_PI_278
  4196. #define LPDDR4__PI_MR23_DATA_F1_0__FLD LPDDR4__DENALI_PI_278__PI_MR23_DATA_F1_0
  4197. #define LPDDR4__DENALI_PI_279_READ_MASK 0xFFFFFFFFU
  4198. #define LPDDR4__DENALI_PI_279_WRITE_MASK 0xFFFFFFFFU
  4199. #define LPDDR4__DENALI_PI_279__PI_MR1_DATA_F2_0_MASK 0x000000FFU
  4200. #define LPDDR4__DENALI_PI_279__PI_MR1_DATA_F2_0_SHIFT 0U
  4201. #define LPDDR4__DENALI_PI_279__PI_MR1_DATA_F2_0_WIDTH 8U
  4202. #define LPDDR4__PI_MR1_DATA_F2_0__REG DENALI_PI_279
  4203. #define LPDDR4__PI_MR1_DATA_F2_0__FLD LPDDR4__DENALI_PI_279__PI_MR1_DATA_F2_0
  4204. #define LPDDR4__DENALI_PI_279__PI_MR2_DATA_F2_0_MASK 0x0000FF00U
  4205. #define LPDDR4__DENALI_PI_279__PI_MR2_DATA_F2_0_SHIFT 8U
  4206. #define LPDDR4__DENALI_PI_279__PI_MR2_DATA_F2_0_WIDTH 8U
  4207. #define LPDDR4__PI_MR2_DATA_F2_0__REG DENALI_PI_279
  4208. #define LPDDR4__PI_MR2_DATA_F2_0__FLD LPDDR4__DENALI_PI_279__PI_MR2_DATA_F2_0
  4209. #define LPDDR4__DENALI_PI_279__PI_MR3_DATA_F2_0_MASK 0x00FF0000U
  4210. #define LPDDR4__DENALI_PI_279__PI_MR3_DATA_F2_0_SHIFT 16U
  4211. #define LPDDR4__DENALI_PI_279__PI_MR3_DATA_F2_0_WIDTH 8U
  4212. #define LPDDR4__PI_MR3_DATA_F2_0__REG DENALI_PI_279
  4213. #define LPDDR4__PI_MR3_DATA_F2_0__FLD LPDDR4__DENALI_PI_279__PI_MR3_DATA_F2_0
  4214. #define LPDDR4__DENALI_PI_279__PI_MR11_DATA_F2_0_MASK 0xFF000000U
  4215. #define LPDDR4__DENALI_PI_279__PI_MR11_DATA_F2_0_SHIFT 24U
  4216. #define LPDDR4__DENALI_PI_279__PI_MR11_DATA_F2_0_WIDTH 8U
  4217. #define LPDDR4__PI_MR11_DATA_F2_0__REG DENALI_PI_279
  4218. #define LPDDR4__PI_MR11_DATA_F2_0__FLD LPDDR4__DENALI_PI_279__PI_MR11_DATA_F2_0
  4219. #define LPDDR4__DENALI_PI_280_READ_MASK 0xFFFFFFFFU
  4220. #define LPDDR4__DENALI_PI_280_WRITE_MASK 0xFFFFFFFFU
  4221. #define LPDDR4__DENALI_PI_280__PI_MR12_DATA_F2_0_MASK 0x000000FFU
  4222. #define LPDDR4__DENALI_PI_280__PI_MR12_DATA_F2_0_SHIFT 0U
  4223. #define LPDDR4__DENALI_PI_280__PI_MR12_DATA_F2_0_WIDTH 8U
  4224. #define LPDDR4__PI_MR12_DATA_F2_0__REG DENALI_PI_280
  4225. #define LPDDR4__PI_MR12_DATA_F2_0__FLD LPDDR4__DENALI_PI_280__PI_MR12_DATA_F2_0
  4226. #define LPDDR4__DENALI_PI_280__PI_MR14_DATA_F2_0_MASK 0x0000FF00U
  4227. #define LPDDR4__DENALI_PI_280__PI_MR14_DATA_F2_0_SHIFT 8U
  4228. #define LPDDR4__DENALI_PI_280__PI_MR14_DATA_F2_0_WIDTH 8U
  4229. #define LPDDR4__PI_MR14_DATA_F2_0__REG DENALI_PI_280
  4230. #define LPDDR4__PI_MR14_DATA_F2_0__FLD LPDDR4__DENALI_PI_280__PI_MR14_DATA_F2_0
  4231. #define LPDDR4__DENALI_PI_280__PI_MR22_DATA_F2_0_MASK 0x00FF0000U
  4232. #define LPDDR4__DENALI_PI_280__PI_MR22_DATA_F2_0_SHIFT 16U
  4233. #define LPDDR4__DENALI_PI_280__PI_MR22_DATA_F2_0_WIDTH 8U
  4234. #define LPDDR4__PI_MR22_DATA_F2_0__REG DENALI_PI_280
  4235. #define LPDDR4__PI_MR22_DATA_F2_0__FLD LPDDR4__DENALI_PI_280__PI_MR22_DATA_F2_0
  4236. #define LPDDR4__DENALI_PI_280__PI_MR23_DATA_F2_0_MASK 0xFF000000U
  4237. #define LPDDR4__DENALI_PI_280__PI_MR23_DATA_F2_0_SHIFT 24U
  4238. #define LPDDR4__DENALI_PI_280__PI_MR23_DATA_F2_0_WIDTH 8U
  4239. #define LPDDR4__PI_MR23_DATA_F2_0__REG DENALI_PI_280
  4240. #define LPDDR4__PI_MR23_DATA_F2_0__FLD LPDDR4__DENALI_PI_280__PI_MR23_DATA_F2_0
  4241. #define LPDDR4__DENALI_PI_281_READ_MASK 0xFFFFFFFFU
  4242. #define LPDDR4__DENALI_PI_281_WRITE_MASK 0xFFFFFFFFU
  4243. #define LPDDR4__DENALI_PI_281__PI_MR1_DATA_F0_1_MASK 0x000000FFU
  4244. #define LPDDR4__DENALI_PI_281__PI_MR1_DATA_F0_1_SHIFT 0U
  4245. #define LPDDR4__DENALI_PI_281__PI_MR1_DATA_F0_1_WIDTH 8U
  4246. #define LPDDR4__PI_MR1_DATA_F0_1__REG DENALI_PI_281
  4247. #define LPDDR4__PI_MR1_DATA_F0_1__FLD LPDDR4__DENALI_PI_281__PI_MR1_DATA_F0_1
  4248. #define LPDDR4__DENALI_PI_281__PI_MR2_DATA_F0_1_MASK 0x0000FF00U
  4249. #define LPDDR4__DENALI_PI_281__PI_MR2_DATA_F0_1_SHIFT 8U
  4250. #define LPDDR4__DENALI_PI_281__PI_MR2_DATA_F0_1_WIDTH 8U
  4251. #define LPDDR4__PI_MR2_DATA_F0_1__REG DENALI_PI_281
  4252. #define LPDDR4__PI_MR2_DATA_F0_1__FLD LPDDR4__DENALI_PI_281__PI_MR2_DATA_F0_1
  4253. #define LPDDR4__DENALI_PI_281__PI_MR3_DATA_F0_1_MASK 0x00FF0000U
  4254. #define LPDDR4__DENALI_PI_281__PI_MR3_DATA_F0_1_SHIFT 16U
  4255. #define LPDDR4__DENALI_PI_281__PI_MR3_DATA_F0_1_WIDTH 8U
  4256. #define LPDDR4__PI_MR3_DATA_F0_1__REG DENALI_PI_281
  4257. #define LPDDR4__PI_MR3_DATA_F0_1__FLD LPDDR4__DENALI_PI_281__PI_MR3_DATA_F0_1
  4258. #define LPDDR4__DENALI_PI_281__PI_MR11_DATA_F0_1_MASK 0xFF000000U
  4259. #define LPDDR4__DENALI_PI_281__PI_MR11_DATA_F0_1_SHIFT 24U
  4260. #define LPDDR4__DENALI_PI_281__PI_MR11_DATA_F0_1_WIDTH 8U
  4261. #define LPDDR4__PI_MR11_DATA_F0_1__REG DENALI_PI_281
  4262. #define LPDDR4__PI_MR11_DATA_F0_1__FLD LPDDR4__DENALI_PI_281__PI_MR11_DATA_F0_1
  4263. #define LPDDR4__DENALI_PI_282_READ_MASK 0xFFFFFFFFU
  4264. #define LPDDR4__DENALI_PI_282_WRITE_MASK 0xFFFFFFFFU
  4265. #define LPDDR4__DENALI_PI_282__PI_MR12_DATA_F0_1_MASK 0x000000FFU
  4266. #define LPDDR4__DENALI_PI_282__PI_MR12_DATA_F0_1_SHIFT 0U
  4267. #define LPDDR4__DENALI_PI_282__PI_MR12_DATA_F0_1_WIDTH 8U
  4268. #define LPDDR4__PI_MR12_DATA_F0_1__REG DENALI_PI_282
  4269. #define LPDDR4__PI_MR12_DATA_F0_1__FLD LPDDR4__DENALI_PI_282__PI_MR12_DATA_F0_1
  4270. #define LPDDR4__DENALI_PI_282__PI_MR14_DATA_F0_1_MASK 0x0000FF00U
  4271. #define LPDDR4__DENALI_PI_282__PI_MR14_DATA_F0_1_SHIFT 8U
  4272. #define LPDDR4__DENALI_PI_282__PI_MR14_DATA_F0_1_WIDTH 8U
  4273. #define LPDDR4__PI_MR14_DATA_F0_1__REG DENALI_PI_282
  4274. #define LPDDR4__PI_MR14_DATA_F0_1__FLD LPDDR4__DENALI_PI_282__PI_MR14_DATA_F0_1
  4275. #define LPDDR4__DENALI_PI_282__PI_MR22_DATA_F0_1_MASK 0x00FF0000U
  4276. #define LPDDR4__DENALI_PI_282__PI_MR22_DATA_F0_1_SHIFT 16U
  4277. #define LPDDR4__DENALI_PI_282__PI_MR22_DATA_F0_1_WIDTH 8U
  4278. #define LPDDR4__PI_MR22_DATA_F0_1__REG DENALI_PI_282
  4279. #define LPDDR4__PI_MR22_DATA_F0_1__FLD LPDDR4__DENALI_PI_282__PI_MR22_DATA_F0_1
  4280. #define LPDDR4__DENALI_PI_282__PI_MR23_DATA_F0_1_MASK 0xFF000000U
  4281. #define LPDDR4__DENALI_PI_282__PI_MR23_DATA_F0_1_SHIFT 24U
  4282. #define LPDDR4__DENALI_PI_282__PI_MR23_DATA_F0_1_WIDTH 8U
  4283. #define LPDDR4__PI_MR23_DATA_F0_1__REG DENALI_PI_282
  4284. #define LPDDR4__PI_MR23_DATA_F0_1__FLD LPDDR4__DENALI_PI_282__PI_MR23_DATA_F0_1
  4285. #define LPDDR4__DENALI_PI_283_READ_MASK 0xFFFFFFFFU
  4286. #define LPDDR4__DENALI_PI_283_WRITE_MASK 0xFFFFFFFFU
  4287. #define LPDDR4__DENALI_PI_283__PI_MR1_DATA_F1_1_MASK 0x000000FFU
  4288. #define LPDDR4__DENALI_PI_283__PI_MR1_DATA_F1_1_SHIFT 0U
  4289. #define LPDDR4__DENALI_PI_283__PI_MR1_DATA_F1_1_WIDTH 8U
  4290. #define LPDDR4__PI_MR1_DATA_F1_1__REG DENALI_PI_283
  4291. #define LPDDR4__PI_MR1_DATA_F1_1__FLD LPDDR4__DENALI_PI_283__PI_MR1_DATA_F1_1
  4292. #define LPDDR4__DENALI_PI_283__PI_MR2_DATA_F1_1_MASK 0x0000FF00U
  4293. #define LPDDR4__DENALI_PI_283__PI_MR2_DATA_F1_1_SHIFT 8U
  4294. #define LPDDR4__DENALI_PI_283__PI_MR2_DATA_F1_1_WIDTH 8U
  4295. #define LPDDR4__PI_MR2_DATA_F1_1__REG DENALI_PI_283
  4296. #define LPDDR4__PI_MR2_DATA_F1_1__FLD LPDDR4__DENALI_PI_283__PI_MR2_DATA_F1_1
  4297. #define LPDDR4__DENALI_PI_283__PI_MR3_DATA_F1_1_MASK 0x00FF0000U
  4298. #define LPDDR4__DENALI_PI_283__PI_MR3_DATA_F1_1_SHIFT 16U
  4299. #define LPDDR4__DENALI_PI_283__PI_MR3_DATA_F1_1_WIDTH 8U
  4300. #define LPDDR4__PI_MR3_DATA_F1_1__REG DENALI_PI_283
  4301. #define LPDDR4__PI_MR3_DATA_F1_1__FLD LPDDR4__DENALI_PI_283__PI_MR3_DATA_F1_1
  4302. #define LPDDR4__DENALI_PI_283__PI_MR11_DATA_F1_1_MASK 0xFF000000U
  4303. #define LPDDR4__DENALI_PI_283__PI_MR11_DATA_F1_1_SHIFT 24U
  4304. #define LPDDR4__DENALI_PI_283__PI_MR11_DATA_F1_1_WIDTH 8U
  4305. #define LPDDR4__PI_MR11_DATA_F1_1__REG DENALI_PI_283
  4306. #define LPDDR4__PI_MR11_DATA_F1_1__FLD LPDDR4__DENALI_PI_283__PI_MR11_DATA_F1_1
  4307. #define LPDDR4__DENALI_PI_284_READ_MASK 0xFFFFFFFFU
  4308. #define LPDDR4__DENALI_PI_284_WRITE_MASK 0xFFFFFFFFU
  4309. #define LPDDR4__DENALI_PI_284__PI_MR12_DATA_F1_1_MASK 0x000000FFU
  4310. #define LPDDR4__DENALI_PI_284__PI_MR12_DATA_F1_1_SHIFT 0U
  4311. #define LPDDR4__DENALI_PI_284__PI_MR12_DATA_F1_1_WIDTH 8U
  4312. #define LPDDR4__PI_MR12_DATA_F1_1__REG DENALI_PI_284
  4313. #define LPDDR4__PI_MR12_DATA_F1_1__FLD LPDDR4__DENALI_PI_284__PI_MR12_DATA_F1_1
  4314. #define LPDDR4__DENALI_PI_284__PI_MR14_DATA_F1_1_MASK 0x0000FF00U
  4315. #define LPDDR4__DENALI_PI_284__PI_MR14_DATA_F1_1_SHIFT 8U
  4316. #define LPDDR4__DENALI_PI_284__PI_MR14_DATA_F1_1_WIDTH 8U
  4317. #define LPDDR4__PI_MR14_DATA_F1_1__REG DENALI_PI_284
  4318. #define LPDDR4__PI_MR14_DATA_F1_1__FLD LPDDR4__DENALI_PI_284__PI_MR14_DATA_F1_1
  4319. #define LPDDR4__DENALI_PI_284__PI_MR22_DATA_F1_1_MASK 0x00FF0000U
  4320. #define LPDDR4__DENALI_PI_284__PI_MR22_DATA_F1_1_SHIFT 16U
  4321. #define LPDDR4__DENALI_PI_284__PI_MR22_DATA_F1_1_WIDTH 8U
  4322. #define LPDDR4__PI_MR22_DATA_F1_1__REG DENALI_PI_284
  4323. #define LPDDR4__PI_MR22_DATA_F1_1__FLD LPDDR4__DENALI_PI_284__PI_MR22_DATA_F1_1
  4324. #define LPDDR4__DENALI_PI_284__PI_MR23_DATA_F1_1_MASK 0xFF000000U
  4325. #define LPDDR4__DENALI_PI_284__PI_MR23_DATA_F1_1_SHIFT 24U
  4326. #define LPDDR4__DENALI_PI_284__PI_MR23_DATA_F1_1_WIDTH 8U
  4327. #define LPDDR4__PI_MR23_DATA_F1_1__REG DENALI_PI_284
  4328. #define LPDDR4__PI_MR23_DATA_F1_1__FLD LPDDR4__DENALI_PI_284__PI_MR23_DATA_F1_1
  4329. #define LPDDR4__DENALI_PI_285_READ_MASK 0xFFFFFFFFU
  4330. #define LPDDR4__DENALI_PI_285_WRITE_MASK 0xFFFFFFFFU
  4331. #define LPDDR4__DENALI_PI_285__PI_MR1_DATA_F2_1_MASK 0x000000FFU
  4332. #define LPDDR4__DENALI_PI_285__PI_MR1_DATA_F2_1_SHIFT 0U
  4333. #define LPDDR4__DENALI_PI_285__PI_MR1_DATA_F2_1_WIDTH 8U
  4334. #define LPDDR4__PI_MR1_DATA_F2_1__REG DENALI_PI_285
  4335. #define LPDDR4__PI_MR1_DATA_F2_1__FLD LPDDR4__DENALI_PI_285__PI_MR1_DATA_F2_1
  4336. #define LPDDR4__DENALI_PI_285__PI_MR2_DATA_F2_1_MASK 0x0000FF00U
  4337. #define LPDDR4__DENALI_PI_285__PI_MR2_DATA_F2_1_SHIFT 8U
  4338. #define LPDDR4__DENALI_PI_285__PI_MR2_DATA_F2_1_WIDTH 8U
  4339. #define LPDDR4__PI_MR2_DATA_F2_1__REG DENALI_PI_285
  4340. #define LPDDR4__PI_MR2_DATA_F2_1__FLD LPDDR4__DENALI_PI_285__PI_MR2_DATA_F2_1
  4341. #define LPDDR4__DENALI_PI_285__PI_MR3_DATA_F2_1_MASK 0x00FF0000U
  4342. #define LPDDR4__DENALI_PI_285__PI_MR3_DATA_F2_1_SHIFT 16U
  4343. #define LPDDR4__DENALI_PI_285__PI_MR3_DATA_F2_1_WIDTH 8U
  4344. #define LPDDR4__PI_MR3_DATA_F2_1__REG DENALI_PI_285
  4345. #define LPDDR4__PI_MR3_DATA_F2_1__FLD LPDDR4__DENALI_PI_285__PI_MR3_DATA_F2_1
  4346. #define LPDDR4__DENALI_PI_285__PI_MR11_DATA_F2_1_MASK 0xFF000000U
  4347. #define LPDDR4__DENALI_PI_285__PI_MR11_DATA_F2_1_SHIFT 24U
  4348. #define LPDDR4__DENALI_PI_285__PI_MR11_DATA_F2_1_WIDTH 8U
  4349. #define LPDDR4__PI_MR11_DATA_F2_1__REG DENALI_PI_285
  4350. #define LPDDR4__PI_MR11_DATA_F2_1__FLD LPDDR4__DENALI_PI_285__PI_MR11_DATA_F2_1
  4351. #define LPDDR4__DENALI_PI_286_READ_MASK 0xFFFFFFFFU
  4352. #define LPDDR4__DENALI_PI_286_WRITE_MASK 0xFFFFFFFFU
  4353. #define LPDDR4__DENALI_PI_286__PI_MR12_DATA_F2_1_MASK 0x000000FFU
  4354. #define LPDDR4__DENALI_PI_286__PI_MR12_DATA_F2_1_SHIFT 0U
  4355. #define LPDDR4__DENALI_PI_286__PI_MR12_DATA_F2_1_WIDTH 8U
  4356. #define LPDDR4__PI_MR12_DATA_F2_1__REG DENALI_PI_286
  4357. #define LPDDR4__PI_MR12_DATA_F2_1__FLD LPDDR4__DENALI_PI_286__PI_MR12_DATA_F2_1
  4358. #define LPDDR4__DENALI_PI_286__PI_MR14_DATA_F2_1_MASK 0x0000FF00U
  4359. #define LPDDR4__DENALI_PI_286__PI_MR14_DATA_F2_1_SHIFT 8U
  4360. #define LPDDR4__DENALI_PI_286__PI_MR14_DATA_F2_1_WIDTH 8U
  4361. #define LPDDR4__PI_MR14_DATA_F2_1__REG DENALI_PI_286
  4362. #define LPDDR4__PI_MR14_DATA_F2_1__FLD LPDDR4__DENALI_PI_286__PI_MR14_DATA_F2_1
  4363. #define LPDDR4__DENALI_PI_286__PI_MR22_DATA_F2_1_MASK 0x00FF0000U
  4364. #define LPDDR4__DENALI_PI_286__PI_MR22_DATA_F2_1_SHIFT 16U
  4365. #define LPDDR4__DENALI_PI_286__PI_MR22_DATA_F2_1_WIDTH 8U
  4366. #define LPDDR4__PI_MR22_DATA_F2_1__REG DENALI_PI_286
  4367. #define LPDDR4__PI_MR22_DATA_F2_1__FLD LPDDR4__DENALI_PI_286__PI_MR22_DATA_F2_1
  4368. #define LPDDR4__DENALI_PI_286__PI_MR23_DATA_F2_1_MASK 0xFF000000U
  4369. #define LPDDR4__DENALI_PI_286__PI_MR23_DATA_F2_1_SHIFT 24U
  4370. #define LPDDR4__DENALI_PI_286__PI_MR23_DATA_F2_1_WIDTH 8U
  4371. #define LPDDR4__PI_MR23_DATA_F2_1__REG DENALI_PI_286
  4372. #define LPDDR4__PI_MR23_DATA_F2_1__FLD LPDDR4__DENALI_PI_286__PI_MR23_DATA_F2_1
  4373. #define LPDDR4__DENALI_PI_287_READ_MASK 0xFFFFFFFFU
  4374. #define LPDDR4__DENALI_PI_287_WRITE_MASK 0xFFFFFFFFU
  4375. #define LPDDR4__DENALI_PI_287__PI_MR1_DATA_F0_2_MASK 0x000000FFU
  4376. #define LPDDR4__DENALI_PI_287__PI_MR1_DATA_F0_2_SHIFT 0U
  4377. #define LPDDR4__DENALI_PI_287__PI_MR1_DATA_F0_2_WIDTH 8U
  4378. #define LPDDR4__PI_MR1_DATA_F0_2__REG DENALI_PI_287
  4379. #define LPDDR4__PI_MR1_DATA_F0_2__FLD LPDDR4__DENALI_PI_287__PI_MR1_DATA_F0_2
  4380. #define LPDDR4__DENALI_PI_287__PI_MR2_DATA_F0_2_MASK 0x0000FF00U
  4381. #define LPDDR4__DENALI_PI_287__PI_MR2_DATA_F0_2_SHIFT 8U
  4382. #define LPDDR4__DENALI_PI_287__PI_MR2_DATA_F0_2_WIDTH 8U
  4383. #define LPDDR4__PI_MR2_DATA_F0_2__REG DENALI_PI_287
  4384. #define LPDDR4__PI_MR2_DATA_F0_2__FLD LPDDR4__DENALI_PI_287__PI_MR2_DATA_F0_2
  4385. #define LPDDR4__DENALI_PI_287__PI_MR3_DATA_F0_2_MASK 0x00FF0000U
  4386. #define LPDDR4__DENALI_PI_287__PI_MR3_DATA_F0_2_SHIFT 16U
  4387. #define LPDDR4__DENALI_PI_287__PI_MR3_DATA_F0_2_WIDTH 8U
  4388. #define LPDDR4__PI_MR3_DATA_F0_2__REG DENALI_PI_287
  4389. #define LPDDR4__PI_MR3_DATA_F0_2__FLD LPDDR4__DENALI_PI_287__PI_MR3_DATA_F0_2
  4390. #define LPDDR4__DENALI_PI_287__PI_MR11_DATA_F0_2_MASK 0xFF000000U
  4391. #define LPDDR4__DENALI_PI_287__PI_MR11_DATA_F0_2_SHIFT 24U
  4392. #define LPDDR4__DENALI_PI_287__PI_MR11_DATA_F0_2_WIDTH 8U
  4393. #define LPDDR4__PI_MR11_DATA_F0_2__REG DENALI_PI_287
  4394. #define LPDDR4__PI_MR11_DATA_F0_2__FLD LPDDR4__DENALI_PI_287__PI_MR11_DATA_F0_2
  4395. #define LPDDR4__DENALI_PI_288_READ_MASK 0xFFFFFFFFU
  4396. #define LPDDR4__DENALI_PI_288_WRITE_MASK 0xFFFFFFFFU
  4397. #define LPDDR4__DENALI_PI_288__PI_MR12_DATA_F0_2_MASK 0x000000FFU
  4398. #define LPDDR4__DENALI_PI_288__PI_MR12_DATA_F0_2_SHIFT 0U
  4399. #define LPDDR4__DENALI_PI_288__PI_MR12_DATA_F0_2_WIDTH 8U
  4400. #define LPDDR4__PI_MR12_DATA_F0_2__REG DENALI_PI_288
  4401. #define LPDDR4__PI_MR12_DATA_F0_2__FLD LPDDR4__DENALI_PI_288__PI_MR12_DATA_F0_2
  4402. #define LPDDR4__DENALI_PI_288__PI_MR14_DATA_F0_2_MASK 0x0000FF00U
  4403. #define LPDDR4__DENALI_PI_288__PI_MR14_DATA_F0_2_SHIFT 8U
  4404. #define LPDDR4__DENALI_PI_288__PI_MR14_DATA_F0_2_WIDTH 8U
  4405. #define LPDDR4__PI_MR14_DATA_F0_2__REG DENALI_PI_288
  4406. #define LPDDR4__PI_MR14_DATA_F0_2__FLD LPDDR4__DENALI_PI_288__PI_MR14_DATA_F0_2
  4407. #define LPDDR4__DENALI_PI_288__PI_MR22_DATA_F0_2_MASK 0x00FF0000U
  4408. #define LPDDR4__DENALI_PI_288__PI_MR22_DATA_F0_2_SHIFT 16U
  4409. #define LPDDR4__DENALI_PI_288__PI_MR22_DATA_F0_2_WIDTH 8U
  4410. #define LPDDR4__PI_MR22_DATA_F0_2__REG DENALI_PI_288
  4411. #define LPDDR4__PI_MR22_DATA_F0_2__FLD LPDDR4__DENALI_PI_288__PI_MR22_DATA_F0_2
  4412. #define LPDDR4__DENALI_PI_288__PI_MR23_DATA_F0_2_MASK 0xFF000000U
  4413. #define LPDDR4__DENALI_PI_288__PI_MR23_DATA_F0_2_SHIFT 24U
  4414. #define LPDDR4__DENALI_PI_288__PI_MR23_DATA_F0_2_WIDTH 8U
  4415. #define LPDDR4__PI_MR23_DATA_F0_2__REG DENALI_PI_288
  4416. #define LPDDR4__PI_MR23_DATA_F0_2__FLD LPDDR4__DENALI_PI_288__PI_MR23_DATA_F0_2
  4417. #define LPDDR4__DENALI_PI_289_READ_MASK 0xFFFFFFFFU
  4418. #define LPDDR4__DENALI_PI_289_WRITE_MASK 0xFFFFFFFFU
  4419. #define LPDDR4__DENALI_PI_289__PI_MR1_DATA_F1_2_MASK 0x000000FFU
  4420. #define LPDDR4__DENALI_PI_289__PI_MR1_DATA_F1_2_SHIFT 0U
  4421. #define LPDDR4__DENALI_PI_289__PI_MR1_DATA_F1_2_WIDTH 8U
  4422. #define LPDDR4__PI_MR1_DATA_F1_2__REG DENALI_PI_289
  4423. #define LPDDR4__PI_MR1_DATA_F1_2__FLD LPDDR4__DENALI_PI_289__PI_MR1_DATA_F1_2
  4424. #define LPDDR4__DENALI_PI_289__PI_MR2_DATA_F1_2_MASK 0x0000FF00U
  4425. #define LPDDR4__DENALI_PI_289__PI_MR2_DATA_F1_2_SHIFT 8U
  4426. #define LPDDR4__DENALI_PI_289__PI_MR2_DATA_F1_2_WIDTH 8U
  4427. #define LPDDR4__PI_MR2_DATA_F1_2__REG DENALI_PI_289
  4428. #define LPDDR4__PI_MR2_DATA_F1_2__FLD LPDDR4__DENALI_PI_289__PI_MR2_DATA_F1_2
  4429. #define LPDDR4__DENALI_PI_289__PI_MR3_DATA_F1_2_MASK 0x00FF0000U
  4430. #define LPDDR4__DENALI_PI_289__PI_MR3_DATA_F1_2_SHIFT 16U
  4431. #define LPDDR4__DENALI_PI_289__PI_MR3_DATA_F1_2_WIDTH 8U
  4432. #define LPDDR4__PI_MR3_DATA_F1_2__REG DENALI_PI_289
  4433. #define LPDDR4__PI_MR3_DATA_F1_2__FLD LPDDR4__DENALI_PI_289__PI_MR3_DATA_F1_2
  4434. #define LPDDR4__DENALI_PI_289__PI_MR11_DATA_F1_2_MASK 0xFF000000U
  4435. #define LPDDR4__DENALI_PI_289__PI_MR11_DATA_F1_2_SHIFT 24U
  4436. #define LPDDR4__DENALI_PI_289__PI_MR11_DATA_F1_2_WIDTH 8U
  4437. #define LPDDR4__PI_MR11_DATA_F1_2__REG DENALI_PI_289
  4438. #define LPDDR4__PI_MR11_DATA_F1_2__FLD LPDDR4__DENALI_PI_289__PI_MR11_DATA_F1_2
  4439. #define LPDDR4__DENALI_PI_290_READ_MASK 0xFFFFFFFFU
  4440. #define LPDDR4__DENALI_PI_290_WRITE_MASK 0xFFFFFFFFU
  4441. #define LPDDR4__DENALI_PI_290__PI_MR12_DATA_F1_2_MASK 0x000000FFU
  4442. #define LPDDR4__DENALI_PI_290__PI_MR12_DATA_F1_2_SHIFT 0U
  4443. #define LPDDR4__DENALI_PI_290__PI_MR12_DATA_F1_2_WIDTH 8U
  4444. #define LPDDR4__PI_MR12_DATA_F1_2__REG DENALI_PI_290
  4445. #define LPDDR4__PI_MR12_DATA_F1_2__FLD LPDDR4__DENALI_PI_290__PI_MR12_DATA_F1_2
  4446. #define LPDDR4__DENALI_PI_290__PI_MR14_DATA_F1_2_MASK 0x0000FF00U
  4447. #define LPDDR4__DENALI_PI_290__PI_MR14_DATA_F1_2_SHIFT 8U
  4448. #define LPDDR4__DENALI_PI_290__PI_MR14_DATA_F1_2_WIDTH 8U
  4449. #define LPDDR4__PI_MR14_DATA_F1_2__REG DENALI_PI_290
  4450. #define LPDDR4__PI_MR14_DATA_F1_2__FLD LPDDR4__DENALI_PI_290__PI_MR14_DATA_F1_2
  4451. #define LPDDR4__DENALI_PI_290__PI_MR22_DATA_F1_2_MASK 0x00FF0000U
  4452. #define LPDDR4__DENALI_PI_290__PI_MR22_DATA_F1_2_SHIFT 16U
  4453. #define LPDDR4__DENALI_PI_290__PI_MR22_DATA_F1_2_WIDTH 8U
  4454. #define LPDDR4__PI_MR22_DATA_F1_2__REG DENALI_PI_290
  4455. #define LPDDR4__PI_MR22_DATA_F1_2__FLD LPDDR4__DENALI_PI_290__PI_MR22_DATA_F1_2
  4456. #define LPDDR4__DENALI_PI_290__PI_MR23_DATA_F1_2_MASK 0xFF000000U
  4457. #define LPDDR4__DENALI_PI_290__PI_MR23_DATA_F1_2_SHIFT 24U
  4458. #define LPDDR4__DENALI_PI_290__PI_MR23_DATA_F1_2_WIDTH 8U
  4459. #define LPDDR4__PI_MR23_DATA_F1_2__REG DENALI_PI_290
  4460. #define LPDDR4__PI_MR23_DATA_F1_2__FLD LPDDR4__DENALI_PI_290__PI_MR23_DATA_F1_2
  4461. #define LPDDR4__DENALI_PI_291_READ_MASK 0xFFFFFFFFU
  4462. #define LPDDR4__DENALI_PI_291_WRITE_MASK 0xFFFFFFFFU
  4463. #define LPDDR4__DENALI_PI_291__PI_MR1_DATA_F2_2_MASK 0x000000FFU
  4464. #define LPDDR4__DENALI_PI_291__PI_MR1_DATA_F2_2_SHIFT 0U
  4465. #define LPDDR4__DENALI_PI_291__PI_MR1_DATA_F2_2_WIDTH 8U
  4466. #define LPDDR4__PI_MR1_DATA_F2_2__REG DENALI_PI_291
  4467. #define LPDDR4__PI_MR1_DATA_F2_2__FLD LPDDR4__DENALI_PI_291__PI_MR1_DATA_F2_2
  4468. #define LPDDR4__DENALI_PI_291__PI_MR2_DATA_F2_2_MASK 0x0000FF00U
  4469. #define LPDDR4__DENALI_PI_291__PI_MR2_DATA_F2_2_SHIFT 8U
  4470. #define LPDDR4__DENALI_PI_291__PI_MR2_DATA_F2_2_WIDTH 8U
  4471. #define LPDDR4__PI_MR2_DATA_F2_2__REG DENALI_PI_291
  4472. #define LPDDR4__PI_MR2_DATA_F2_2__FLD LPDDR4__DENALI_PI_291__PI_MR2_DATA_F2_2
  4473. #define LPDDR4__DENALI_PI_291__PI_MR3_DATA_F2_2_MASK 0x00FF0000U
  4474. #define LPDDR4__DENALI_PI_291__PI_MR3_DATA_F2_2_SHIFT 16U
  4475. #define LPDDR4__DENALI_PI_291__PI_MR3_DATA_F2_2_WIDTH 8U
  4476. #define LPDDR4__PI_MR3_DATA_F2_2__REG DENALI_PI_291
  4477. #define LPDDR4__PI_MR3_DATA_F2_2__FLD LPDDR4__DENALI_PI_291__PI_MR3_DATA_F2_2
  4478. #define LPDDR4__DENALI_PI_291__PI_MR11_DATA_F2_2_MASK 0xFF000000U
  4479. #define LPDDR4__DENALI_PI_291__PI_MR11_DATA_F2_2_SHIFT 24U
  4480. #define LPDDR4__DENALI_PI_291__PI_MR11_DATA_F2_2_WIDTH 8U
  4481. #define LPDDR4__PI_MR11_DATA_F2_2__REG DENALI_PI_291
  4482. #define LPDDR4__PI_MR11_DATA_F2_2__FLD LPDDR4__DENALI_PI_291__PI_MR11_DATA_F2_2
  4483. #define LPDDR4__DENALI_PI_292_READ_MASK 0xFFFFFFFFU
  4484. #define LPDDR4__DENALI_PI_292_WRITE_MASK 0xFFFFFFFFU
  4485. #define LPDDR4__DENALI_PI_292__PI_MR12_DATA_F2_2_MASK 0x000000FFU
  4486. #define LPDDR4__DENALI_PI_292__PI_MR12_DATA_F2_2_SHIFT 0U
  4487. #define LPDDR4__DENALI_PI_292__PI_MR12_DATA_F2_2_WIDTH 8U
  4488. #define LPDDR4__PI_MR12_DATA_F2_2__REG DENALI_PI_292
  4489. #define LPDDR4__PI_MR12_DATA_F2_2__FLD LPDDR4__DENALI_PI_292__PI_MR12_DATA_F2_2
  4490. #define LPDDR4__DENALI_PI_292__PI_MR14_DATA_F2_2_MASK 0x0000FF00U
  4491. #define LPDDR4__DENALI_PI_292__PI_MR14_DATA_F2_2_SHIFT 8U
  4492. #define LPDDR4__DENALI_PI_292__PI_MR14_DATA_F2_2_WIDTH 8U
  4493. #define LPDDR4__PI_MR14_DATA_F2_2__REG DENALI_PI_292
  4494. #define LPDDR4__PI_MR14_DATA_F2_2__FLD LPDDR4__DENALI_PI_292__PI_MR14_DATA_F2_2
  4495. #define LPDDR4__DENALI_PI_292__PI_MR22_DATA_F2_2_MASK 0x00FF0000U
  4496. #define LPDDR4__DENALI_PI_292__PI_MR22_DATA_F2_2_SHIFT 16U
  4497. #define LPDDR4__DENALI_PI_292__PI_MR22_DATA_F2_2_WIDTH 8U
  4498. #define LPDDR4__PI_MR22_DATA_F2_2__REG DENALI_PI_292
  4499. #define LPDDR4__PI_MR22_DATA_F2_2__FLD LPDDR4__DENALI_PI_292__PI_MR22_DATA_F2_2
  4500. #define LPDDR4__DENALI_PI_292__PI_MR23_DATA_F2_2_MASK 0xFF000000U
  4501. #define LPDDR4__DENALI_PI_292__PI_MR23_DATA_F2_2_SHIFT 24U
  4502. #define LPDDR4__DENALI_PI_292__PI_MR23_DATA_F2_2_WIDTH 8U
  4503. #define LPDDR4__PI_MR23_DATA_F2_2__REG DENALI_PI_292
  4504. #define LPDDR4__PI_MR23_DATA_F2_2__FLD LPDDR4__DENALI_PI_292__PI_MR23_DATA_F2_2
  4505. #define LPDDR4__DENALI_PI_293_READ_MASK 0xFFFFFFFFU
  4506. #define LPDDR4__DENALI_PI_293_WRITE_MASK 0xFFFFFFFFU
  4507. #define LPDDR4__DENALI_PI_293__PI_MR1_DATA_F0_3_MASK 0x000000FFU
  4508. #define LPDDR4__DENALI_PI_293__PI_MR1_DATA_F0_3_SHIFT 0U
  4509. #define LPDDR4__DENALI_PI_293__PI_MR1_DATA_F0_3_WIDTH 8U
  4510. #define LPDDR4__PI_MR1_DATA_F0_3__REG DENALI_PI_293
  4511. #define LPDDR4__PI_MR1_DATA_F0_3__FLD LPDDR4__DENALI_PI_293__PI_MR1_DATA_F0_3
  4512. #define LPDDR4__DENALI_PI_293__PI_MR2_DATA_F0_3_MASK 0x0000FF00U
  4513. #define LPDDR4__DENALI_PI_293__PI_MR2_DATA_F0_3_SHIFT 8U
  4514. #define LPDDR4__DENALI_PI_293__PI_MR2_DATA_F0_3_WIDTH 8U
  4515. #define LPDDR4__PI_MR2_DATA_F0_3__REG DENALI_PI_293
  4516. #define LPDDR4__PI_MR2_DATA_F0_3__FLD LPDDR4__DENALI_PI_293__PI_MR2_DATA_F0_3
  4517. #define LPDDR4__DENALI_PI_293__PI_MR3_DATA_F0_3_MASK 0x00FF0000U
  4518. #define LPDDR4__DENALI_PI_293__PI_MR3_DATA_F0_3_SHIFT 16U
  4519. #define LPDDR4__DENALI_PI_293__PI_MR3_DATA_F0_3_WIDTH 8U
  4520. #define LPDDR4__PI_MR3_DATA_F0_3__REG DENALI_PI_293
  4521. #define LPDDR4__PI_MR3_DATA_F0_3__FLD LPDDR4__DENALI_PI_293__PI_MR3_DATA_F0_3
  4522. #define LPDDR4__DENALI_PI_293__PI_MR11_DATA_F0_3_MASK 0xFF000000U
  4523. #define LPDDR4__DENALI_PI_293__PI_MR11_DATA_F0_3_SHIFT 24U
  4524. #define LPDDR4__DENALI_PI_293__PI_MR11_DATA_F0_3_WIDTH 8U
  4525. #define LPDDR4__PI_MR11_DATA_F0_3__REG DENALI_PI_293
  4526. #define LPDDR4__PI_MR11_DATA_F0_3__FLD LPDDR4__DENALI_PI_293__PI_MR11_DATA_F0_3
  4527. #define LPDDR4__DENALI_PI_294_READ_MASK 0xFFFFFFFFU
  4528. #define LPDDR4__DENALI_PI_294_WRITE_MASK 0xFFFFFFFFU
  4529. #define LPDDR4__DENALI_PI_294__PI_MR12_DATA_F0_3_MASK 0x000000FFU
  4530. #define LPDDR4__DENALI_PI_294__PI_MR12_DATA_F0_3_SHIFT 0U
  4531. #define LPDDR4__DENALI_PI_294__PI_MR12_DATA_F0_3_WIDTH 8U
  4532. #define LPDDR4__PI_MR12_DATA_F0_3__REG DENALI_PI_294
  4533. #define LPDDR4__PI_MR12_DATA_F0_3__FLD LPDDR4__DENALI_PI_294__PI_MR12_DATA_F0_3
  4534. #define LPDDR4__DENALI_PI_294__PI_MR14_DATA_F0_3_MASK 0x0000FF00U
  4535. #define LPDDR4__DENALI_PI_294__PI_MR14_DATA_F0_3_SHIFT 8U
  4536. #define LPDDR4__DENALI_PI_294__PI_MR14_DATA_F0_3_WIDTH 8U
  4537. #define LPDDR4__PI_MR14_DATA_F0_3__REG DENALI_PI_294
  4538. #define LPDDR4__PI_MR14_DATA_F0_3__FLD LPDDR4__DENALI_PI_294__PI_MR14_DATA_F0_3
  4539. #define LPDDR4__DENALI_PI_294__PI_MR22_DATA_F0_3_MASK 0x00FF0000U
  4540. #define LPDDR4__DENALI_PI_294__PI_MR22_DATA_F0_3_SHIFT 16U
  4541. #define LPDDR4__DENALI_PI_294__PI_MR22_DATA_F0_3_WIDTH 8U
  4542. #define LPDDR4__PI_MR22_DATA_F0_3__REG DENALI_PI_294
  4543. #define LPDDR4__PI_MR22_DATA_F0_3__FLD LPDDR4__DENALI_PI_294__PI_MR22_DATA_F0_3
  4544. #define LPDDR4__DENALI_PI_294__PI_MR23_DATA_F0_3_MASK 0xFF000000U
  4545. #define LPDDR4__DENALI_PI_294__PI_MR23_DATA_F0_3_SHIFT 24U
  4546. #define LPDDR4__DENALI_PI_294__PI_MR23_DATA_F0_3_WIDTH 8U
  4547. #define LPDDR4__PI_MR23_DATA_F0_3__REG DENALI_PI_294
  4548. #define LPDDR4__PI_MR23_DATA_F0_3__FLD LPDDR4__DENALI_PI_294__PI_MR23_DATA_F0_3
  4549. #define LPDDR4__DENALI_PI_295_READ_MASK 0xFFFFFFFFU
  4550. #define LPDDR4__DENALI_PI_295_WRITE_MASK 0xFFFFFFFFU
  4551. #define LPDDR4__DENALI_PI_295__PI_MR1_DATA_F1_3_MASK 0x000000FFU
  4552. #define LPDDR4__DENALI_PI_295__PI_MR1_DATA_F1_3_SHIFT 0U
  4553. #define LPDDR4__DENALI_PI_295__PI_MR1_DATA_F1_3_WIDTH 8U
  4554. #define LPDDR4__PI_MR1_DATA_F1_3__REG DENALI_PI_295
  4555. #define LPDDR4__PI_MR1_DATA_F1_3__FLD LPDDR4__DENALI_PI_295__PI_MR1_DATA_F1_3
  4556. #define LPDDR4__DENALI_PI_295__PI_MR2_DATA_F1_3_MASK 0x0000FF00U
  4557. #define LPDDR4__DENALI_PI_295__PI_MR2_DATA_F1_3_SHIFT 8U
  4558. #define LPDDR4__DENALI_PI_295__PI_MR2_DATA_F1_3_WIDTH 8U
  4559. #define LPDDR4__PI_MR2_DATA_F1_3__REG DENALI_PI_295
  4560. #define LPDDR4__PI_MR2_DATA_F1_3__FLD LPDDR4__DENALI_PI_295__PI_MR2_DATA_F1_3
  4561. #define LPDDR4__DENALI_PI_295__PI_MR3_DATA_F1_3_MASK 0x00FF0000U
  4562. #define LPDDR4__DENALI_PI_295__PI_MR3_DATA_F1_3_SHIFT 16U
  4563. #define LPDDR4__DENALI_PI_295__PI_MR3_DATA_F1_3_WIDTH 8U
  4564. #define LPDDR4__PI_MR3_DATA_F1_3__REG DENALI_PI_295
  4565. #define LPDDR4__PI_MR3_DATA_F1_3__FLD LPDDR4__DENALI_PI_295__PI_MR3_DATA_F1_3
  4566. #define LPDDR4__DENALI_PI_295__PI_MR11_DATA_F1_3_MASK 0xFF000000U
  4567. #define LPDDR4__DENALI_PI_295__PI_MR11_DATA_F1_3_SHIFT 24U
  4568. #define LPDDR4__DENALI_PI_295__PI_MR11_DATA_F1_3_WIDTH 8U
  4569. #define LPDDR4__PI_MR11_DATA_F1_3__REG DENALI_PI_295
  4570. #define LPDDR4__PI_MR11_DATA_F1_3__FLD LPDDR4__DENALI_PI_295__PI_MR11_DATA_F1_3
  4571. #define LPDDR4__DENALI_PI_296_READ_MASK 0xFFFFFFFFU
  4572. #define LPDDR4__DENALI_PI_296_WRITE_MASK 0xFFFFFFFFU
  4573. #define LPDDR4__DENALI_PI_296__PI_MR12_DATA_F1_3_MASK 0x000000FFU
  4574. #define LPDDR4__DENALI_PI_296__PI_MR12_DATA_F1_3_SHIFT 0U
  4575. #define LPDDR4__DENALI_PI_296__PI_MR12_DATA_F1_3_WIDTH 8U
  4576. #define LPDDR4__PI_MR12_DATA_F1_3__REG DENALI_PI_296
  4577. #define LPDDR4__PI_MR12_DATA_F1_3__FLD LPDDR4__DENALI_PI_296__PI_MR12_DATA_F1_3
  4578. #define LPDDR4__DENALI_PI_296__PI_MR14_DATA_F1_3_MASK 0x0000FF00U
  4579. #define LPDDR4__DENALI_PI_296__PI_MR14_DATA_F1_3_SHIFT 8U
  4580. #define LPDDR4__DENALI_PI_296__PI_MR14_DATA_F1_3_WIDTH 8U
  4581. #define LPDDR4__PI_MR14_DATA_F1_3__REG DENALI_PI_296
  4582. #define LPDDR4__PI_MR14_DATA_F1_3__FLD LPDDR4__DENALI_PI_296__PI_MR14_DATA_F1_3
  4583. #define LPDDR4__DENALI_PI_296__PI_MR22_DATA_F1_3_MASK 0x00FF0000U
  4584. #define LPDDR4__DENALI_PI_296__PI_MR22_DATA_F1_3_SHIFT 16U
  4585. #define LPDDR4__DENALI_PI_296__PI_MR22_DATA_F1_3_WIDTH 8U
  4586. #define LPDDR4__PI_MR22_DATA_F1_3__REG DENALI_PI_296
  4587. #define LPDDR4__PI_MR22_DATA_F1_3__FLD LPDDR4__DENALI_PI_296__PI_MR22_DATA_F1_3
  4588. #define LPDDR4__DENALI_PI_296__PI_MR23_DATA_F1_3_MASK 0xFF000000U
  4589. #define LPDDR4__DENALI_PI_296__PI_MR23_DATA_F1_3_SHIFT 24U
  4590. #define LPDDR4__DENALI_PI_296__PI_MR23_DATA_F1_3_WIDTH 8U
  4591. #define LPDDR4__PI_MR23_DATA_F1_3__REG DENALI_PI_296
  4592. #define LPDDR4__PI_MR23_DATA_F1_3__FLD LPDDR4__DENALI_PI_296__PI_MR23_DATA_F1_3
  4593. #define LPDDR4__DENALI_PI_297_READ_MASK 0xFFFFFFFFU
  4594. #define LPDDR4__DENALI_PI_297_WRITE_MASK 0xFFFFFFFFU
  4595. #define LPDDR4__DENALI_PI_297__PI_MR1_DATA_F2_3_MASK 0x000000FFU
  4596. #define LPDDR4__DENALI_PI_297__PI_MR1_DATA_F2_3_SHIFT 0U
  4597. #define LPDDR4__DENALI_PI_297__PI_MR1_DATA_F2_3_WIDTH 8U
  4598. #define LPDDR4__PI_MR1_DATA_F2_3__REG DENALI_PI_297
  4599. #define LPDDR4__PI_MR1_DATA_F2_3__FLD LPDDR4__DENALI_PI_297__PI_MR1_DATA_F2_3
  4600. #define LPDDR4__DENALI_PI_297__PI_MR2_DATA_F2_3_MASK 0x0000FF00U
  4601. #define LPDDR4__DENALI_PI_297__PI_MR2_DATA_F2_3_SHIFT 8U
  4602. #define LPDDR4__DENALI_PI_297__PI_MR2_DATA_F2_3_WIDTH 8U
  4603. #define LPDDR4__PI_MR2_DATA_F2_3__REG DENALI_PI_297
  4604. #define LPDDR4__PI_MR2_DATA_F2_3__FLD LPDDR4__DENALI_PI_297__PI_MR2_DATA_F2_3
  4605. #define LPDDR4__DENALI_PI_297__PI_MR3_DATA_F2_3_MASK 0x00FF0000U
  4606. #define LPDDR4__DENALI_PI_297__PI_MR3_DATA_F2_3_SHIFT 16U
  4607. #define LPDDR4__DENALI_PI_297__PI_MR3_DATA_F2_3_WIDTH 8U
  4608. #define LPDDR4__PI_MR3_DATA_F2_3__REG DENALI_PI_297
  4609. #define LPDDR4__PI_MR3_DATA_F2_3__FLD LPDDR4__DENALI_PI_297__PI_MR3_DATA_F2_3
  4610. #define LPDDR4__DENALI_PI_297__PI_MR11_DATA_F2_3_MASK 0xFF000000U
  4611. #define LPDDR4__DENALI_PI_297__PI_MR11_DATA_F2_3_SHIFT 24U
  4612. #define LPDDR4__DENALI_PI_297__PI_MR11_DATA_F2_3_WIDTH 8U
  4613. #define LPDDR4__PI_MR11_DATA_F2_3__REG DENALI_PI_297
  4614. #define LPDDR4__PI_MR11_DATA_F2_3__FLD LPDDR4__DENALI_PI_297__PI_MR11_DATA_F2_3
  4615. #define LPDDR4__DENALI_PI_298_READ_MASK 0xFFFFFFFFU
  4616. #define LPDDR4__DENALI_PI_298_WRITE_MASK 0xFFFFFFFFU
  4617. #define LPDDR4__DENALI_PI_298__PI_MR12_DATA_F2_3_MASK 0x000000FFU
  4618. #define LPDDR4__DENALI_PI_298__PI_MR12_DATA_F2_3_SHIFT 0U
  4619. #define LPDDR4__DENALI_PI_298__PI_MR12_DATA_F2_3_WIDTH 8U
  4620. #define LPDDR4__PI_MR12_DATA_F2_3__REG DENALI_PI_298
  4621. #define LPDDR4__PI_MR12_DATA_F2_3__FLD LPDDR4__DENALI_PI_298__PI_MR12_DATA_F2_3
  4622. #define LPDDR4__DENALI_PI_298__PI_MR14_DATA_F2_3_MASK 0x0000FF00U
  4623. #define LPDDR4__DENALI_PI_298__PI_MR14_DATA_F2_3_SHIFT 8U
  4624. #define LPDDR4__DENALI_PI_298__PI_MR14_DATA_F2_3_WIDTH 8U
  4625. #define LPDDR4__PI_MR14_DATA_F2_3__REG DENALI_PI_298
  4626. #define LPDDR4__PI_MR14_DATA_F2_3__FLD LPDDR4__DENALI_PI_298__PI_MR14_DATA_F2_3
  4627. #define LPDDR4__DENALI_PI_298__PI_MR22_DATA_F2_3_MASK 0x00FF0000U
  4628. #define LPDDR4__DENALI_PI_298__PI_MR22_DATA_F2_3_SHIFT 16U
  4629. #define LPDDR4__DENALI_PI_298__PI_MR22_DATA_F2_3_WIDTH 8U
  4630. #define LPDDR4__PI_MR22_DATA_F2_3__REG DENALI_PI_298
  4631. #define LPDDR4__PI_MR22_DATA_F2_3__FLD LPDDR4__DENALI_PI_298__PI_MR22_DATA_F2_3
  4632. #define LPDDR4__DENALI_PI_298__PI_MR23_DATA_F2_3_MASK 0xFF000000U
  4633. #define LPDDR4__DENALI_PI_298__PI_MR23_DATA_F2_3_SHIFT 24U
  4634. #define LPDDR4__DENALI_PI_298__PI_MR23_DATA_F2_3_WIDTH 8U
  4635. #define LPDDR4__PI_MR23_DATA_F2_3__REG DENALI_PI_298
  4636. #define LPDDR4__PI_MR23_DATA_F2_3__FLD LPDDR4__DENALI_PI_298__PI_MR23_DATA_F2_3
  4637. #define LPDDR4__DENALI_PI_299_READ_MASK 0x000007FFU
  4638. #define LPDDR4__DENALI_PI_299_WRITE_MASK 0x000007FFU
  4639. #define LPDDR4__DENALI_PI_299__PI_PARITY_ERROR_REGIF_MASK 0x000007FFU
  4640. #define LPDDR4__DENALI_PI_299__PI_PARITY_ERROR_REGIF_SHIFT 0U
  4641. #define LPDDR4__DENALI_PI_299__PI_PARITY_ERROR_REGIF_WIDTH 11U
  4642. #define LPDDR4__PI_PARITY_ERROR_REGIF__REG DENALI_PI_299
  4643. #define LPDDR4__PI_PARITY_ERROR_REGIF__FLD LPDDR4__DENALI_PI_299__PI_PARITY_ERROR_REGIF
  4644. #endif /* REG_LPDDR4_PI_MACROS_H_ */