lpddr4_ddr_controller_macros.h 455 KB

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  1. /* SPDX-License-Identifier: BSD-3-Clause */
  2. /**********************************************************************
  3. * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
  4. *
  5. * THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT
  6. *
  7. **********************************************************************
  8. */
  9. #ifndef REG_LPDDR4_DDR_CONTROLLER_MACROS_H_
  10. #define REG_LPDDR4_DDR_CONTROLLER_MACROS_H_
  11. #define LPDDR4__DENALI_CTL_0_READ_MASK 0xFFFF0F01U
  12. #define LPDDR4__DENALI_CTL_0_WRITE_MASK 0xFFFF0F01U
  13. #define LPDDR4__DENALI_CTL_0__START_MASK 0x00000001U
  14. #define LPDDR4__DENALI_CTL_0__START_SHIFT 0U
  15. #define LPDDR4__DENALI_CTL_0__START_WIDTH 1U
  16. #define LPDDR4__DENALI_CTL_0__START_WOCLR 0U
  17. #define LPDDR4__DENALI_CTL_0__START_WOSET 0U
  18. #define LPDDR4__START__REG DENALI_CTL_0
  19. #define LPDDR4__START__FLD LPDDR4__DENALI_CTL_0__START
  20. #define LPDDR4__DENALI_CTL_0__DRAM_CLASS_MASK 0x00000F00U
  21. #define LPDDR4__DENALI_CTL_0__DRAM_CLASS_SHIFT 8U
  22. #define LPDDR4__DENALI_CTL_0__DRAM_CLASS_WIDTH 4U
  23. #define LPDDR4__DRAM_CLASS__REG DENALI_CTL_0
  24. #define LPDDR4__DRAM_CLASS__FLD LPDDR4__DENALI_CTL_0__DRAM_CLASS
  25. #define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_MASK 0xFFFF0000U
  26. #define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_SHIFT 16U
  27. #define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_WIDTH 16U
  28. #define LPDDR4__CONTROLLER_ID__REG DENALI_CTL_0
  29. #define LPDDR4__CONTROLLER_ID__FLD LPDDR4__DENALI_CTL_0__CONTROLLER_ID
  30. #define LPDDR4__DENALI_CTL_1_READ_MASK 0xFFFFFFFFU
  31. #define LPDDR4__DENALI_CTL_1_WRITE_MASK 0xFFFFFFFFU
  32. #define LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0_MASK 0xFFFFFFFFU
  33. #define LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0_SHIFT 0U
  34. #define LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0_WIDTH 32U
  35. #define LPDDR4__CONTROLLER_VERSION_0__REG DENALI_CTL_1
  36. #define LPDDR4__CONTROLLER_VERSION_0__FLD LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0
  37. #define LPDDR4__DENALI_CTL_2_READ_MASK 0xFFFFFFFFU
  38. #define LPDDR4__DENALI_CTL_2_WRITE_MASK 0xFFFFFFFFU
  39. #define LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1_MASK 0xFFFFFFFFU
  40. #define LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1_SHIFT 0U
  41. #define LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1_WIDTH 32U
  42. #define LPDDR4__CONTROLLER_VERSION_1__REG DENALI_CTL_2
  43. #define LPDDR4__CONTROLLER_VERSION_1__FLD LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1
  44. #define LPDDR4__DENALI_CTL_3_READ_MASK 0xFF030F1FU
  45. #define LPDDR4__DENALI_CTL_3_WRITE_MASK 0xFF030F1FU
  46. #define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_MASK 0x0000001FU
  47. #define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_SHIFT 0U
  48. #define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_WIDTH 5U
  49. #define LPDDR4__MAX_ROW_REG__REG DENALI_CTL_3
  50. #define LPDDR4__MAX_ROW_REG__FLD LPDDR4__DENALI_CTL_3__MAX_ROW_REG
  51. #define LPDDR4__DENALI_CTL_3__MAX_COL_REG_MASK 0x00000F00U
  52. #define LPDDR4__DENALI_CTL_3__MAX_COL_REG_SHIFT 8U
  53. #define LPDDR4__DENALI_CTL_3__MAX_COL_REG_WIDTH 4U
  54. #define LPDDR4__MAX_COL_REG__REG DENALI_CTL_3
  55. #define LPDDR4__MAX_COL_REG__FLD LPDDR4__DENALI_CTL_3__MAX_COL_REG
  56. #define LPDDR4__DENALI_CTL_3__MAX_CS_REG_MASK 0x00030000U
  57. #define LPDDR4__DENALI_CTL_3__MAX_CS_REG_SHIFT 16U
  58. #define LPDDR4__DENALI_CTL_3__MAX_CS_REG_WIDTH 2U
  59. #define LPDDR4__MAX_CS_REG__REG DENALI_CTL_3
  60. #define LPDDR4__MAX_CS_REG__FLD LPDDR4__DENALI_CTL_3__MAX_CS_REG
  61. #define LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH_MASK 0xFF000000U
  62. #define LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH_SHIFT 24U
  63. #define LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH_WIDTH 8U
  64. #define LPDDR4__READ_DATA_FIFO_DEPTH__REG DENALI_CTL_3
  65. #define LPDDR4__READ_DATA_FIFO_DEPTH__FLD LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH
  66. #define LPDDR4__DENALI_CTL_4_READ_MASK 0x00FFFFFFU
  67. #define LPDDR4__DENALI_CTL_4_WRITE_MASK 0x00FFFFFFU
  68. #define LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH_MASK 0x000000FFU
  69. #define LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH_SHIFT 0U
  70. #define LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH_WIDTH 8U
  71. #define LPDDR4__READ_DATA_FIFO_PTR_WIDTH__REG DENALI_CTL_4
  72. #define LPDDR4__READ_DATA_FIFO_PTR_WIDTH__FLD LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH
  73. #define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH_MASK 0x0000FF00U
  74. #define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH_SHIFT 8U
  75. #define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH_WIDTH 8U
  76. #define LPDDR4__WRITE_DATA_FIFO_DEPTH__REG DENALI_CTL_4
  77. #define LPDDR4__WRITE_DATA_FIFO_DEPTH__FLD LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH
  78. #define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH_MASK 0x00FF0000U
  79. #define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH_SHIFT 16U
  80. #define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH_WIDTH 8U
  81. #define LPDDR4__WRITE_DATA_FIFO_PTR_WIDTH__REG DENALI_CTL_4
  82. #define LPDDR4__WRITE_DATA_FIFO_PTR_WIDTH__FLD LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH
  83. #define LPDDR4__DENALI_CTL_5_READ_MASK 0xFFFFFFFFU
  84. #define LPDDR4__DENALI_CTL_5_WRITE_MASK 0xFFFFFFFFU
  85. #define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH_MASK 0x0000FFFFU
  86. #define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH_SHIFT 0U
  87. #define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH_WIDTH 16U
  88. #define LPDDR4__MEMCD_RMODW_FIFO_DEPTH__REG DENALI_CTL_5
  89. #define LPDDR4__MEMCD_RMODW_FIFO_DEPTH__FLD LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH
  90. #define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH_MASK 0x00FF0000U
  91. #define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH_SHIFT 16U
  92. #define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH_WIDTH 8U
  93. #define LPDDR4__MEMCD_RMODW_FIFO_PTR_WIDTH__REG DENALI_CTL_5
  94. #define LPDDR4__MEMCD_RMODW_FIFO_PTR_WIDTH__FLD LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH
  95. #define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_MASK 0xFF000000U
  96. #define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_SHIFT 24U
  97. #define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_WIDTH 8U
  98. #define LPDDR4__ASYNC_CDC_STAGES__REG DENALI_CTL_5
  99. #define LPDDR4__ASYNC_CDC_STAGES__FLD LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES
  100. #define LPDDR4__DENALI_CTL_6_READ_MASK 0xFFFFFFFFU
  101. #define LPDDR4__DENALI_CTL_6_WRITE_MASK 0xFFFFFFFFU
  102. #define LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH_MASK 0x000000FFU
  103. #define LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH_SHIFT 0U
  104. #define LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH_WIDTH 8U
  105. #define LPDDR4__AXI0_CMDFIFO_LOG2_DEPTH__REG DENALI_CTL_6
  106. #define LPDDR4__AXI0_CMDFIFO_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH
  107. #define LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH_MASK 0x0000FF00U
  108. #define LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH_SHIFT 8U
  109. #define LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH_WIDTH 8U
  110. #define LPDDR4__AXI0_RDFIFO_LOG2_DEPTH__REG DENALI_CTL_6
  111. #define LPDDR4__AXI0_RDFIFO_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH
  112. #define LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH_MASK 0x00FF0000U
  113. #define LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH_SHIFT 16U
  114. #define LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH_WIDTH 8U
  115. #define LPDDR4__AXI0_WR_ARRAY_LOG2_DEPTH__REG DENALI_CTL_6
  116. #define LPDDR4__AXI0_WR_ARRAY_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH
  117. #define LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH_MASK 0xFF000000U
  118. #define LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH_SHIFT 24U
  119. #define LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH_WIDTH 8U
  120. #define LPDDR4__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH__REG DENALI_CTL_6
  121. #define LPDDR4__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH
  122. #define LPDDR4__DENALI_CTL_7_READ_MASK 0x00FFFFFFU
  123. #define LPDDR4__DENALI_CTL_7_WRITE_MASK 0x00FFFFFFU
  124. #define LPDDR4__DENALI_CTL_7__TINIT_F0_MASK 0x00FFFFFFU
  125. #define LPDDR4__DENALI_CTL_7__TINIT_F0_SHIFT 0U
  126. #define LPDDR4__DENALI_CTL_7__TINIT_F0_WIDTH 24U
  127. #define LPDDR4__TINIT_F0__REG DENALI_CTL_7
  128. #define LPDDR4__TINIT_F0__FLD LPDDR4__DENALI_CTL_7__TINIT_F0
  129. #define LPDDR4__DENALI_CTL_8_READ_MASK 0x00FFFFFFU
  130. #define LPDDR4__DENALI_CTL_8_WRITE_MASK 0x00FFFFFFU
  131. #define LPDDR4__DENALI_CTL_8__TINIT3_F0_MASK 0x00FFFFFFU
  132. #define LPDDR4__DENALI_CTL_8__TINIT3_F0_SHIFT 0U
  133. #define LPDDR4__DENALI_CTL_8__TINIT3_F0_WIDTH 24U
  134. #define LPDDR4__TINIT3_F0__REG DENALI_CTL_8
  135. #define LPDDR4__TINIT3_F0__FLD LPDDR4__DENALI_CTL_8__TINIT3_F0
  136. #define LPDDR4__DENALI_CTL_9_READ_MASK 0x00FFFFFFU
  137. #define LPDDR4__DENALI_CTL_9_WRITE_MASK 0x00FFFFFFU
  138. #define LPDDR4__DENALI_CTL_9__TINIT4_F0_MASK 0x00FFFFFFU
  139. #define LPDDR4__DENALI_CTL_9__TINIT4_F0_SHIFT 0U
  140. #define LPDDR4__DENALI_CTL_9__TINIT4_F0_WIDTH 24U
  141. #define LPDDR4__TINIT4_F0__REG DENALI_CTL_9
  142. #define LPDDR4__TINIT4_F0__FLD LPDDR4__DENALI_CTL_9__TINIT4_F0
  143. #define LPDDR4__DENALI_CTL_10_READ_MASK 0x00FFFFFFU
  144. #define LPDDR4__DENALI_CTL_10_WRITE_MASK 0x00FFFFFFU
  145. #define LPDDR4__DENALI_CTL_10__TINIT5_F0_MASK 0x00FFFFFFU
  146. #define LPDDR4__DENALI_CTL_10__TINIT5_F0_SHIFT 0U
  147. #define LPDDR4__DENALI_CTL_10__TINIT5_F0_WIDTH 24U
  148. #define LPDDR4__TINIT5_F0__REG DENALI_CTL_10
  149. #define LPDDR4__TINIT5_F0__FLD LPDDR4__DENALI_CTL_10__TINIT5_F0
  150. #define LPDDR4__DENALI_CTL_11_READ_MASK 0x00FFFFFFU
  151. #define LPDDR4__DENALI_CTL_11_WRITE_MASK 0x00FFFFFFU
  152. #define LPDDR4__DENALI_CTL_11__TINIT_F1_MASK 0x00FFFFFFU
  153. #define LPDDR4__DENALI_CTL_11__TINIT_F1_SHIFT 0U
  154. #define LPDDR4__DENALI_CTL_11__TINIT_F1_WIDTH 24U
  155. #define LPDDR4__TINIT_F1__REG DENALI_CTL_11
  156. #define LPDDR4__TINIT_F1__FLD LPDDR4__DENALI_CTL_11__TINIT_F1
  157. #define LPDDR4__DENALI_CTL_12_READ_MASK 0x00FFFFFFU
  158. #define LPDDR4__DENALI_CTL_12_WRITE_MASK 0x00FFFFFFU
  159. #define LPDDR4__DENALI_CTL_12__TINIT3_F1_MASK 0x00FFFFFFU
  160. #define LPDDR4__DENALI_CTL_12__TINIT3_F1_SHIFT 0U
  161. #define LPDDR4__DENALI_CTL_12__TINIT3_F1_WIDTH 24U
  162. #define LPDDR4__TINIT3_F1__REG DENALI_CTL_12
  163. #define LPDDR4__TINIT3_F1__FLD LPDDR4__DENALI_CTL_12__TINIT3_F1
  164. #define LPDDR4__DENALI_CTL_13_READ_MASK 0x00FFFFFFU
  165. #define LPDDR4__DENALI_CTL_13_WRITE_MASK 0x00FFFFFFU
  166. #define LPDDR4__DENALI_CTL_13__TINIT4_F1_MASK 0x00FFFFFFU
  167. #define LPDDR4__DENALI_CTL_13__TINIT4_F1_SHIFT 0U
  168. #define LPDDR4__DENALI_CTL_13__TINIT4_F1_WIDTH 24U
  169. #define LPDDR4__TINIT4_F1__REG DENALI_CTL_13
  170. #define LPDDR4__TINIT4_F1__FLD LPDDR4__DENALI_CTL_13__TINIT4_F1
  171. #define LPDDR4__DENALI_CTL_14_READ_MASK 0x00FFFFFFU
  172. #define LPDDR4__DENALI_CTL_14_WRITE_MASK 0x00FFFFFFU
  173. #define LPDDR4__DENALI_CTL_14__TINIT5_F1_MASK 0x00FFFFFFU
  174. #define LPDDR4__DENALI_CTL_14__TINIT5_F1_SHIFT 0U
  175. #define LPDDR4__DENALI_CTL_14__TINIT5_F1_WIDTH 24U
  176. #define LPDDR4__TINIT5_F1__REG DENALI_CTL_14
  177. #define LPDDR4__TINIT5_F1__FLD LPDDR4__DENALI_CTL_14__TINIT5_F1
  178. #define LPDDR4__DENALI_CTL_15_READ_MASK 0x00FFFFFFU
  179. #define LPDDR4__DENALI_CTL_15_WRITE_MASK 0x00FFFFFFU
  180. #define LPDDR4__DENALI_CTL_15__TINIT_F2_MASK 0x00FFFFFFU
  181. #define LPDDR4__DENALI_CTL_15__TINIT_F2_SHIFT 0U
  182. #define LPDDR4__DENALI_CTL_15__TINIT_F2_WIDTH 24U
  183. #define LPDDR4__TINIT_F2__REG DENALI_CTL_15
  184. #define LPDDR4__TINIT_F2__FLD LPDDR4__DENALI_CTL_15__TINIT_F2
  185. #define LPDDR4__DENALI_CTL_16_READ_MASK 0x00FFFFFFU
  186. #define LPDDR4__DENALI_CTL_16_WRITE_MASK 0x00FFFFFFU
  187. #define LPDDR4__DENALI_CTL_16__TINIT3_F2_MASK 0x00FFFFFFU
  188. #define LPDDR4__DENALI_CTL_16__TINIT3_F2_SHIFT 0U
  189. #define LPDDR4__DENALI_CTL_16__TINIT3_F2_WIDTH 24U
  190. #define LPDDR4__TINIT3_F2__REG DENALI_CTL_16
  191. #define LPDDR4__TINIT3_F2__FLD LPDDR4__DENALI_CTL_16__TINIT3_F2
  192. #define LPDDR4__DENALI_CTL_17_READ_MASK 0x00FFFFFFU
  193. #define LPDDR4__DENALI_CTL_17_WRITE_MASK 0x00FFFFFFU
  194. #define LPDDR4__DENALI_CTL_17__TINIT4_F2_MASK 0x00FFFFFFU
  195. #define LPDDR4__DENALI_CTL_17__TINIT4_F2_SHIFT 0U
  196. #define LPDDR4__DENALI_CTL_17__TINIT4_F2_WIDTH 24U
  197. #define LPDDR4__TINIT4_F2__REG DENALI_CTL_17
  198. #define LPDDR4__TINIT4_F2__FLD LPDDR4__DENALI_CTL_17__TINIT4_F2
  199. #define LPDDR4__DENALI_CTL_18_READ_MASK 0x01FFFFFFU
  200. #define LPDDR4__DENALI_CTL_18_WRITE_MASK 0x01FFFFFFU
  201. #define LPDDR4__DENALI_CTL_18__TINIT5_F2_MASK 0x00FFFFFFU
  202. #define LPDDR4__DENALI_CTL_18__TINIT5_F2_SHIFT 0U
  203. #define LPDDR4__DENALI_CTL_18__TINIT5_F2_WIDTH 24U
  204. #define LPDDR4__TINIT5_F2__REG DENALI_CTL_18
  205. #define LPDDR4__TINIT5_F2__FLD LPDDR4__DENALI_CTL_18__TINIT5_F2
  206. #define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_MASK 0x01000000U
  207. #define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_SHIFT 24U
  208. #define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WIDTH 1U
  209. #define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WOCLR 0U
  210. #define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WOSET 0U
  211. #define LPDDR4__NO_AUTO_MRR_INIT__REG DENALI_CTL_18
  212. #define LPDDR4__NO_AUTO_MRR_INIT__FLD LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT
  213. #define LPDDR4__DENALI_CTL_19_READ_MASK 0x01010101U
  214. #define LPDDR4__DENALI_CTL_19_WRITE_MASK 0x01010101U
  215. #define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_MASK 0x00000001U
  216. #define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_SHIFT 0U
  217. #define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WIDTH 1U
  218. #define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WOCLR 0U
  219. #define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WOSET 0U
  220. #define LPDDR4__MRR_ERROR_STATUS__REG DENALI_CTL_19
  221. #define LPDDR4__MRR_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS
  222. #define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_MASK 0x00000100U
  223. #define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_SHIFT 8U
  224. #define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_WIDTH 1U
  225. #define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_WOCLR 0U
  226. #define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_WOSET 0U
  227. #define LPDDR4__DFI_INV_DATA_CS__REG DENALI_CTL_19
  228. #define LPDDR4__DFI_INV_DATA_CS__FLD LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS
  229. #define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_MASK 0x00010000U
  230. #define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_SHIFT 16U
  231. #define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_WIDTH 1U
  232. #define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_WOCLR 0U
  233. #define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_WOSET 0U
  234. #define LPDDR4__NO_MRW_INIT__REG DENALI_CTL_19
  235. #define LPDDR4__NO_MRW_INIT__FLD LPDDR4__DENALI_CTL_19__NO_MRW_INIT
  236. #define LPDDR4__DENALI_CTL_19__ODT_VALUE_MASK 0x01000000U
  237. #define LPDDR4__DENALI_CTL_19__ODT_VALUE_SHIFT 24U
  238. #define LPDDR4__DENALI_CTL_19__ODT_VALUE_WIDTH 1U
  239. #define LPDDR4__DENALI_CTL_19__ODT_VALUE_WOCLR 0U
  240. #define LPDDR4__DENALI_CTL_19__ODT_VALUE_WOSET 0U
  241. #define LPDDR4__ODT_VALUE__REG DENALI_CTL_19
  242. #define LPDDR4__ODT_VALUE__FLD LPDDR4__DENALI_CTL_19__ODT_VALUE
  243. #define LPDDR4__DENALI_CTL_20_READ_MASK 0x03013F01U
  244. #define LPDDR4__DENALI_CTL_20_WRITE_MASK 0x03013F01U
  245. #define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_MASK 0x00000001U
  246. #define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_SHIFT 0U
  247. #define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WIDTH 1U
  248. #define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WOCLR 0U
  249. #define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WOSET 0U
  250. #define LPDDR4__PHY_INDEP_TRAIN_MODE__REG DENALI_CTL_20
  251. #define LPDDR4__PHY_INDEP_TRAIN_MODE__FLD LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE
  252. #define LPDDR4__DENALI_CTL_20__TSREF2PHYMSTR_MASK 0x00003F00U
  253. #define LPDDR4__DENALI_CTL_20__TSREF2PHYMSTR_SHIFT 8U
  254. #define LPDDR4__DENALI_CTL_20__TSREF2PHYMSTR_WIDTH 6U
  255. #define LPDDR4__TSREF2PHYMSTR__REG DENALI_CTL_20
  256. #define LPDDR4__TSREF2PHYMSTR__FLD LPDDR4__DENALI_CTL_20__TSREF2PHYMSTR
  257. #define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_MASK 0x00010000U
  258. #define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_SHIFT 16U
  259. #define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_WIDTH 1U
  260. #define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_WOCLR 0U
  261. #define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_WOSET 0U
  262. #define LPDDR4__PHY_INDEP_INIT_MODE__REG DENALI_CTL_20
  263. #define LPDDR4__PHY_INDEP_INIT_MODE__FLD LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE
  264. #define LPDDR4__DENALI_CTL_20__DFIBUS_FREQ_INIT_MASK 0x03000000U
  265. #define LPDDR4__DENALI_CTL_20__DFIBUS_FREQ_INIT_SHIFT 24U
  266. #define LPDDR4__DENALI_CTL_20__DFIBUS_FREQ_INIT_WIDTH 2U
  267. #define LPDDR4__DFIBUS_FREQ_INIT__REG DENALI_CTL_20
  268. #define LPDDR4__DFIBUS_FREQ_INIT__FLD LPDDR4__DENALI_CTL_20__DFIBUS_FREQ_INIT
  269. #define LPDDR4__DENALI_CTL_21_READ_MASK 0x1F1F1F03U
  270. #define LPDDR4__DENALI_CTL_21_WRITE_MASK 0x1F1F1F03U
  271. #define LPDDR4__DENALI_CTL_21__DFIBUS_BOOT_FREQ_MASK 0x00000003U
  272. #define LPDDR4__DENALI_CTL_21__DFIBUS_BOOT_FREQ_SHIFT 0U
  273. #define LPDDR4__DENALI_CTL_21__DFIBUS_BOOT_FREQ_WIDTH 2U
  274. #define LPDDR4__DFIBUS_BOOT_FREQ__REG DENALI_CTL_21
  275. #define LPDDR4__DFIBUS_BOOT_FREQ__FLD LPDDR4__DENALI_CTL_21__DFIBUS_BOOT_FREQ
  276. #define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_MASK 0x00001F00U
  277. #define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_SHIFT 8U
  278. #define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_WIDTH 5U
  279. #define LPDDR4__DFIBUS_FREQ_F0__REG DENALI_CTL_21
  280. #define LPDDR4__DFIBUS_FREQ_F0__FLD LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0
  281. #define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_MASK 0x001F0000U
  282. #define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_SHIFT 16U
  283. #define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_WIDTH 5U
  284. #define LPDDR4__DFIBUS_FREQ_F1__REG DENALI_CTL_21
  285. #define LPDDR4__DFIBUS_FREQ_F1__FLD LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1
  286. #define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F2_MASK 0x1F000000U
  287. #define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F2_SHIFT 24U
  288. #define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F2_WIDTH 5U
  289. #define LPDDR4__DFIBUS_FREQ_F2__REG DENALI_CTL_21
  290. #define LPDDR4__DFIBUS_FREQ_F2__FLD LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F2
  291. #define LPDDR4__DENALI_CTL_22_READ_MASK 0x00030303U
  292. #define LPDDR4__DENALI_CTL_22_WRITE_MASK 0x00030303U
  293. #define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0_MASK 0x00000003U
  294. #define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0_SHIFT 0U
  295. #define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0_WIDTH 2U
  296. #define LPDDR4__FREQ_CHANGE_TYPE_F0__REG DENALI_CTL_22
  297. #define LPDDR4__FREQ_CHANGE_TYPE_F0__FLD LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0
  298. #define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1_MASK 0x00000300U
  299. #define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1_SHIFT 8U
  300. #define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1_WIDTH 2U
  301. #define LPDDR4__FREQ_CHANGE_TYPE_F1__REG DENALI_CTL_22
  302. #define LPDDR4__FREQ_CHANGE_TYPE_F1__FLD LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1
  303. #define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2_MASK 0x00030000U
  304. #define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2_SHIFT 16U
  305. #define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2_WIDTH 2U
  306. #define LPDDR4__FREQ_CHANGE_TYPE_F2__REG DENALI_CTL_22
  307. #define LPDDR4__FREQ_CHANGE_TYPE_F2__FLD LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2
  308. #define LPDDR4__DENALI_CTL_23_READ_MASK 0xFFFFFFFFU
  309. #define LPDDR4__DENALI_CTL_23_WRITE_MASK 0xFFFFFFFFU
  310. #define LPDDR4__DENALI_CTL_23__TRST_PWRON_MASK 0xFFFFFFFFU
  311. #define LPDDR4__DENALI_CTL_23__TRST_PWRON_SHIFT 0U
  312. #define LPDDR4__DENALI_CTL_23__TRST_PWRON_WIDTH 32U
  313. #define LPDDR4__TRST_PWRON__REG DENALI_CTL_23
  314. #define LPDDR4__TRST_PWRON__FLD LPDDR4__DENALI_CTL_23__TRST_PWRON
  315. #define LPDDR4__DENALI_CTL_24_READ_MASK 0xFFFFFFFFU
  316. #define LPDDR4__DENALI_CTL_24_WRITE_MASK 0xFFFFFFFFU
  317. #define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_MASK 0xFFFFFFFFU
  318. #define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_SHIFT 0U
  319. #define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_WIDTH 32U
  320. #define LPDDR4__CKE_INACTIVE__REG DENALI_CTL_24
  321. #define LPDDR4__CKE_INACTIVE__FLD LPDDR4__DENALI_CTL_24__CKE_INACTIVE
  322. #define LPDDR4__DENALI_CTL_25_READ_MASK 0xFFFFFF01U
  323. #define LPDDR4__DENALI_CTL_25_WRITE_MASK 0xFFFFFF01U
  324. #define LPDDR4__DENALI_CTL_25__MC_RESERVED0_MASK 0x00000001U
  325. #define LPDDR4__DENALI_CTL_25__MC_RESERVED0_SHIFT 0U
  326. #define LPDDR4__DENALI_CTL_25__MC_RESERVED0_WIDTH 1U
  327. #define LPDDR4__DENALI_CTL_25__MC_RESERVED0_WOCLR 0U
  328. #define LPDDR4__DENALI_CTL_25__MC_RESERVED0_WOSET 0U
  329. #define LPDDR4__MC_RESERVED0__REG DENALI_CTL_25
  330. #define LPDDR4__MC_RESERVED0__FLD LPDDR4__DENALI_CTL_25__MC_RESERVED0
  331. #define LPDDR4__DENALI_CTL_25__MC_RESERVED1_MASK 0xFFFFFF00U
  332. #define LPDDR4__DENALI_CTL_25__MC_RESERVED1_SHIFT 8U
  333. #define LPDDR4__DENALI_CTL_25__MC_RESERVED1_WIDTH 24U
  334. #define LPDDR4__MC_RESERVED1__REG DENALI_CTL_25
  335. #define LPDDR4__MC_RESERVED1__FLD LPDDR4__DENALI_CTL_25__MC_RESERVED1
  336. #define LPDDR4__DENALI_CTL_26_READ_MASK 0x0001FFFFU
  337. #define LPDDR4__DENALI_CTL_26_WRITE_MASK 0x0001FFFFU
  338. #define LPDDR4__DENALI_CTL_26__MC_RESERVED2_MASK 0x000000FFU
  339. #define LPDDR4__DENALI_CTL_26__MC_RESERVED2_SHIFT 0U
  340. #define LPDDR4__DENALI_CTL_26__MC_RESERVED2_WIDTH 8U
  341. #define LPDDR4__MC_RESERVED2__REG DENALI_CTL_26
  342. #define LPDDR4__MC_RESERVED2__FLD LPDDR4__DENALI_CTL_26__MC_RESERVED2
  343. #define LPDDR4__DENALI_CTL_26__MC_RESERVED3_MASK 0x0000FF00U
  344. #define LPDDR4__DENALI_CTL_26__MC_RESERVED3_SHIFT 8U
  345. #define LPDDR4__DENALI_CTL_26__MC_RESERVED3_WIDTH 8U
  346. #define LPDDR4__MC_RESERVED3__REG DENALI_CTL_26
  347. #define LPDDR4__MC_RESERVED3__FLD LPDDR4__DENALI_CTL_26__MC_RESERVED3
  348. #define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_MASK 0x00010000U
  349. #define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_SHIFT 16U
  350. #define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_WIDTH 1U
  351. #define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_WOCLR 0U
  352. #define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_WOSET 0U
  353. #define LPDDR4__DQS_OSC_ENABLE__REG DENALI_CTL_26
  354. #define LPDDR4__DQS_OSC_ENABLE__FLD LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE
  355. #define LPDDR4__DENALI_CTL_27_READ_MASK 0xFF0F7FFFU
  356. #define LPDDR4__DENALI_CTL_27_WRITE_MASK 0xFF0F7FFFU
  357. #define LPDDR4__DENALI_CTL_27__DQS_OSC_PERIOD_MASK 0x00007FFFU
  358. #define LPDDR4__DENALI_CTL_27__DQS_OSC_PERIOD_SHIFT 0U
  359. #define LPDDR4__DENALI_CTL_27__DQS_OSC_PERIOD_WIDTH 15U
  360. #define LPDDR4__DQS_OSC_PERIOD__REG DENALI_CTL_27
  361. #define LPDDR4__DQS_OSC_PERIOD__FLD LPDDR4__DENALI_CTL_27__DQS_OSC_PERIOD
  362. #define LPDDR4__DENALI_CTL_27__FUNC_VALID_CYCLES_MASK 0x000F0000U
  363. #define LPDDR4__DENALI_CTL_27__FUNC_VALID_CYCLES_SHIFT 16U
  364. #define LPDDR4__DENALI_CTL_27__FUNC_VALID_CYCLES_WIDTH 4U
  365. #define LPDDR4__FUNC_VALID_CYCLES__REG DENALI_CTL_27
  366. #define LPDDR4__FUNC_VALID_CYCLES__FLD LPDDR4__DENALI_CTL_27__FUNC_VALID_CYCLES
  367. #define LPDDR4__DENALI_CTL_27__TOSCO_F0_MASK 0xFF000000U
  368. #define LPDDR4__DENALI_CTL_27__TOSCO_F0_SHIFT 24U
  369. #define LPDDR4__DENALI_CTL_27__TOSCO_F0_WIDTH 8U
  370. #define LPDDR4__TOSCO_F0__REG DENALI_CTL_27
  371. #define LPDDR4__TOSCO_F0__FLD LPDDR4__DENALI_CTL_27__TOSCO_F0
  372. #define LPDDR4__DENALI_CTL_28_READ_MASK 0xFFFFFFFFU
  373. #define LPDDR4__DENALI_CTL_28_WRITE_MASK 0xFFFFFFFFU
  374. #define LPDDR4__DENALI_CTL_28__TOSCO_F1_MASK 0x000000FFU
  375. #define LPDDR4__DENALI_CTL_28__TOSCO_F1_SHIFT 0U
  376. #define LPDDR4__DENALI_CTL_28__TOSCO_F1_WIDTH 8U
  377. #define LPDDR4__TOSCO_F1__REG DENALI_CTL_28
  378. #define LPDDR4__TOSCO_F1__FLD LPDDR4__DENALI_CTL_28__TOSCO_F1
  379. #define LPDDR4__DENALI_CTL_28__TOSCO_F2_MASK 0x0000FF00U
  380. #define LPDDR4__DENALI_CTL_28__TOSCO_F2_SHIFT 8U
  381. #define LPDDR4__DENALI_CTL_28__TOSCO_F2_WIDTH 8U
  382. #define LPDDR4__TOSCO_F2__REG DENALI_CTL_28
  383. #define LPDDR4__TOSCO_F2__FLD LPDDR4__DENALI_CTL_28__TOSCO_F2
  384. #define LPDDR4__DENALI_CTL_28__DQS_OSC_NORM_THRESHOLD_MASK 0x00FF0000U
  385. #define LPDDR4__DENALI_CTL_28__DQS_OSC_NORM_THRESHOLD_SHIFT 16U
  386. #define LPDDR4__DENALI_CTL_28__DQS_OSC_NORM_THRESHOLD_WIDTH 8U
  387. #define LPDDR4__DQS_OSC_NORM_THRESHOLD__REG DENALI_CTL_28
  388. #define LPDDR4__DQS_OSC_NORM_THRESHOLD__FLD LPDDR4__DENALI_CTL_28__DQS_OSC_NORM_THRESHOLD
  389. #define LPDDR4__DENALI_CTL_28__DQS_OSC_HIGH_THRESHOLD_MASK 0xFF000000U
  390. #define LPDDR4__DENALI_CTL_28__DQS_OSC_HIGH_THRESHOLD_SHIFT 24U
  391. #define LPDDR4__DENALI_CTL_28__DQS_OSC_HIGH_THRESHOLD_WIDTH 8U
  392. #define LPDDR4__DQS_OSC_HIGH_THRESHOLD__REG DENALI_CTL_28
  393. #define LPDDR4__DQS_OSC_HIGH_THRESHOLD__FLD LPDDR4__DENALI_CTL_28__DQS_OSC_HIGH_THRESHOLD
  394. #define LPDDR4__DENALI_CTL_29_READ_MASK 0xFFFFFFFFU
  395. #define LPDDR4__DENALI_CTL_29_WRITE_MASK 0xFFFFFFFFU
  396. #define LPDDR4__DENALI_CTL_29__DQS_OSC_TIMEOUT_MASK 0x000000FFU
  397. #define LPDDR4__DENALI_CTL_29__DQS_OSC_TIMEOUT_SHIFT 0U
  398. #define LPDDR4__DENALI_CTL_29__DQS_OSC_TIMEOUT_WIDTH 8U
  399. #define LPDDR4__DQS_OSC_TIMEOUT__REG DENALI_CTL_29
  400. #define LPDDR4__DQS_OSC_TIMEOUT__FLD LPDDR4__DENALI_CTL_29__DQS_OSC_TIMEOUT
  401. #define LPDDR4__DENALI_CTL_29__DQS_OSC_PROMOTE_THRESHOLD_MASK 0x0000FF00U
  402. #define LPDDR4__DENALI_CTL_29__DQS_OSC_PROMOTE_THRESHOLD_SHIFT 8U
  403. #define LPDDR4__DENALI_CTL_29__DQS_OSC_PROMOTE_THRESHOLD_WIDTH 8U
  404. #define LPDDR4__DQS_OSC_PROMOTE_THRESHOLD__REG DENALI_CTL_29
  405. #define LPDDR4__DQS_OSC_PROMOTE_THRESHOLD__FLD LPDDR4__DENALI_CTL_29__DQS_OSC_PROMOTE_THRESHOLD
  406. #define LPDDR4__DENALI_CTL_29__OSC_VARIANCE_LIMIT_MASK 0xFFFF0000U
  407. #define LPDDR4__DENALI_CTL_29__OSC_VARIANCE_LIMIT_SHIFT 16U
  408. #define LPDDR4__DENALI_CTL_29__OSC_VARIANCE_LIMIT_WIDTH 16U
  409. #define LPDDR4__OSC_VARIANCE_LIMIT__REG DENALI_CTL_29
  410. #define LPDDR4__OSC_VARIANCE_LIMIT__FLD LPDDR4__DENALI_CTL_29__OSC_VARIANCE_LIMIT
  411. #define LPDDR4__DENALI_CTL_30_READ_MASK 0x00FFFF00U
  412. #define LPDDR4__DENALI_CTL_30_WRITE_MASK 0x00FFFF00U
  413. #define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_MASK 0x00000001U
  414. #define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_SHIFT 0U
  415. #define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_WIDTH 1U
  416. #define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_WOCLR 0U
  417. #define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_WOSET 0U
  418. #define LPDDR4__DQS_OSC_REQUEST__REG DENALI_CTL_30
  419. #define LPDDR4__DQS_OSC_REQUEST__FLD LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST
  420. #define LPDDR4__DENALI_CTL_30__OSC_BASE_VALUE_0_CS0_MASK 0x00FFFF00U
  421. #define LPDDR4__DENALI_CTL_30__OSC_BASE_VALUE_0_CS0_SHIFT 8U
  422. #define LPDDR4__DENALI_CTL_30__OSC_BASE_VALUE_0_CS0_WIDTH 16U
  423. #define LPDDR4__OSC_BASE_VALUE_0_CS0__REG DENALI_CTL_30
  424. #define LPDDR4__OSC_BASE_VALUE_0_CS0__FLD LPDDR4__DENALI_CTL_30__OSC_BASE_VALUE_0_CS0
  425. #define LPDDR4__DENALI_CTL_31_READ_MASK 0xFFFFFFFFU
  426. #define LPDDR4__DENALI_CTL_31_WRITE_MASK 0xFFFFFFFFU
  427. #define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_1_CS0_MASK 0x0000FFFFU
  428. #define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_1_CS0_SHIFT 0U
  429. #define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_1_CS0_WIDTH 16U
  430. #define LPDDR4__OSC_BASE_VALUE_1_CS0__REG DENALI_CTL_31
  431. #define LPDDR4__OSC_BASE_VALUE_1_CS0__FLD LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_1_CS0
  432. #define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_2_CS0_MASK 0xFFFF0000U
  433. #define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_2_CS0_SHIFT 16U
  434. #define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_2_CS0_WIDTH 16U
  435. #define LPDDR4__OSC_BASE_VALUE_2_CS0__REG DENALI_CTL_31
  436. #define LPDDR4__OSC_BASE_VALUE_2_CS0__FLD LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_2_CS0
  437. #define LPDDR4__DENALI_CTL_32_READ_MASK 0xFFFFFFFFU
  438. #define LPDDR4__DENALI_CTL_32_WRITE_MASK 0xFFFFFFFFU
  439. #define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_3_CS0_MASK 0x0000FFFFU
  440. #define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_3_CS0_SHIFT 0U
  441. #define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_3_CS0_WIDTH 16U
  442. #define LPDDR4__OSC_BASE_VALUE_3_CS0__REG DENALI_CTL_32
  443. #define LPDDR4__OSC_BASE_VALUE_3_CS0__FLD LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_3_CS0
  444. #define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_0_CS1_MASK 0xFFFF0000U
  445. #define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_0_CS1_SHIFT 16U
  446. #define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_0_CS1_WIDTH 16U
  447. #define LPDDR4__OSC_BASE_VALUE_0_CS1__REG DENALI_CTL_32
  448. #define LPDDR4__OSC_BASE_VALUE_0_CS1__FLD LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_0_CS1
  449. #define LPDDR4__DENALI_CTL_33_READ_MASK 0xFFFFFFFFU
  450. #define LPDDR4__DENALI_CTL_33_WRITE_MASK 0xFFFFFFFFU
  451. #define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_1_CS1_MASK 0x0000FFFFU
  452. #define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_1_CS1_SHIFT 0U
  453. #define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_1_CS1_WIDTH 16U
  454. #define LPDDR4__OSC_BASE_VALUE_1_CS1__REG DENALI_CTL_33
  455. #define LPDDR4__OSC_BASE_VALUE_1_CS1__FLD LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_1_CS1
  456. #define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_2_CS1_MASK 0xFFFF0000U
  457. #define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_2_CS1_SHIFT 16U
  458. #define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_2_CS1_WIDTH 16U
  459. #define LPDDR4__OSC_BASE_VALUE_2_CS1__REG DENALI_CTL_33
  460. #define LPDDR4__OSC_BASE_VALUE_2_CS1__FLD LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_2_CS1
  461. #define LPDDR4__DENALI_CTL_34_READ_MASK 0x7F7FFFFFU
  462. #define LPDDR4__DENALI_CTL_34_WRITE_MASK 0x7F7FFFFFU
  463. #define LPDDR4__DENALI_CTL_34__OSC_BASE_VALUE_3_CS1_MASK 0x0000FFFFU
  464. #define LPDDR4__DENALI_CTL_34__OSC_BASE_VALUE_3_CS1_SHIFT 0U
  465. #define LPDDR4__DENALI_CTL_34__OSC_BASE_VALUE_3_CS1_WIDTH 16U
  466. #define LPDDR4__OSC_BASE_VALUE_3_CS1__REG DENALI_CTL_34
  467. #define LPDDR4__OSC_BASE_VALUE_3_CS1__FLD LPDDR4__DENALI_CTL_34__OSC_BASE_VALUE_3_CS1
  468. #define LPDDR4__DENALI_CTL_34__CASLAT_LIN_F0_MASK 0x007F0000U
  469. #define LPDDR4__DENALI_CTL_34__CASLAT_LIN_F0_SHIFT 16U
  470. #define LPDDR4__DENALI_CTL_34__CASLAT_LIN_F0_WIDTH 7U
  471. #define LPDDR4__CASLAT_LIN_F0__REG DENALI_CTL_34
  472. #define LPDDR4__CASLAT_LIN_F0__FLD LPDDR4__DENALI_CTL_34__CASLAT_LIN_F0
  473. #define LPDDR4__DENALI_CTL_34__WRLAT_F0_MASK 0x7F000000U
  474. #define LPDDR4__DENALI_CTL_34__WRLAT_F0_SHIFT 24U
  475. #define LPDDR4__DENALI_CTL_34__WRLAT_F0_WIDTH 7U
  476. #define LPDDR4__WRLAT_F0__REG DENALI_CTL_34
  477. #define LPDDR4__WRLAT_F0__FLD LPDDR4__DENALI_CTL_34__WRLAT_F0
  478. #define LPDDR4__DENALI_CTL_35_READ_MASK 0x7F7F7F7FU
  479. #define LPDDR4__DENALI_CTL_35_WRITE_MASK 0x7F7F7F7FU
  480. #define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F1_MASK 0x0000007FU
  481. #define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F1_SHIFT 0U
  482. #define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F1_WIDTH 7U
  483. #define LPDDR4__CASLAT_LIN_F1__REG DENALI_CTL_35
  484. #define LPDDR4__CASLAT_LIN_F1__FLD LPDDR4__DENALI_CTL_35__CASLAT_LIN_F1
  485. #define LPDDR4__DENALI_CTL_35__WRLAT_F1_MASK 0x00007F00U
  486. #define LPDDR4__DENALI_CTL_35__WRLAT_F1_SHIFT 8U
  487. #define LPDDR4__DENALI_CTL_35__WRLAT_F1_WIDTH 7U
  488. #define LPDDR4__WRLAT_F1__REG DENALI_CTL_35
  489. #define LPDDR4__WRLAT_F1__FLD LPDDR4__DENALI_CTL_35__WRLAT_F1
  490. #define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F2_MASK 0x007F0000U
  491. #define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F2_SHIFT 16U
  492. #define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F2_WIDTH 7U
  493. #define LPDDR4__CASLAT_LIN_F2__REG DENALI_CTL_35
  494. #define LPDDR4__CASLAT_LIN_F2__FLD LPDDR4__DENALI_CTL_35__CASLAT_LIN_F2
  495. #define LPDDR4__DENALI_CTL_35__WRLAT_F2_MASK 0x7F000000U
  496. #define LPDDR4__DENALI_CTL_35__WRLAT_F2_SHIFT 24U
  497. #define LPDDR4__DENALI_CTL_35__WRLAT_F2_WIDTH 7U
  498. #define LPDDR4__WRLAT_F2__REG DENALI_CTL_35
  499. #define LPDDR4__WRLAT_F2__FLD LPDDR4__DENALI_CTL_35__WRLAT_F2
  500. #define LPDDR4__DENALI_CTL_36_READ_MASK 0x00FF1F07U
  501. #define LPDDR4__DENALI_CTL_36_WRITE_MASK 0x00FF1F07U
  502. #define LPDDR4__DENALI_CTL_36__TBST_INT_INTERVAL_MASK 0x00000007U
  503. #define LPDDR4__DENALI_CTL_36__TBST_INT_INTERVAL_SHIFT 0U
  504. #define LPDDR4__DENALI_CTL_36__TBST_INT_INTERVAL_WIDTH 3U
  505. #define LPDDR4__TBST_INT_INTERVAL__REG DENALI_CTL_36
  506. #define LPDDR4__TBST_INT_INTERVAL__FLD LPDDR4__DENALI_CTL_36__TBST_INT_INTERVAL
  507. #define LPDDR4__DENALI_CTL_36__TCCD_MASK 0x00001F00U
  508. #define LPDDR4__DENALI_CTL_36__TCCD_SHIFT 8U
  509. #define LPDDR4__DENALI_CTL_36__TCCD_WIDTH 5U
  510. #define LPDDR4__TCCD__REG DENALI_CTL_36
  511. #define LPDDR4__TCCD__FLD LPDDR4__DENALI_CTL_36__TCCD
  512. #define LPDDR4__DENALI_CTL_36__TRRD_F0_MASK 0x00FF0000U
  513. #define LPDDR4__DENALI_CTL_36__TRRD_F0_SHIFT 16U
  514. #define LPDDR4__DENALI_CTL_36__TRRD_F0_WIDTH 8U
  515. #define LPDDR4__TRRD_F0__REG DENALI_CTL_36
  516. #define LPDDR4__TRRD_F0__FLD LPDDR4__DENALI_CTL_36__TRRD_F0
  517. #define LPDDR4__DENALI_CTL_37_READ_MASK 0x3FFF01FFU
  518. #define LPDDR4__DENALI_CTL_37_WRITE_MASK 0x3FFF01FFU
  519. #define LPDDR4__DENALI_CTL_37__TRC_F0_MASK 0x000001FFU
  520. #define LPDDR4__DENALI_CTL_37__TRC_F0_SHIFT 0U
  521. #define LPDDR4__DENALI_CTL_37__TRC_F0_WIDTH 9U
  522. #define LPDDR4__TRC_F0__REG DENALI_CTL_37
  523. #define LPDDR4__TRC_F0__FLD LPDDR4__DENALI_CTL_37__TRC_F0
  524. #define LPDDR4__DENALI_CTL_37__TRAS_MIN_F0_MASK 0x00FF0000U
  525. #define LPDDR4__DENALI_CTL_37__TRAS_MIN_F0_SHIFT 16U
  526. #define LPDDR4__DENALI_CTL_37__TRAS_MIN_F0_WIDTH 8U
  527. #define LPDDR4__TRAS_MIN_F0__REG DENALI_CTL_37
  528. #define LPDDR4__TRAS_MIN_F0__FLD LPDDR4__DENALI_CTL_37__TRAS_MIN_F0
  529. #define LPDDR4__DENALI_CTL_37__TWTR_F0_MASK 0x3F000000U
  530. #define LPDDR4__DENALI_CTL_37__TWTR_F0_SHIFT 24U
  531. #define LPDDR4__DENALI_CTL_37__TWTR_F0_WIDTH 6U
  532. #define LPDDR4__TWTR_F0__REG DENALI_CTL_37
  533. #define LPDDR4__TWTR_F0__FLD LPDDR4__DENALI_CTL_37__TWTR_F0
  534. #define LPDDR4__DENALI_CTL_38_READ_MASK 0xFF01FFFFU
  535. #define LPDDR4__DENALI_CTL_38_WRITE_MASK 0xFF01FFFFU
  536. #define LPDDR4__DENALI_CTL_38__TRP_F0_MASK 0x000000FFU
  537. #define LPDDR4__DENALI_CTL_38__TRP_F0_SHIFT 0U
  538. #define LPDDR4__DENALI_CTL_38__TRP_F0_WIDTH 8U
  539. #define LPDDR4__TRP_F0__REG DENALI_CTL_38
  540. #define LPDDR4__TRP_F0__FLD LPDDR4__DENALI_CTL_38__TRP_F0
  541. #define LPDDR4__DENALI_CTL_38__TFAW_F0_MASK 0x0001FF00U
  542. #define LPDDR4__DENALI_CTL_38__TFAW_F0_SHIFT 8U
  543. #define LPDDR4__DENALI_CTL_38__TFAW_F0_WIDTH 9U
  544. #define LPDDR4__TFAW_F0__REG DENALI_CTL_38
  545. #define LPDDR4__TFAW_F0__FLD LPDDR4__DENALI_CTL_38__TFAW_F0
  546. #define LPDDR4__DENALI_CTL_38__TRRD_F1_MASK 0xFF000000U
  547. #define LPDDR4__DENALI_CTL_38__TRRD_F1_SHIFT 24U
  548. #define LPDDR4__DENALI_CTL_38__TRRD_F1_WIDTH 8U
  549. #define LPDDR4__TRRD_F1__REG DENALI_CTL_38
  550. #define LPDDR4__TRRD_F1__FLD LPDDR4__DENALI_CTL_38__TRRD_F1
  551. #define LPDDR4__DENALI_CTL_39_READ_MASK 0x3FFF01FFU
  552. #define LPDDR4__DENALI_CTL_39_WRITE_MASK 0x3FFF01FFU
  553. #define LPDDR4__DENALI_CTL_39__TRC_F1_MASK 0x000001FFU
  554. #define LPDDR4__DENALI_CTL_39__TRC_F1_SHIFT 0U
  555. #define LPDDR4__DENALI_CTL_39__TRC_F1_WIDTH 9U
  556. #define LPDDR4__TRC_F1__REG DENALI_CTL_39
  557. #define LPDDR4__TRC_F1__FLD LPDDR4__DENALI_CTL_39__TRC_F1
  558. #define LPDDR4__DENALI_CTL_39__TRAS_MIN_F1_MASK 0x00FF0000U
  559. #define LPDDR4__DENALI_CTL_39__TRAS_MIN_F1_SHIFT 16U
  560. #define LPDDR4__DENALI_CTL_39__TRAS_MIN_F1_WIDTH 8U
  561. #define LPDDR4__TRAS_MIN_F1__REG DENALI_CTL_39
  562. #define LPDDR4__TRAS_MIN_F1__FLD LPDDR4__DENALI_CTL_39__TRAS_MIN_F1
  563. #define LPDDR4__DENALI_CTL_39__TWTR_F1_MASK 0x3F000000U
  564. #define LPDDR4__DENALI_CTL_39__TWTR_F1_SHIFT 24U
  565. #define LPDDR4__DENALI_CTL_39__TWTR_F1_WIDTH 6U
  566. #define LPDDR4__TWTR_F1__REG DENALI_CTL_39
  567. #define LPDDR4__TWTR_F1__FLD LPDDR4__DENALI_CTL_39__TWTR_F1
  568. #define LPDDR4__DENALI_CTL_40_READ_MASK 0xFF01FFFFU
  569. #define LPDDR4__DENALI_CTL_40_WRITE_MASK 0xFF01FFFFU
  570. #define LPDDR4__DENALI_CTL_40__TRP_F1_MASK 0x000000FFU
  571. #define LPDDR4__DENALI_CTL_40__TRP_F1_SHIFT 0U
  572. #define LPDDR4__DENALI_CTL_40__TRP_F1_WIDTH 8U
  573. #define LPDDR4__TRP_F1__REG DENALI_CTL_40
  574. #define LPDDR4__TRP_F1__FLD LPDDR4__DENALI_CTL_40__TRP_F1
  575. #define LPDDR4__DENALI_CTL_40__TFAW_F1_MASK 0x0001FF00U
  576. #define LPDDR4__DENALI_CTL_40__TFAW_F1_SHIFT 8U
  577. #define LPDDR4__DENALI_CTL_40__TFAW_F1_WIDTH 9U
  578. #define LPDDR4__TFAW_F1__REG DENALI_CTL_40
  579. #define LPDDR4__TFAW_F1__FLD LPDDR4__DENALI_CTL_40__TFAW_F1
  580. #define LPDDR4__DENALI_CTL_40__TRRD_F2_MASK 0xFF000000U
  581. #define LPDDR4__DENALI_CTL_40__TRRD_F2_SHIFT 24U
  582. #define LPDDR4__DENALI_CTL_40__TRRD_F2_WIDTH 8U
  583. #define LPDDR4__TRRD_F2__REG DENALI_CTL_40
  584. #define LPDDR4__TRRD_F2__FLD LPDDR4__DENALI_CTL_40__TRRD_F2
  585. #define LPDDR4__DENALI_CTL_41_READ_MASK 0x3FFF01FFU
  586. #define LPDDR4__DENALI_CTL_41_WRITE_MASK 0x3FFF01FFU
  587. #define LPDDR4__DENALI_CTL_41__TRC_F2_MASK 0x000001FFU
  588. #define LPDDR4__DENALI_CTL_41__TRC_F2_SHIFT 0U
  589. #define LPDDR4__DENALI_CTL_41__TRC_F2_WIDTH 9U
  590. #define LPDDR4__TRC_F2__REG DENALI_CTL_41
  591. #define LPDDR4__TRC_F2__FLD LPDDR4__DENALI_CTL_41__TRC_F2
  592. #define LPDDR4__DENALI_CTL_41__TRAS_MIN_F2_MASK 0x00FF0000U
  593. #define LPDDR4__DENALI_CTL_41__TRAS_MIN_F2_SHIFT 16U
  594. #define LPDDR4__DENALI_CTL_41__TRAS_MIN_F2_WIDTH 8U
  595. #define LPDDR4__TRAS_MIN_F2__REG DENALI_CTL_41
  596. #define LPDDR4__TRAS_MIN_F2__FLD LPDDR4__DENALI_CTL_41__TRAS_MIN_F2
  597. #define LPDDR4__DENALI_CTL_41__TWTR_F2_MASK 0x3F000000U
  598. #define LPDDR4__DENALI_CTL_41__TWTR_F2_SHIFT 24U
  599. #define LPDDR4__DENALI_CTL_41__TWTR_F2_WIDTH 6U
  600. #define LPDDR4__TWTR_F2__REG DENALI_CTL_41
  601. #define LPDDR4__TWTR_F2__FLD LPDDR4__DENALI_CTL_41__TWTR_F2
  602. #define LPDDR4__DENALI_CTL_42_READ_MASK 0x3F01FFFFU
  603. #define LPDDR4__DENALI_CTL_42_WRITE_MASK 0x3F01FFFFU
  604. #define LPDDR4__DENALI_CTL_42__TRP_F2_MASK 0x000000FFU
  605. #define LPDDR4__DENALI_CTL_42__TRP_F2_SHIFT 0U
  606. #define LPDDR4__DENALI_CTL_42__TRP_F2_WIDTH 8U
  607. #define LPDDR4__TRP_F2__REG DENALI_CTL_42
  608. #define LPDDR4__TRP_F2__FLD LPDDR4__DENALI_CTL_42__TRP_F2
  609. #define LPDDR4__DENALI_CTL_42__TFAW_F2_MASK 0x0001FF00U
  610. #define LPDDR4__DENALI_CTL_42__TFAW_F2_SHIFT 8U
  611. #define LPDDR4__DENALI_CTL_42__TFAW_F2_WIDTH 9U
  612. #define LPDDR4__TFAW_F2__REG DENALI_CTL_42
  613. #define LPDDR4__TFAW_F2__FLD LPDDR4__DENALI_CTL_42__TFAW_F2
  614. #define LPDDR4__DENALI_CTL_42__TCCDMW_MASK 0x3F000000U
  615. #define LPDDR4__DENALI_CTL_42__TCCDMW_SHIFT 24U
  616. #define LPDDR4__DENALI_CTL_42__TCCDMW_WIDTH 6U
  617. #define LPDDR4__TCCDMW__REG DENALI_CTL_42
  618. #define LPDDR4__TCCDMW__FLD LPDDR4__DENALI_CTL_42__TCCDMW
  619. #define LPDDR4__DENALI_CTL_43_READ_MASK 0x00FFFFFFU
  620. #define LPDDR4__DENALI_CTL_43_WRITE_MASK 0x00FFFFFFU
  621. #define LPDDR4__DENALI_CTL_43__TRTP_F0_MASK 0x000000FFU
  622. #define LPDDR4__DENALI_CTL_43__TRTP_F0_SHIFT 0U
  623. #define LPDDR4__DENALI_CTL_43__TRTP_F0_WIDTH 8U
  624. #define LPDDR4__TRTP_F0__REG DENALI_CTL_43
  625. #define LPDDR4__TRTP_F0__FLD LPDDR4__DENALI_CTL_43__TRTP_F0
  626. #define LPDDR4__DENALI_CTL_43__TMRD_F0_MASK 0x0000FF00U
  627. #define LPDDR4__DENALI_CTL_43__TMRD_F0_SHIFT 8U
  628. #define LPDDR4__DENALI_CTL_43__TMRD_F0_WIDTH 8U
  629. #define LPDDR4__TMRD_F0__REG DENALI_CTL_43
  630. #define LPDDR4__TMRD_F0__FLD LPDDR4__DENALI_CTL_43__TMRD_F0
  631. #define LPDDR4__DENALI_CTL_43__TMOD_F0_MASK 0x00FF0000U
  632. #define LPDDR4__DENALI_CTL_43__TMOD_F0_SHIFT 16U
  633. #define LPDDR4__DENALI_CTL_43__TMOD_F0_WIDTH 8U
  634. #define LPDDR4__TMOD_F0__REG DENALI_CTL_43
  635. #define LPDDR4__TMOD_F0__FLD LPDDR4__DENALI_CTL_43__TMOD_F0
  636. #define LPDDR4__DENALI_CTL_44_READ_MASK 0x1F01FFFFU
  637. #define LPDDR4__DENALI_CTL_44_WRITE_MASK 0x1F01FFFFU
  638. #define LPDDR4__DENALI_CTL_44__TRAS_MAX_F0_MASK 0x0001FFFFU
  639. #define LPDDR4__DENALI_CTL_44__TRAS_MAX_F0_SHIFT 0U
  640. #define LPDDR4__DENALI_CTL_44__TRAS_MAX_F0_WIDTH 17U
  641. #define LPDDR4__TRAS_MAX_F0__REG DENALI_CTL_44
  642. #define LPDDR4__TRAS_MAX_F0__FLD LPDDR4__DENALI_CTL_44__TRAS_MAX_F0
  643. #define LPDDR4__DENALI_CTL_44__TCKE_F0_MASK 0x1F000000U
  644. #define LPDDR4__DENALI_CTL_44__TCKE_F0_SHIFT 24U
  645. #define LPDDR4__DENALI_CTL_44__TCKE_F0_WIDTH 5U
  646. #define LPDDR4__TCKE_F0__REG DENALI_CTL_44
  647. #define LPDDR4__TCKE_F0__FLD LPDDR4__DENALI_CTL_44__TCKE_F0
  648. #define LPDDR4__DENALI_CTL_45_READ_MASK 0xFFFFFFFFU
  649. #define LPDDR4__DENALI_CTL_45_WRITE_MASK 0xFFFFFFFFU
  650. #define LPDDR4__DENALI_CTL_45__TCKESR_F0_MASK 0x000000FFU
  651. #define LPDDR4__DENALI_CTL_45__TCKESR_F0_SHIFT 0U
  652. #define LPDDR4__DENALI_CTL_45__TCKESR_F0_WIDTH 8U
  653. #define LPDDR4__TCKESR_F0__REG DENALI_CTL_45
  654. #define LPDDR4__TCKESR_F0__FLD LPDDR4__DENALI_CTL_45__TCKESR_F0
  655. #define LPDDR4__DENALI_CTL_45__TRTP_F1_MASK 0x0000FF00U
  656. #define LPDDR4__DENALI_CTL_45__TRTP_F1_SHIFT 8U
  657. #define LPDDR4__DENALI_CTL_45__TRTP_F1_WIDTH 8U
  658. #define LPDDR4__TRTP_F1__REG DENALI_CTL_45
  659. #define LPDDR4__TRTP_F1__FLD LPDDR4__DENALI_CTL_45__TRTP_F1
  660. #define LPDDR4__DENALI_CTL_45__TMRD_F1_MASK 0x00FF0000U
  661. #define LPDDR4__DENALI_CTL_45__TMRD_F1_SHIFT 16U
  662. #define LPDDR4__DENALI_CTL_45__TMRD_F1_WIDTH 8U
  663. #define LPDDR4__TMRD_F1__REG DENALI_CTL_45
  664. #define LPDDR4__TMRD_F1__FLD LPDDR4__DENALI_CTL_45__TMRD_F1
  665. #define LPDDR4__DENALI_CTL_45__TMOD_F1_MASK 0xFF000000U
  666. #define LPDDR4__DENALI_CTL_45__TMOD_F1_SHIFT 24U
  667. #define LPDDR4__DENALI_CTL_45__TMOD_F1_WIDTH 8U
  668. #define LPDDR4__TMOD_F1__REG DENALI_CTL_45
  669. #define LPDDR4__TMOD_F1__FLD LPDDR4__DENALI_CTL_45__TMOD_F1
  670. #define LPDDR4__DENALI_CTL_46_READ_MASK 0x1F01FFFFU
  671. #define LPDDR4__DENALI_CTL_46_WRITE_MASK 0x1F01FFFFU
  672. #define LPDDR4__DENALI_CTL_46__TRAS_MAX_F1_MASK 0x0001FFFFU
  673. #define LPDDR4__DENALI_CTL_46__TRAS_MAX_F1_SHIFT 0U
  674. #define LPDDR4__DENALI_CTL_46__TRAS_MAX_F1_WIDTH 17U
  675. #define LPDDR4__TRAS_MAX_F1__REG DENALI_CTL_46
  676. #define LPDDR4__TRAS_MAX_F1__FLD LPDDR4__DENALI_CTL_46__TRAS_MAX_F1
  677. #define LPDDR4__DENALI_CTL_46__TCKE_F1_MASK 0x1F000000U
  678. #define LPDDR4__DENALI_CTL_46__TCKE_F1_SHIFT 24U
  679. #define LPDDR4__DENALI_CTL_46__TCKE_F1_WIDTH 5U
  680. #define LPDDR4__TCKE_F1__REG DENALI_CTL_46
  681. #define LPDDR4__TCKE_F1__FLD LPDDR4__DENALI_CTL_46__TCKE_F1
  682. #define LPDDR4__DENALI_CTL_47_READ_MASK 0xFFFFFFFFU
  683. #define LPDDR4__DENALI_CTL_47_WRITE_MASK 0xFFFFFFFFU
  684. #define LPDDR4__DENALI_CTL_47__TCKESR_F1_MASK 0x000000FFU
  685. #define LPDDR4__DENALI_CTL_47__TCKESR_F1_SHIFT 0U
  686. #define LPDDR4__DENALI_CTL_47__TCKESR_F1_WIDTH 8U
  687. #define LPDDR4__TCKESR_F1__REG DENALI_CTL_47
  688. #define LPDDR4__TCKESR_F1__FLD LPDDR4__DENALI_CTL_47__TCKESR_F1
  689. #define LPDDR4__DENALI_CTL_47__TRTP_F2_MASK 0x0000FF00U
  690. #define LPDDR4__DENALI_CTL_47__TRTP_F2_SHIFT 8U
  691. #define LPDDR4__DENALI_CTL_47__TRTP_F2_WIDTH 8U
  692. #define LPDDR4__TRTP_F2__REG DENALI_CTL_47
  693. #define LPDDR4__TRTP_F2__FLD LPDDR4__DENALI_CTL_47__TRTP_F2
  694. #define LPDDR4__DENALI_CTL_47__TMRD_F2_MASK 0x00FF0000U
  695. #define LPDDR4__DENALI_CTL_47__TMRD_F2_SHIFT 16U
  696. #define LPDDR4__DENALI_CTL_47__TMRD_F2_WIDTH 8U
  697. #define LPDDR4__TMRD_F2__REG DENALI_CTL_47
  698. #define LPDDR4__TMRD_F2__FLD LPDDR4__DENALI_CTL_47__TMRD_F2
  699. #define LPDDR4__DENALI_CTL_47__TMOD_F2_MASK 0xFF000000U
  700. #define LPDDR4__DENALI_CTL_47__TMOD_F2_SHIFT 24U
  701. #define LPDDR4__DENALI_CTL_47__TMOD_F2_WIDTH 8U
  702. #define LPDDR4__TMOD_F2__REG DENALI_CTL_47
  703. #define LPDDR4__TMOD_F2__FLD LPDDR4__DENALI_CTL_47__TMOD_F2
  704. #define LPDDR4__DENALI_CTL_48_READ_MASK 0x1F01FFFFU
  705. #define LPDDR4__DENALI_CTL_48_WRITE_MASK 0x1F01FFFFU
  706. #define LPDDR4__DENALI_CTL_48__TRAS_MAX_F2_MASK 0x0001FFFFU
  707. #define LPDDR4__DENALI_CTL_48__TRAS_MAX_F2_SHIFT 0U
  708. #define LPDDR4__DENALI_CTL_48__TRAS_MAX_F2_WIDTH 17U
  709. #define LPDDR4__TRAS_MAX_F2__REG DENALI_CTL_48
  710. #define LPDDR4__TRAS_MAX_F2__FLD LPDDR4__DENALI_CTL_48__TRAS_MAX_F2
  711. #define LPDDR4__DENALI_CTL_48__TCKE_F2_MASK 0x1F000000U
  712. #define LPDDR4__DENALI_CTL_48__TCKE_F2_SHIFT 24U
  713. #define LPDDR4__DENALI_CTL_48__TCKE_F2_WIDTH 5U
  714. #define LPDDR4__TCKE_F2__REG DENALI_CTL_48
  715. #define LPDDR4__TCKE_F2__FLD LPDDR4__DENALI_CTL_48__TCKE_F2
  716. #define LPDDR4__DENALI_CTL_49_READ_MASK 0x070707FFU
  717. #define LPDDR4__DENALI_CTL_49_WRITE_MASK 0x070707FFU
  718. #define LPDDR4__DENALI_CTL_49__TCKESR_F2_MASK 0x000000FFU
  719. #define LPDDR4__DENALI_CTL_49__TCKESR_F2_SHIFT 0U
  720. #define LPDDR4__DENALI_CTL_49__TCKESR_F2_WIDTH 8U
  721. #define LPDDR4__TCKESR_F2__REG DENALI_CTL_49
  722. #define LPDDR4__TCKESR_F2__FLD LPDDR4__DENALI_CTL_49__TCKESR_F2
  723. #define LPDDR4__DENALI_CTL_49__TPPD_MASK 0x00000700U
  724. #define LPDDR4__DENALI_CTL_49__TPPD_SHIFT 8U
  725. #define LPDDR4__DENALI_CTL_49__TPPD_WIDTH 3U
  726. #define LPDDR4__TPPD__REG DENALI_CTL_49
  727. #define LPDDR4__TPPD__FLD LPDDR4__DENALI_CTL_49__TPPD
  728. #define LPDDR4__DENALI_CTL_49__MC_RESERVED4_MASK 0x00070000U
  729. #define LPDDR4__DENALI_CTL_49__MC_RESERVED4_SHIFT 16U
  730. #define LPDDR4__DENALI_CTL_49__MC_RESERVED4_WIDTH 3U
  731. #define LPDDR4__MC_RESERVED4__REG DENALI_CTL_49
  732. #define LPDDR4__MC_RESERVED4__FLD LPDDR4__DENALI_CTL_49__MC_RESERVED4
  733. #define LPDDR4__DENALI_CTL_49__MC_RESERVED5_MASK 0x07000000U
  734. #define LPDDR4__DENALI_CTL_49__MC_RESERVED5_SHIFT 24U
  735. #define LPDDR4__DENALI_CTL_49__MC_RESERVED5_WIDTH 3U
  736. #define LPDDR4__MC_RESERVED5__REG DENALI_CTL_49
  737. #define LPDDR4__MC_RESERVED5__FLD LPDDR4__DENALI_CTL_49__MC_RESERVED5
  738. #define LPDDR4__DENALI_CTL_50_READ_MASK 0xFFFFFF01U
  739. #define LPDDR4__DENALI_CTL_50_WRITE_MASK 0xFFFFFF01U
  740. #define LPDDR4__DENALI_CTL_50__WRITEINTERP_MASK 0x00000001U
  741. #define LPDDR4__DENALI_CTL_50__WRITEINTERP_SHIFT 0U
  742. #define LPDDR4__DENALI_CTL_50__WRITEINTERP_WIDTH 1U
  743. #define LPDDR4__DENALI_CTL_50__WRITEINTERP_WOCLR 0U
  744. #define LPDDR4__DENALI_CTL_50__WRITEINTERP_WOSET 0U
  745. #define LPDDR4__WRITEINTERP__REG DENALI_CTL_50
  746. #define LPDDR4__WRITEINTERP__FLD LPDDR4__DENALI_CTL_50__WRITEINTERP
  747. #define LPDDR4__DENALI_CTL_50__TRCD_F0_MASK 0x0000FF00U
  748. #define LPDDR4__DENALI_CTL_50__TRCD_F0_SHIFT 8U
  749. #define LPDDR4__DENALI_CTL_50__TRCD_F0_WIDTH 8U
  750. #define LPDDR4__TRCD_F0__REG DENALI_CTL_50
  751. #define LPDDR4__TRCD_F0__FLD LPDDR4__DENALI_CTL_50__TRCD_F0
  752. #define LPDDR4__DENALI_CTL_50__TWR_F0_MASK 0x00FF0000U
  753. #define LPDDR4__DENALI_CTL_50__TWR_F0_SHIFT 16U
  754. #define LPDDR4__DENALI_CTL_50__TWR_F0_WIDTH 8U
  755. #define LPDDR4__TWR_F0__REG DENALI_CTL_50
  756. #define LPDDR4__TWR_F0__FLD LPDDR4__DENALI_CTL_50__TWR_F0
  757. #define LPDDR4__DENALI_CTL_50__TRCD_F1_MASK 0xFF000000U
  758. #define LPDDR4__DENALI_CTL_50__TRCD_F1_SHIFT 24U
  759. #define LPDDR4__DENALI_CTL_50__TRCD_F1_WIDTH 8U
  760. #define LPDDR4__TRCD_F1__REG DENALI_CTL_50
  761. #define LPDDR4__TRCD_F1__FLD LPDDR4__DENALI_CTL_50__TRCD_F1
  762. #define LPDDR4__DENALI_CTL_51_READ_MASK 0x0FFFFFFFU
  763. #define LPDDR4__DENALI_CTL_51_WRITE_MASK 0x0FFFFFFFU
  764. #define LPDDR4__DENALI_CTL_51__TWR_F1_MASK 0x000000FFU
  765. #define LPDDR4__DENALI_CTL_51__TWR_F1_SHIFT 0U
  766. #define LPDDR4__DENALI_CTL_51__TWR_F1_WIDTH 8U
  767. #define LPDDR4__TWR_F1__REG DENALI_CTL_51
  768. #define LPDDR4__TWR_F1__FLD LPDDR4__DENALI_CTL_51__TWR_F1
  769. #define LPDDR4__DENALI_CTL_51__TRCD_F2_MASK 0x0000FF00U
  770. #define LPDDR4__DENALI_CTL_51__TRCD_F2_SHIFT 8U
  771. #define LPDDR4__DENALI_CTL_51__TRCD_F2_WIDTH 8U
  772. #define LPDDR4__TRCD_F2__REG DENALI_CTL_51
  773. #define LPDDR4__TRCD_F2__FLD LPDDR4__DENALI_CTL_51__TRCD_F2
  774. #define LPDDR4__DENALI_CTL_51__TWR_F2_MASK 0x00FF0000U
  775. #define LPDDR4__DENALI_CTL_51__TWR_F2_SHIFT 16U
  776. #define LPDDR4__DENALI_CTL_51__TWR_F2_WIDTH 8U
  777. #define LPDDR4__TWR_F2__REG DENALI_CTL_51
  778. #define LPDDR4__TWR_F2__FLD LPDDR4__DENALI_CTL_51__TWR_F2
  779. #define LPDDR4__DENALI_CTL_51__TMRR_MASK 0x0F000000U
  780. #define LPDDR4__DENALI_CTL_51__TMRR_SHIFT 24U
  781. #define LPDDR4__DENALI_CTL_51__TMRR_WIDTH 4U
  782. #define LPDDR4__TMRR__REG DENALI_CTL_51
  783. #define LPDDR4__TMRR__FLD LPDDR4__DENALI_CTL_51__TMRR
  784. #define LPDDR4__DENALI_CTL_52_READ_MASK 0x3F03FF1FU
  785. #define LPDDR4__DENALI_CTL_52_WRITE_MASK 0x3F03FF1FU
  786. #define LPDDR4__DENALI_CTL_52__TCACKEL_MASK 0x0000001FU
  787. #define LPDDR4__DENALI_CTL_52__TCACKEL_SHIFT 0U
  788. #define LPDDR4__DENALI_CTL_52__TCACKEL_WIDTH 5U
  789. #define LPDDR4__TCACKEL__REG DENALI_CTL_52
  790. #define LPDDR4__TCACKEL__FLD LPDDR4__DENALI_CTL_52__TCACKEL
  791. #define LPDDR4__DENALI_CTL_52__TCAENT_MASK 0x0003FF00U
  792. #define LPDDR4__DENALI_CTL_52__TCAENT_SHIFT 8U
  793. #define LPDDR4__DENALI_CTL_52__TCAENT_WIDTH 10U
  794. #define LPDDR4__TCAENT__REG DENALI_CTL_52
  795. #define LPDDR4__TCAENT__FLD LPDDR4__DENALI_CTL_52__TCAENT
  796. #define LPDDR4__DENALI_CTL_52__TCAMRD_MASK 0x3F000000U
  797. #define LPDDR4__DENALI_CTL_52__TCAMRD_SHIFT 24U
  798. #define LPDDR4__DENALI_CTL_52__TCAMRD_WIDTH 6U
  799. #define LPDDR4__TCAMRD__REG DENALI_CTL_52
  800. #define LPDDR4__TCAMRD__FLD LPDDR4__DENALI_CTL_52__TCAMRD
  801. #define LPDDR4__DENALI_CTL_53_READ_MASK 0x1F1F1F1FU
  802. #define LPDDR4__DENALI_CTL_53_WRITE_MASK 0x1F1F1F1FU
  803. #define LPDDR4__DENALI_CTL_53__TCAEXT_MASK 0x0000001FU
  804. #define LPDDR4__DENALI_CTL_53__TCAEXT_SHIFT 0U
  805. #define LPDDR4__DENALI_CTL_53__TCAEXT_WIDTH 5U
  806. #define LPDDR4__TCAEXT__REG DENALI_CTL_53
  807. #define LPDDR4__TCAEXT__FLD LPDDR4__DENALI_CTL_53__TCAEXT
  808. #define LPDDR4__DENALI_CTL_53__TCACKEH_MASK 0x00001F00U
  809. #define LPDDR4__DENALI_CTL_53__TCACKEH_SHIFT 8U
  810. #define LPDDR4__DENALI_CTL_53__TCACKEH_WIDTH 5U
  811. #define LPDDR4__TCACKEH__REG DENALI_CTL_53
  812. #define LPDDR4__TCACKEH__FLD LPDDR4__DENALI_CTL_53__TCACKEH
  813. #define LPDDR4__DENALI_CTL_53__TMRZ_F0_MASK 0x001F0000U
  814. #define LPDDR4__DENALI_CTL_53__TMRZ_F0_SHIFT 16U
  815. #define LPDDR4__DENALI_CTL_53__TMRZ_F0_WIDTH 5U
  816. #define LPDDR4__TMRZ_F0__REG DENALI_CTL_53
  817. #define LPDDR4__TMRZ_F0__FLD LPDDR4__DENALI_CTL_53__TMRZ_F0
  818. #define LPDDR4__DENALI_CTL_53__TMRZ_F1_MASK 0x1F000000U
  819. #define LPDDR4__DENALI_CTL_53__TMRZ_F1_SHIFT 24U
  820. #define LPDDR4__DENALI_CTL_53__TMRZ_F1_WIDTH 5U
  821. #define LPDDR4__TMRZ_F1__REG DENALI_CTL_53
  822. #define LPDDR4__TMRZ_F1__FLD LPDDR4__DENALI_CTL_53__TMRZ_F1
  823. #define LPDDR4__DENALI_CTL_54_READ_MASK 0x0101011FU
  824. #define LPDDR4__DENALI_CTL_54_WRITE_MASK 0x0101011FU
  825. #define LPDDR4__DENALI_CTL_54__TMRZ_F2_MASK 0x0000001FU
  826. #define LPDDR4__DENALI_CTL_54__TMRZ_F2_SHIFT 0U
  827. #define LPDDR4__DENALI_CTL_54__TMRZ_F2_WIDTH 5U
  828. #define LPDDR4__TMRZ_F2__REG DENALI_CTL_54
  829. #define LPDDR4__TMRZ_F2__FLD LPDDR4__DENALI_CTL_54__TMRZ_F2
  830. #define LPDDR4__DENALI_CTL_54__AP_MASK 0x00000100U
  831. #define LPDDR4__DENALI_CTL_54__AP_SHIFT 8U
  832. #define LPDDR4__DENALI_CTL_54__AP_WIDTH 1U
  833. #define LPDDR4__DENALI_CTL_54__AP_WOCLR 0U
  834. #define LPDDR4__DENALI_CTL_54__AP_WOSET 0U
  835. #define LPDDR4__AP__REG DENALI_CTL_54
  836. #define LPDDR4__AP__FLD LPDDR4__DENALI_CTL_54__AP
  837. #define LPDDR4__DENALI_CTL_54__CONCURRENTAP_MASK 0x00010000U
  838. #define LPDDR4__DENALI_CTL_54__CONCURRENTAP_SHIFT 16U
  839. #define LPDDR4__DENALI_CTL_54__CONCURRENTAP_WIDTH 1U
  840. #define LPDDR4__DENALI_CTL_54__CONCURRENTAP_WOCLR 0U
  841. #define LPDDR4__DENALI_CTL_54__CONCURRENTAP_WOSET 0U
  842. #define LPDDR4__CONCURRENTAP__REG DENALI_CTL_54
  843. #define LPDDR4__CONCURRENTAP__FLD LPDDR4__DENALI_CTL_54__CONCURRENTAP
  844. #define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_MASK 0x01000000U
  845. #define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_SHIFT 24U
  846. #define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_WIDTH 1U
  847. #define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_WOCLR 0U
  848. #define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_WOSET 0U
  849. #define LPDDR4__TRAS_LOCKOUT__REG DENALI_CTL_54
  850. #define LPDDR4__TRAS_LOCKOUT__FLD LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT
  851. #define LPDDR4__DENALI_CTL_55_READ_MASK 0x1FFFFFFFU
  852. #define LPDDR4__DENALI_CTL_55_WRITE_MASK 0x1FFFFFFFU
  853. #define LPDDR4__DENALI_CTL_55__TDAL_F0_MASK 0x000000FFU
  854. #define LPDDR4__DENALI_CTL_55__TDAL_F0_SHIFT 0U
  855. #define LPDDR4__DENALI_CTL_55__TDAL_F0_WIDTH 8U
  856. #define LPDDR4__TDAL_F0__REG DENALI_CTL_55
  857. #define LPDDR4__TDAL_F0__FLD LPDDR4__DENALI_CTL_55__TDAL_F0
  858. #define LPDDR4__DENALI_CTL_55__TDAL_F1_MASK 0x0000FF00U
  859. #define LPDDR4__DENALI_CTL_55__TDAL_F1_SHIFT 8U
  860. #define LPDDR4__DENALI_CTL_55__TDAL_F1_WIDTH 8U
  861. #define LPDDR4__TDAL_F1__REG DENALI_CTL_55
  862. #define LPDDR4__TDAL_F1__FLD LPDDR4__DENALI_CTL_55__TDAL_F1
  863. #define LPDDR4__DENALI_CTL_55__TDAL_F2_MASK 0x00FF0000U
  864. #define LPDDR4__DENALI_CTL_55__TDAL_F2_SHIFT 16U
  865. #define LPDDR4__DENALI_CTL_55__TDAL_F2_WIDTH 8U
  866. #define LPDDR4__TDAL_F2__REG DENALI_CTL_55
  867. #define LPDDR4__TDAL_F2__FLD LPDDR4__DENALI_CTL_55__TDAL_F2
  868. #define LPDDR4__DENALI_CTL_55__BSTLEN_MASK 0x1F000000U
  869. #define LPDDR4__DENALI_CTL_55__BSTLEN_SHIFT 24U
  870. #define LPDDR4__DENALI_CTL_55__BSTLEN_WIDTH 5U
  871. #define LPDDR4__BSTLEN__REG DENALI_CTL_55
  872. #define LPDDR4__BSTLEN__FLD LPDDR4__DENALI_CTL_55__BSTLEN
  873. #define LPDDR4__DENALI_CTL_56_READ_MASK 0xFFFFFFFFU
  874. #define LPDDR4__DENALI_CTL_56_WRITE_MASK 0xFFFFFFFFU
  875. #define LPDDR4__DENALI_CTL_56__TRP_AB_F0_0_MASK 0x000000FFU
  876. #define LPDDR4__DENALI_CTL_56__TRP_AB_F0_0_SHIFT 0U
  877. #define LPDDR4__DENALI_CTL_56__TRP_AB_F0_0_WIDTH 8U
  878. #define LPDDR4__TRP_AB_F0_0__REG DENALI_CTL_56
  879. #define LPDDR4__TRP_AB_F0_0__FLD LPDDR4__DENALI_CTL_56__TRP_AB_F0_0
  880. #define LPDDR4__DENALI_CTL_56__TRP_AB_F1_0_MASK 0x0000FF00U
  881. #define LPDDR4__DENALI_CTL_56__TRP_AB_F1_0_SHIFT 8U
  882. #define LPDDR4__DENALI_CTL_56__TRP_AB_F1_0_WIDTH 8U
  883. #define LPDDR4__TRP_AB_F1_0__REG DENALI_CTL_56
  884. #define LPDDR4__TRP_AB_F1_0__FLD LPDDR4__DENALI_CTL_56__TRP_AB_F1_0
  885. #define LPDDR4__DENALI_CTL_56__TRP_AB_F2_0_MASK 0x00FF0000U
  886. #define LPDDR4__DENALI_CTL_56__TRP_AB_F2_0_SHIFT 16U
  887. #define LPDDR4__DENALI_CTL_56__TRP_AB_F2_0_WIDTH 8U
  888. #define LPDDR4__TRP_AB_F2_0__REG DENALI_CTL_56
  889. #define LPDDR4__TRP_AB_F2_0__FLD LPDDR4__DENALI_CTL_56__TRP_AB_F2_0
  890. #define LPDDR4__DENALI_CTL_56__TRP_AB_F0_1_MASK 0xFF000000U
  891. #define LPDDR4__DENALI_CTL_56__TRP_AB_F0_1_SHIFT 24U
  892. #define LPDDR4__DENALI_CTL_56__TRP_AB_F0_1_WIDTH 8U
  893. #define LPDDR4__TRP_AB_F0_1__REG DENALI_CTL_56
  894. #define LPDDR4__TRP_AB_F0_1__FLD LPDDR4__DENALI_CTL_56__TRP_AB_F0_1
  895. #define LPDDR4__DENALI_CTL_57_READ_MASK 0x0301FFFFU
  896. #define LPDDR4__DENALI_CTL_57_WRITE_MASK 0x0301FFFFU
  897. #define LPDDR4__DENALI_CTL_57__TRP_AB_F1_1_MASK 0x000000FFU
  898. #define LPDDR4__DENALI_CTL_57__TRP_AB_F1_1_SHIFT 0U
  899. #define LPDDR4__DENALI_CTL_57__TRP_AB_F1_1_WIDTH 8U
  900. #define LPDDR4__TRP_AB_F1_1__REG DENALI_CTL_57
  901. #define LPDDR4__TRP_AB_F1_1__FLD LPDDR4__DENALI_CTL_57__TRP_AB_F1_1
  902. #define LPDDR4__DENALI_CTL_57__TRP_AB_F2_1_MASK 0x0000FF00U
  903. #define LPDDR4__DENALI_CTL_57__TRP_AB_F2_1_SHIFT 8U
  904. #define LPDDR4__DENALI_CTL_57__TRP_AB_F2_1_WIDTH 8U
  905. #define LPDDR4__TRP_AB_F2_1__REG DENALI_CTL_57
  906. #define LPDDR4__TRP_AB_F2_1__FLD LPDDR4__DENALI_CTL_57__TRP_AB_F2_1
  907. #define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_MASK 0x00010000U
  908. #define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_SHIFT 16U
  909. #define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_WIDTH 1U
  910. #define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_WOCLR 0U
  911. #define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_WOSET 0U
  912. #define LPDDR4__REG_DIMM_ENABLE__REG DENALI_CTL_57
  913. #define LPDDR4__REG_DIMM_ENABLE__FLD LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE
  914. #define LPDDR4__DENALI_CTL_57__MC_RESERVED6_MASK 0x03000000U
  915. #define LPDDR4__DENALI_CTL_57__MC_RESERVED6_SHIFT 24U
  916. #define LPDDR4__DENALI_CTL_57__MC_RESERVED6_WIDTH 2U
  917. #define LPDDR4__MC_RESERVED6__REG DENALI_CTL_57
  918. #define LPDDR4__MC_RESERVED6__FLD LPDDR4__DENALI_CTL_57__MC_RESERVED6
  919. #define LPDDR4__DENALI_CTL_58_READ_MASK 0x0101017FU
  920. #define LPDDR4__DENALI_CTL_58_WRITE_MASK 0x0101017FU
  921. #define LPDDR4__DENALI_CTL_58__MC_RESERVED7_MASK 0x0000007FU
  922. #define LPDDR4__DENALI_CTL_58__MC_RESERVED7_SHIFT 0U
  923. #define LPDDR4__DENALI_CTL_58__MC_RESERVED7_WIDTH 7U
  924. #define LPDDR4__MC_RESERVED7__REG DENALI_CTL_58
  925. #define LPDDR4__MC_RESERVED7__FLD LPDDR4__DENALI_CTL_58__MC_RESERVED7
  926. #define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_MASK 0x00000100U
  927. #define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_SHIFT 8U
  928. #define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_WIDTH 1U
  929. #define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_WOCLR 0U
  930. #define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_WOSET 0U
  931. #define LPDDR4__OPTIMAL_RMODW_EN__REG DENALI_CTL_58
  932. #define LPDDR4__OPTIMAL_RMODW_EN__FLD LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN
  933. #define LPDDR4__DENALI_CTL_58__MC_RESERVED8_MASK 0x00010000U
  934. #define LPDDR4__DENALI_CTL_58__MC_RESERVED8_SHIFT 16U
  935. #define LPDDR4__DENALI_CTL_58__MC_RESERVED8_WIDTH 1U
  936. #define LPDDR4__DENALI_CTL_58__MC_RESERVED8_WOCLR 0U
  937. #define LPDDR4__DENALI_CTL_58__MC_RESERVED8_WOSET 0U
  938. #define LPDDR4__MC_RESERVED8__REG DENALI_CTL_58
  939. #define LPDDR4__MC_RESERVED8__FLD LPDDR4__DENALI_CTL_58__MC_RESERVED8
  940. #define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_MASK 0x01000000U
  941. #define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_SHIFT 24U
  942. #define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_WIDTH 1U
  943. #define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_WOCLR 0U
  944. #define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_WOSET 0U
  945. #define LPDDR4__NO_MEMORY_DM__REG DENALI_CTL_58
  946. #define LPDDR4__NO_MEMORY_DM__FLD LPDDR4__DENALI_CTL_58__NO_MEMORY_DM
  947. #define LPDDR4__DENALI_CTL_59_READ_MASK 0x07010100U
  948. #define LPDDR4__DENALI_CTL_59_WRITE_MASK 0x07010100U
  949. #define LPDDR4__DENALI_CTL_59__AREFRESH_MASK 0x00000001U
  950. #define LPDDR4__DENALI_CTL_59__AREFRESH_SHIFT 0U
  951. #define LPDDR4__DENALI_CTL_59__AREFRESH_WIDTH 1U
  952. #define LPDDR4__DENALI_CTL_59__AREFRESH_WOCLR 0U
  953. #define LPDDR4__DENALI_CTL_59__AREFRESH_WOSET 0U
  954. #define LPDDR4__AREFRESH__REG DENALI_CTL_59
  955. #define LPDDR4__AREFRESH__FLD LPDDR4__DENALI_CTL_59__AREFRESH
  956. #define LPDDR4__DENALI_CTL_59__AREF_STATUS_MASK 0x00000100U
  957. #define LPDDR4__DENALI_CTL_59__AREF_STATUS_SHIFT 8U
  958. #define LPDDR4__DENALI_CTL_59__AREF_STATUS_WIDTH 1U
  959. #define LPDDR4__DENALI_CTL_59__AREF_STATUS_WOCLR 0U
  960. #define LPDDR4__DENALI_CTL_59__AREF_STATUS_WOSET 0U
  961. #define LPDDR4__AREF_STATUS__REG DENALI_CTL_59
  962. #define LPDDR4__AREF_STATUS__FLD LPDDR4__DENALI_CTL_59__AREF_STATUS
  963. #define LPDDR4__DENALI_CTL_59__TREF_ENABLE_MASK 0x00010000U
  964. #define LPDDR4__DENALI_CTL_59__TREF_ENABLE_SHIFT 16U
  965. #define LPDDR4__DENALI_CTL_59__TREF_ENABLE_WIDTH 1U
  966. #define LPDDR4__DENALI_CTL_59__TREF_ENABLE_WOCLR 0U
  967. #define LPDDR4__DENALI_CTL_59__TREF_ENABLE_WOSET 0U
  968. #define LPDDR4__TREF_ENABLE__REG DENALI_CTL_59
  969. #define LPDDR4__TREF_ENABLE__FLD LPDDR4__DENALI_CTL_59__TREF_ENABLE
  970. #define LPDDR4__DENALI_CTL_59__MC_RESERVED9_MASK 0x07000000U
  971. #define LPDDR4__DENALI_CTL_59__MC_RESERVED9_SHIFT 24U
  972. #define LPDDR4__DENALI_CTL_59__MC_RESERVED9_WIDTH 3U
  973. #define LPDDR4__MC_RESERVED9__REG DENALI_CTL_59
  974. #define LPDDR4__MC_RESERVED9__FLD LPDDR4__DENALI_CTL_59__MC_RESERVED9
  975. #define LPDDR4__DENALI_CTL_60_READ_MASK 0x0003FF3FU
  976. #define LPDDR4__DENALI_CTL_60_WRITE_MASK 0x0003FF3FU
  977. #define LPDDR4__DENALI_CTL_60__CS_COMPARISON_FOR_REFRESH_DEPTH_MASK 0x0000003FU
  978. #define LPDDR4__DENALI_CTL_60__CS_COMPARISON_FOR_REFRESH_DEPTH_SHIFT 0U
  979. #define LPDDR4__DENALI_CTL_60__CS_COMPARISON_FOR_REFRESH_DEPTH_WIDTH 6U
  980. #define LPDDR4__CS_COMPARISON_FOR_REFRESH_DEPTH__REG DENALI_CTL_60
  981. #define LPDDR4__CS_COMPARISON_FOR_REFRESH_DEPTH__FLD LPDDR4__DENALI_CTL_60__CS_COMPARISON_FOR_REFRESH_DEPTH
  982. #define LPDDR4__DENALI_CTL_60__TRFC_F0_MASK 0x0003FF00U
  983. #define LPDDR4__DENALI_CTL_60__TRFC_F0_SHIFT 8U
  984. #define LPDDR4__DENALI_CTL_60__TRFC_F0_WIDTH 10U
  985. #define LPDDR4__TRFC_F0__REG DENALI_CTL_60
  986. #define LPDDR4__TRFC_F0__FLD LPDDR4__DENALI_CTL_60__TRFC_F0
  987. #define LPDDR4__DENALI_CTL_61_READ_MASK 0x000FFFFFU
  988. #define LPDDR4__DENALI_CTL_61_WRITE_MASK 0x000FFFFFU
  989. #define LPDDR4__DENALI_CTL_61__TREF_F0_MASK 0x000FFFFFU
  990. #define LPDDR4__DENALI_CTL_61__TREF_F0_SHIFT 0U
  991. #define LPDDR4__DENALI_CTL_61__TREF_F0_WIDTH 20U
  992. #define LPDDR4__TREF_F0__REG DENALI_CTL_61
  993. #define LPDDR4__TREF_F0__FLD LPDDR4__DENALI_CTL_61__TREF_F0
  994. #define LPDDR4__DENALI_CTL_62_READ_MASK 0x000003FFU
  995. #define LPDDR4__DENALI_CTL_62_WRITE_MASK 0x000003FFU
  996. #define LPDDR4__DENALI_CTL_62__TRFC_F1_MASK 0x000003FFU
  997. #define LPDDR4__DENALI_CTL_62__TRFC_F1_SHIFT 0U
  998. #define LPDDR4__DENALI_CTL_62__TRFC_F1_WIDTH 10U
  999. #define LPDDR4__TRFC_F1__REG DENALI_CTL_62
  1000. #define LPDDR4__TRFC_F1__FLD LPDDR4__DENALI_CTL_62__TRFC_F1
  1001. #define LPDDR4__DENALI_CTL_63_READ_MASK 0x000FFFFFU
  1002. #define LPDDR4__DENALI_CTL_63_WRITE_MASK 0x000FFFFFU
  1003. #define LPDDR4__DENALI_CTL_63__TREF_F1_MASK 0x000FFFFFU
  1004. #define LPDDR4__DENALI_CTL_63__TREF_F1_SHIFT 0U
  1005. #define LPDDR4__DENALI_CTL_63__TREF_F1_WIDTH 20U
  1006. #define LPDDR4__TREF_F1__REG DENALI_CTL_63
  1007. #define LPDDR4__TREF_F1__FLD LPDDR4__DENALI_CTL_63__TREF_F1
  1008. #define LPDDR4__DENALI_CTL_64_READ_MASK 0x000003FFU
  1009. #define LPDDR4__DENALI_CTL_64_WRITE_MASK 0x000003FFU
  1010. #define LPDDR4__DENALI_CTL_64__TRFC_F2_MASK 0x000003FFU
  1011. #define LPDDR4__DENALI_CTL_64__TRFC_F2_SHIFT 0U
  1012. #define LPDDR4__DENALI_CTL_64__TRFC_F2_WIDTH 10U
  1013. #define LPDDR4__TRFC_F2__REG DENALI_CTL_64
  1014. #define LPDDR4__TRFC_F2__FLD LPDDR4__DENALI_CTL_64__TRFC_F2
  1015. #define LPDDR4__DENALI_CTL_65_READ_MASK 0x000FFFFFU
  1016. #define LPDDR4__DENALI_CTL_65_WRITE_MASK 0x000FFFFFU
  1017. #define LPDDR4__DENALI_CTL_65__TREF_F2_MASK 0x000FFFFFU
  1018. #define LPDDR4__DENALI_CTL_65__TREF_F2_SHIFT 0U
  1019. #define LPDDR4__DENALI_CTL_65__TREF_F2_WIDTH 20U
  1020. #define LPDDR4__TREF_F2__REG DENALI_CTL_65
  1021. #define LPDDR4__TREF_F2__FLD LPDDR4__DENALI_CTL_65__TREF_F2
  1022. #define LPDDR4__DENALI_CTL_66_READ_MASK 0x000FFFFFU
  1023. #define LPDDR4__DENALI_CTL_66_WRITE_MASK 0x000FFFFFU
  1024. #define LPDDR4__DENALI_CTL_66__TREF_INTERVAL_MASK 0x000FFFFFU
  1025. #define LPDDR4__DENALI_CTL_66__TREF_INTERVAL_SHIFT 0U
  1026. #define LPDDR4__DENALI_CTL_66__TREF_INTERVAL_WIDTH 20U
  1027. #define LPDDR4__TREF_INTERVAL__REG DENALI_CTL_66
  1028. #define LPDDR4__TREF_INTERVAL__FLD LPDDR4__DENALI_CTL_66__TREF_INTERVAL
  1029. #define LPDDR4__DENALI_CTL_67_READ_MASK 0x03FF0101U
  1030. #define LPDDR4__DENALI_CTL_67_WRITE_MASK 0x03FF0101U
  1031. #define LPDDR4__DENALI_CTL_67__PBR_EN_MASK 0x00000001U
  1032. #define LPDDR4__DENALI_CTL_67__PBR_EN_SHIFT 0U
  1033. #define LPDDR4__DENALI_CTL_67__PBR_EN_WIDTH 1U
  1034. #define LPDDR4__DENALI_CTL_67__PBR_EN_WOCLR 0U
  1035. #define LPDDR4__DENALI_CTL_67__PBR_EN_WOSET 0U
  1036. #define LPDDR4__PBR_EN__REG DENALI_CTL_67
  1037. #define LPDDR4__PBR_EN__FLD LPDDR4__DENALI_CTL_67__PBR_EN
  1038. #define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_MASK 0x00000100U
  1039. #define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_SHIFT 8U
  1040. #define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_WIDTH 1U
  1041. #define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_WOCLR 0U
  1042. #define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_WOSET 0U
  1043. #define LPDDR4__PBR_NUMERIC_ORDER__REG DENALI_CTL_67
  1044. #define LPDDR4__PBR_NUMERIC_ORDER__FLD LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER
  1045. #define LPDDR4__DENALI_CTL_67__TRFC_PB_F0_MASK 0x03FF0000U
  1046. #define LPDDR4__DENALI_CTL_67__TRFC_PB_F0_SHIFT 16U
  1047. #define LPDDR4__DENALI_CTL_67__TRFC_PB_F0_WIDTH 10U
  1048. #define LPDDR4__TRFC_PB_F0__REG DENALI_CTL_67
  1049. #define LPDDR4__TRFC_PB_F0__FLD LPDDR4__DENALI_CTL_67__TRFC_PB_F0
  1050. #define LPDDR4__DENALI_CTL_68_READ_MASK 0x03FFFFFFU
  1051. #define LPDDR4__DENALI_CTL_68_WRITE_MASK 0x03FFFFFFU
  1052. #define LPDDR4__DENALI_CTL_68__TREFI_PB_F0_MASK 0x0000FFFFU
  1053. #define LPDDR4__DENALI_CTL_68__TREFI_PB_F0_SHIFT 0U
  1054. #define LPDDR4__DENALI_CTL_68__TREFI_PB_F0_WIDTH 16U
  1055. #define LPDDR4__TREFI_PB_F0__REG DENALI_CTL_68
  1056. #define LPDDR4__TREFI_PB_F0__FLD LPDDR4__DENALI_CTL_68__TREFI_PB_F0
  1057. #define LPDDR4__DENALI_CTL_68__TRFC_PB_F1_MASK 0x03FF0000U
  1058. #define LPDDR4__DENALI_CTL_68__TRFC_PB_F1_SHIFT 16U
  1059. #define LPDDR4__DENALI_CTL_68__TRFC_PB_F1_WIDTH 10U
  1060. #define LPDDR4__TRFC_PB_F1__REG DENALI_CTL_68
  1061. #define LPDDR4__TRFC_PB_F1__FLD LPDDR4__DENALI_CTL_68__TRFC_PB_F1
  1062. #define LPDDR4__DENALI_CTL_69_READ_MASK 0x03FFFFFFU
  1063. #define LPDDR4__DENALI_CTL_69_WRITE_MASK 0x03FFFFFFU
  1064. #define LPDDR4__DENALI_CTL_69__TREFI_PB_F1_MASK 0x0000FFFFU
  1065. #define LPDDR4__DENALI_CTL_69__TREFI_PB_F1_SHIFT 0U
  1066. #define LPDDR4__DENALI_CTL_69__TREFI_PB_F1_WIDTH 16U
  1067. #define LPDDR4__TREFI_PB_F1__REG DENALI_CTL_69
  1068. #define LPDDR4__TREFI_PB_F1__FLD LPDDR4__DENALI_CTL_69__TREFI_PB_F1
  1069. #define LPDDR4__DENALI_CTL_69__TRFC_PB_F2_MASK 0x03FF0000U
  1070. #define LPDDR4__DENALI_CTL_69__TRFC_PB_F2_SHIFT 16U
  1071. #define LPDDR4__DENALI_CTL_69__TRFC_PB_F2_WIDTH 10U
  1072. #define LPDDR4__TRFC_PB_F2__REG DENALI_CTL_69
  1073. #define LPDDR4__TRFC_PB_F2__FLD LPDDR4__DENALI_CTL_69__TRFC_PB_F2
  1074. #define LPDDR4__DENALI_CTL_70_READ_MASK 0xFFFFFFFFU
  1075. #define LPDDR4__DENALI_CTL_70_WRITE_MASK 0xFFFFFFFFU
  1076. #define LPDDR4__DENALI_CTL_70__TREFI_PB_F2_MASK 0x0000FFFFU
  1077. #define LPDDR4__DENALI_CTL_70__TREFI_PB_F2_SHIFT 0U
  1078. #define LPDDR4__DENALI_CTL_70__TREFI_PB_F2_WIDTH 16U
  1079. #define LPDDR4__TREFI_PB_F2__REG DENALI_CTL_70
  1080. #define LPDDR4__TREFI_PB_F2__FLD LPDDR4__DENALI_CTL_70__TREFI_PB_F2
  1081. #define LPDDR4__DENALI_CTL_70__PBR_MAX_BANK_WAIT_MASK 0xFFFF0000U
  1082. #define LPDDR4__DENALI_CTL_70__PBR_MAX_BANK_WAIT_SHIFT 16U
  1083. #define LPDDR4__DENALI_CTL_70__PBR_MAX_BANK_WAIT_WIDTH 16U
  1084. #define LPDDR4__PBR_MAX_BANK_WAIT__REG DENALI_CTL_70
  1085. #define LPDDR4__PBR_MAX_BANK_WAIT__FLD LPDDR4__DENALI_CTL_70__PBR_MAX_BANK_WAIT
  1086. #define LPDDR4__DENALI_CTL_71_READ_MASK 0x1F1F010FU
  1087. #define LPDDR4__DENALI_CTL_71_WRITE_MASK 0x1F1F010FU
  1088. #define LPDDR4__DENALI_CTL_71__PBR_BANK_SELECT_DELAY_MASK 0x0000000FU
  1089. #define LPDDR4__DENALI_CTL_71__PBR_BANK_SELECT_DELAY_SHIFT 0U
  1090. #define LPDDR4__DENALI_CTL_71__PBR_BANK_SELECT_DELAY_WIDTH 4U
  1091. #define LPDDR4__PBR_BANK_SELECT_DELAY__REG DENALI_CTL_71
  1092. #define LPDDR4__PBR_BANK_SELECT_DELAY__FLD LPDDR4__DENALI_CTL_71__PBR_BANK_SELECT_DELAY
  1093. #define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_MASK 0x00000100U
  1094. #define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_SHIFT 8U
  1095. #define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_WIDTH 1U
  1096. #define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_WOCLR 0U
  1097. #define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_WOSET 0U
  1098. #define LPDDR4__PBR_CONT_REQ_EN__REG DENALI_CTL_71
  1099. #define LPDDR4__PBR_CONT_REQ_EN__FLD LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN
  1100. #define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_EN_THRESHOLD_MASK 0x001F0000U
  1101. #define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_EN_THRESHOLD_SHIFT 16U
  1102. #define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_EN_THRESHOLD_WIDTH 5U
  1103. #define LPDDR4__AREF_PBR_CONT_EN_THRESHOLD__REG DENALI_CTL_71
  1104. #define LPDDR4__AREF_PBR_CONT_EN_THRESHOLD__FLD LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_EN_THRESHOLD
  1105. #define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_DIS_THRESHOLD_MASK 0x1F000000U
  1106. #define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_DIS_THRESHOLD_SHIFT 24U
  1107. #define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_DIS_THRESHOLD_WIDTH 5U
  1108. #define LPDDR4__AREF_PBR_CONT_DIS_THRESHOLD__REG DENALI_CTL_71
  1109. #define LPDDR4__AREF_PBR_CONT_DIS_THRESHOLD__FLD LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_DIS_THRESHOLD
  1110. #define LPDDR4__DENALI_CTL_72_READ_MASK 0xFFFFFFFFU
  1111. #define LPDDR4__DENALI_CTL_72_WRITE_MASK 0xFFFFFFFFU
  1112. #define LPDDR4__DENALI_CTL_72__TPDEX_F0_MASK 0x0000FFFFU
  1113. #define LPDDR4__DENALI_CTL_72__TPDEX_F0_SHIFT 0U
  1114. #define LPDDR4__DENALI_CTL_72__TPDEX_F0_WIDTH 16U
  1115. #define LPDDR4__TPDEX_F0__REG DENALI_CTL_72
  1116. #define LPDDR4__TPDEX_F0__FLD LPDDR4__DENALI_CTL_72__TPDEX_F0
  1117. #define LPDDR4__DENALI_CTL_72__TPDEX_F1_MASK 0xFFFF0000U
  1118. #define LPDDR4__DENALI_CTL_72__TPDEX_F1_SHIFT 16U
  1119. #define LPDDR4__DENALI_CTL_72__TPDEX_F1_WIDTH 16U
  1120. #define LPDDR4__TPDEX_F1__REG DENALI_CTL_72
  1121. #define LPDDR4__TPDEX_F1__FLD LPDDR4__DENALI_CTL_72__TPDEX_F1
  1122. #define LPDDR4__DENALI_CTL_73_READ_MASK 0xFFFFFFFFU
  1123. #define LPDDR4__DENALI_CTL_73_WRITE_MASK 0xFFFFFFFFU
  1124. #define LPDDR4__DENALI_CTL_73__TPDEX_F2_MASK 0x0000FFFFU
  1125. #define LPDDR4__DENALI_CTL_73__TPDEX_F2_SHIFT 0U
  1126. #define LPDDR4__DENALI_CTL_73__TPDEX_F2_WIDTH 16U
  1127. #define LPDDR4__TPDEX_F2__REG DENALI_CTL_73
  1128. #define LPDDR4__TPDEX_F2__FLD LPDDR4__DENALI_CTL_73__TPDEX_F2
  1129. #define LPDDR4__DENALI_CTL_73__TMRRI_F0_MASK 0x00FF0000U
  1130. #define LPDDR4__DENALI_CTL_73__TMRRI_F0_SHIFT 16U
  1131. #define LPDDR4__DENALI_CTL_73__TMRRI_F0_WIDTH 8U
  1132. #define LPDDR4__TMRRI_F0__REG DENALI_CTL_73
  1133. #define LPDDR4__TMRRI_F0__FLD LPDDR4__DENALI_CTL_73__TMRRI_F0
  1134. #define LPDDR4__DENALI_CTL_73__TMRRI_F1_MASK 0xFF000000U
  1135. #define LPDDR4__DENALI_CTL_73__TMRRI_F1_SHIFT 24U
  1136. #define LPDDR4__DENALI_CTL_73__TMRRI_F1_WIDTH 8U
  1137. #define LPDDR4__TMRRI_F1__REG DENALI_CTL_73
  1138. #define LPDDR4__TMRRI_F1__FLD LPDDR4__DENALI_CTL_73__TMRRI_F1
  1139. #define LPDDR4__DENALI_CTL_74_READ_MASK 0x1F1F1FFFU
  1140. #define LPDDR4__DENALI_CTL_74_WRITE_MASK 0x1F1F1FFFU
  1141. #define LPDDR4__DENALI_CTL_74__TMRRI_F2_MASK 0x000000FFU
  1142. #define LPDDR4__DENALI_CTL_74__TMRRI_F2_SHIFT 0U
  1143. #define LPDDR4__DENALI_CTL_74__TMRRI_F2_WIDTH 8U
  1144. #define LPDDR4__TMRRI_F2__REG DENALI_CTL_74
  1145. #define LPDDR4__TMRRI_F2__FLD LPDDR4__DENALI_CTL_74__TMRRI_F2
  1146. #define LPDDR4__DENALI_CTL_74__TCSCKE_F0_MASK 0x00001F00U
  1147. #define LPDDR4__DENALI_CTL_74__TCSCKE_F0_SHIFT 8U
  1148. #define LPDDR4__DENALI_CTL_74__TCSCKE_F0_WIDTH 5U
  1149. #define LPDDR4__TCSCKE_F0__REG DENALI_CTL_74
  1150. #define LPDDR4__TCSCKE_F0__FLD LPDDR4__DENALI_CTL_74__TCSCKE_F0
  1151. #define LPDDR4__DENALI_CTL_74__TCKELCS_F0_MASK 0x001F0000U
  1152. #define LPDDR4__DENALI_CTL_74__TCKELCS_F0_SHIFT 16U
  1153. #define LPDDR4__DENALI_CTL_74__TCKELCS_F0_WIDTH 5U
  1154. #define LPDDR4__TCKELCS_F0__REG DENALI_CTL_74
  1155. #define LPDDR4__TCKELCS_F0__FLD LPDDR4__DENALI_CTL_74__TCKELCS_F0
  1156. #define LPDDR4__DENALI_CTL_74__TCKEHCS_F0_MASK 0x1F000000U
  1157. #define LPDDR4__DENALI_CTL_74__TCKEHCS_F0_SHIFT 24U
  1158. #define LPDDR4__DENALI_CTL_74__TCKEHCS_F0_WIDTH 5U
  1159. #define LPDDR4__TCKEHCS_F0__REG DENALI_CTL_74
  1160. #define LPDDR4__TCKEHCS_F0__FLD LPDDR4__DENALI_CTL_74__TCKEHCS_F0
  1161. #define LPDDR4__DENALI_CTL_75_READ_MASK 0x1F010F1FU
  1162. #define LPDDR4__DENALI_CTL_75_WRITE_MASK 0x1F010F1FU
  1163. #define LPDDR4__DENALI_CTL_75__TMRWCKEL_F0_MASK 0x0000001FU
  1164. #define LPDDR4__DENALI_CTL_75__TMRWCKEL_F0_SHIFT 0U
  1165. #define LPDDR4__DENALI_CTL_75__TMRWCKEL_F0_WIDTH 5U
  1166. #define LPDDR4__TMRWCKEL_F0__REG DENALI_CTL_75
  1167. #define LPDDR4__TMRWCKEL_F0__FLD LPDDR4__DENALI_CTL_75__TMRWCKEL_F0
  1168. #define LPDDR4__DENALI_CTL_75__TZQCKE_F0_MASK 0x00000F00U
  1169. #define LPDDR4__DENALI_CTL_75__TZQCKE_F0_SHIFT 8U
  1170. #define LPDDR4__DENALI_CTL_75__TZQCKE_F0_WIDTH 4U
  1171. #define LPDDR4__TZQCKE_F0__REG DENALI_CTL_75
  1172. #define LPDDR4__TZQCKE_F0__FLD LPDDR4__DENALI_CTL_75__TZQCKE_F0
  1173. #define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_MASK 0x00010000U
  1174. #define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_SHIFT 16U
  1175. #define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_WIDTH 1U
  1176. #define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_WOCLR 0U
  1177. #define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_WOSET 0U
  1178. #define LPDDR4__CA_DEFAULT_VAL_F0__REG DENALI_CTL_75
  1179. #define LPDDR4__CA_DEFAULT_VAL_F0__FLD LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0
  1180. #define LPDDR4__DENALI_CTL_75__TCSCKE_F1_MASK 0x1F000000U
  1181. #define LPDDR4__DENALI_CTL_75__TCSCKE_F1_SHIFT 24U
  1182. #define LPDDR4__DENALI_CTL_75__TCSCKE_F1_WIDTH 5U
  1183. #define LPDDR4__TCSCKE_F1__REG DENALI_CTL_75
  1184. #define LPDDR4__TCSCKE_F1__FLD LPDDR4__DENALI_CTL_75__TCSCKE_F1
  1185. #define LPDDR4__DENALI_CTL_76_READ_MASK 0x0F1F1F1FU
  1186. #define LPDDR4__DENALI_CTL_76_WRITE_MASK 0x0F1F1F1FU
  1187. #define LPDDR4__DENALI_CTL_76__TCKELCS_F1_MASK 0x0000001FU
  1188. #define LPDDR4__DENALI_CTL_76__TCKELCS_F1_SHIFT 0U
  1189. #define LPDDR4__DENALI_CTL_76__TCKELCS_F1_WIDTH 5U
  1190. #define LPDDR4__TCKELCS_F1__REG DENALI_CTL_76
  1191. #define LPDDR4__TCKELCS_F1__FLD LPDDR4__DENALI_CTL_76__TCKELCS_F1
  1192. #define LPDDR4__DENALI_CTL_76__TCKEHCS_F1_MASK 0x00001F00U
  1193. #define LPDDR4__DENALI_CTL_76__TCKEHCS_F1_SHIFT 8U
  1194. #define LPDDR4__DENALI_CTL_76__TCKEHCS_F1_WIDTH 5U
  1195. #define LPDDR4__TCKEHCS_F1__REG DENALI_CTL_76
  1196. #define LPDDR4__TCKEHCS_F1__FLD LPDDR4__DENALI_CTL_76__TCKEHCS_F1
  1197. #define LPDDR4__DENALI_CTL_76__TMRWCKEL_F1_MASK 0x001F0000U
  1198. #define LPDDR4__DENALI_CTL_76__TMRWCKEL_F1_SHIFT 16U
  1199. #define LPDDR4__DENALI_CTL_76__TMRWCKEL_F1_WIDTH 5U
  1200. #define LPDDR4__TMRWCKEL_F1__REG DENALI_CTL_76
  1201. #define LPDDR4__TMRWCKEL_F1__FLD LPDDR4__DENALI_CTL_76__TMRWCKEL_F1
  1202. #define LPDDR4__DENALI_CTL_76__TZQCKE_F1_MASK 0x0F000000U
  1203. #define LPDDR4__DENALI_CTL_76__TZQCKE_F1_SHIFT 24U
  1204. #define LPDDR4__DENALI_CTL_76__TZQCKE_F1_WIDTH 4U
  1205. #define LPDDR4__TZQCKE_F1__REG DENALI_CTL_76
  1206. #define LPDDR4__TZQCKE_F1__FLD LPDDR4__DENALI_CTL_76__TZQCKE_F1
  1207. #define LPDDR4__DENALI_CTL_77_READ_MASK 0x1F1F1F01U
  1208. #define LPDDR4__DENALI_CTL_77_WRITE_MASK 0x1F1F1F01U
  1209. #define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_MASK 0x00000001U
  1210. #define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_SHIFT 0U
  1211. #define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_WIDTH 1U
  1212. #define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_WOCLR 0U
  1213. #define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_WOSET 0U
  1214. #define LPDDR4__CA_DEFAULT_VAL_F1__REG DENALI_CTL_77
  1215. #define LPDDR4__CA_DEFAULT_VAL_F1__FLD LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1
  1216. #define LPDDR4__DENALI_CTL_77__TCSCKE_F2_MASK 0x00001F00U
  1217. #define LPDDR4__DENALI_CTL_77__TCSCKE_F2_SHIFT 8U
  1218. #define LPDDR4__DENALI_CTL_77__TCSCKE_F2_WIDTH 5U
  1219. #define LPDDR4__TCSCKE_F2__REG DENALI_CTL_77
  1220. #define LPDDR4__TCSCKE_F2__FLD LPDDR4__DENALI_CTL_77__TCSCKE_F2
  1221. #define LPDDR4__DENALI_CTL_77__TCKELCS_F2_MASK 0x001F0000U
  1222. #define LPDDR4__DENALI_CTL_77__TCKELCS_F2_SHIFT 16U
  1223. #define LPDDR4__DENALI_CTL_77__TCKELCS_F2_WIDTH 5U
  1224. #define LPDDR4__TCKELCS_F2__REG DENALI_CTL_77
  1225. #define LPDDR4__TCKELCS_F2__FLD LPDDR4__DENALI_CTL_77__TCKELCS_F2
  1226. #define LPDDR4__DENALI_CTL_77__TCKEHCS_F2_MASK 0x1F000000U
  1227. #define LPDDR4__DENALI_CTL_77__TCKEHCS_F2_SHIFT 24U
  1228. #define LPDDR4__DENALI_CTL_77__TCKEHCS_F2_WIDTH 5U
  1229. #define LPDDR4__TCKEHCS_F2__REG DENALI_CTL_77
  1230. #define LPDDR4__TCKEHCS_F2__FLD LPDDR4__DENALI_CTL_77__TCKEHCS_F2
  1231. #define LPDDR4__DENALI_CTL_78_READ_MASK 0x00010F1FU
  1232. #define LPDDR4__DENALI_CTL_78_WRITE_MASK 0x00010F1FU
  1233. #define LPDDR4__DENALI_CTL_78__TMRWCKEL_F2_MASK 0x0000001FU
  1234. #define LPDDR4__DENALI_CTL_78__TMRWCKEL_F2_SHIFT 0U
  1235. #define LPDDR4__DENALI_CTL_78__TMRWCKEL_F2_WIDTH 5U
  1236. #define LPDDR4__TMRWCKEL_F2__REG DENALI_CTL_78
  1237. #define LPDDR4__TMRWCKEL_F2__FLD LPDDR4__DENALI_CTL_78__TMRWCKEL_F2
  1238. #define LPDDR4__DENALI_CTL_78__TZQCKE_F2_MASK 0x00000F00U
  1239. #define LPDDR4__DENALI_CTL_78__TZQCKE_F2_SHIFT 8U
  1240. #define LPDDR4__DENALI_CTL_78__TZQCKE_F2_WIDTH 4U
  1241. #define LPDDR4__TZQCKE_F2__REG DENALI_CTL_78
  1242. #define LPDDR4__TZQCKE_F2__FLD LPDDR4__DENALI_CTL_78__TZQCKE_F2
  1243. #define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_MASK 0x00010000U
  1244. #define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_SHIFT 16U
  1245. #define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_WIDTH 1U
  1246. #define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_WOCLR 0U
  1247. #define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_WOSET 0U
  1248. #define LPDDR4__CA_DEFAULT_VAL_F2__REG DENALI_CTL_78
  1249. #define LPDDR4__CA_DEFAULT_VAL_F2__FLD LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2
  1250. #define LPDDR4__DENALI_CTL_79_READ_MASK 0xFFFFFFFFU
  1251. #define LPDDR4__DENALI_CTL_79_WRITE_MASK 0xFFFFFFFFU
  1252. #define LPDDR4__DENALI_CTL_79__TXSR_F0_MASK 0x0000FFFFU
  1253. #define LPDDR4__DENALI_CTL_79__TXSR_F0_SHIFT 0U
  1254. #define LPDDR4__DENALI_CTL_79__TXSR_F0_WIDTH 16U
  1255. #define LPDDR4__TXSR_F0__REG DENALI_CTL_79
  1256. #define LPDDR4__TXSR_F0__FLD LPDDR4__DENALI_CTL_79__TXSR_F0
  1257. #define LPDDR4__DENALI_CTL_79__TXSNR_F0_MASK 0xFFFF0000U
  1258. #define LPDDR4__DENALI_CTL_79__TXSNR_F0_SHIFT 16U
  1259. #define LPDDR4__DENALI_CTL_79__TXSNR_F0_WIDTH 16U
  1260. #define LPDDR4__TXSNR_F0__REG DENALI_CTL_79
  1261. #define LPDDR4__TXSNR_F0__FLD LPDDR4__DENALI_CTL_79__TXSNR_F0
  1262. #define LPDDR4__DENALI_CTL_80_READ_MASK 0xFFFFFFFFU
  1263. #define LPDDR4__DENALI_CTL_80_WRITE_MASK 0xFFFFFFFFU
  1264. #define LPDDR4__DENALI_CTL_80__TXSR_F1_MASK 0x0000FFFFU
  1265. #define LPDDR4__DENALI_CTL_80__TXSR_F1_SHIFT 0U
  1266. #define LPDDR4__DENALI_CTL_80__TXSR_F1_WIDTH 16U
  1267. #define LPDDR4__TXSR_F1__REG DENALI_CTL_80
  1268. #define LPDDR4__TXSR_F1__FLD LPDDR4__DENALI_CTL_80__TXSR_F1
  1269. #define LPDDR4__DENALI_CTL_80__TXSNR_F1_MASK 0xFFFF0000U
  1270. #define LPDDR4__DENALI_CTL_80__TXSNR_F1_SHIFT 16U
  1271. #define LPDDR4__DENALI_CTL_80__TXSNR_F1_WIDTH 16U
  1272. #define LPDDR4__TXSNR_F1__REG DENALI_CTL_80
  1273. #define LPDDR4__TXSNR_F1__FLD LPDDR4__DENALI_CTL_80__TXSNR_F1
  1274. #define LPDDR4__DENALI_CTL_81_READ_MASK 0xFFFFFFFFU
  1275. #define LPDDR4__DENALI_CTL_81_WRITE_MASK 0xFFFFFFFFU
  1276. #define LPDDR4__DENALI_CTL_81__TXSR_F2_MASK 0x0000FFFFU
  1277. #define LPDDR4__DENALI_CTL_81__TXSR_F2_SHIFT 0U
  1278. #define LPDDR4__DENALI_CTL_81__TXSR_F2_WIDTH 16U
  1279. #define LPDDR4__TXSR_F2__REG DENALI_CTL_81
  1280. #define LPDDR4__TXSR_F2__FLD LPDDR4__DENALI_CTL_81__TXSR_F2
  1281. #define LPDDR4__DENALI_CTL_81__TXSNR_F2_MASK 0xFFFF0000U
  1282. #define LPDDR4__DENALI_CTL_81__TXSNR_F2_SHIFT 16U
  1283. #define LPDDR4__DENALI_CTL_81__TXSNR_F2_WIDTH 16U
  1284. #define LPDDR4__TXSNR_F2__REG DENALI_CTL_81
  1285. #define LPDDR4__TXSNR_F2__FLD LPDDR4__DENALI_CTL_81__TXSNR_F2
  1286. #define LPDDR4__DENALI_CTL_82_READ_MASK 0xFF1F1F1FU
  1287. #define LPDDR4__DENALI_CTL_82_WRITE_MASK 0xFF1F1F1FU
  1288. #define LPDDR4__DENALI_CTL_82__TCKELCMD_F0_MASK 0x0000001FU
  1289. #define LPDDR4__DENALI_CTL_82__TCKELCMD_F0_SHIFT 0U
  1290. #define LPDDR4__DENALI_CTL_82__TCKELCMD_F0_WIDTH 5U
  1291. #define LPDDR4__TCKELCMD_F0__REG DENALI_CTL_82
  1292. #define LPDDR4__TCKELCMD_F0__FLD LPDDR4__DENALI_CTL_82__TCKELCMD_F0
  1293. #define LPDDR4__DENALI_CTL_82__TCKEHCMD_F0_MASK 0x00001F00U
  1294. #define LPDDR4__DENALI_CTL_82__TCKEHCMD_F0_SHIFT 8U
  1295. #define LPDDR4__DENALI_CTL_82__TCKEHCMD_F0_WIDTH 5U
  1296. #define LPDDR4__TCKEHCMD_F0__REG DENALI_CTL_82
  1297. #define LPDDR4__TCKEHCMD_F0__FLD LPDDR4__DENALI_CTL_82__TCKEHCMD_F0
  1298. #define LPDDR4__DENALI_CTL_82__TCKCKEL_F0_MASK 0x001F0000U
  1299. #define LPDDR4__DENALI_CTL_82__TCKCKEL_F0_SHIFT 16U
  1300. #define LPDDR4__DENALI_CTL_82__TCKCKEL_F0_WIDTH 5U
  1301. #define LPDDR4__TCKCKEL_F0__REG DENALI_CTL_82
  1302. #define LPDDR4__TCKCKEL_F0__FLD LPDDR4__DENALI_CTL_82__TCKCKEL_F0
  1303. #define LPDDR4__DENALI_CTL_82__TSR_F0_MASK 0xFF000000U
  1304. #define LPDDR4__DENALI_CTL_82__TSR_F0_SHIFT 24U
  1305. #define LPDDR4__DENALI_CTL_82__TSR_F0_WIDTH 8U
  1306. #define LPDDR4__TSR_F0__REG DENALI_CTL_82
  1307. #define LPDDR4__TSR_F0__FLD LPDDR4__DENALI_CTL_82__TSR_F0
  1308. #define LPDDR4__DENALI_CTL_83_READ_MASK 0x1F1F1F07U
  1309. #define LPDDR4__DENALI_CTL_83_WRITE_MASK 0x1F1F1F07U
  1310. #define LPDDR4__DENALI_CTL_83__TESCKE_F0_MASK 0x00000007U
  1311. #define LPDDR4__DENALI_CTL_83__TESCKE_F0_SHIFT 0U
  1312. #define LPDDR4__DENALI_CTL_83__TESCKE_F0_WIDTH 3U
  1313. #define LPDDR4__TESCKE_F0__REG DENALI_CTL_83
  1314. #define LPDDR4__TESCKE_F0__FLD LPDDR4__DENALI_CTL_83__TESCKE_F0
  1315. #define LPDDR4__DENALI_CTL_83__TCKELPD_F0_MASK 0x00001F00U
  1316. #define LPDDR4__DENALI_CTL_83__TCKELPD_F0_SHIFT 8U
  1317. #define LPDDR4__DENALI_CTL_83__TCKELPD_F0_WIDTH 5U
  1318. #define LPDDR4__TCKELPD_F0__REG DENALI_CTL_83
  1319. #define LPDDR4__TCKELPD_F0__FLD LPDDR4__DENALI_CTL_83__TCKELPD_F0
  1320. #define LPDDR4__DENALI_CTL_83__TCSCKEH_F0_MASK 0x001F0000U
  1321. #define LPDDR4__DENALI_CTL_83__TCSCKEH_F0_SHIFT 16U
  1322. #define LPDDR4__DENALI_CTL_83__TCSCKEH_F0_WIDTH 5U
  1323. #define LPDDR4__TCSCKEH_F0__REG DENALI_CTL_83
  1324. #define LPDDR4__TCSCKEH_F0__FLD LPDDR4__DENALI_CTL_83__TCSCKEH_F0
  1325. #define LPDDR4__DENALI_CTL_83__TCMDCKE_F0_MASK 0x1F000000U
  1326. #define LPDDR4__DENALI_CTL_83__TCMDCKE_F0_SHIFT 24U
  1327. #define LPDDR4__DENALI_CTL_83__TCMDCKE_F0_WIDTH 5U
  1328. #define LPDDR4__TCMDCKE_F0__REG DENALI_CTL_83
  1329. #define LPDDR4__TCMDCKE_F0__FLD LPDDR4__DENALI_CTL_83__TCMDCKE_F0
  1330. #define LPDDR4__DENALI_CTL_84_READ_MASK 0xFF1F1F1FU
  1331. #define LPDDR4__DENALI_CTL_84_WRITE_MASK 0xFF1F1F1FU
  1332. #define LPDDR4__DENALI_CTL_84__TCKELCMD_F1_MASK 0x0000001FU
  1333. #define LPDDR4__DENALI_CTL_84__TCKELCMD_F1_SHIFT 0U
  1334. #define LPDDR4__DENALI_CTL_84__TCKELCMD_F1_WIDTH 5U
  1335. #define LPDDR4__TCKELCMD_F1__REG DENALI_CTL_84
  1336. #define LPDDR4__TCKELCMD_F1__FLD LPDDR4__DENALI_CTL_84__TCKELCMD_F1
  1337. #define LPDDR4__DENALI_CTL_84__TCKEHCMD_F1_MASK 0x00001F00U
  1338. #define LPDDR4__DENALI_CTL_84__TCKEHCMD_F1_SHIFT 8U
  1339. #define LPDDR4__DENALI_CTL_84__TCKEHCMD_F1_WIDTH 5U
  1340. #define LPDDR4__TCKEHCMD_F1__REG DENALI_CTL_84
  1341. #define LPDDR4__TCKEHCMD_F1__FLD LPDDR4__DENALI_CTL_84__TCKEHCMD_F1
  1342. #define LPDDR4__DENALI_CTL_84__TCKCKEL_F1_MASK 0x001F0000U
  1343. #define LPDDR4__DENALI_CTL_84__TCKCKEL_F1_SHIFT 16U
  1344. #define LPDDR4__DENALI_CTL_84__TCKCKEL_F1_WIDTH 5U
  1345. #define LPDDR4__TCKCKEL_F1__REG DENALI_CTL_84
  1346. #define LPDDR4__TCKCKEL_F1__FLD LPDDR4__DENALI_CTL_84__TCKCKEL_F1
  1347. #define LPDDR4__DENALI_CTL_84__TSR_F1_MASK 0xFF000000U
  1348. #define LPDDR4__DENALI_CTL_84__TSR_F1_SHIFT 24U
  1349. #define LPDDR4__DENALI_CTL_84__TSR_F1_WIDTH 8U
  1350. #define LPDDR4__TSR_F1__REG DENALI_CTL_84
  1351. #define LPDDR4__TSR_F1__FLD LPDDR4__DENALI_CTL_84__TSR_F1
  1352. #define LPDDR4__DENALI_CTL_85_READ_MASK 0x1F1F1F07U
  1353. #define LPDDR4__DENALI_CTL_85_WRITE_MASK 0x1F1F1F07U
  1354. #define LPDDR4__DENALI_CTL_85__TESCKE_F1_MASK 0x00000007U
  1355. #define LPDDR4__DENALI_CTL_85__TESCKE_F1_SHIFT 0U
  1356. #define LPDDR4__DENALI_CTL_85__TESCKE_F1_WIDTH 3U
  1357. #define LPDDR4__TESCKE_F1__REG DENALI_CTL_85
  1358. #define LPDDR4__TESCKE_F1__FLD LPDDR4__DENALI_CTL_85__TESCKE_F1
  1359. #define LPDDR4__DENALI_CTL_85__TCKELPD_F1_MASK 0x00001F00U
  1360. #define LPDDR4__DENALI_CTL_85__TCKELPD_F1_SHIFT 8U
  1361. #define LPDDR4__DENALI_CTL_85__TCKELPD_F1_WIDTH 5U
  1362. #define LPDDR4__TCKELPD_F1__REG DENALI_CTL_85
  1363. #define LPDDR4__TCKELPD_F1__FLD LPDDR4__DENALI_CTL_85__TCKELPD_F1
  1364. #define LPDDR4__DENALI_CTL_85__TCSCKEH_F1_MASK 0x001F0000U
  1365. #define LPDDR4__DENALI_CTL_85__TCSCKEH_F1_SHIFT 16U
  1366. #define LPDDR4__DENALI_CTL_85__TCSCKEH_F1_WIDTH 5U
  1367. #define LPDDR4__TCSCKEH_F1__REG DENALI_CTL_85
  1368. #define LPDDR4__TCSCKEH_F1__FLD LPDDR4__DENALI_CTL_85__TCSCKEH_F1
  1369. #define LPDDR4__DENALI_CTL_85__TCMDCKE_F1_MASK 0x1F000000U
  1370. #define LPDDR4__DENALI_CTL_85__TCMDCKE_F1_SHIFT 24U
  1371. #define LPDDR4__DENALI_CTL_85__TCMDCKE_F1_WIDTH 5U
  1372. #define LPDDR4__TCMDCKE_F1__REG DENALI_CTL_85
  1373. #define LPDDR4__TCMDCKE_F1__FLD LPDDR4__DENALI_CTL_85__TCMDCKE_F1
  1374. #define LPDDR4__DENALI_CTL_86_READ_MASK 0xFF1F1F1FU
  1375. #define LPDDR4__DENALI_CTL_86_WRITE_MASK 0xFF1F1F1FU
  1376. #define LPDDR4__DENALI_CTL_86__TCKELCMD_F2_MASK 0x0000001FU
  1377. #define LPDDR4__DENALI_CTL_86__TCKELCMD_F2_SHIFT 0U
  1378. #define LPDDR4__DENALI_CTL_86__TCKELCMD_F2_WIDTH 5U
  1379. #define LPDDR4__TCKELCMD_F2__REG DENALI_CTL_86
  1380. #define LPDDR4__TCKELCMD_F2__FLD LPDDR4__DENALI_CTL_86__TCKELCMD_F2
  1381. #define LPDDR4__DENALI_CTL_86__TCKEHCMD_F2_MASK 0x00001F00U
  1382. #define LPDDR4__DENALI_CTL_86__TCKEHCMD_F2_SHIFT 8U
  1383. #define LPDDR4__DENALI_CTL_86__TCKEHCMD_F2_WIDTH 5U
  1384. #define LPDDR4__TCKEHCMD_F2__REG DENALI_CTL_86
  1385. #define LPDDR4__TCKEHCMD_F2__FLD LPDDR4__DENALI_CTL_86__TCKEHCMD_F2
  1386. #define LPDDR4__DENALI_CTL_86__TCKCKEL_F2_MASK 0x001F0000U
  1387. #define LPDDR4__DENALI_CTL_86__TCKCKEL_F2_SHIFT 16U
  1388. #define LPDDR4__DENALI_CTL_86__TCKCKEL_F2_WIDTH 5U
  1389. #define LPDDR4__TCKCKEL_F2__REG DENALI_CTL_86
  1390. #define LPDDR4__TCKCKEL_F2__FLD LPDDR4__DENALI_CTL_86__TCKCKEL_F2
  1391. #define LPDDR4__DENALI_CTL_86__TSR_F2_MASK 0xFF000000U
  1392. #define LPDDR4__DENALI_CTL_86__TSR_F2_SHIFT 24U
  1393. #define LPDDR4__DENALI_CTL_86__TSR_F2_WIDTH 8U
  1394. #define LPDDR4__TSR_F2__REG DENALI_CTL_86
  1395. #define LPDDR4__TSR_F2__FLD LPDDR4__DENALI_CTL_86__TSR_F2
  1396. #define LPDDR4__DENALI_CTL_87_READ_MASK 0x1F1F1F07U
  1397. #define LPDDR4__DENALI_CTL_87_WRITE_MASK 0x1F1F1F07U
  1398. #define LPDDR4__DENALI_CTL_87__TESCKE_F2_MASK 0x00000007U
  1399. #define LPDDR4__DENALI_CTL_87__TESCKE_F2_SHIFT 0U
  1400. #define LPDDR4__DENALI_CTL_87__TESCKE_F2_WIDTH 3U
  1401. #define LPDDR4__TESCKE_F2__REG DENALI_CTL_87
  1402. #define LPDDR4__TESCKE_F2__FLD LPDDR4__DENALI_CTL_87__TESCKE_F2
  1403. #define LPDDR4__DENALI_CTL_87__TCKELPD_F2_MASK 0x00001F00U
  1404. #define LPDDR4__DENALI_CTL_87__TCKELPD_F2_SHIFT 8U
  1405. #define LPDDR4__DENALI_CTL_87__TCKELPD_F2_WIDTH 5U
  1406. #define LPDDR4__TCKELPD_F2__REG DENALI_CTL_87
  1407. #define LPDDR4__TCKELPD_F2__FLD LPDDR4__DENALI_CTL_87__TCKELPD_F2
  1408. #define LPDDR4__DENALI_CTL_87__TCSCKEH_F2_MASK 0x001F0000U
  1409. #define LPDDR4__DENALI_CTL_87__TCSCKEH_F2_SHIFT 16U
  1410. #define LPDDR4__DENALI_CTL_87__TCSCKEH_F2_WIDTH 5U
  1411. #define LPDDR4__TCSCKEH_F2__REG DENALI_CTL_87
  1412. #define LPDDR4__TCSCKEH_F2__FLD LPDDR4__DENALI_CTL_87__TCSCKEH_F2
  1413. #define LPDDR4__DENALI_CTL_87__TCMDCKE_F2_MASK 0x1F000000U
  1414. #define LPDDR4__DENALI_CTL_87__TCMDCKE_F2_SHIFT 24U
  1415. #define LPDDR4__DENALI_CTL_87__TCMDCKE_F2_WIDTH 5U
  1416. #define LPDDR4__TCMDCKE_F2__REG DENALI_CTL_87
  1417. #define LPDDR4__TCMDCKE_F2__FLD LPDDR4__DENALI_CTL_87__TCMDCKE_F2
  1418. #define LPDDR4__DENALI_CTL_88_READ_MASK 0x07010101U
  1419. #define LPDDR4__DENALI_CTL_88_WRITE_MASK 0x07010101U
  1420. #define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_MASK 0x00000001U
  1421. #define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_SHIFT 0U
  1422. #define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_WIDTH 1U
  1423. #define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_WOCLR 0U
  1424. #define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_WOSET 0U
  1425. #define LPDDR4__PWRUP_SREFRESH_EXIT__REG DENALI_CTL_88
  1426. #define LPDDR4__PWRUP_SREFRESH_EXIT__FLD LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT
  1427. #define LPDDR4__DENALI_CTL_88__MC_RESERVED10_MASK 0x00000100U
  1428. #define LPDDR4__DENALI_CTL_88__MC_RESERVED10_SHIFT 8U
  1429. #define LPDDR4__DENALI_CTL_88__MC_RESERVED10_WIDTH 1U
  1430. #define LPDDR4__DENALI_CTL_88__MC_RESERVED10_WOCLR 0U
  1431. #define LPDDR4__DENALI_CTL_88__MC_RESERVED10_WOSET 0U
  1432. #define LPDDR4__MC_RESERVED10__REG DENALI_CTL_88
  1433. #define LPDDR4__MC_RESERVED10__FLD LPDDR4__DENALI_CTL_88__MC_RESERVED10
  1434. #define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_MASK 0x00010000U
  1435. #define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_SHIFT 16U
  1436. #define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_WIDTH 1U
  1437. #define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_WOCLR 0U
  1438. #define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_WOSET 0U
  1439. #define LPDDR4__ENABLE_QUICK_SREFRESH__REG DENALI_CTL_88
  1440. #define LPDDR4__ENABLE_QUICK_SREFRESH__FLD LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH
  1441. #define LPDDR4__DENALI_CTL_88__CKE_DELAY_MASK 0x07000000U
  1442. #define LPDDR4__DENALI_CTL_88__CKE_DELAY_SHIFT 24U
  1443. #define LPDDR4__DENALI_CTL_88__CKE_DELAY_WIDTH 3U
  1444. #define LPDDR4__CKE_DELAY__REG DENALI_CTL_88
  1445. #define LPDDR4__CKE_DELAY__FLD LPDDR4__DENALI_CTL_88__CKE_DELAY
  1446. #define LPDDR4__DENALI_CTL_89_READ_MASK 0x01010300U
  1447. #define LPDDR4__DENALI_CTL_89_WRITE_MASK 0x01010300U
  1448. #define LPDDR4__DENALI_CTL_89__MC_RESERVED11_MASK 0x0000001FU
  1449. #define LPDDR4__DENALI_CTL_89__MC_RESERVED11_SHIFT 0U
  1450. #define LPDDR4__DENALI_CTL_89__MC_RESERVED11_WIDTH 5U
  1451. #define LPDDR4__MC_RESERVED11__REG DENALI_CTL_89
  1452. #define LPDDR4__MC_RESERVED11__FLD LPDDR4__DENALI_CTL_89__MC_RESERVED11
  1453. #define LPDDR4__DENALI_CTL_89__DFS_STATUS_MASK 0x00000300U
  1454. #define LPDDR4__DENALI_CTL_89__DFS_STATUS_SHIFT 8U
  1455. #define LPDDR4__DENALI_CTL_89__DFS_STATUS_WIDTH 2U
  1456. #define LPDDR4__DFS_STATUS__REG DENALI_CTL_89
  1457. #define LPDDR4__DFS_STATUS__FLD LPDDR4__DENALI_CTL_89__DFS_STATUS
  1458. #define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_MASK 0x00010000U
  1459. #define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_SHIFT 16U
  1460. #define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_WIDTH 1U
  1461. #define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_WOCLR 0U
  1462. #define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_WOSET 0U
  1463. #define LPDDR4__DFS_ZQ_EN__REG DENALI_CTL_89
  1464. #define LPDDR4__DFS_ZQ_EN__FLD LPDDR4__DENALI_CTL_89__DFS_ZQ_EN
  1465. #define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_MASK 0x01000000U
  1466. #define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_SHIFT 24U
  1467. #define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_WIDTH 1U
  1468. #define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_WOCLR 0U
  1469. #define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_WOSET 0U
  1470. #define LPDDR4__DFS_CALVL_EN__REG DENALI_CTL_89
  1471. #define LPDDR4__DFS_CALVL_EN__FLD LPDDR4__DENALI_CTL_89__DFS_CALVL_EN
  1472. #define LPDDR4__DENALI_CTL_90_READ_MASK 0x00010101U
  1473. #define LPDDR4__DENALI_CTL_90_WRITE_MASK 0x00010101U
  1474. #define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_MASK 0x00000001U
  1475. #define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_SHIFT 0U
  1476. #define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_WIDTH 1U
  1477. #define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_WOCLR 0U
  1478. #define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_WOSET 0U
  1479. #define LPDDR4__DFS_WRLVL_EN__REG DENALI_CTL_90
  1480. #define LPDDR4__DFS_WRLVL_EN__FLD LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN
  1481. #define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_MASK 0x00000100U
  1482. #define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_SHIFT 8U
  1483. #define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_WIDTH 1U
  1484. #define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_WOCLR 0U
  1485. #define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_WOSET 0U
  1486. #define LPDDR4__DFS_RDLVL_EN__REG DENALI_CTL_90
  1487. #define LPDDR4__DFS_RDLVL_EN__FLD LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN
  1488. #define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_MASK 0x00010000U
  1489. #define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_SHIFT 16U
  1490. #define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_WIDTH 1U
  1491. #define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_WOCLR 0U
  1492. #define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_WOSET 0U
  1493. #define LPDDR4__DFS_RDLVL_GATE_EN__REG DENALI_CTL_90
  1494. #define LPDDR4__DFS_RDLVL_GATE_EN__FLD LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN
  1495. #define LPDDR4__DENALI_CTL_91_READ_MASK 0xFFFFFFFFU
  1496. #define LPDDR4__DENALI_CTL_91_WRITE_MASK 0xFFFFFFFFU
  1497. #define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
  1498. #define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F0_SHIFT 0U
  1499. #define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F0_WIDTH 16U
  1500. #define LPDDR4__DFS_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_91
  1501. #define LPDDR4__DFS_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F0
  1502. #define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U
  1503. #define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F1_SHIFT 16U
  1504. #define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F1_WIDTH 16U
  1505. #define LPDDR4__DFS_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_91
  1506. #define LPDDR4__DFS_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F1
  1507. #define LPDDR4__DENALI_CTL_92_READ_MASK 0x0707FFFFU
  1508. #define LPDDR4__DENALI_CTL_92_WRITE_MASK 0x0707FFFFU
  1509. #define LPDDR4__DENALI_CTL_92__DFS_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
  1510. #define LPDDR4__DENALI_CTL_92__DFS_PROMOTE_THRESHOLD_F2_SHIFT 0U
  1511. #define LPDDR4__DENALI_CTL_92__DFS_PROMOTE_THRESHOLD_F2_WIDTH 16U
  1512. #define LPDDR4__DFS_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_92
  1513. #define LPDDR4__DFS_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_92__DFS_PROMOTE_THRESHOLD_F2
  1514. #define LPDDR4__DENALI_CTL_92__ZQ_STATUS_LOG_MASK 0x00070000U
  1515. #define LPDDR4__DENALI_CTL_92__ZQ_STATUS_LOG_SHIFT 16U
  1516. #define LPDDR4__DENALI_CTL_92__ZQ_STATUS_LOG_WIDTH 3U
  1517. #define LPDDR4__ZQ_STATUS_LOG__REG DENALI_CTL_92
  1518. #define LPDDR4__ZQ_STATUS_LOG__FLD LPDDR4__DENALI_CTL_92__ZQ_STATUS_LOG
  1519. #define LPDDR4__DENALI_CTL_92__MC_RESERVED12_MASK 0x07000000U
  1520. #define LPDDR4__DENALI_CTL_92__MC_RESERVED12_SHIFT 24U
  1521. #define LPDDR4__DENALI_CTL_92__MC_RESERVED12_WIDTH 3U
  1522. #define LPDDR4__MC_RESERVED12__REG DENALI_CTL_92
  1523. #define LPDDR4__MC_RESERVED12__FLD LPDDR4__DENALI_CTL_92__MC_RESERVED12
  1524. #define LPDDR4__DENALI_CTL_93_READ_MASK 0xFFFFFF07U
  1525. #define LPDDR4__DENALI_CTL_93_WRITE_MASK 0xFFFFFF07U
  1526. #define LPDDR4__DENALI_CTL_93__MC_RESERVED13_MASK 0x00000007U
  1527. #define LPDDR4__DENALI_CTL_93__MC_RESERVED13_SHIFT 0U
  1528. #define LPDDR4__DENALI_CTL_93__MC_RESERVED13_WIDTH 3U
  1529. #define LPDDR4__MC_RESERVED13__REG DENALI_CTL_93
  1530. #define LPDDR4__MC_RESERVED13__FLD LPDDR4__DENALI_CTL_93__MC_RESERVED13
  1531. #define LPDDR4__DENALI_CTL_93__MC_RESERVED14_MASK 0x0000FF00U
  1532. #define LPDDR4__DENALI_CTL_93__MC_RESERVED14_SHIFT 8U
  1533. #define LPDDR4__DENALI_CTL_93__MC_RESERVED14_WIDTH 8U
  1534. #define LPDDR4__MC_RESERVED14__REG DENALI_CTL_93
  1535. #define LPDDR4__MC_RESERVED14__FLD LPDDR4__DENALI_CTL_93__MC_RESERVED14
  1536. #define LPDDR4__DENALI_CTL_93__MC_RESERVED15_MASK 0x00FF0000U
  1537. #define LPDDR4__DENALI_CTL_93__MC_RESERVED15_SHIFT 16U
  1538. #define LPDDR4__DENALI_CTL_93__MC_RESERVED15_WIDTH 8U
  1539. #define LPDDR4__MC_RESERVED15__REG DENALI_CTL_93
  1540. #define LPDDR4__MC_RESERVED15__FLD LPDDR4__DENALI_CTL_93__MC_RESERVED15
  1541. #define LPDDR4__DENALI_CTL_93__MC_RESERVED16_MASK 0xFF000000U
  1542. #define LPDDR4__DENALI_CTL_93__MC_RESERVED16_SHIFT 24U
  1543. #define LPDDR4__DENALI_CTL_93__MC_RESERVED16_WIDTH 8U
  1544. #define LPDDR4__MC_RESERVED16__REG DENALI_CTL_93
  1545. #define LPDDR4__MC_RESERVED16__FLD LPDDR4__DENALI_CTL_93__MC_RESERVED16
  1546. #define LPDDR4__DENALI_CTL_94_READ_MASK 0xFFFFFFFFU
  1547. #define LPDDR4__DENALI_CTL_94_WRITE_MASK 0xFFFFFFFFU
  1548. #define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_NORM_THRESHOLD_F0_MASK 0x0000FFFFU
  1549. #define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_NORM_THRESHOLD_F0_SHIFT 0U
  1550. #define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_NORM_THRESHOLD_F0_WIDTH 16U
  1551. #define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F0__REG DENALI_CTL_94
  1552. #define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_NORM_THRESHOLD_F0
  1553. #define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_HIGH_THRESHOLD_F0_MASK 0xFFFF0000U
  1554. #define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_HIGH_THRESHOLD_F0_SHIFT 16U
  1555. #define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_HIGH_THRESHOLD_F0_WIDTH 16U
  1556. #define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F0__REG DENALI_CTL_94
  1557. #define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_HIGH_THRESHOLD_F0
  1558. #define LPDDR4__DENALI_CTL_95_READ_MASK 0xFFFFFFFFU
  1559. #define LPDDR4__DENALI_CTL_95_WRITE_MASK 0xFFFFFFFFU
  1560. #define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_TIMEOUT_F0_MASK 0x0000FFFFU
  1561. #define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_TIMEOUT_F0_SHIFT 0U
  1562. #define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_TIMEOUT_F0_WIDTH 16U
  1563. #define LPDDR4__UPD_CTRLUPD_TIMEOUT_F0__REG DENALI_CTL_95
  1564. #define LPDDR4__UPD_CTRLUPD_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_TIMEOUT_F0
  1565. #define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U
  1566. #define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0_SHIFT 16U
  1567. #define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0_WIDTH 16U
  1568. #define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_95
  1569. #define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0
  1570. #define LPDDR4__DENALI_CTL_96_READ_MASK 0xFFFFFFFFU
  1571. #define LPDDR4__DENALI_CTL_96_WRITE_MASK 0xFFFFFFFFU
  1572. #define LPDDR4__DENALI_CTL_96__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
  1573. #define LPDDR4__DENALI_CTL_96__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0_SHIFT 0U
  1574. #define LPDDR4__DENALI_CTL_96__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0_WIDTH 16U
  1575. #define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_96
  1576. #define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_96__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0
  1577. #define LPDDR4__DENALI_CTL_96__UPD_CTRLUPD_NORM_THRESHOLD_F1_MASK 0xFFFF0000U
  1578. #define LPDDR4__DENALI_CTL_96__UPD_CTRLUPD_NORM_THRESHOLD_F1_SHIFT 16U
  1579. #define LPDDR4__DENALI_CTL_96__UPD_CTRLUPD_NORM_THRESHOLD_F1_WIDTH 16U
  1580. #define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F1__REG DENALI_CTL_96
  1581. #define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_96__UPD_CTRLUPD_NORM_THRESHOLD_F1
  1582. #define LPDDR4__DENALI_CTL_97_READ_MASK 0xFFFFFFFFU
  1583. #define LPDDR4__DENALI_CTL_97_WRITE_MASK 0xFFFFFFFFU
  1584. #define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_HIGH_THRESHOLD_F1_MASK 0x0000FFFFU
  1585. #define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_HIGH_THRESHOLD_F1_SHIFT 0U
  1586. #define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_HIGH_THRESHOLD_F1_WIDTH 16U
  1587. #define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F1__REG DENALI_CTL_97
  1588. #define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_HIGH_THRESHOLD_F1
  1589. #define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_TIMEOUT_F1_MASK 0xFFFF0000U
  1590. #define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_TIMEOUT_F1_SHIFT 16U
  1591. #define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_TIMEOUT_F1_WIDTH 16U
  1592. #define LPDDR4__UPD_CTRLUPD_TIMEOUT_F1__REG DENALI_CTL_97
  1593. #define LPDDR4__UPD_CTRLUPD_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_TIMEOUT_F1
  1594. #define LPDDR4__DENALI_CTL_98_READ_MASK 0xFFFFFFFFU
  1595. #define LPDDR4__DENALI_CTL_98_WRITE_MASK 0xFFFFFFFFU
  1596. #define LPDDR4__DENALI_CTL_98__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU
  1597. #define LPDDR4__DENALI_CTL_98__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1_SHIFT 0U
  1598. #define LPDDR4__DENALI_CTL_98__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1_WIDTH 16U
  1599. #define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_98
  1600. #define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_98__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1
  1601. #define LPDDR4__DENALI_CTL_98__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U
  1602. #define LPDDR4__DENALI_CTL_98__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1_SHIFT 16U
  1603. #define LPDDR4__DENALI_CTL_98__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1_WIDTH 16U
  1604. #define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_98
  1605. #define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_98__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1
  1606. #define LPDDR4__DENALI_CTL_99_READ_MASK 0xFFFFFFFFU
  1607. #define LPDDR4__DENALI_CTL_99_WRITE_MASK 0xFFFFFFFFU
  1608. #define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_NORM_THRESHOLD_F2_MASK 0x0000FFFFU
  1609. #define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_NORM_THRESHOLD_F2_SHIFT 0U
  1610. #define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_NORM_THRESHOLD_F2_WIDTH 16U
  1611. #define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F2__REG DENALI_CTL_99
  1612. #define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_NORM_THRESHOLD_F2
  1613. #define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_HIGH_THRESHOLD_F2_MASK 0xFFFF0000U
  1614. #define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_HIGH_THRESHOLD_F2_SHIFT 16U
  1615. #define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_HIGH_THRESHOLD_F2_WIDTH 16U
  1616. #define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F2__REG DENALI_CTL_99
  1617. #define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_HIGH_THRESHOLD_F2
  1618. #define LPDDR4__DENALI_CTL_100_READ_MASK 0xFFFFFFFFU
  1619. #define LPDDR4__DENALI_CTL_100_WRITE_MASK 0xFFFFFFFFU
  1620. #define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_TIMEOUT_F2_MASK 0x0000FFFFU
  1621. #define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_TIMEOUT_F2_SHIFT 0U
  1622. #define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_TIMEOUT_F2_WIDTH 16U
  1623. #define LPDDR4__UPD_CTRLUPD_TIMEOUT_F2__REG DENALI_CTL_100
  1624. #define LPDDR4__UPD_CTRLUPD_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_TIMEOUT_F2
  1625. #define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U
  1626. #define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2_SHIFT 16U
  1627. #define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2_WIDTH 16U
  1628. #define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_100
  1629. #define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2
  1630. #define LPDDR4__DENALI_CTL_101_READ_MASK 0x0000FFFFU
  1631. #define LPDDR4__DENALI_CTL_101_WRITE_MASK 0x0000FFFFU
  1632. #define LPDDR4__DENALI_CTL_101__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
  1633. #define LPDDR4__DENALI_CTL_101__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2_SHIFT 0U
  1634. #define LPDDR4__DENALI_CTL_101__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2_WIDTH 16U
  1635. #define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_101
  1636. #define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_101__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2
  1637. #define LPDDR4__DENALI_CTL_102_READ_MASK 0xFFFFFFFFU
  1638. #define LPDDR4__DENALI_CTL_102_WRITE_MASK 0xFFFFFFFFU
  1639. #define LPDDR4__DENALI_CTL_102__TDFI_PHYMSTR_MAX_F0_MASK 0xFFFFFFFFU
  1640. #define LPDDR4__DENALI_CTL_102__TDFI_PHYMSTR_MAX_F0_SHIFT 0U
  1641. #define LPDDR4__DENALI_CTL_102__TDFI_PHYMSTR_MAX_F0_WIDTH 32U
  1642. #define LPDDR4__TDFI_PHYMSTR_MAX_F0__REG DENALI_CTL_102
  1643. #define LPDDR4__TDFI_PHYMSTR_MAX_F0__FLD LPDDR4__DENALI_CTL_102__TDFI_PHYMSTR_MAX_F0
  1644. #define LPDDR4__DENALI_CTL_103_READ_MASK 0xFFFFFFFFU
  1645. #define LPDDR4__DENALI_CTL_103_WRITE_MASK 0xFFFFFFFFU
  1646. #define LPDDR4__DENALI_CTL_103__TDFI_PHYMSTR_MAX_TYPE0_F0_MASK 0xFFFFFFFFU
  1647. #define LPDDR4__DENALI_CTL_103__TDFI_PHYMSTR_MAX_TYPE0_F0_SHIFT 0U
  1648. #define LPDDR4__DENALI_CTL_103__TDFI_PHYMSTR_MAX_TYPE0_F0_WIDTH 32U
  1649. #define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F0__REG DENALI_CTL_103
  1650. #define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F0__FLD LPDDR4__DENALI_CTL_103__TDFI_PHYMSTR_MAX_TYPE0_F0
  1651. #define LPDDR4__DENALI_CTL_104_READ_MASK 0xFFFFFFFFU
  1652. #define LPDDR4__DENALI_CTL_104_WRITE_MASK 0xFFFFFFFFU
  1653. #define LPDDR4__DENALI_CTL_104__TDFI_PHYMSTR_MAX_TYPE1_F0_MASK 0xFFFFFFFFU
  1654. #define LPDDR4__DENALI_CTL_104__TDFI_PHYMSTR_MAX_TYPE1_F0_SHIFT 0U
  1655. #define LPDDR4__DENALI_CTL_104__TDFI_PHYMSTR_MAX_TYPE1_F0_WIDTH 32U
  1656. #define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F0__REG DENALI_CTL_104
  1657. #define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F0__FLD LPDDR4__DENALI_CTL_104__TDFI_PHYMSTR_MAX_TYPE1_F0
  1658. #define LPDDR4__DENALI_CTL_105_READ_MASK 0xFFFFFFFFU
  1659. #define LPDDR4__DENALI_CTL_105_WRITE_MASK 0xFFFFFFFFU
  1660. #define LPDDR4__DENALI_CTL_105__TDFI_PHYMSTR_MAX_TYPE2_F0_MASK 0xFFFFFFFFU
  1661. #define LPDDR4__DENALI_CTL_105__TDFI_PHYMSTR_MAX_TYPE2_F0_SHIFT 0U
  1662. #define LPDDR4__DENALI_CTL_105__TDFI_PHYMSTR_MAX_TYPE2_F0_WIDTH 32U
  1663. #define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F0__REG DENALI_CTL_105
  1664. #define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F0__FLD LPDDR4__DENALI_CTL_105__TDFI_PHYMSTR_MAX_TYPE2_F0
  1665. #define LPDDR4__DENALI_CTL_106_READ_MASK 0xFFFFFFFFU
  1666. #define LPDDR4__DENALI_CTL_106_WRITE_MASK 0xFFFFFFFFU
  1667. #define LPDDR4__DENALI_CTL_106__TDFI_PHYMSTR_MAX_TYPE3_F0_MASK 0xFFFFFFFFU
  1668. #define LPDDR4__DENALI_CTL_106__TDFI_PHYMSTR_MAX_TYPE3_F0_SHIFT 0U
  1669. #define LPDDR4__DENALI_CTL_106__TDFI_PHYMSTR_MAX_TYPE3_F0_WIDTH 32U
  1670. #define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F0__REG DENALI_CTL_106
  1671. #define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F0__FLD LPDDR4__DENALI_CTL_106__TDFI_PHYMSTR_MAX_TYPE3_F0
  1672. #define LPDDR4__DENALI_CTL_107_READ_MASK 0x0000FFFFU
  1673. #define LPDDR4__DENALI_CTL_107_WRITE_MASK 0x0000FFFFU
  1674. #define LPDDR4__DENALI_CTL_107__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
  1675. #define LPDDR4__DENALI_CTL_107__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0_SHIFT 0U
  1676. #define LPDDR4__DENALI_CTL_107__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0_WIDTH 16U
  1677. #define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_107
  1678. #define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_107__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0
  1679. #define LPDDR4__DENALI_CTL_108_READ_MASK 0x000FFFFFU
  1680. #define LPDDR4__DENALI_CTL_108_WRITE_MASK 0x000FFFFFU
  1681. #define LPDDR4__DENALI_CTL_108__TDFI_PHYMSTR_RESP_F0_MASK 0x000FFFFFU
  1682. #define LPDDR4__DENALI_CTL_108__TDFI_PHYMSTR_RESP_F0_SHIFT 0U
  1683. #define LPDDR4__DENALI_CTL_108__TDFI_PHYMSTR_RESP_F0_WIDTH 20U
  1684. #define LPDDR4__TDFI_PHYMSTR_RESP_F0__REG DENALI_CTL_108
  1685. #define LPDDR4__TDFI_PHYMSTR_RESP_F0__FLD LPDDR4__DENALI_CTL_108__TDFI_PHYMSTR_RESP_F0
  1686. #define LPDDR4__DENALI_CTL_109_READ_MASK 0xFFFFFFFFU
  1687. #define LPDDR4__DENALI_CTL_109_WRITE_MASK 0xFFFFFFFFU
  1688. #define LPDDR4__DENALI_CTL_109__TDFI_PHYMSTR_MAX_F1_MASK 0xFFFFFFFFU
  1689. #define LPDDR4__DENALI_CTL_109__TDFI_PHYMSTR_MAX_F1_SHIFT 0U
  1690. #define LPDDR4__DENALI_CTL_109__TDFI_PHYMSTR_MAX_F1_WIDTH 32U
  1691. #define LPDDR4__TDFI_PHYMSTR_MAX_F1__REG DENALI_CTL_109
  1692. #define LPDDR4__TDFI_PHYMSTR_MAX_F1__FLD LPDDR4__DENALI_CTL_109__TDFI_PHYMSTR_MAX_F1
  1693. #define LPDDR4__DENALI_CTL_110_READ_MASK 0xFFFFFFFFU
  1694. #define LPDDR4__DENALI_CTL_110_WRITE_MASK 0xFFFFFFFFU
  1695. #define LPDDR4__DENALI_CTL_110__TDFI_PHYMSTR_MAX_TYPE0_F1_MASK 0xFFFFFFFFU
  1696. #define LPDDR4__DENALI_CTL_110__TDFI_PHYMSTR_MAX_TYPE0_F1_SHIFT 0U
  1697. #define LPDDR4__DENALI_CTL_110__TDFI_PHYMSTR_MAX_TYPE0_F1_WIDTH 32U
  1698. #define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F1__REG DENALI_CTL_110
  1699. #define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F1__FLD LPDDR4__DENALI_CTL_110__TDFI_PHYMSTR_MAX_TYPE0_F1
  1700. #define LPDDR4__DENALI_CTL_111_READ_MASK 0xFFFFFFFFU
  1701. #define LPDDR4__DENALI_CTL_111_WRITE_MASK 0xFFFFFFFFU
  1702. #define LPDDR4__DENALI_CTL_111__TDFI_PHYMSTR_MAX_TYPE1_F1_MASK 0xFFFFFFFFU
  1703. #define LPDDR4__DENALI_CTL_111__TDFI_PHYMSTR_MAX_TYPE1_F1_SHIFT 0U
  1704. #define LPDDR4__DENALI_CTL_111__TDFI_PHYMSTR_MAX_TYPE1_F1_WIDTH 32U
  1705. #define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F1__REG DENALI_CTL_111
  1706. #define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F1__FLD LPDDR4__DENALI_CTL_111__TDFI_PHYMSTR_MAX_TYPE1_F1
  1707. #define LPDDR4__DENALI_CTL_112_READ_MASK 0xFFFFFFFFU
  1708. #define LPDDR4__DENALI_CTL_112_WRITE_MASK 0xFFFFFFFFU
  1709. #define LPDDR4__DENALI_CTL_112__TDFI_PHYMSTR_MAX_TYPE2_F1_MASK 0xFFFFFFFFU
  1710. #define LPDDR4__DENALI_CTL_112__TDFI_PHYMSTR_MAX_TYPE2_F1_SHIFT 0U
  1711. #define LPDDR4__DENALI_CTL_112__TDFI_PHYMSTR_MAX_TYPE2_F1_WIDTH 32U
  1712. #define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F1__REG DENALI_CTL_112
  1713. #define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F1__FLD LPDDR4__DENALI_CTL_112__TDFI_PHYMSTR_MAX_TYPE2_F1
  1714. #define LPDDR4__DENALI_CTL_113_READ_MASK 0xFFFFFFFFU
  1715. #define LPDDR4__DENALI_CTL_113_WRITE_MASK 0xFFFFFFFFU
  1716. #define LPDDR4__DENALI_CTL_113__TDFI_PHYMSTR_MAX_TYPE3_F1_MASK 0xFFFFFFFFU
  1717. #define LPDDR4__DENALI_CTL_113__TDFI_PHYMSTR_MAX_TYPE3_F1_SHIFT 0U
  1718. #define LPDDR4__DENALI_CTL_113__TDFI_PHYMSTR_MAX_TYPE3_F1_WIDTH 32U
  1719. #define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F1__REG DENALI_CTL_113
  1720. #define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F1__FLD LPDDR4__DENALI_CTL_113__TDFI_PHYMSTR_MAX_TYPE3_F1
  1721. #define LPDDR4__DENALI_CTL_114_READ_MASK 0x0000FFFFU
  1722. #define LPDDR4__DENALI_CTL_114_WRITE_MASK 0x0000FFFFU
  1723. #define LPDDR4__DENALI_CTL_114__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU
  1724. #define LPDDR4__DENALI_CTL_114__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1_SHIFT 0U
  1725. #define LPDDR4__DENALI_CTL_114__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1_WIDTH 16U
  1726. #define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_114
  1727. #define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_114__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1
  1728. #define LPDDR4__DENALI_CTL_115_READ_MASK 0x000FFFFFU
  1729. #define LPDDR4__DENALI_CTL_115_WRITE_MASK 0x000FFFFFU
  1730. #define LPDDR4__DENALI_CTL_115__TDFI_PHYMSTR_RESP_F1_MASK 0x000FFFFFU
  1731. #define LPDDR4__DENALI_CTL_115__TDFI_PHYMSTR_RESP_F1_SHIFT 0U
  1732. #define LPDDR4__DENALI_CTL_115__TDFI_PHYMSTR_RESP_F1_WIDTH 20U
  1733. #define LPDDR4__TDFI_PHYMSTR_RESP_F1__REG DENALI_CTL_115
  1734. #define LPDDR4__TDFI_PHYMSTR_RESP_F1__FLD LPDDR4__DENALI_CTL_115__TDFI_PHYMSTR_RESP_F1
  1735. #define LPDDR4__DENALI_CTL_116_READ_MASK 0xFFFFFFFFU
  1736. #define LPDDR4__DENALI_CTL_116_WRITE_MASK 0xFFFFFFFFU
  1737. #define LPDDR4__DENALI_CTL_116__TDFI_PHYMSTR_MAX_F2_MASK 0xFFFFFFFFU
  1738. #define LPDDR4__DENALI_CTL_116__TDFI_PHYMSTR_MAX_F2_SHIFT 0U
  1739. #define LPDDR4__DENALI_CTL_116__TDFI_PHYMSTR_MAX_F2_WIDTH 32U
  1740. #define LPDDR4__TDFI_PHYMSTR_MAX_F2__REG DENALI_CTL_116
  1741. #define LPDDR4__TDFI_PHYMSTR_MAX_F2__FLD LPDDR4__DENALI_CTL_116__TDFI_PHYMSTR_MAX_F2
  1742. #define LPDDR4__DENALI_CTL_117_READ_MASK 0xFFFFFFFFU
  1743. #define LPDDR4__DENALI_CTL_117_WRITE_MASK 0xFFFFFFFFU
  1744. #define LPDDR4__DENALI_CTL_117__TDFI_PHYMSTR_MAX_TYPE0_F2_MASK 0xFFFFFFFFU
  1745. #define LPDDR4__DENALI_CTL_117__TDFI_PHYMSTR_MAX_TYPE0_F2_SHIFT 0U
  1746. #define LPDDR4__DENALI_CTL_117__TDFI_PHYMSTR_MAX_TYPE0_F2_WIDTH 32U
  1747. #define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F2__REG DENALI_CTL_117
  1748. #define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F2__FLD LPDDR4__DENALI_CTL_117__TDFI_PHYMSTR_MAX_TYPE0_F2
  1749. #define LPDDR4__DENALI_CTL_118_READ_MASK 0xFFFFFFFFU
  1750. #define LPDDR4__DENALI_CTL_118_WRITE_MASK 0xFFFFFFFFU
  1751. #define LPDDR4__DENALI_CTL_118__TDFI_PHYMSTR_MAX_TYPE1_F2_MASK 0xFFFFFFFFU
  1752. #define LPDDR4__DENALI_CTL_118__TDFI_PHYMSTR_MAX_TYPE1_F2_SHIFT 0U
  1753. #define LPDDR4__DENALI_CTL_118__TDFI_PHYMSTR_MAX_TYPE1_F2_WIDTH 32U
  1754. #define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F2__REG DENALI_CTL_118
  1755. #define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F2__FLD LPDDR4__DENALI_CTL_118__TDFI_PHYMSTR_MAX_TYPE1_F2
  1756. #define LPDDR4__DENALI_CTL_119_READ_MASK 0xFFFFFFFFU
  1757. #define LPDDR4__DENALI_CTL_119_WRITE_MASK 0xFFFFFFFFU
  1758. #define LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_TYPE2_F2_MASK 0xFFFFFFFFU
  1759. #define LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_TYPE2_F2_SHIFT 0U
  1760. #define LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_TYPE2_F2_WIDTH 32U
  1761. #define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F2__REG DENALI_CTL_119
  1762. #define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F2__FLD LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_TYPE2_F2
  1763. #define LPDDR4__DENALI_CTL_120_READ_MASK 0xFFFFFFFFU
  1764. #define LPDDR4__DENALI_CTL_120_WRITE_MASK 0xFFFFFFFFU
  1765. #define LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE3_F2_MASK 0xFFFFFFFFU
  1766. #define LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE3_F2_SHIFT 0U
  1767. #define LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE3_F2_WIDTH 32U
  1768. #define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F2__REG DENALI_CTL_120
  1769. #define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F2__FLD LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE3_F2
  1770. #define LPDDR4__DENALI_CTL_121_READ_MASK 0x0000FFFFU
  1771. #define LPDDR4__DENALI_CTL_121_WRITE_MASK 0x0000FFFFU
  1772. #define LPDDR4__DENALI_CTL_121__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
  1773. #define LPDDR4__DENALI_CTL_121__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2_SHIFT 0U
  1774. #define LPDDR4__DENALI_CTL_121__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2_WIDTH 16U
  1775. #define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_121
  1776. #define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_121__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2
  1777. #define LPDDR4__DENALI_CTL_122_READ_MASK 0x010FFFFFU
  1778. #define LPDDR4__DENALI_CTL_122_WRITE_MASK 0x010FFFFFU
  1779. #define LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_RESP_F2_MASK 0x000FFFFFU
  1780. #define LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_RESP_F2_SHIFT 0U
  1781. #define LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_RESP_F2_WIDTH 20U
  1782. #define LPDDR4__TDFI_PHYMSTR_RESP_F2__REG DENALI_CTL_122
  1783. #define LPDDR4__TDFI_PHYMSTR_RESP_F2__FLD LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_RESP_F2
  1784. #define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_MASK 0x01000000U
  1785. #define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_SHIFT 24U
  1786. #define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_WIDTH 1U
  1787. #define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_WOCLR 0U
  1788. #define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_WOSET 0U
  1789. #define LPDDR4__PHYMSTR_NO_AREF__REG DENALI_CTL_122
  1790. #define LPDDR4__PHYMSTR_NO_AREF__FLD LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF
  1791. #define LPDDR4__DENALI_CTL_123_READ_MASK 0x00010103U
  1792. #define LPDDR4__DENALI_CTL_123_WRITE_MASK 0x00010103U
  1793. #define LPDDR4__DENALI_CTL_123__PHYMSTR_ERROR_STATUS_MASK 0x00000003U
  1794. #define LPDDR4__DENALI_CTL_123__PHYMSTR_ERROR_STATUS_SHIFT 0U
  1795. #define LPDDR4__DENALI_CTL_123__PHYMSTR_ERROR_STATUS_WIDTH 2U
  1796. #define LPDDR4__PHYMSTR_ERROR_STATUS__REG DENALI_CTL_123
  1797. #define LPDDR4__PHYMSTR_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_123__PHYMSTR_ERROR_STATUS
  1798. #define LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1_MASK 0x00000100U
  1799. #define LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1_SHIFT 8U
  1800. #define LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1_WIDTH 1U
  1801. #define LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1_WOCLR 0U
  1802. #define LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1_WOSET 0U
  1803. #define LPDDR4__PHYMSTR_DFI_VERSION_4P0V1__REG DENALI_CTL_123
  1804. #define LPDDR4__PHYMSTR_DFI_VERSION_4P0V1__FLD LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1
  1805. #define LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_MASK 0x00010000U
  1806. #define LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_SHIFT 16U
  1807. #define LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_WIDTH 1U
  1808. #define LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_WOCLR 0U
  1809. #define LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_WOSET 0U
  1810. #define LPDDR4__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE__REG DENALI_CTL_123
  1811. #define LPDDR4__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE__FLD LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE
  1812. #define LPDDR4__DENALI_CTL_124_READ_MASK 0xFFFFFFFFU
  1813. #define LPDDR4__DENALI_CTL_124_WRITE_MASK 0xFFFFFFFFU
  1814. #define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_NORM_THRESHOLD_F0_MASK 0x0000FFFFU
  1815. #define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_NORM_THRESHOLD_F0_SHIFT 0U
  1816. #define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_NORM_THRESHOLD_F0_WIDTH 16U
  1817. #define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F0__REG DENALI_CTL_124
  1818. #define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_NORM_THRESHOLD_F0
  1819. #define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_HIGH_THRESHOLD_F0_MASK 0xFFFF0000U
  1820. #define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_HIGH_THRESHOLD_F0_SHIFT 16U
  1821. #define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_HIGH_THRESHOLD_F0_WIDTH 16U
  1822. #define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F0__REG DENALI_CTL_124
  1823. #define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_HIGH_THRESHOLD_F0
  1824. #define LPDDR4__DENALI_CTL_125_READ_MASK 0xFFFFFFFFU
  1825. #define LPDDR4__DENALI_CTL_125_WRITE_MASK 0xFFFFFFFFU
  1826. #define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_TIMEOUT_F0_MASK 0x0000FFFFU
  1827. #define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_TIMEOUT_F0_SHIFT 0U
  1828. #define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_TIMEOUT_F0_WIDTH 16U
  1829. #define LPDDR4__MRR_TEMPCHK_TIMEOUT_F0__REG DENALI_CTL_125
  1830. #define LPDDR4__MRR_TEMPCHK_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_TIMEOUT_F0
  1831. #define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_NORM_THRESHOLD_F1_MASK 0xFFFF0000U
  1832. #define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_NORM_THRESHOLD_F1_SHIFT 16U
  1833. #define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_NORM_THRESHOLD_F1_WIDTH 16U
  1834. #define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F1__REG DENALI_CTL_125
  1835. #define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_NORM_THRESHOLD_F1
  1836. #define LPDDR4__DENALI_CTL_126_READ_MASK 0xFFFFFFFFU
  1837. #define LPDDR4__DENALI_CTL_126_WRITE_MASK 0xFFFFFFFFU
  1838. #define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_HIGH_THRESHOLD_F1_MASK 0x0000FFFFU
  1839. #define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_HIGH_THRESHOLD_F1_SHIFT 0U
  1840. #define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_HIGH_THRESHOLD_F1_WIDTH 16U
  1841. #define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F1__REG DENALI_CTL_126
  1842. #define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_HIGH_THRESHOLD_F1
  1843. #define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_TIMEOUT_F1_MASK 0xFFFF0000U
  1844. #define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_TIMEOUT_F1_SHIFT 16U
  1845. #define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_TIMEOUT_F1_WIDTH 16U
  1846. #define LPDDR4__MRR_TEMPCHK_TIMEOUT_F1__REG DENALI_CTL_126
  1847. #define LPDDR4__MRR_TEMPCHK_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_TIMEOUT_F1
  1848. #define LPDDR4__DENALI_CTL_127_READ_MASK 0xFFFFFFFFU
  1849. #define LPDDR4__DENALI_CTL_127_WRITE_MASK 0xFFFFFFFFU
  1850. #define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_NORM_THRESHOLD_F2_MASK 0x0000FFFFU
  1851. #define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_NORM_THRESHOLD_F2_SHIFT 0U
  1852. #define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_NORM_THRESHOLD_F2_WIDTH 16U
  1853. #define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F2__REG DENALI_CTL_127
  1854. #define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_NORM_THRESHOLD_F2
  1855. #define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_HIGH_THRESHOLD_F2_MASK 0xFFFF0000U
  1856. #define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_HIGH_THRESHOLD_F2_SHIFT 16U
  1857. #define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_HIGH_THRESHOLD_F2_WIDTH 16U
  1858. #define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F2__REG DENALI_CTL_127
  1859. #define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_HIGH_THRESHOLD_F2
  1860. #define LPDDR4__DENALI_CTL_128_READ_MASK 0x0001FFFFU
  1861. #define LPDDR4__DENALI_CTL_128_WRITE_MASK 0x0001FFFFU
  1862. #define LPDDR4__DENALI_CTL_128__MRR_TEMPCHK_TIMEOUT_F2_MASK 0x0000FFFFU
  1863. #define LPDDR4__DENALI_CTL_128__MRR_TEMPCHK_TIMEOUT_F2_SHIFT 0U
  1864. #define LPDDR4__DENALI_CTL_128__MRR_TEMPCHK_TIMEOUT_F2_WIDTH 16U
  1865. #define LPDDR4__MRR_TEMPCHK_TIMEOUT_F2__REG DENALI_CTL_128
  1866. #define LPDDR4__MRR_TEMPCHK_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_128__MRR_TEMPCHK_TIMEOUT_F2
  1867. #define LPDDR4__DENALI_CTL_128__PPR_CONTROL_MASK 0x00010000U
  1868. #define LPDDR4__DENALI_CTL_128__PPR_CONTROL_SHIFT 16U
  1869. #define LPDDR4__DENALI_CTL_128__PPR_CONTROL_WIDTH 1U
  1870. #define LPDDR4__DENALI_CTL_128__PPR_CONTROL_WOCLR 0U
  1871. #define LPDDR4__DENALI_CTL_128__PPR_CONTROL_WOSET 0U
  1872. #define LPDDR4__PPR_CONTROL__REG DENALI_CTL_128
  1873. #define LPDDR4__PPR_CONTROL__FLD LPDDR4__DENALI_CTL_128__PPR_CONTROL
  1874. #define LPDDR4__DENALI_CTL_128__PPR_COMMAND_MASK 0x07000000U
  1875. #define LPDDR4__DENALI_CTL_128__PPR_COMMAND_SHIFT 24U
  1876. #define LPDDR4__DENALI_CTL_128__PPR_COMMAND_WIDTH 3U
  1877. #define LPDDR4__PPR_COMMAND__REG DENALI_CTL_128
  1878. #define LPDDR4__PPR_COMMAND__FLD LPDDR4__DENALI_CTL_128__PPR_COMMAND
  1879. #define LPDDR4__DENALI_CTL_129_READ_MASK 0x01FFFFFFU
  1880. #define LPDDR4__DENALI_CTL_129_WRITE_MASK 0x01FFFFFFU
  1881. #define LPDDR4__DENALI_CTL_129__PPR_COMMAND_MRW_MASK 0x000000FFU
  1882. #define LPDDR4__DENALI_CTL_129__PPR_COMMAND_MRW_SHIFT 0U
  1883. #define LPDDR4__DENALI_CTL_129__PPR_COMMAND_MRW_WIDTH 8U
  1884. #define LPDDR4__PPR_COMMAND_MRW__REG DENALI_CTL_129
  1885. #define LPDDR4__PPR_COMMAND_MRW__FLD LPDDR4__DENALI_CTL_129__PPR_COMMAND_MRW
  1886. #define LPDDR4__DENALI_CTL_129__PPR_ROW_ADDRESS_MASK 0x01FFFF00U
  1887. #define LPDDR4__DENALI_CTL_129__PPR_ROW_ADDRESS_SHIFT 8U
  1888. #define LPDDR4__DENALI_CTL_129__PPR_ROW_ADDRESS_WIDTH 17U
  1889. #define LPDDR4__PPR_ROW_ADDRESS__REG DENALI_CTL_129
  1890. #define LPDDR4__PPR_ROW_ADDRESS__FLD LPDDR4__DENALI_CTL_129__PPR_ROW_ADDRESS
  1891. #define LPDDR4__DENALI_CTL_130_READ_MASK 0x01030107U
  1892. #define LPDDR4__DENALI_CTL_130_WRITE_MASK 0x01030107U
  1893. #define LPDDR4__DENALI_CTL_130__PPR_BANK_ADDRESS_MASK 0x00000007U
  1894. #define LPDDR4__DENALI_CTL_130__PPR_BANK_ADDRESS_SHIFT 0U
  1895. #define LPDDR4__DENALI_CTL_130__PPR_BANK_ADDRESS_WIDTH 3U
  1896. #define LPDDR4__PPR_BANK_ADDRESS__REG DENALI_CTL_130
  1897. #define LPDDR4__PPR_BANK_ADDRESS__FLD LPDDR4__DENALI_CTL_130__PPR_BANK_ADDRESS
  1898. #define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_MASK 0x00000100U
  1899. #define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_SHIFT 8U
  1900. #define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_WIDTH 1U
  1901. #define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_WOCLR 0U
  1902. #define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_WOSET 0U
  1903. #define LPDDR4__PPR_CS_ADDRESS__REG DENALI_CTL_130
  1904. #define LPDDR4__PPR_CS_ADDRESS__FLD LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS
  1905. #define LPDDR4__DENALI_CTL_130__PPR_STATUS_MASK 0x00030000U
  1906. #define LPDDR4__DENALI_CTL_130__PPR_STATUS_SHIFT 16U
  1907. #define LPDDR4__DENALI_CTL_130__PPR_STATUS_WIDTH 2U
  1908. #define LPDDR4__PPR_STATUS__REG DENALI_CTL_130
  1909. #define LPDDR4__PPR_STATUS__FLD LPDDR4__DENALI_CTL_130__PPR_STATUS
  1910. #define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_MASK 0x01000000U
  1911. #define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_SHIFT 24U
  1912. #define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_WIDTH 1U
  1913. #define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_WOCLR 0U
  1914. #define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_WOSET 0U
  1915. #define LPDDR4__FM_OVRIDE_CONTROL__REG DENALI_CTL_130
  1916. #define LPDDR4__FM_OVRIDE_CONTROL__FLD LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL
  1917. #define LPDDR4__DENALI_CTL_131_READ_MASK 0xFFFFFF03U
  1918. #define LPDDR4__DENALI_CTL_131_WRITE_MASK 0xFFFFFF03U
  1919. #define LPDDR4__DENALI_CTL_131__LOWPOWER_REFRESH_ENABLE_MASK 0x00000003U
  1920. #define LPDDR4__DENALI_CTL_131__LOWPOWER_REFRESH_ENABLE_SHIFT 0U
  1921. #define LPDDR4__DENALI_CTL_131__LOWPOWER_REFRESH_ENABLE_WIDTH 2U
  1922. #define LPDDR4__LOWPOWER_REFRESH_ENABLE__REG DENALI_CTL_131
  1923. #define LPDDR4__LOWPOWER_REFRESH_ENABLE__FLD LPDDR4__DENALI_CTL_131__LOWPOWER_REFRESH_ENABLE
  1924. #define LPDDR4__DENALI_CTL_131__CKSRE_F0_MASK 0x0000FF00U
  1925. #define LPDDR4__DENALI_CTL_131__CKSRE_F0_SHIFT 8U
  1926. #define LPDDR4__DENALI_CTL_131__CKSRE_F0_WIDTH 8U
  1927. #define LPDDR4__CKSRE_F0__REG DENALI_CTL_131
  1928. #define LPDDR4__CKSRE_F0__FLD LPDDR4__DENALI_CTL_131__CKSRE_F0
  1929. #define LPDDR4__DENALI_CTL_131__CKSRX_F0_MASK 0x00FF0000U
  1930. #define LPDDR4__DENALI_CTL_131__CKSRX_F0_SHIFT 16U
  1931. #define LPDDR4__DENALI_CTL_131__CKSRX_F0_WIDTH 8U
  1932. #define LPDDR4__CKSRX_F0__REG DENALI_CTL_131
  1933. #define LPDDR4__CKSRX_F0__FLD LPDDR4__DENALI_CTL_131__CKSRX_F0
  1934. #define LPDDR4__DENALI_CTL_131__CKSRE_F1_MASK 0xFF000000U
  1935. #define LPDDR4__DENALI_CTL_131__CKSRE_F1_SHIFT 24U
  1936. #define LPDDR4__DENALI_CTL_131__CKSRE_F1_WIDTH 8U
  1937. #define LPDDR4__CKSRE_F1__REG DENALI_CTL_131
  1938. #define LPDDR4__CKSRE_F1__FLD LPDDR4__DENALI_CTL_131__CKSRE_F1
  1939. #define LPDDR4__DENALI_CTL_132_READ_MASK 0x00FFFFFFU
  1940. #define LPDDR4__DENALI_CTL_132_WRITE_MASK 0x00FFFFFFU
  1941. #define LPDDR4__DENALI_CTL_132__CKSRX_F1_MASK 0x000000FFU
  1942. #define LPDDR4__DENALI_CTL_132__CKSRX_F1_SHIFT 0U
  1943. #define LPDDR4__DENALI_CTL_132__CKSRX_F1_WIDTH 8U
  1944. #define LPDDR4__CKSRX_F1__REG DENALI_CTL_132
  1945. #define LPDDR4__CKSRX_F1__FLD LPDDR4__DENALI_CTL_132__CKSRX_F1
  1946. #define LPDDR4__DENALI_CTL_132__CKSRE_F2_MASK 0x0000FF00U
  1947. #define LPDDR4__DENALI_CTL_132__CKSRE_F2_SHIFT 8U
  1948. #define LPDDR4__DENALI_CTL_132__CKSRE_F2_WIDTH 8U
  1949. #define LPDDR4__CKSRE_F2__REG DENALI_CTL_132
  1950. #define LPDDR4__CKSRE_F2__FLD LPDDR4__DENALI_CTL_132__CKSRE_F2
  1951. #define LPDDR4__DENALI_CTL_132__CKSRX_F2_MASK 0x00FF0000U
  1952. #define LPDDR4__DENALI_CTL_132__CKSRX_F2_SHIFT 16U
  1953. #define LPDDR4__DENALI_CTL_132__CKSRX_F2_WIDTH 8U
  1954. #define LPDDR4__CKSRX_F2__REG DENALI_CTL_132
  1955. #define LPDDR4__CKSRX_F2__FLD LPDDR4__DENALI_CTL_132__CKSRX_F2
  1956. #define LPDDR4__DENALI_CTL_132__LP_CMD_MASK 0x7F000000U
  1957. #define LPDDR4__DENALI_CTL_132__LP_CMD_SHIFT 24U
  1958. #define LPDDR4__DENALI_CTL_132__LP_CMD_WIDTH 7U
  1959. #define LPDDR4__LP_CMD__REG DENALI_CTL_132
  1960. #define LPDDR4__LP_CMD__FLD LPDDR4__DENALI_CTL_132__LP_CMD
  1961. #define LPDDR4__DENALI_CTL_133_READ_MASK 0x0F0F0F0FU
  1962. #define LPDDR4__DENALI_CTL_133_WRITE_MASK 0x0F0F0F0FU
  1963. #define LPDDR4__DENALI_CTL_133__LPI_CTRL_IDLE_WAKEUP_F0_MASK 0x0000000FU
  1964. #define LPDDR4__DENALI_CTL_133__LPI_CTRL_IDLE_WAKEUP_F0_SHIFT 0U
  1965. #define LPDDR4__DENALI_CTL_133__LPI_CTRL_IDLE_WAKEUP_F0_WIDTH 4U
  1966. #define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F0__REG DENALI_CTL_133
  1967. #define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_133__LPI_CTRL_IDLE_WAKEUP_F0
  1968. #define LPDDR4__DENALI_CTL_133__LPI_SR_SHORT_WAKEUP_F0_MASK 0x00000F00U
  1969. #define LPDDR4__DENALI_CTL_133__LPI_SR_SHORT_WAKEUP_F0_SHIFT 8U
  1970. #define LPDDR4__DENALI_CTL_133__LPI_SR_SHORT_WAKEUP_F0_WIDTH 4U
  1971. #define LPDDR4__LPI_SR_SHORT_WAKEUP_F0__REG DENALI_CTL_133
  1972. #define LPDDR4__LPI_SR_SHORT_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_133__LPI_SR_SHORT_WAKEUP_F0
  1973. #define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_WAKEUP_F0_MASK 0x000F0000U
  1974. #define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_WAKEUP_F0_SHIFT 16U
  1975. #define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_WAKEUP_F0_WIDTH 4U
  1976. #define LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG DENALI_CTL_133
  1977. #define LPDDR4__LPI_SR_LONG_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_133__LPI_SR_LONG_WAKEUP_F0
  1978. #define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0_MASK 0x0F000000U
  1979. #define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0_SHIFT 24U
  1980. #define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0_WIDTH 4U
  1981. #define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__REG DENALI_CTL_133
  1982. #define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_133__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0
  1983. #define LPDDR4__DENALI_CTL_134_READ_MASK 0x0F0F0F0FU
  1984. #define LPDDR4__DENALI_CTL_134_WRITE_MASK 0x0F0F0F0FU
  1985. #define LPDDR4__DENALI_CTL_134__LPI_PD_WAKEUP_F0_MASK 0x0000000FU
  1986. #define LPDDR4__DENALI_CTL_134__LPI_PD_WAKEUP_F0_SHIFT 0U
  1987. #define LPDDR4__DENALI_CTL_134__LPI_PD_WAKEUP_F0_WIDTH 4U
  1988. #define LPDDR4__LPI_PD_WAKEUP_F0__REG DENALI_CTL_134
  1989. #define LPDDR4__LPI_PD_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_134__LPI_PD_WAKEUP_F0
  1990. #define LPDDR4__DENALI_CTL_134__LPI_SRPD_SHORT_WAKEUP_F0_MASK 0x00000F00U
  1991. #define LPDDR4__DENALI_CTL_134__LPI_SRPD_SHORT_WAKEUP_F0_SHIFT 8U
  1992. #define LPDDR4__DENALI_CTL_134__LPI_SRPD_SHORT_WAKEUP_F0_WIDTH 4U
  1993. #define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__REG DENALI_CTL_134
  1994. #define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_134__LPI_SRPD_SHORT_WAKEUP_F0
  1995. #define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_WAKEUP_F0_MASK 0x000F0000U
  1996. #define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_WAKEUP_F0_SHIFT 16U
  1997. #define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_WAKEUP_F0_WIDTH 4U
  1998. #define LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__REG DENALI_CTL_134
  1999. #define LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_WAKEUP_F0
  2000. #define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0_MASK 0x0F000000U
  2001. #define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0_SHIFT 24U
  2002. #define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0_WIDTH 4U
  2003. #define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__REG DENALI_CTL_134
  2004. #define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0
  2005. #define LPDDR4__DENALI_CTL_135_READ_MASK 0x0F0F0F0FU
  2006. #define LPDDR4__DENALI_CTL_135_WRITE_MASK 0x0F0F0F0FU
  2007. #define LPDDR4__DENALI_CTL_135__LPI_TIMER_WAKEUP_F0_MASK 0x0000000FU
  2008. #define LPDDR4__DENALI_CTL_135__LPI_TIMER_WAKEUP_F0_SHIFT 0U
  2009. #define LPDDR4__DENALI_CTL_135__LPI_TIMER_WAKEUP_F0_WIDTH 4U
  2010. #define LPDDR4__LPI_TIMER_WAKEUP_F0__REG DENALI_CTL_135
  2011. #define LPDDR4__LPI_TIMER_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_135__LPI_TIMER_WAKEUP_F0
  2012. #define LPDDR4__DENALI_CTL_135__LPI_CTRL_IDLE_WAKEUP_F1_MASK 0x00000F00U
  2013. #define LPDDR4__DENALI_CTL_135__LPI_CTRL_IDLE_WAKEUP_F1_SHIFT 8U
  2014. #define LPDDR4__DENALI_CTL_135__LPI_CTRL_IDLE_WAKEUP_F1_WIDTH 4U
  2015. #define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F1__REG DENALI_CTL_135
  2016. #define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_135__LPI_CTRL_IDLE_WAKEUP_F1
  2017. #define LPDDR4__DENALI_CTL_135__LPI_SR_SHORT_WAKEUP_F1_MASK 0x000F0000U
  2018. #define LPDDR4__DENALI_CTL_135__LPI_SR_SHORT_WAKEUP_F1_SHIFT 16U
  2019. #define LPDDR4__DENALI_CTL_135__LPI_SR_SHORT_WAKEUP_F1_WIDTH 4U
  2020. #define LPDDR4__LPI_SR_SHORT_WAKEUP_F1__REG DENALI_CTL_135
  2021. #define LPDDR4__LPI_SR_SHORT_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_135__LPI_SR_SHORT_WAKEUP_F1
  2022. #define LPDDR4__DENALI_CTL_135__LPI_SR_LONG_WAKEUP_F1_MASK 0x0F000000U
  2023. #define LPDDR4__DENALI_CTL_135__LPI_SR_LONG_WAKEUP_F1_SHIFT 24U
  2024. #define LPDDR4__DENALI_CTL_135__LPI_SR_LONG_WAKEUP_F1_WIDTH 4U
  2025. #define LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG DENALI_CTL_135
  2026. #define LPDDR4__LPI_SR_LONG_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_135__LPI_SR_LONG_WAKEUP_F1
  2027. #define LPDDR4__DENALI_CTL_136_READ_MASK 0x0F0F0F0FU
  2028. #define LPDDR4__DENALI_CTL_136_WRITE_MASK 0x0F0F0F0FU
  2029. #define LPDDR4__DENALI_CTL_136__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1_MASK 0x0000000FU
  2030. #define LPDDR4__DENALI_CTL_136__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1_SHIFT 0U
  2031. #define LPDDR4__DENALI_CTL_136__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1_WIDTH 4U
  2032. #define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__REG DENALI_CTL_136
  2033. #define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_136__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1
  2034. #define LPDDR4__DENALI_CTL_136__LPI_PD_WAKEUP_F1_MASK 0x00000F00U
  2035. #define LPDDR4__DENALI_CTL_136__LPI_PD_WAKEUP_F1_SHIFT 8U
  2036. #define LPDDR4__DENALI_CTL_136__LPI_PD_WAKEUP_F1_WIDTH 4U
  2037. #define LPDDR4__LPI_PD_WAKEUP_F1__REG DENALI_CTL_136
  2038. #define LPDDR4__LPI_PD_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_136__LPI_PD_WAKEUP_F1
  2039. #define LPDDR4__DENALI_CTL_136__LPI_SRPD_SHORT_WAKEUP_F1_MASK 0x000F0000U
  2040. #define LPDDR4__DENALI_CTL_136__LPI_SRPD_SHORT_WAKEUP_F1_SHIFT 16U
  2041. #define LPDDR4__DENALI_CTL_136__LPI_SRPD_SHORT_WAKEUP_F1_WIDTH 4U
  2042. #define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__REG DENALI_CTL_136
  2043. #define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_136__LPI_SRPD_SHORT_WAKEUP_F1
  2044. #define LPDDR4__DENALI_CTL_136__LPI_SRPD_LONG_WAKEUP_F1_MASK 0x0F000000U
  2045. #define LPDDR4__DENALI_CTL_136__LPI_SRPD_LONG_WAKEUP_F1_SHIFT 24U
  2046. #define LPDDR4__DENALI_CTL_136__LPI_SRPD_LONG_WAKEUP_F1_WIDTH 4U
  2047. #define LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__REG DENALI_CTL_136
  2048. #define LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_136__LPI_SRPD_LONG_WAKEUP_F1
  2049. #define LPDDR4__DENALI_CTL_137_READ_MASK 0x0F0F0F0FU
  2050. #define LPDDR4__DENALI_CTL_137_WRITE_MASK 0x0F0F0F0FU
  2051. #define LPDDR4__DENALI_CTL_137__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1_MASK 0x0000000FU
  2052. #define LPDDR4__DENALI_CTL_137__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1_SHIFT 0U
  2053. #define LPDDR4__DENALI_CTL_137__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1_WIDTH 4U
  2054. #define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__REG DENALI_CTL_137
  2055. #define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_137__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1
  2056. #define LPDDR4__DENALI_CTL_137__LPI_TIMER_WAKEUP_F1_MASK 0x00000F00U
  2057. #define LPDDR4__DENALI_CTL_137__LPI_TIMER_WAKEUP_F1_SHIFT 8U
  2058. #define LPDDR4__DENALI_CTL_137__LPI_TIMER_WAKEUP_F1_WIDTH 4U
  2059. #define LPDDR4__LPI_TIMER_WAKEUP_F1__REG DENALI_CTL_137
  2060. #define LPDDR4__LPI_TIMER_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_137__LPI_TIMER_WAKEUP_F1
  2061. #define LPDDR4__DENALI_CTL_137__LPI_CTRL_IDLE_WAKEUP_F2_MASK 0x000F0000U
  2062. #define LPDDR4__DENALI_CTL_137__LPI_CTRL_IDLE_WAKEUP_F2_SHIFT 16U
  2063. #define LPDDR4__DENALI_CTL_137__LPI_CTRL_IDLE_WAKEUP_F2_WIDTH 4U
  2064. #define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F2__REG DENALI_CTL_137
  2065. #define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_137__LPI_CTRL_IDLE_WAKEUP_F2
  2066. #define LPDDR4__DENALI_CTL_137__LPI_SR_SHORT_WAKEUP_F2_MASK 0x0F000000U
  2067. #define LPDDR4__DENALI_CTL_137__LPI_SR_SHORT_WAKEUP_F2_SHIFT 24U
  2068. #define LPDDR4__DENALI_CTL_137__LPI_SR_SHORT_WAKEUP_F2_WIDTH 4U
  2069. #define LPDDR4__LPI_SR_SHORT_WAKEUP_F2__REG DENALI_CTL_137
  2070. #define LPDDR4__LPI_SR_SHORT_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_137__LPI_SR_SHORT_WAKEUP_F2
  2071. #define LPDDR4__DENALI_CTL_138_READ_MASK 0x0F0F0F0FU
  2072. #define LPDDR4__DENALI_CTL_138_WRITE_MASK 0x0F0F0F0FU
  2073. #define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_WAKEUP_F2_MASK 0x0000000FU
  2074. #define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_WAKEUP_F2_SHIFT 0U
  2075. #define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_WAKEUP_F2_WIDTH 4U
  2076. #define LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG DENALI_CTL_138
  2077. #define LPDDR4__LPI_SR_LONG_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_138__LPI_SR_LONG_WAKEUP_F2
  2078. #define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2_MASK 0x00000F00U
  2079. #define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2_SHIFT 8U
  2080. #define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2_WIDTH 4U
  2081. #define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__REG DENALI_CTL_138
  2082. #define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_138__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2
  2083. #define LPDDR4__DENALI_CTL_138__LPI_PD_WAKEUP_F2_MASK 0x000F0000U
  2084. #define LPDDR4__DENALI_CTL_138__LPI_PD_WAKEUP_F2_SHIFT 16U
  2085. #define LPDDR4__DENALI_CTL_138__LPI_PD_WAKEUP_F2_WIDTH 4U
  2086. #define LPDDR4__LPI_PD_WAKEUP_F2__REG DENALI_CTL_138
  2087. #define LPDDR4__LPI_PD_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_138__LPI_PD_WAKEUP_F2
  2088. #define LPDDR4__DENALI_CTL_138__LPI_SRPD_SHORT_WAKEUP_F2_MASK 0x0F000000U
  2089. #define LPDDR4__DENALI_CTL_138__LPI_SRPD_SHORT_WAKEUP_F2_SHIFT 24U
  2090. #define LPDDR4__DENALI_CTL_138__LPI_SRPD_SHORT_WAKEUP_F2_WIDTH 4U
  2091. #define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__REG DENALI_CTL_138
  2092. #define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_138__LPI_SRPD_SHORT_WAKEUP_F2
  2093. #define LPDDR4__DENALI_CTL_139_READ_MASK 0x3F0F0F0FU
  2094. #define LPDDR4__DENALI_CTL_139_WRITE_MASK 0x3F0F0F0FU
  2095. #define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_WAKEUP_F2_MASK 0x0000000FU
  2096. #define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_WAKEUP_F2_SHIFT 0U
  2097. #define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_WAKEUP_F2_WIDTH 4U
  2098. #define LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__REG DENALI_CTL_139
  2099. #define LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_WAKEUP_F2
  2100. #define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2_MASK 0x00000F00U
  2101. #define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2_SHIFT 8U
  2102. #define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2_WIDTH 4U
  2103. #define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__REG DENALI_CTL_139
  2104. #define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2
  2105. #define LPDDR4__DENALI_CTL_139__LPI_TIMER_WAKEUP_F2_MASK 0x000F0000U
  2106. #define LPDDR4__DENALI_CTL_139__LPI_TIMER_WAKEUP_F2_SHIFT 16U
  2107. #define LPDDR4__DENALI_CTL_139__LPI_TIMER_WAKEUP_F2_WIDTH 4U
  2108. #define LPDDR4__LPI_TIMER_WAKEUP_F2__REG DENALI_CTL_139
  2109. #define LPDDR4__LPI_TIMER_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_139__LPI_TIMER_WAKEUP_F2
  2110. #define LPDDR4__DENALI_CTL_139__LPI_WAKEUP_EN_MASK 0x3F000000U
  2111. #define LPDDR4__DENALI_CTL_139__LPI_WAKEUP_EN_SHIFT 24U
  2112. #define LPDDR4__DENALI_CTL_139__LPI_WAKEUP_EN_WIDTH 6U
  2113. #define LPDDR4__LPI_WAKEUP_EN__REG DENALI_CTL_139
  2114. #define LPDDR4__LPI_WAKEUP_EN__FLD LPDDR4__DENALI_CTL_139__LPI_WAKEUP_EN
  2115. #define LPDDR4__DENALI_CTL_140_READ_MASK 0x070FFF01U
  2116. #define LPDDR4__DENALI_CTL_140_WRITE_MASK 0x070FFF01U
  2117. #define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_MASK 0x00000001U
  2118. #define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_SHIFT 0U
  2119. #define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_WIDTH 1U
  2120. #define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_WOCLR 0U
  2121. #define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_WOSET 0U
  2122. #define LPDDR4__LPI_CTRL_REQ_EN__REG DENALI_CTL_140
  2123. #define LPDDR4__LPI_CTRL_REQ_EN__FLD LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN
  2124. #define LPDDR4__DENALI_CTL_140__LPI_WAKEUP_TIMEOUT_MASK 0x000FFF00U
  2125. #define LPDDR4__DENALI_CTL_140__LPI_WAKEUP_TIMEOUT_SHIFT 8U
  2126. #define LPDDR4__DENALI_CTL_140__LPI_WAKEUP_TIMEOUT_WIDTH 12U
  2127. #define LPDDR4__LPI_WAKEUP_TIMEOUT__REG DENALI_CTL_140
  2128. #define LPDDR4__LPI_WAKEUP_TIMEOUT__FLD LPDDR4__DENALI_CTL_140__LPI_WAKEUP_TIMEOUT
  2129. #define LPDDR4__DENALI_CTL_140__TDFI_LP_RESP_MASK 0x07000000U
  2130. #define LPDDR4__DENALI_CTL_140__TDFI_LP_RESP_SHIFT 24U
  2131. #define LPDDR4__DENALI_CTL_140__TDFI_LP_RESP_WIDTH 3U
  2132. #define LPDDR4__TDFI_LP_RESP__REG DENALI_CTL_140
  2133. #define LPDDR4__TDFI_LP_RESP__FLD LPDDR4__DENALI_CTL_140__TDFI_LP_RESP
  2134. #define LPDDR4__DENALI_CTL_141_READ_MASK 0x0F0F7F7FU
  2135. #define LPDDR4__DENALI_CTL_141_WRITE_MASK 0x0F0F7F7FU
  2136. #define LPDDR4__DENALI_CTL_141__LP_STATE_CS0_MASK 0x0000007FU
  2137. #define LPDDR4__DENALI_CTL_141__LP_STATE_CS0_SHIFT 0U
  2138. #define LPDDR4__DENALI_CTL_141__LP_STATE_CS0_WIDTH 7U
  2139. #define LPDDR4__LP_STATE_CS0__REG DENALI_CTL_141
  2140. #define LPDDR4__LP_STATE_CS0__FLD LPDDR4__DENALI_CTL_141__LP_STATE_CS0
  2141. #define LPDDR4__DENALI_CTL_141__LP_STATE_CS1_MASK 0x00007F00U
  2142. #define LPDDR4__DENALI_CTL_141__LP_STATE_CS1_SHIFT 8U
  2143. #define LPDDR4__DENALI_CTL_141__LP_STATE_CS1_WIDTH 7U
  2144. #define LPDDR4__LP_STATE_CS1__REG DENALI_CTL_141
  2145. #define LPDDR4__LP_STATE_CS1__FLD LPDDR4__DENALI_CTL_141__LP_STATE_CS1
  2146. #define LPDDR4__DENALI_CTL_141__LP_AUTO_ENTRY_EN_MASK 0x000F0000U
  2147. #define LPDDR4__DENALI_CTL_141__LP_AUTO_ENTRY_EN_SHIFT 16U
  2148. #define LPDDR4__DENALI_CTL_141__LP_AUTO_ENTRY_EN_WIDTH 4U
  2149. #define LPDDR4__LP_AUTO_ENTRY_EN__REG DENALI_CTL_141
  2150. #define LPDDR4__LP_AUTO_ENTRY_EN__FLD LPDDR4__DENALI_CTL_141__LP_AUTO_ENTRY_EN
  2151. #define LPDDR4__DENALI_CTL_141__LP_AUTO_EXIT_EN_MASK 0x0F000000U
  2152. #define LPDDR4__DENALI_CTL_141__LP_AUTO_EXIT_EN_SHIFT 24U
  2153. #define LPDDR4__DENALI_CTL_141__LP_AUTO_EXIT_EN_WIDTH 4U
  2154. #define LPDDR4__LP_AUTO_EXIT_EN__REG DENALI_CTL_141
  2155. #define LPDDR4__LP_AUTO_EXIT_EN__FLD LPDDR4__DENALI_CTL_141__LP_AUTO_EXIT_EN
  2156. #define LPDDR4__DENALI_CTL_142_READ_MASK 0x000FFF07U
  2157. #define LPDDR4__DENALI_CTL_142_WRITE_MASK 0x000FFF07U
  2158. #define LPDDR4__DENALI_CTL_142__LP_AUTO_MEM_GATE_EN_MASK 0x00000007U
  2159. #define LPDDR4__DENALI_CTL_142__LP_AUTO_MEM_GATE_EN_SHIFT 0U
  2160. #define LPDDR4__DENALI_CTL_142__LP_AUTO_MEM_GATE_EN_WIDTH 3U
  2161. #define LPDDR4__LP_AUTO_MEM_GATE_EN__REG DENALI_CTL_142
  2162. #define LPDDR4__LP_AUTO_MEM_GATE_EN__FLD LPDDR4__DENALI_CTL_142__LP_AUTO_MEM_GATE_EN
  2163. #define LPDDR4__DENALI_CTL_142__LP_AUTO_PD_IDLE_MASK 0x000FFF00U
  2164. #define LPDDR4__DENALI_CTL_142__LP_AUTO_PD_IDLE_SHIFT 8U
  2165. #define LPDDR4__DENALI_CTL_142__LP_AUTO_PD_IDLE_WIDTH 12U
  2166. #define LPDDR4__LP_AUTO_PD_IDLE__REG DENALI_CTL_142
  2167. #define LPDDR4__LP_AUTO_PD_IDLE__FLD LPDDR4__DENALI_CTL_142__LP_AUTO_PD_IDLE
  2168. #define LPDDR4__DENALI_CTL_143_READ_MASK 0xFFFF0FFFU
  2169. #define LPDDR4__DENALI_CTL_143_WRITE_MASK 0xFFFF0FFFU
  2170. #define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_SHORT_IDLE_MASK 0x00000FFFU
  2171. #define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_SHORT_IDLE_SHIFT 0U
  2172. #define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_SHORT_IDLE_WIDTH 12U
  2173. #define LPDDR4__LP_AUTO_SR_SHORT_IDLE__REG DENALI_CTL_143
  2174. #define LPDDR4__LP_AUTO_SR_SHORT_IDLE__FLD LPDDR4__DENALI_CTL_143__LP_AUTO_SR_SHORT_IDLE
  2175. #define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_IDLE_MASK 0x00FF0000U
  2176. #define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_IDLE_SHIFT 16U
  2177. #define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_IDLE_WIDTH 8U
  2178. #define LPDDR4__LP_AUTO_SR_LONG_IDLE__REG DENALI_CTL_143
  2179. #define LPDDR4__LP_AUTO_SR_LONG_IDLE__FLD LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_IDLE
  2180. #define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_MC_GATE_IDLE_MASK 0xFF000000U
  2181. #define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_MC_GATE_IDLE_SHIFT 24U
  2182. #define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_MC_GATE_IDLE_WIDTH 8U
  2183. #define LPDDR4__LP_AUTO_SR_LONG_MC_GATE_IDLE__REG DENALI_CTL_143
  2184. #define LPDDR4__LP_AUTO_SR_LONG_MC_GATE_IDLE__FLD LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_MC_GATE_IDLE
  2185. #define LPDDR4__DENALI_CTL_144_READ_MASK 0xFFFFFFFFU
  2186. #define LPDDR4__DENALI_CTL_144_WRITE_MASK 0xFFFFFFFFU
  2187. #define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
  2188. #define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F0_SHIFT 0U
  2189. #define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F0_WIDTH 16U
  2190. #define LPDDR4__HW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_144
  2191. #define LPDDR4__HW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F0
  2192. #define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U
  2193. #define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F1_SHIFT 16U
  2194. #define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F1_WIDTH 16U
  2195. #define LPDDR4__HW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_144
  2196. #define LPDDR4__HW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F1
  2197. #define LPDDR4__DENALI_CTL_145_READ_MASK 0xFFFFFFFFU
  2198. #define LPDDR4__DENALI_CTL_145_WRITE_MASK 0xFFFFFFFFU
  2199. #define LPDDR4__DENALI_CTL_145__HW_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
  2200. #define LPDDR4__DENALI_CTL_145__HW_PROMOTE_THRESHOLD_F2_SHIFT 0U
  2201. #define LPDDR4__DENALI_CTL_145__HW_PROMOTE_THRESHOLD_F2_WIDTH 16U
  2202. #define LPDDR4__HW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_145
  2203. #define LPDDR4__HW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_145__HW_PROMOTE_THRESHOLD_F2
  2204. #define LPDDR4__DENALI_CTL_145__LPC_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U
  2205. #define LPDDR4__DENALI_CTL_145__LPC_PROMOTE_THRESHOLD_F0_SHIFT 16U
  2206. #define LPDDR4__DENALI_CTL_145__LPC_PROMOTE_THRESHOLD_F0_WIDTH 16U
  2207. #define LPDDR4__LPC_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_145
  2208. #define LPDDR4__LPC_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_145__LPC_PROMOTE_THRESHOLD_F0
  2209. #define LPDDR4__DENALI_CTL_146_READ_MASK 0xFFFFFFFFU
  2210. #define LPDDR4__DENALI_CTL_146_WRITE_MASK 0xFFFFFFFFU
  2211. #define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU
  2212. #define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F1_SHIFT 0U
  2213. #define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F1_WIDTH 16U
  2214. #define LPDDR4__LPC_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_146
  2215. #define LPDDR4__LPC_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F1
  2216. #define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U
  2217. #define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F2_SHIFT 16U
  2218. #define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F2_WIDTH 16U
  2219. #define LPDDR4__LPC_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_146
  2220. #define LPDDR4__LPC_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F2
  2221. #define LPDDR4__DENALI_CTL_147_READ_MASK 0x01010101U
  2222. #define LPDDR4__DENALI_CTL_147_WRITE_MASK 0x01010101U
  2223. #define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_MASK 0x00000001U
  2224. #define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_SHIFT 0U
  2225. #define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_WIDTH 1U
  2226. #define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_WOCLR 0U
  2227. #define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_WOSET 0U
  2228. #define LPDDR4__LPC_SR_CTRLUPD_EN__REG DENALI_CTL_147
  2229. #define LPDDR4__LPC_SR_CTRLUPD_EN__FLD LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN
  2230. #define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_MASK 0x00000100U
  2231. #define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_SHIFT 8U
  2232. #define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_WIDTH 1U
  2233. #define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_WOCLR 0U
  2234. #define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_WOSET 0U
  2235. #define LPDDR4__LPC_SR_PHYUPD_EN__REG DENALI_CTL_147
  2236. #define LPDDR4__LPC_SR_PHYUPD_EN__FLD LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN
  2237. #define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_MASK 0x00010000U
  2238. #define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_SHIFT 16U
  2239. #define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_WIDTH 1U
  2240. #define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_WOCLR 0U
  2241. #define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_WOSET 0U
  2242. #define LPDDR4__LPC_SR_PHYMSTR_EN__REG DENALI_CTL_147
  2243. #define LPDDR4__LPC_SR_PHYMSTR_EN__FLD LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN
  2244. #define LPDDR4__DENALI_CTL_147__MC_RESERVED17_MASK 0x01000000U
  2245. #define LPDDR4__DENALI_CTL_147__MC_RESERVED17_SHIFT 24U
  2246. #define LPDDR4__DENALI_CTL_147__MC_RESERVED17_WIDTH 1U
  2247. #define LPDDR4__DENALI_CTL_147__MC_RESERVED17_WOCLR 0U
  2248. #define LPDDR4__DENALI_CTL_147__MC_RESERVED17_WOSET 0U
  2249. #define LPDDR4__MC_RESERVED17__REG DENALI_CTL_147
  2250. #define LPDDR4__MC_RESERVED17__FLD LPDDR4__DENALI_CTL_147__MC_RESERVED17
  2251. #define LPDDR4__DENALI_CTL_148_READ_MASK 0x3F3F0101U
  2252. #define LPDDR4__DENALI_CTL_148_WRITE_MASK 0x3F3F0101U
  2253. #define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_MASK 0x00000001U
  2254. #define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_SHIFT 0U
  2255. #define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_WIDTH 1U
  2256. #define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_WOCLR 0U
  2257. #define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_WOSET 0U
  2258. #define LPDDR4__LPC_SR_ZQ_EN__REG DENALI_CTL_148
  2259. #define LPDDR4__LPC_SR_ZQ_EN__FLD LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN
  2260. #define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_MASK 0x00000100U
  2261. #define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_SHIFT 8U
  2262. #define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_WIDTH 1U
  2263. #define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_WOCLR 0U
  2264. #define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_WOSET 0U
  2265. #define LPDDR4__PCPCS_PD_EN__REG DENALI_CTL_148
  2266. #define LPDDR4__PCPCS_PD_EN__FLD LPDDR4__DENALI_CTL_148__PCPCS_PD_EN
  2267. #define LPDDR4__DENALI_CTL_148__PCPCS_PD_ENTER_DEPTH_MASK 0x003F0000U
  2268. #define LPDDR4__DENALI_CTL_148__PCPCS_PD_ENTER_DEPTH_SHIFT 16U
  2269. #define LPDDR4__DENALI_CTL_148__PCPCS_PD_ENTER_DEPTH_WIDTH 6U
  2270. #define LPDDR4__PCPCS_PD_ENTER_DEPTH__REG DENALI_CTL_148
  2271. #define LPDDR4__PCPCS_PD_ENTER_DEPTH__FLD LPDDR4__DENALI_CTL_148__PCPCS_PD_ENTER_DEPTH
  2272. #define LPDDR4__DENALI_CTL_148__PCPCS_PD_EXIT_DEPTH_MASK 0x3F000000U
  2273. #define LPDDR4__DENALI_CTL_148__PCPCS_PD_EXIT_DEPTH_SHIFT 24U
  2274. #define LPDDR4__DENALI_CTL_148__PCPCS_PD_EXIT_DEPTH_WIDTH 6U
  2275. #define LPDDR4__PCPCS_PD_EXIT_DEPTH__REG DENALI_CTL_148
  2276. #define LPDDR4__PCPCS_PD_EXIT_DEPTH__FLD LPDDR4__DENALI_CTL_148__PCPCS_PD_EXIT_DEPTH
  2277. #define LPDDR4__DENALI_CTL_149_READ_MASK 0x01FF03FFU
  2278. #define LPDDR4__DENALI_CTL_149_WRITE_MASK 0x01FF03FFU
  2279. #define LPDDR4__DENALI_CTL_149__PCPCS_PD_ENTER_TIMER_MASK 0x000000FFU
  2280. #define LPDDR4__DENALI_CTL_149__PCPCS_PD_ENTER_TIMER_SHIFT 0U
  2281. #define LPDDR4__DENALI_CTL_149__PCPCS_PD_ENTER_TIMER_WIDTH 8U
  2282. #define LPDDR4__PCPCS_PD_ENTER_TIMER__REG DENALI_CTL_149
  2283. #define LPDDR4__PCPCS_PD_ENTER_TIMER__FLD LPDDR4__DENALI_CTL_149__PCPCS_PD_ENTER_TIMER
  2284. #define LPDDR4__DENALI_CTL_149__PCPCS_PD_MASK_MASK 0x00000300U
  2285. #define LPDDR4__DENALI_CTL_149__PCPCS_PD_MASK_SHIFT 8U
  2286. #define LPDDR4__DENALI_CTL_149__PCPCS_PD_MASK_WIDTH 2U
  2287. #define LPDDR4__PCPCS_PD_MASK__REG DENALI_CTL_149
  2288. #define LPDDR4__PCPCS_PD_MASK__FLD LPDDR4__DENALI_CTL_149__PCPCS_PD_MASK
  2289. #define LPDDR4__DENALI_CTL_149__MC_RESERVED18_MASK 0x00FF0000U
  2290. #define LPDDR4__DENALI_CTL_149__MC_RESERVED18_SHIFT 16U
  2291. #define LPDDR4__DENALI_CTL_149__MC_RESERVED18_WIDTH 8U
  2292. #define LPDDR4__MC_RESERVED18__REG DENALI_CTL_149
  2293. #define LPDDR4__MC_RESERVED18__FLD LPDDR4__DENALI_CTL_149__MC_RESERVED18
  2294. #define LPDDR4__DENALI_CTL_149__DFS_ENABLE_MASK 0x01000000U
  2295. #define LPDDR4__DENALI_CTL_149__DFS_ENABLE_SHIFT 24U
  2296. #define LPDDR4__DENALI_CTL_149__DFS_ENABLE_WIDTH 1U
  2297. #define LPDDR4__DENALI_CTL_149__DFS_ENABLE_WOCLR 0U
  2298. #define LPDDR4__DENALI_CTL_149__DFS_ENABLE_WOSET 0U
  2299. #define LPDDR4__DFS_ENABLE__REG DENALI_CTL_149
  2300. #define LPDDR4__DFS_ENABLE__FLD LPDDR4__DENALI_CTL_149__DFS_ENABLE
  2301. #define LPDDR4__DENALI_CTL_150_READ_MASK 0xFFFF03FFU
  2302. #define LPDDR4__DENALI_CTL_150_WRITE_MASK 0xFFFF03FFU
  2303. #define LPDDR4__DENALI_CTL_150__TDFI_INIT_START_F0_MASK 0x000003FFU
  2304. #define LPDDR4__DENALI_CTL_150__TDFI_INIT_START_F0_SHIFT 0U
  2305. #define LPDDR4__DENALI_CTL_150__TDFI_INIT_START_F0_WIDTH 10U
  2306. #define LPDDR4__TDFI_INIT_START_F0__REG DENALI_CTL_150
  2307. #define LPDDR4__TDFI_INIT_START_F0__FLD LPDDR4__DENALI_CTL_150__TDFI_INIT_START_F0
  2308. #define LPDDR4__DENALI_CTL_150__TDFI_INIT_COMPLETE_F0_MASK 0xFFFF0000U
  2309. #define LPDDR4__DENALI_CTL_150__TDFI_INIT_COMPLETE_F0_SHIFT 16U
  2310. #define LPDDR4__DENALI_CTL_150__TDFI_INIT_COMPLETE_F0_WIDTH 16U
  2311. #define LPDDR4__TDFI_INIT_COMPLETE_F0__REG DENALI_CTL_150
  2312. #define LPDDR4__TDFI_INIT_COMPLETE_F0__FLD LPDDR4__DENALI_CTL_150__TDFI_INIT_COMPLETE_F0
  2313. #define LPDDR4__DENALI_CTL_151_READ_MASK 0xFFFF03FFU
  2314. #define LPDDR4__DENALI_CTL_151_WRITE_MASK 0xFFFF03FFU
  2315. #define LPDDR4__DENALI_CTL_151__TDFI_INIT_START_F1_MASK 0x000003FFU
  2316. #define LPDDR4__DENALI_CTL_151__TDFI_INIT_START_F1_SHIFT 0U
  2317. #define LPDDR4__DENALI_CTL_151__TDFI_INIT_START_F1_WIDTH 10U
  2318. #define LPDDR4__TDFI_INIT_START_F1__REG DENALI_CTL_151
  2319. #define LPDDR4__TDFI_INIT_START_F1__FLD LPDDR4__DENALI_CTL_151__TDFI_INIT_START_F1
  2320. #define LPDDR4__DENALI_CTL_151__TDFI_INIT_COMPLETE_F1_MASK 0xFFFF0000U
  2321. #define LPDDR4__DENALI_CTL_151__TDFI_INIT_COMPLETE_F1_SHIFT 16U
  2322. #define LPDDR4__DENALI_CTL_151__TDFI_INIT_COMPLETE_F1_WIDTH 16U
  2323. #define LPDDR4__TDFI_INIT_COMPLETE_F1__REG DENALI_CTL_151
  2324. #define LPDDR4__TDFI_INIT_COMPLETE_F1__FLD LPDDR4__DENALI_CTL_151__TDFI_INIT_COMPLETE_F1
  2325. #define LPDDR4__DENALI_CTL_152_READ_MASK 0xFFFF03FFU
  2326. #define LPDDR4__DENALI_CTL_152_WRITE_MASK 0xFFFF03FFU
  2327. #define LPDDR4__DENALI_CTL_152__TDFI_INIT_START_F2_MASK 0x000003FFU
  2328. #define LPDDR4__DENALI_CTL_152__TDFI_INIT_START_F2_SHIFT 0U
  2329. #define LPDDR4__DENALI_CTL_152__TDFI_INIT_START_F2_WIDTH 10U
  2330. #define LPDDR4__TDFI_INIT_START_F2__REG DENALI_CTL_152
  2331. #define LPDDR4__TDFI_INIT_START_F2__FLD LPDDR4__DENALI_CTL_152__TDFI_INIT_START_F2
  2332. #define LPDDR4__DENALI_CTL_152__TDFI_INIT_COMPLETE_F2_MASK 0xFFFF0000U
  2333. #define LPDDR4__DENALI_CTL_152__TDFI_INIT_COMPLETE_F2_SHIFT 16U
  2334. #define LPDDR4__DENALI_CTL_152__TDFI_INIT_COMPLETE_F2_WIDTH 16U
  2335. #define LPDDR4__TDFI_INIT_COMPLETE_F2__REG DENALI_CTL_152
  2336. #define LPDDR4__TDFI_INIT_COMPLETE_F2__FLD LPDDR4__DENALI_CTL_152__TDFI_INIT_COMPLETE_F2
  2337. #define LPDDR4__DENALI_CTL_153_READ_MASK 0x00000103U
  2338. #define LPDDR4__DENALI_CTL_153_WRITE_MASK 0x00000103U
  2339. #define LPDDR4__DENALI_CTL_153__CURRENT_REG_COPY_MASK 0x00000003U
  2340. #define LPDDR4__DENALI_CTL_153__CURRENT_REG_COPY_SHIFT 0U
  2341. #define LPDDR4__DENALI_CTL_153__CURRENT_REG_COPY_WIDTH 2U
  2342. #define LPDDR4__CURRENT_REG_COPY__REG DENALI_CTL_153
  2343. #define LPDDR4__CURRENT_REG_COPY__FLD LPDDR4__DENALI_CTL_153__CURRENT_REG_COPY
  2344. #define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_MASK 0x00000100U
  2345. #define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_SHIFT 8U
  2346. #define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_WIDTH 1U
  2347. #define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_WOCLR 0U
  2348. #define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_WOSET 0U
  2349. #define LPDDR4__DFS_PHY_REG_WRITE_EN__REG DENALI_CTL_153
  2350. #define LPDDR4__DFS_PHY_REG_WRITE_EN__FLD LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN
  2351. #define LPDDR4__DENALI_CTL_154_READ_MASK 0xFFFFFFFFU
  2352. #define LPDDR4__DENALI_CTL_154_WRITE_MASK 0xFFFFFFFFU
  2353. #define LPDDR4__DENALI_CTL_154__DFS_PHY_REG_WRITE_ADDR_MASK 0xFFFFFFFFU
  2354. #define LPDDR4__DENALI_CTL_154__DFS_PHY_REG_WRITE_ADDR_SHIFT 0U
  2355. #define LPDDR4__DENALI_CTL_154__DFS_PHY_REG_WRITE_ADDR_WIDTH 32U
  2356. #define LPDDR4__DFS_PHY_REG_WRITE_ADDR__REG DENALI_CTL_154
  2357. #define LPDDR4__DFS_PHY_REG_WRITE_ADDR__FLD LPDDR4__DENALI_CTL_154__DFS_PHY_REG_WRITE_ADDR
  2358. #define LPDDR4__DENALI_CTL_155_READ_MASK 0xFFFFFFFFU
  2359. #define LPDDR4__DENALI_CTL_155_WRITE_MASK 0xFFFFFFFFU
  2360. #define LPDDR4__DENALI_CTL_155__DFS_PHY_REG_WRITE_DATA_F0_MASK 0xFFFFFFFFU
  2361. #define LPDDR4__DENALI_CTL_155__DFS_PHY_REG_WRITE_DATA_F0_SHIFT 0U
  2362. #define LPDDR4__DENALI_CTL_155__DFS_PHY_REG_WRITE_DATA_F0_WIDTH 32U
  2363. #define LPDDR4__DFS_PHY_REG_WRITE_DATA_F0__REG DENALI_CTL_155
  2364. #define LPDDR4__DFS_PHY_REG_WRITE_DATA_F0__FLD LPDDR4__DENALI_CTL_155__DFS_PHY_REG_WRITE_DATA_F0
  2365. #define LPDDR4__DENALI_CTL_156_READ_MASK 0xFFFFFFFFU
  2366. #define LPDDR4__DENALI_CTL_156_WRITE_MASK 0xFFFFFFFFU
  2367. #define LPDDR4__DENALI_CTL_156__DFS_PHY_REG_WRITE_DATA_F1_MASK 0xFFFFFFFFU
  2368. #define LPDDR4__DENALI_CTL_156__DFS_PHY_REG_WRITE_DATA_F1_SHIFT 0U
  2369. #define LPDDR4__DENALI_CTL_156__DFS_PHY_REG_WRITE_DATA_F1_WIDTH 32U
  2370. #define LPDDR4__DFS_PHY_REG_WRITE_DATA_F1__REG DENALI_CTL_156
  2371. #define LPDDR4__DFS_PHY_REG_WRITE_DATA_F1__FLD LPDDR4__DENALI_CTL_156__DFS_PHY_REG_WRITE_DATA_F1
  2372. #define LPDDR4__DENALI_CTL_157_READ_MASK 0xFFFFFFFFU
  2373. #define LPDDR4__DENALI_CTL_157_WRITE_MASK 0xFFFFFFFFU
  2374. #define LPDDR4__DENALI_CTL_157__DFS_PHY_REG_WRITE_DATA_F2_MASK 0xFFFFFFFFU
  2375. #define LPDDR4__DENALI_CTL_157__DFS_PHY_REG_WRITE_DATA_F2_SHIFT 0U
  2376. #define LPDDR4__DENALI_CTL_157__DFS_PHY_REG_WRITE_DATA_F2_WIDTH 32U
  2377. #define LPDDR4__DFS_PHY_REG_WRITE_DATA_F2__REG DENALI_CTL_157
  2378. #define LPDDR4__DFS_PHY_REG_WRITE_DATA_F2__FLD LPDDR4__DENALI_CTL_157__DFS_PHY_REG_WRITE_DATA_F2
  2379. #define LPDDR4__DENALI_CTL_158_READ_MASK 0x00FFFF0FU
  2380. #define LPDDR4__DENALI_CTL_158_WRITE_MASK 0x00FFFF0FU
  2381. #define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_MASK_MASK 0x0000000FU
  2382. #define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_MASK_SHIFT 0U
  2383. #define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_MASK_WIDTH 4U
  2384. #define LPDDR4__DFS_PHY_REG_WRITE_MASK__REG DENALI_CTL_158
  2385. #define LPDDR4__DFS_PHY_REG_WRITE_MASK__FLD LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_MASK
  2386. #define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_WAIT_MASK 0x00FFFF00U
  2387. #define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_WAIT_SHIFT 8U
  2388. #define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_WAIT_WIDTH 16U
  2389. #define LPDDR4__DFS_PHY_REG_WRITE_WAIT__REG DENALI_CTL_158
  2390. #define LPDDR4__DFS_PHY_REG_WRITE_WAIT__FLD LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_WAIT
  2391. #define LPDDR4__DENALI_CTL_159_READ_MASK 0x07FFFFFFU
  2392. #define LPDDR4__DENALI_CTL_159_WRITE_MASK 0x07FFFFFFU
  2393. #define LPDDR4__DENALI_CTL_159__WRITE_MODEREG_MASK 0x07FFFFFFU
  2394. #define LPDDR4__DENALI_CTL_159__WRITE_MODEREG_SHIFT 0U
  2395. #define LPDDR4__DENALI_CTL_159__WRITE_MODEREG_WIDTH 27U
  2396. #define LPDDR4__WRITE_MODEREG__REG DENALI_CTL_159
  2397. #define LPDDR4__WRITE_MODEREG__FLD LPDDR4__DENALI_CTL_159__WRITE_MODEREG
  2398. #define LPDDR4__DENALI_CTL_160_READ_MASK 0x01FFFFFFU
  2399. #define LPDDR4__DENALI_CTL_160_WRITE_MASK 0x01FFFFFFU
  2400. #define LPDDR4__DENALI_CTL_160__MRW_STATUS_MASK 0x000000FFU
  2401. #define LPDDR4__DENALI_CTL_160__MRW_STATUS_SHIFT 0U
  2402. #define LPDDR4__DENALI_CTL_160__MRW_STATUS_WIDTH 8U
  2403. #define LPDDR4__MRW_STATUS__REG DENALI_CTL_160
  2404. #define LPDDR4__MRW_STATUS__FLD LPDDR4__DENALI_CTL_160__MRW_STATUS
  2405. #define LPDDR4__DENALI_CTL_160__READ_MODEREG_MASK 0x01FFFF00U
  2406. #define LPDDR4__DENALI_CTL_160__READ_MODEREG_SHIFT 8U
  2407. #define LPDDR4__DENALI_CTL_160__READ_MODEREG_WIDTH 17U
  2408. #define LPDDR4__READ_MODEREG__REG DENALI_CTL_160
  2409. #define LPDDR4__READ_MODEREG__FLD LPDDR4__DENALI_CTL_160__READ_MODEREG
  2410. #define LPDDR4__DENALI_CTL_161_READ_MASK 0xFFFFFFFFU
  2411. #define LPDDR4__DENALI_CTL_161_WRITE_MASK 0xFFFFFFFFU
  2412. #define LPDDR4__DENALI_CTL_161__PERIPHERAL_MRR_DATA_0_MASK 0xFFFFFFFFU
  2413. #define LPDDR4__DENALI_CTL_161__PERIPHERAL_MRR_DATA_0_SHIFT 0U
  2414. #define LPDDR4__DENALI_CTL_161__PERIPHERAL_MRR_DATA_0_WIDTH 32U
  2415. #define LPDDR4__PERIPHERAL_MRR_DATA_0__REG DENALI_CTL_161
  2416. #define LPDDR4__PERIPHERAL_MRR_DATA_0__FLD LPDDR4__DENALI_CTL_161__PERIPHERAL_MRR_DATA_0
  2417. #define LPDDR4__DENALI_CTL_162_READ_MASK 0x00FFFFFFU
  2418. #define LPDDR4__DENALI_CTL_162_WRITE_MASK 0x00FFFFFFU
  2419. #define LPDDR4__DENALI_CTL_162__PERIPHERAL_MRR_DATA_1_MASK 0x000000FFU
  2420. #define LPDDR4__DENALI_CTL_162__PERIPHERAL_MRR_DATA_1_SHIFT 0U
  2421. #define LPDDR4__DENALI_CTL_162__PERIPHERAL_MRR_DATA_1_WIDTH 8U
  2422. #define LPDDR4__PERIPHERAL_MRR_DATA_1__REG DENALI_CTL_162
  2423. #define LPDDR4__PERIPHERAL_MRR_DATA_1__FLD LPDDR4__DENALI_CTL_162__PERIPHERAL_MRR_DATA_1
  2424. #define LPDDR4__DENALI_CTL_162__AUTO_TEMPCHK_VAL_0_MASK 0x00FFFF00U
  2425. #define LPDDR4__DENALI_CTL_162__AUTO_TEMPCHK_VAL_0_SHIFT 8U
  2426. #define LPDDR4__DENALI_CTL_162__AUTO_TEMPCHK_VAL_0_WIDTH 16U
  2427. #define LPDDR4__AUTO_TEMPCHK_VAL_0__REG DENALI_CTL_162
  2428. #define LPDDR4__AUTO_TEMPCHK_VAL_0__FLD LPDDR4__DENALI_CTL_162__AUTO_TEMPCHK_VAL_0
  2429. #define LPDDR4__DENALI_CTL_163_READ_MASK 0x0001FFFFU
  2430. #define LPDDR4__DENALI_CTL_163_WRITE_MASK 0x0001FFFFU
  2431. #define LPDDR4__DENALI_CTL_163__AUTO_TEMPCHK_VAL_1_MASK 0x0000FFFFU
  2432. #define LPDDR4__DENALI_CTL_163__AUTO_TEMPCHK_VAL_1_SHIFT 0U
  2433. #define LPDDR4__DENALI_CTL_163__AUTO_TEMPCHK_VAL_1_WIDTH 16U
  2434. #define LPDDR4__AUTO_TEMPCHK_VAL_1__REG DENALI_CTL_163
  2435. #define LPDDR4__AUTO_TEMPCHK_VAL_1__FLD LPDDR4__DENALI_CTL_163__AUTO_TEMPCHK_VAL_1
  2436. #define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_MASK 0x00010000U
  2437. #define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_SHIFT 16U
  2438. #define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_WIDTH 1U
  2439. #define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_WOCLR 0U
  2440. #define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_WOSET 0U
  2441. #define LPDDR4__DISABLE_UPDATE_TVRCG__REG DENALI_CTL_163
  2442. #define LPDDR4__DISABLE_UPDATE_TVRCG__FLD LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG
  2443. #define LPDDR4__DENALI_CTL_164_READ_MASK 0x03FF0003U
  2444. #define LPDDR4__DENALI_CTL_164_WRITE_MASK 0x03FF0003U
  2445. #define LPDDR4__DENALI_CTL_164__MRW_DFS_UPDATE_FRC_MASK 0x00000003U
  2446. #define LPDDR4__DENALI_CTL_164__MRW_DFS_UPDATE_FRC_SHIFT 0U
  2447. #define LPDDR4__DENALI_CTL_164__MRW_DFS_UPDATE_FRC_WIDTH 2U
  2448. #define LPDDR4__MRW_DFS_UPDATE_FRC__REG DENALI_CTL_164
  2449. #define LPDDR4__MRW_DFS_UPDATE_FRC__FLD LPDDR4__DENALI_CTL_164__MRW_DFS_UPDATE_FRC
  2450. #define LPDDR4__DENALI_CTL_164__TVRCG_ENABLE_F0_MASK 0x03FF0000U
  2451. #define LPDDR4__DENALI_CTL_164__TVRCG_ENABLE_F0_SHIFT 16U
  2452. #define LPDDR4__DENALI_CTL_164__TVRCG_ENABLE_F0_WIDTH 10U
  2453. #define LPDDR4__TVRCG_ENABLE_F0__REG DENALI_CTL_164
  2454. #define LPDDR4__TVRCG_ENABLE_F0__FLD LPDDR4__DENALI_CTL_164__TVRCG_ENABLE_F0
  2455. #define LPDDR4__DENALI_CTL_165_READ_MASK 0x03FF03FFU
  2456. #define LPDDR4__DENALI_CTL_165_WRITE_MASK 0x03FF03FFU
  2457. #define LPDDR4__DENALI_CTL_165__TVRCG_DISABLE_F0_MASK 0x000003FFU
  2458. #define LPDDR4__DENALI_CTL_165__TVRCG_DISABLE_F0_SHIFT 0U
  2459. #define LPDDR4__DENALI_CTL_165__TVRCG_DISABLE_F0_WIDTH 10U
  2460. #define LPDDR4__TVRCG_DISABLE_F0__REG DENALI_CTL_165
  2461. #define LPDDR4__TVRCG_DISABLE_F0__FLD LPDDR4__DENALI_CTL_165__TVRCG_DISABLE_F0
  2462. #define LPDDR4__DENALI_CTL_165__TFC_F0_MASK 0x03FF0000U
  2463. #define LPDDR4__DENALI_CTL_165__TFC_F0_SHIFT 16U
  2464. #define LPDDR4__DENALI_CTL_165__TFC_F0_WIDTH 10U
  2465. #define LPDDR4__TFC_F0__REG DENALI_CTL_165
  2466. #define LPDDR4__TFC_F0__FLD LPDDR4__DENALI_CTL_165__TFC_F0
  2467. #define LPDDR4__DENALI_CTL_166_READ_MASK 0xFFFF1F1FU
  2468. #define LPDDR4__DENALI_CTL_166_WRITE_MASK 0xFFFF1F1FU
  2469. #define LPDDR4__DENALI_CTL_166__TCKFSPE_F0_MASK 0x0000001FU
  2470. #define LPDDR4__DENALI_CTL_166__TCKFSPE_F0_SHIFT 0U
  2471. #define LPDDR4__DENALI_CTL_166__TCKFSPE_F0_WIDTH 5U
  2472. #define LPDDR4__TCKFSPE_F0__REG DENALI_CTL_166
  2473. #define LPDDR4__TCKFSPE_F0__FLD LPDDR4__DENALI_CTL_166__TCKFSPE_F0
  2474. #define LPDDR4__DENALI_CTL_166__TCKFSPX_F0_MASK 0x00001F00U
  2475. #define LPDDR4__DENALI_CTL_166__TCKFSPX_F0_SHIFT 8U
  2476. #define LPDDR4__DENALI_CTL_166__TCKFSPX_F0_WIDTH 5U
  2477. #define LPDDR4__TCKFSPX_F0__REG DENALI_CTL_166
  2478. #define LPDDR4__TCKFSPX_F0__FLD LPDDR4__DENALI_CTL_166__TCKFSPX_F0
  2479. #define LPDDR4__DENALI_CTL_166__TVREF_LONG_F0_MASK 0xFFFF0000U
  2480. #define LPDDR4__DENALI_CTL_166__TVREF_LONG_F0_SHIFT 16U
  2481. #define LPDDR4__DENALI_CTL_166__TVREF_LONG_F0_WIDTH 16U
  2482. #define LPDDR4__TVREF_LONG_F0__REG DENALI_CTL_166
  2483. #define LPDDR4__TVREF_LONG_F0__FLD LPDDR4__DENALI_CTL_166__TVREF_LONG_F0
  2484. #define LPDDR4__DENALI_CTL_167_READ_MASK 0x03FF03FFU
  2485. #define LPDDR4__DENALI_CTL_167_WRITE_MASK 0x03FF03FFU
  2486. #define LPDDR4__DENALI_CTL_167__TVRCG_ENABLE_F1_MASK 0x000003FFU
  2487. #define LPDDR4__DENALI_CTL_167__TVRCG_ENABLE_F1_SHIFT 0U
  2488. #define LPDDR4__DENALI_CTL_167__TVRCG_ENABLE_F1_WIDTH 10U
  2489. #define LPDDR4__TVRCG_ENABLE_F1__REG DENALI_CTL_167
  2490. #define LPDDR4__TVRCG_ENABLE_F1__FLD LPDDR4__DENALI_CTL_167__TVRCG_ENABLE_F1
  2491. #define LPDDR4__DENALI_CTL_167__TVRCG_DISABLE_F1_MASK 0x03FF0000U
  2492. #define LPDDR4__DENALI_CTL_167__TVRCG_DISABLE_F1_SHIFT 16U
  2493. #define LPDDR4__DENALI_CTL_167__TVRCG_DISABLE_F1_WIDTH 10U
  2494. #define LPDDR4__TVRCG_DISABLE_F1__REG DENALI_CTL_167
  2495. #define LPDDR4__TVRCG_DISABLE_F1__FLD LPDDR4__DENALI_CTL_167__TVRCG_DISABLE_F1
  2496. #define LPDDR4__DENALI_CTL_168_READ_MASK 0x1F1F03FFU
  2497. #define LPDDR4__DENALI_CTL_168_WRITE_MASK 0x1F1F03FFU
  2498. #define LPDDR4__DENALI_CTL_168__TFC_F1_MASK 0x000003FFU
  2499. #define LPDDR4__DENALI_CTL_168__TFC_F1_SHIFT 0U
  2500. #define LPDDR4__DENALI_CTL_168__TFC_F1_WIDTH 10U
  2501. #define LPDDR4__TFC_F1__REG DENALI_CTL_168
  2502. #define LPDDR4__TFC_F1__FLD LPDDR4__DENALI_CTL_168__TFC_F1
  2503. #define LPDDR4__DENALI_CTL_168__TCKFSPE_F1_MASK 0x001F0000U
  2504. #define LPDDR4__DENALI_CTL_168__TCKFSPE_F1_SHIFT 16U
  2505. #define LPDDR4__DENALI_CTL_168__TCKFSPE_F1_WIDTH 5U
  2506. #define LPDDR4__TCKFSPE_F1__REG DENALI_CTL_168
  2507. #define LPDDR4__TCKFSPE_F1__FLD LPDDR4__DENALI_CTL_168__TCKFSPE_F1
  2508. #define LPDDR4__DENALI_CTL_168__TCKFSPX_F1_MASK 0x1F000000U
  2509. #define LPDDR4__DENALI_CTL_168__TCKFSPX_F1_SHIFT 24U
  2510. #define LPDDR4__DENALI_CTL_168__TCKFSPX_F1_WIDTH 5U
  2511. #define LPDDR4__TCKFSPX_F1__REG DENALI_CTL_168
  2512. #define LPDDR4__TCKFSPX_F1__FLD LPDDR4__DENALI_CTL_168__TCKFSPX_F1
  2513. #define LPDDR4__DENALI_CTL_169_READ_MASK 0x03FFFFFFU
  2514. #define LPDDR4__DENALI_CTL_169_WRITE_MASK 0x03FFFFFFU
  2515. #define LPDDR4__DENALI_CTL_169__TVREF_LONG_F1_MASK 0x0000FFFFU
  2516. #define LPDDR4__DENALI_CTL_169__TVREF_LONG_F1_SHIFT 0U
  2517. #define LPDDR4__DENALI_CTL_169__TVREF_LONG_F1_WIDTH 16U
  2518. #define LPDDR4__TVREF_LONG_F1__REG DENALI_CTL_169
  2519. #define LPDDR4__TVREF_LONG_F1__FLD LPDDR4__DENALI_CTL_169__TVREF_LONG_F1
  2520. #define LPDDR4__DENALI_CTL_169__TVRCG_ENABLE_F2_MASK 0x03FF0000U
  2521. #define LPDDR4__DENALI_CTL_169__TVRCG_ENABLE_F2_SHIFT 16U
  2522. #define LPDDR4__DENALI_CTL_169__TVRCG_ENABLE_F2_WIDTH 10U
  2523. #define LPDDR4__TVRCG_ENABLE_F2__REG DENALI_CTL_169
  2524. #define LPDDR4__TVRCG_ENABLE_F2__FLD LPDDR4__DENALI_CTL_169__TVRCG_ENABLE_F2
  2525. #define LPDDR4__DENALI_CTL_170_READ_MASK 0x03FF03FFU
  2526. #define LPDDR4__DENALI_CTL_170_WRITE_MASK 0x03FF03FFU
  2527. #define LPDDR4__DENALI_CTL_170__TVRCG_DISABLE_F2_MASK 0x000003FFU
  2528. #define LPDDR4__DENALI_CTL_170__TVRCG_DISABLE_F2_SHIFT 0U
  2529. #define LPDDR4__DENALI_CTL_170__TVRCG_DISABLE_F2_WIDTH 10U
  2530. #define LPDDR4__TVRCG_DISABLE_F2__REG DENALI_CTL_170
  2531. #define LPDDR4__TVRCG_DISABLE_F2__FLD LPDDR4__DENALI_CTL_170__TVRCG_DISABLE_F2
  2532. #define LPDDR4__DENALI_CTL_170__TFC_F2_MASK 0x03FF0000U
  2533. #define LPDDR4__DENALI_CTL_170__TFC_F2_SHIFT 16U
  2534. #define LPDDR4__DENALI_CTL_170__TFC_F2_WIDTH 10U
  2535. #define LPDDR4__TFC_F2__REG DENALI_CTL_170
  2536. #define LPDDR4__TFC_F2__FLD LPDDR4__DENALI_CTL_170__TFC_F2
  2537. #define LPDDR4__DENALI_CTL_171_READ_MASK 0xFFFF1F1FU
  2538. #define LPDDR4__DENALI_CTL_171_WRITE_MASK 0xFFFF1F1FU
  2539. #define LPDDR4__DENALI_CTL_171__TCKFSPE_F2_MASK 0x0000001FU
  2540. #define LPDDR4__DENALI_CTL_171__TCKFSPE_F2_SHIFT 0U
  2541. #define LPDDR4__DENALI_CTL_171__TCKFSPE_F2_WIDTH 5U
  2542. #define LPDDR4__TCKFSPE_F2__REG DENALI_CTL_171
  2543. #define LPDDR4__TCKFSPE_F2__FLD LPDDR4__DENALI_CTL_171__TCKFSPE_F2
  2544. #define LPDDR4__DENALI_CTL_171__TCKFSPX_F2_MASK 0x00001F00U
  2545. #define LPDDR4__DENALI_CTL_171__TCKFSPX_F2_SHIFT 8U
  2546. #define LPDDR4__DENALI_CTL_171__TCKFSPX_F2_WIDTH 5U
  2547. #define LPDDR4__TCKFSPX_F2__REG DENALI_CTL_171
  2548. #define LPDDR4__TCKFSPX_F2__FLD LPDDR4__DENALI_CTL_171__TCKFSPX_F2
  2549. #define LPDDR4__DENALI_CTL_171__TVREF_LONG_F2_MASK 0xFFFF0000U
  2550. #define LPDDR4__DENALI_CTL_171__TVREF_LONG_F2_SHIFT 16U
  2551. #define LPDDR4__DENALI_CTL_171__TVREF_LONG_F2_WIDTH 16U
  2552. #define LPDDR4__TVREF_LONG_F2__REG DENALI_CTL_171
  2553. #define LPDDR4__TVREF_LONG_F2__FLD LPDDR4__DENALI_CTL_171__TVREF_LONG_F2
  2554. #define LPDDR4__DENALI_CTL_172_READ_MASK 0xFFFFFFFFU
  2555. #define LPDDR4__DENALI_CTL_172_WRITE_MASK 0xFFFFFFFFU
  2556. #define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
  2557. #define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F0_SHIFT 0U
  2558. #define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F0_WIDTH 16U
  2559. #define LPDDR4__MRR_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_172
  2560. #define LPDDR4__MRR_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F0
  2561. #define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U
  2562. #define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F1_SHIFT 16U
  2563. #define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F1_WIDTH 16U
  2564. #define LPDDR4__MRR_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_172
  2565. #define LPDDR4__MRR_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F1
  2566. #define LPDDR4__DENALI_CTL_173_READ_MASK 0xFFFFFFFFU
  2567. #define LPDDR4__DENALI_CTL_173_WRITE_MASK 0xFFFFFFFFU
  2568. #define LPDDR4__DENALI_CTL_173__MRR_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
  2569. #define LPDDR4__DENALI_CTL_173__MRR_PROMOTE_THRESHOLD_F2_SHIFT 0U
  2570. #define LPDDR4__DENALI_CTL_173__MRR_PROMOTE_THRESHOLD_F2_WIDTH 16U
  2571. #define LPDDR4__MRR_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_173
  2572. #define LPDDR4__MRR_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_173__MRR_PROMOTE_THRESHOLD_F2
  2573. #define LPDDR4__DENALI_CTL_173__MRW_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U
  2574. #define LPDDR4__DENALI_CTL_173__MRW_PROMOTE_THRESHOLD_F0_SHIFT 16U
  2575. #define LPDDR4__DENALI_CTL_173__MRW_PROMOTE_THRESHOLD_F0_WIDTH 16U
  2576. #define LPDDR4__MRW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_173
  2577. #define LPDDR4__MRW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_173__MRW_PROMOTE_THRESHOLD_F0
  2578. #define LPDDR4__DENALI_CTL_174_READ_MASK 0xFFFFFFFFU
  2579. #define LPDDR4__DENALI_CTL_174_WRITE_MASK 0xFFFFFFFFU
  2580. #define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU
  2581. #define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F1_SHIFT 0U
  2582. #define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F1_WIDTH 16U
  2583. #define LPDDR4__MRW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_174
  2584. #define LPDDR4__MRW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F1
  2585. #define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U
  2586. #define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F2_SHIFT 16U
  2587. #define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F2_WIDTH 16U
  2588. #define LPDDR4__MRW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_174
  2589. #define LPDDR4__MRW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F2
  2590. #define LPDDR4__DENALI_CTL_175_READ_MASK 0xFFFFFFFFU
  2591. #define LPDDR4__DENALI_CTL_175_WRITE_MASK 0xFFFFFFFFU
  2592. #define LPDDR4__DENALI_CTL_175__MR1_DATA_F0_0_MASK 0x000000FFU
  2593. #define LPDDR4__DENALI_CTL_175__MR1_DATA_F0_0_SHIFT 0U
  2594. #define LPDDR4__DENALI_CTL_175__MR1_DATA_F0_0_WIDTH 8U
  2595. #define LPDDR4__MR1_DATA_F0_0__REG DENALI_CTL_175
  2596. #define LPDDR4__MR1_DATA_F0_0__FLD LPDDR4__DENALI_CTL_175__MR1_DATA_F0_0
  2597. #define LPDDR4__DENALI_CTL_175__MR2_DATA_F0_0_MASK 0x0000FF00U
  2598. #define LPDDR4__DENALI_CTL_175__MR2_DATA_F0_0_SHIFT 8U
  2599. #define LPDDR4__DENALI_CTL_175__MR2_DATA_F0_0_WIDTH 8U
  2600. #define LPDDR4__MR2_DATA_F0_0__REG DENALI_CTL_175
  2601. #define LPDDR4__MR2_DATA_F0_0__FLD LPDDR4__DENALI_CTL_175__MR2_DATA_F0_0
  2602. #define LPDDR4__DENALI_CTL_175__MR1_DATA_F1_0_MASK 0x00FF0000U
  2603. #define LPDDR4__DENALI_CTL_175__MR1_DATA_F1_0_SHIFT 16U
  2604. #define LPDDR4__DENALI_CTL_175__MR1_DATA_F1_0_WIDTH 8U
  2605. #define LPDDR4__MR1_DATA_F1_0__REG DENALI_CTL_175
  2606. #define LPDDR4__MR1_DATA_F1_0__FLD LPDDR4__DENALI_CTL_175__MR1_DATA_F1_0
  2607. #define LPDDR4__DENALI_CTL_175__MR2_DATA_F1_0_MASK 0xFF000000U
  2608. #define LPDDR4__DENALI_CTL_175__MR2_DATA_F1_0_SHIFT 24U
  2609. #define LPDDR4__DENALI_CTL_175__MR2_DATA_F1_0_WIDTH 8U
  2610. #define LPDDR4__MR2_DATA_F1_0__REG DENALI_CTL_175
  2611. #define LPDDR4__MR2_DATA_F1_0__FLD LPDDR4__DENALI_CTL_175__MR2_DATA_F1_0
  2612. #define LPDDR4__DENALI_CTL_176_READ_MASK 0xFFFFFFFFU
  2613. #define LPDDR4__DENALI_CTL_176_WRITE_MASK 0xFFFFFFFFU
  2614. #define LPDDR4__DENALI_CTL_176__MR1_DATA_F2_0_MASK 0x000000FFU
  2615. #define LPDDR4__DENALI_CTL_176__MR1_DATA_F2_0_SHIFT 0U
  2616. #define LPDDR4__DENALI_CTL_176__MR1_DATA_F2_0_WIDTH 8U
  2617. #define LPDDR4__MR1_DATA_F2_0__REG DENALI_CTL_176
  2618. #define LPDDR4__MR1_DATA_F2_0__FLD LPDDR4__DENALI_CTL_176__MR1_DATA_F2_0
  2619. #define LPDDR4__DENALI_CTL_176__MR2_DATA_F2_0_MASK 0x0000FF00U
  2620. #define LPDDR4__DENALI_CTL_176__MR2_DATA_F2_0_SHIFT 8U
  2621. #define LPDDR4__DENALI_CTL_176__MR2_DATA_F2_0_WIDTH 8U
  2622. #define LPDDR4__MR2_DATA_F2_0__REG DENALI_CTL_176
  2623. #define LPDDR4__MR2_DATA_F2_0__FLD LPDDR4__DENALI_CTL_176__MR2_DATA_F2_0
  2624. #define LPDDR4__DENALI_CTL_176__MRSINGLE_DATA_0_MASK 0x00FF0000U
  2625. #define LPDDR4__DENALI_CTL_176__MRSINGLE_DATA_0_SHIFT 16U
  2626. #define LPDDR4__DENALI_CTL_176__MRSINGLE_DATA_0_WIDTH 8U
  2627. #define LPDDR4__MRSINGLE_DATA_0__REG DENALI_CTL_176
  2628. #define LPDDR4__MRSINGLE_DATA_0__FLD LPDDR4__DENALI_CTL_176__MRSINGLE_DATA_0
  2629. #define LPDDR4__DENALI_CTL_176__MR3_DATA_F0_0_MASK 0xFF000000U
  2630. #define LPDDR4__DENALI_CTL_176__MR3_DATA_F0_0_SHIFT 24U
  2631. #define LPDDR4__DENALI_CTL_176__MR3_DATA_F0_0_WIDTH 8U
  2632. #define LPDDR4__MR3_DATA_F0_0__REG DENALI_CTL_176
  2633. #define LPDDR4__MR3_DATA_F0_0__FLD LPDDR4__DENALI_CTL_176__MR3_DATA_F0_0
  2634. #define LPDDR4__DENALI_CTL_177_READ_MASK 0xFFFFFFFFU
  2635. #define LPDDR4__DENALI_CTL_177_WRITE_MASK 0xFFFFFFFFU
  2636. #define LPDDR4__DENALI_CTL_177__MR3_DATA_F1_0_MASK 0x000000FFU
  2637. #define LPDDR4__DENALI_CTL_177__MR3_DATA_F1_0_SHIFT 0U
  2638. #define LPDDR4__DENALI_CTL_177__MR3_DATA_F1_0_WIDTH 8U
  2639. #define LPDDR4__MR3_DATA_F1_0__REG DENALI_CTL_177
  2640. #define LPDDR4__MR3_DATA_F1_0__FLD LPDDR4__DENALI_CTL_177__MR3_DATA_F1_0
  2641. #define LPDDR4__DENALI_CTL_177__MR3_DATA_F2_0_MASK 0x0000FF00U
  2642. #define LPDDR4__DENALI_CTL_177__MR3_DATA_F2_0_SHIFT 8U
  2643. #define LPDDR4__DENALI_CTL_177__MR3_DATA_F2_0_WIDTH 8U
  2644. #define LPDDR4__MR3_DATA_F2_0__REG DENALI_CTL_177
  2645. #define LPDDR4__MR3_DATA_F2_0__FLD LPDDR4__DENALI_CTL_177__MR3_DATA_F2_0
  2646. #define LPDDR4__DENALI_CTL_177__MR4_DATA_F0_0_MASK 0x00FF0000U
  2647. #define LPDDR4__DENALI_CTL_177__MR4_DATA_F0_0_SHIFT 16U
  2648. #define LPDDR4__DENALI_CTL_177__MR4_DATA_F0_0_WIDTH 8U
  2649. #define LPDDR4__MR4_DATA_F0_0__REG DENALI_CTL_177
  2650. #define LPDDR4__MR4_DATA_F0_0__FLD LPDDR4__DENALI_CTL_177__MR4_DATA_F0_0
  2651. #define LPDDR4__DENALI_CTL_177__MR4_DATA_F1_0_MASK 0xFF000000U
  2652. #define LPDDR4__DENALI_CTL_177__MR4_DATA_F1_0_SHIFT 24U
  2653. #define LPDDR4__DENALI_CTL_177__MR4_DATA_F1_0_WIDTH 8U
  2654. #define LPDDR4__MR4_DATA_F1_0__REG DENALI_CTL_177
  2655. #define LPDDR4__MR4_DATA_F1_0__FLD LPDDR4__DENALI_CTL_177__MR4_DATA_F1_0
  2656. #define LPDDR4__DENALI_CTL_178_READ_MASK 0xFFFFFFFFU
  2657. #define LPDDR4__DENALI_CTL_178_WRITE_MASK 0xFFFFFFFFU
  2658. #define LPDDR4__DENALI_CTL_178__MR4_DATA_F2_0_MASK 0x000000FFU
  2659. #define LPDDR4__DENALI_CTL_178__MR4_DATA_F2_0_SHIFT 0U
  2660. #define LPDDR4__DENALI_CTL_178__MR4_DATA_F2_0_WIDTH 8U
  2661. #define LPDDR4__MR4_DATA_F2_0__REG DENALI_CTL_178
  2662. #define LPDDR4__MR4_DATA_F2_0__FLD LPDDR4__DENALI_CTL_178__MR4_DATA_F2_0
  2663. #define LPDDR4__DENALI_CTL_178__MR8_DATA_0_MASK 0x0000FF00U
  2664. #define LPDDR4__DENALI_CTL_178__MR8_DATA_0_SHIFT 8U
  2665. #define LPDDR4__DENALI_CTL_178__MR8_DATA_0_WIDTH 8U
  2666. #define LPDDR4__MR8_DATA_0__REG DENALI_CTL_178
  2667. #define LPDDR4__MR8_DATA_0__FLD LPDDR4__DENALI_CTL_178__MR8_DATA_0
  2668. #define LPDDR4__DENALI_CTL_178__MR11_DATA_F0_0_MASK 0x00FF0000U
  2669. #define LPDDR4__DENALI_CTL_178__MR11_DATA_F0_0_SHIFT 16U
  2670. #define LPDDR4__DENALI_CTL_178__MR11_DATA_F0_0_WIDTH 8U
  2671. #define LPDDR4__MR11_DATA_F0_0__REG DENALI_CTL_178
  2672. #define LPDDR4__MR11_DATA_F0_0__FLD LPDDR4__DENALI_CTL_178__MR11_DATA_F0_0
  2673. #define LPDDR4__DENALI_CTL_178__MR11_DATA_F1_0_MASK 0xFF000000U
  2674. #define LPDDR4__DENALI_CTL_178__MR11_DATA_F1_0_SHIFT 24U
  2675. #define LPDDR4__DENALI_CTL_178__MR11_DATA_F1_0_WIDTH 8U
  2676. #define LPDDR4__MR11_DATA_F1_0__REG DENALI_CTL_178
  2677. #define LPDDR4__MR11_DATA_F1_0__FLD LPDDR4__DENALI_CTL_178__MR11_DATA_F1_0
  2678. #define LPDDR4__DENALI_CTL_179_READ_MASK 0xFFFFFFFFU
  2679. #define LPDDR4__DENALI_CTL_179_WRITE_MASK 0xFFFFFFFFU
  2680. #define LPDDR4__DENALI_CTL_179__MR11_DATA_F2_0_MASK 0x000000FFU
  2681. #define LPDDR4__DENALI_CTL_179__MR11_DATA_F2_0_SHIFT 0U
  2682. #define LPDDR4__DENALI_CTL_179__MR11_DATA_F2_0_WIDTH 8U
  2683. #define LPDDR4__MR11_DATA_F2_0__REG DENALI_CTL_179
  2684. #define LPDDR4__MR11_DATA_F2_0__FLD LPDDR4__DENALI_CTL_179__MR11_DATA_F2_0
  2685. #define LPDDR4__DENALI_CTL_179__MR12_DATA_F0_0_MASK 0x0000FF00U
  2686. #define LPDDR4__DENALI_CTL_179__MR12_DATA_F0_0_SHIFT 8U
  2687. #define LPDDR4__DENALI_CTL_179__MR12_DATA_F0_0_WIDTH 8U
  2688. #define LPDDR4__MR12_DATA_F0_0__REG DENALI_CTL_179
  2689. #define LPDDR4__MR12_DATA_F0_0__FLD LPDDR4__DENALI_CTL_179__MR12_DATA_F0_0
  2690. #define LPDDR4__DENALI_CTL_179__MR12_DATA_F1_0_MASK 0x00FF0000U
  2691. #define LPDDR4__DENALI_CTL_179__MR12_DATA_F1_0_SHIFT 16U
  2692. #define LPDDR4__DENALI_CTL_179__MR12_DATA_F1_0_WIDTH 8U
  2693. #define LPDDR4__MR12_DATA_F1_0__REG DENALI_CTL_179
  2694. #define LPDDR4__MR12_DATA_F1_0__FLD LPDDR4__DENALI_CTL_179__MR12_DATA_F1_0
  2695. #define LPDDR4__DENALI_CTL_179__MR12_DATA_F2_0_MASK 0xFF000000U
  2696. #define LPDDR4__DENALI_CTL_179__MR12_DATA_F2_0_SHIFT 24U
  2697. #define LPDDR4__DENALI_CTL_179__MR12_DATA_F2_0_WIDTH 8U
  2698. #define LPDDR4__MR12_DATA_F2_0__REG DENALI_CTL_179
  2699. #define LPDDR4__MR12_DATA_F2_0__FLD LPDDR4__DENALI_CTL_179__MR12_DATA_F2_0
  2700. #define LPDDR4__DENALI_CTL_180_READ_MASK 0xFFFFFFFFU
  2701. #define LPDDR4__DENALI_CTL_180_WRITE_MASK 0xFFFFFFFFU
  2702. #define LPDDR4__DENALI_CTL_180__MR13_DATA_0_MASK 0x000000FFU
  2703. #define LPDDR4__DENALI_CTL_180__MR13_DATA_0_SHIFT 0U
  2704. #define LPDDR4__DENALI_CTL_180__MR13_DATA_0_WIDTH 8U
  2705. #define LPDDR4__MR13_DATA_0__REG DENALI_CTL_180
  2706. #define LPDDR4__MR13_DATA_0__FLD LPDDR4__DENALI_CTL_180__MR13_DATA_0
  2707. #define LPDDR4__DENALI_CTL_180__MR14_DATA_F0_0_MASK 0x0000FF00U
  2708. #define LPDDR4__DENALI_CTL_180__MR14_DATA_F0_0_SHIFT 8U
  2709. #define LPDDR4__DENALI_CTL_180__MR14_DATA_F0_0_WIDTH 8U
  2710. #define LPDDR4__MR14_DATA_F0_0__REG DENALI_CTL_180
  2711. #define LPDDR4__MR14_DATA_F0_0__FLD LPDDR4__DENALI_CTL_180__MR14_DATA_F0_0
  2712. #define LPDDR4__DENALI_CTL_180__MR14_DATA_F1_0_MASK 0x00FF0000U
  2713. #define LPDDR4__DENALI_CTL_180__MR14_DATA_F1_0_SHIFT 16U
  2714. #define LPDDR4__DENALI_CTL_180__MR14_DATA_F1_0_WIDTH 8U
  2715. #define LPDDR4__MR14_DATA_F1_0__REG DENALI_CTL_180
  2716. #define LPDDR4__MR14_DATA_F1_0__FLD LPDDR4__DENALI_CTL_180__MR14_DATA_F1_0
  2717. #define LPDDR4__DENALI_CTL_180__MR14_DATA_F2_0_MASK 0xFF000000U
  2718. #define LPDDR4__DENALI_CTL_180__MR14_DATA_F2_0_SHIFT 24U
  2719. #define LPDDR4__DENALI_CTL_180__MR14_DATA_F2_0_WIDTH 8U
  2720. #define LPDDR4__MR14_DATA_F2_0__REG DENALI_CTL_180
  2721. #define LPDDR4__MR14_DATA_F2_0__FLD LPDDR4__DENALI_CTL_180__MR14_DATA_F2_0
  2722. #define LPDDR4__DENALI_CTL_181_READ_MASK 0xFFFFFFFFU
  2723. #define LPDDR4__DENALI_CTL_181_WRITE_MASK 0xFFFFFFFFU
  2724. #define LPDDR4__DENALI_CTL_181__MR16_DATA_0_MASK 0x000000FFU
  2725. #define LPDDR4__DENALI_CTL_181__MR16_DATA_0_SHIFT 0U
  2726. #define LPDDR4__DENALI_CTL_181__MR16_DATA_0_WIDTH 8U
  2727. #define LPDDR4__MR16_DATA_0__REG DENALI_CTL_181
  2728. #define LPDDR4__MR16_DATA_0__FLD LPDDR4__DENALI_CTL_181__MR16_DATA_0
  2729. #define LPDDR4__DENALI_CTL_181__MR17_DATA_0_MASK 0x0000FF00U
  2730. #define LPDDR4__DENALI_CTL_181__MR17_DATA_0_SHIFT 8U
  2731. #define LPDDR4__DENALI_CTL_181__MR17_DATA_0_WIDTH 8U
  2732. #define LPDDR4__MR17_DATA_0__REG DENALI_CTL_181
  2733. #define LPDDR4__MR17_DATA_0__FLD LPDDR4__DENALI_CTL_181__MR17_DATA_0
  2734. #define LPDDR4__DENALI_CTL_181__MR20_DATA_0_MASK 0x00FF0000U
  2735. #define LPDDR4__DENALI_CTL_181__MR20_DATA_0_SHIFT 16U
  2736. #define LPDDR4__DENALI_CTL_181__MR20_DATA_0_WIDTH 8U
  2737. #define LPDDR4__MR20_DATA_0__REG DENALI_CTL_181
  2738. #define LPDDR4__MR20_DATA_0__FLD LPDDR4__DENALI_CTL_181__MR20_DATA_0
  2739. #define LPDDR4__DENALI_CTL_181__MR22_DATA_F0_0_MASK 0xFF000000U
  2740. #define LPDDR4__DENALI_CTL_181__MR22_DATA_F0_0_SHIFT 24U
  2741. #define LPDDR4__DENALI_CTL_181__MR22_DATA_F0_0_WIDTH 8U
  2742. #define LPDDR4__MR22_DATA_F0_0__REG DENALI_CTL_181
  2743. #define LPDDR4__MR22_DATA_F0_0__FLD LPDDR4__DENALI_CTL_181__MR22_DATA_F0_0
  2744. #define LPDDR4__DENALI_CTL_182_READ_MASK 0xFFFFFFFFU
  2745. #define LPDDR4__DENALI_CTL_182_WRITE_MASK 0xFFFFFFFFU
  2746. #define LPDDR4__DENALI_CTL_182__MR22_DATA_F1_0_MASK 0x000000FFU
  2747. #define LPDDR4__DENALI_CTL_182__MR22_DATA_F1_0_SHIFT 0U
  2748. #define LPDDR4__DENALI_CTL_182__MR22_DATA_F1_0_WIDTH 8U
  2749. #define LPDDR4__MR22_DATA_F1_0__REG DENALI_CTL_182
  2750. #define LPDDR4__MR22_DATA_F1_0__FLD LPDDR4__DENALI_CTL_182__MR22_DATA_F1_0
  2751. #define LPDDR4__DENALI_CTL_182__MR22_DATA_F2_0_MASK 0x0000FF00U
  2752. #define LPDDR4__DENALI_CTL_182__MR22_DATA_F2_0_SHIFT 8U
  2753. #define LPDDR4__DENALI_CTL_182__MR22_DATA_F2_0_WIDTH 8U
  2754. #define LPDDR4__MR22_DATA_F2_0__REG DENALI_CTL_182
  2755. #define LPDDR4__MR22_DATA_F2_0__FLD LPDDR4__DENALI_CTL_182__MR22_DATA_F2_0
  2756. #define LPDDR4__DENALI_CTL_182__MR1_DATA_F0_1_MASK 0x00FF0000U
  2757. #define LPDDR4__DENALI_CTL_182__MR1_DATA_F0_1_SHIFT 16U
  2758. #define LPDDR4__DENALI_CTL_182__MR1_DATA_F0_1_WIDTH 8U
  2759. #define LPDDR4__MR1_DATA_F0_1__REG DENALI_CTL_182
  2760. #define LPDDR4__MR1_DATA_F0_1__FLD LPDDR4__DENALI_CTL_182__MR1_DATA_F0_1
  2761. #define LPDDR4__DENALI_CTL_182__MR2_DATA_F0_1_MASK 0xFF000000U
  2762. #define LPDDR4__DENALI_CTL_182__MR2_DATA_F0_1_SHIFT 24U
  2763. #define LPDDR4__DENALI_CTL_182__MR2_DATA_F0_1_WIDTH 8U
  2764. #define LPDDR4__MR2_DATA_F0_1__REG DENALI_CTL_182
  2765. #define LPDDR4__MR2_DATA_F0_1__FLD LPDDR4__DENALI_CTL_182__MR2_DATA_F0_1
  2766. #define LPDDR4__DENALI_CTL_183_READ_MASK 0xFFFFFFFFU
  2767. #define LPDDR4__DENALI_CTL_183_WRITE_MASK 0xFFFFFFFFU
  2768. #define LPDDR4__DENALI_CTL_183__MR1_DATA_F1_1_MASK 0x000000FFU
  2769. #define LPDDR4__DENALI_CTL_183__MR1_DATA_F1_1_SHIFT 0U
  2770. #define LPDDR4__DENALI_CTL_183__MR1_DATA_F1_1_WIDTH 8U
  2771. #define LPDDR4__MR1_DATA_F1_1__REG DENALI_CTL_183
  2772. #define LPDDR4__MR1_DATA_F1_1__FLD LPDDR4__DENALI_CTL_183__MR1_DATA_F1_1
  2773. #define LPDDR4__DENALI_CTL_183__MR2_DATA_F1_1_MASK 0x0000FF00U
  2774. #define LPDDR4__DENALI_CTL_183__MR2_DATA_F1_1_SHIFT 8U
  2775. #define LPDDR4__DENALI_CTL_183__MR2_DATA_F1_1_WIDTH 8U
  2776. #define LPDDR4__MR2_DATA_F1_1__REG DENALI_CTL_183
  2777. #define LPDDR4__MR2_DATA_F1_1__FLD LPDDR4__DENALI_CTL_183__MR2_DATA_F1_1
  2778. #define LPDDR4__DENALI_CTL_183__MR1_DATA_F2_1_MASK 0x00FF0000U
  2779. #define LPDDR4__DENALI_CTL_183__MR1_DATA_F2_1_SHIFT 16U
  2780. #define LPDDR4__DENALI_CTL_183__MR1_DATA_F2_1_WIDTH 8U
  2781. #define LPDDR4__MR1_DATA_F2_1__REG DENALI_CTL_183
  2782. #define LPDDR4__MR1_DATA_F2_1__FLD LPDDR4__DENALI_CTL_183__MR1_DATA_F2_1
  2783. #define LPDDR4__DENALI_CTL_183__MR2_DATA_F2_1_MASK 0xFF000000U
  2784. #define LPDDR4__DENALI_CTL_183__MR2_DATA_F2_1_SHIFT 24U
  2785. #define LPDDR4__DENALI_CTL_183__MR2_DATA_F2_1_WIDTH 8U
  2786. #define LPDDR4__MR2_DATA_F2_1__REG DENALI_CTL_183
  2787. #define LPDDR4__MR2_DATA_F2_1__FLD LPDDR4__DENALI_CTL_183__MR2_DATA_F2_1
  2788. #define LPDDR4__DENALI_CTL_184_READ_MASK 0xFFFFFFFFU
  2789. #define LPDDR4__DENALI_CTL_184_WRITE_MASK 0xFFFFFFFFU
  2790. #define LPDDR4__DENALI_CTL_184__MRSINGLE_DATA_1_MASK 0x000000FFU
  2791. #define LPDDR4__DENALI_CTL_184__MRSINGLE_DATA_1_SHIFT 0U
  2792. #define LPDDR4__DENALI_CTL_184__MRSINGLE_DATA_1_WIDTH 8U
  2793. #define LPDDR4__MRSINGLE_DATA_1__REG DENALI_CTL_184
  2794. #define LPDDR4__MRSINGLE_DATA_1__FLD LPDDR4__DENALI_CTL_184__MRSINGLE_DATA_1
  2795. #define LPDDR4__DENALI_CTL_184__MR3_DATA_F0_1_MASK 0x0000FF00U
  2796. #define LPDDR4__DENALI_CTL_184__MR3_DATA_F0_1_SHIFT 8U
  2797. #define LPDDR4__DENALI_CTL_184__MR3_DATA_F0_1_WIDTH 8U
  2798. #define LPDDR4__MR3_DATA_F0_1__REG DENALI_CTL_184
  2799. #define LPDDR4__MR3_DATA_F0_1__FLD LPDDR4__DENALI_CTL_184__MR3_DATA_F0_1
  2800. #define LPDDR4__DENALI_CTL_184__MR3_DATA_F1_1_MASK 0x00FF0000U
  2801. #define LPDDR4__DENALI_CTL_184__MR3_DATA_F1_1_SHIFT 16U
  2802. #define LPDDR4__DENALI_CTL_184__MR3_DATA_F1_1_WIDTH 8U
  2803. #define LPDDR4__MR3_DATA_F1_1__REG DENALI_CTL_184
  2804. #define LPDDR4__MR3_DATA_F1_1__FLD LPDDR4__DENALI_CTL_184__MR3_DATA_F1_1
  2805. #define LPDDR4__DENALI_CTL_184__MR3_DATA_F2_1_MASK 0xFF000000U
  2806. #define LPDDR4__DENALI_CTL_184__MR3_DATA_F2_1_SHIFT 24U
  2807. #define LPDDR4__DENALI_CTL_184__MR3_DATA_F2_1_WIDTH 8U
  2808. #define LPDDR4__MR3_DATA_F2_1__REG DENALI_CTL_184
  2809. #define LPDDR4__MR3_DATA_F2_1__FLD LPDDR4__DENALI_CTL_184__MR3_DATA_F2_1
  2810. #define LPDDR4__DENALI_CTL_185_READ_MASK 0xFFFFFFFFU
  2811. #define LPDDR4__DENALI_CTL_185_WRITE_MASK 0xFFFFFFFFU
  2812. #define LPDDR4__DENALI_CTL_185__MR4_DATA_F0_1_MASK 0x000000FFU
  2813. #define LPDDR4__DENALI_CTL_185__MR4_DATA_F0_1_SHIFT 0U
  2814. #define LPDDR4__DENALI_CTL_185__MR4_DATA_F0_1_WIDTH 8U
  2815. #define LPDDR4__MR4_DATA_F0_1__REG DENALI_CTL_185
  2816. #define LPDDR4__MR4_DATA_F0_1__FLD LPDDR4__DENALI_CTL_185__MR4_DATA_F0_1
  2817. #define LPDDR4__DENALI_CTL_185__MR4_DATA_F1_1_MASK 0x0000FF00U
  2818. #define LPDDR4__DENALI_CTL_185__MR4_DATA_F1_1_SHIFT 8U
  2819. #define LPDDR4__DENALI_CTL_185__MR4_DATA_F1_1_WIDTH 8U
  2820. #define LPDDR4__MR4_DATA_F1_1__REG DENALI_CTL_185
  2821. #define LPDDR4__MR4_DATA_F1_1__FLD LPDDR4__DENALI_CTL_185__MR4_DATA_F1_1
  2822. #define LPDDR4__DENALI_CTL_185__MR4_DATA_F2_1_MASK 0x00FF0000U
  2823. #define LPDDR4__DENALI_CTL_185__MR4_DATA_F2_1_SHIFT 16U
  2824. #define LPDDR4__DENALI_CTL_185__MR4_DATA_F2_1_WIDTH 8U
  2825. #define LPDDR4__MR4_DATA_F2_1__REG DENALI_CTL_185
  2826. #define LPDDR4__MR4_DATA_F2_1__FLD LPDDR4__DENALI_CTL_185__MR4_DATA_F2_1
  2827. #define LPDDR4__DENALI_CTL_185__MR8_DATA_1_MASK 0xFF000000U
  2828. #define LPDDR4__DENALI_CTL_185__MR8_DATA_1_SHIFT 24U
  2829. #define LPDDR4__DENALI_CTL_185__MR8_DATA_1_WIDTH 8U
  2830. #define LPDDR4__MR8_DATA_1__REG DENALI_CTL_185
  2831. #define LPDDR4__MR8_DATA_1__FLD LPDDR4__DENALI_CTL_185__MR8_DATA_1
  2832. #define LPDDR4__DENALI_CTL_186_READ_MASK 0xFFFFFFFFU
  2833. #define LPDDR4__DENALI_CTL_186_WRITE_MASK 0xFFFFFFFFU
  2834. #define LPDDR4__DENALI_CTL_186__MR11_DATA_F0_1_MASK 0x000000FFU
  2835. #define LPDDR4__DENALI_CTL_186__MR11_DATA_F0_1_SHIFT 0U
  2836. #define LPDDR4__DENALI_CTL_186__MR11_DATA_F0_1_WIDTH 8U
  2837. #define LPDDR4__MR11_DATA_F0_1__REG DENALI_CTL_186
  2838. #define LPDDR4__MR11_DATA_F0_1__FLD LPDDR4__DENALI_CTL_186__MR11_DATA_F0_1
  2839. #define LPDDR4__DENALI_CTL_186__MR11_DATA_F1_1_MASK 0x0000FF00U
  2840. #define LPDDR4__DENALI_CTL_186__MR11_DATA_F1_1_SHIFT 8U
  2841. #define LPDDR4__DENALI_CTL_186__MR11_DATA_F1_1_WIDTH 8U
  2842. #define LPDDR4__MR11_DATA_F1_1__REG DENALI_CTL_186
  2843. #define LPDDR4__MR11_DATA_F1_1__FLD LPDDR4__DENALI_CTL_186__MR11_DATA_F1_1
  2844. #define LPDDR4__DENALI_CTL_186__MR11_DATA_F2_1_MASK 0x00FF0000U
  2845. #define LPDDR4__DENALI_CTL_186__MR11_DATA_F2_1_SHIFT 16U
  2846. #define LPDDR4__DENALI_CTL_186__MR11_DATA_F2_1_WIDTH 8U
  2847. #define LPDDR4__MR11_DATA_F2_1__REG DENALI_CTL_186
  2848. #define LPDDR4__MR11_DATA_F2_1__FLD LPDDR4__DENALI_CTL_186__MR11_DATA_F2_1
  2849. #define LPDDR4__DENALI_CTL_186__MR12_DATA_F0_1_MASK 0xFF000000U
  2850. #define LPDDR4__DENALI_CTL_186__MR12_DATA_F0_1_SHIFT 24U
  2851. #define LPDDR4__DENALI_CTL_186__MR12_DATA_F0_1_WIDTH 8U
  2852. #define LPDDR4__MR12_DATA_F0_1__REG DENALI_CTL_186
  2853. #define LPDDR4__MR12_DATA_F0_1__FLD LPDDR4__DENALI_CTL_186__MR12_DATA_F0_1
  2854. #define LPDDR4__DENALI_CTL_187_READ_MASK 0xFFFFFFFFU
  2855. #define LPDDR4__DENALI_CTL_187_WRITE_MASK 0xFFFFFFFFU
  2856. #define LPDDR4__DENALI_CTL_187__MR12_DATA_F1_1_MASK 0x000000FFU
  2857. #define LPDDR4__DENALI_CTL_187__MR12_DATA_F1_1_SHIFT 0U
  2858. #define LPDDR4__DENALI_CTL_187__MR12_DATA_F1_1_WIDTH 8U
  2859. #define LPDDR4__MR12_DATA_F1_1__REG DENALI_CTL_187
  2860. #define LPDDR4__MR12_DATA_F1_1__FLD LPDDR4__DENALI_CTL_187__MR12_DATA_F1_1
  2861. #define LPDDR4__DENALI_CTL_187__MR12_DATA_F2_1_MASK 0x0000FF00U
  2862. #define LPDDR4__DENALI_CTL_187__MR12_DATA_F2_1_SHIFT 8U
  2863. #define LPDDR4__DENALI_CTL_187__MR12_DATA_F2_1_WIDTH 8U
  2864. #define LPDDR4__MR12_DATA_F2_1__REG DENALI_CTL_187
  2865. #define LPDDR4__MR12_DATA_F2_1__FLD LPDDR4__DENALI_CTL_187__MR12_DATA_F2_1
  2866. #define LPDDR4__DENALI_CTL_187__MR13_DATA_1_MASK 0x00FF0000U
  2867. #define LPDDR4__DENALI_CTL_187__MR13_DATA_1_SHIFT 16U
  2868. #define LPDDR4__DENALI_CTL_187__MR13_DATA_1_WIDTH 8U
  2869. #define LPDDR4__MR13_DATA_1__REG DENALI_CTL_187
  2870. #define LPDDR4__MR13_DATA_1__FLD LPDDR4__DENALI_CTL_187__MR13_DATA_1
  2871. #define LPDDR4__DENALI_CTL_187__MR14_DATA_F0_1_MASK 0xFF000000U
  2872. #define LPDDR4__DENALI_CTL_187__MR14_DATA_F0_1_SHIFT 24U
  2873. #define LPDDR4__DENALI_CTL_187__MR14_DATA_F0_1_WIDTH 8U
  2874. #define LPDDR4__MR14_DATA_F0_1__REG DENALI_CTL_187
  2875. #define LPDDR4__MR14_DATA_F0_1__FLD LPDDR4__DENALI_CTL_187__MR14_DATA_F0_1
  2876. #define LPDDR4__DENALI_CTL_188_READ_MASK 0xFFFFFFFFU
  2877. #define LPDDR4__DENALI_CTL_188_WRITE_MASK 0xFFFFFFFFU
  2878. #define LPDDR4__DENALI_CTL_188__MR14_DATA_F1_1_MASK 0x000000FFU
  2879. #define LPDDR4__DENALI_CTL_188__MR14_DATA_F1_1_SHIFT 0U
  2880. #define LPDDR4__DENALI_CTL_188__MR14_DATA_F1_1_WIDTH 8U
  2881. #define LPDDR4__MR14_DATA_F1_1__REG DENALI_CTL_188
  2882. #define LPDDR4__MR14_DATA_F1_1__FLD LPDDR4__DENALI_CTL_188__MR14_DATA_F1_1
  2883. #define LPDDR4__DENALI_CTL_188__MR14_DATA_F2_1_MASK 0x0000FF00U
  2884. #define LPDDR4__DENALI_CTL_188__MR14_DATA_F2_1_SHIFT 8U
  2885. #define LPDDR4__DENALI_CTL_188__MR14_DATA_F2_1_WIDTH 8U
  2886. #define LPDDR4__MR14_DATA_F2_1__REG DENALI_CTL_188
  2887. #define LPDDR4__MR14_DATA_F2_1__FLD LPDDR4__DENALI_CTL_188__MR14_DATA_F2_1
  2888. #define LPDDR4__DENALI_CTL_188__MR16_DATA_1_MASK 0x00FF0000U
  2889. #define LPDDR4__DENALI_CTL_188__MR16_DATA_1_SHIFT 16U
  2890. #define LPDDR4__DENALI_CTL_188__MR16_DATA_1_WIDTH 8U
  2891. #define LPDDR4__MR16_DATA_1__REG DENALI_CTL_188
  2892. #define LPDDR4__MR16_DATA_1__FLD LPDDR4__DENALI_CTL_188__MR16_DATA_1
  2893. #define LPDDR4__DENALI_CTL_188__MR17_DATA_1_MASK 0xFF000000U
  2894. #define LPDDR4__DENALI_CTL_188__MR17_DATA_1_SHIFT 24U
  2895. #define LPDDR4__DENALI_CTL_188__MR17_DATA_1_WIDTH 8U
  2896. #define LPDDR4__MR17_DATA_1__REG DENALI_CTL_188
  2897. #define LPDDR4__MR17_DATA_1__FLD LPDDR4__DENALI_CTL_188__MR17_DATA_1
  2898. #define LPDDR4__DENALI_CTL_189_READ_MASK 0xFFFFFFFFU
  2899. #define LPDDR4__DENALI_CTL_189_WRITE_MASK 0xFFFFFFFFU
  2900. #define LPDDR4__DENALI_CTL_189__MR20_DATA_1_MASK 0x000000FFU
  2901. #define LPDDR4__DENALI_CTL_189__MR20_DATA_1_SHIFT 0U
  2902. #define LPDDR4__DENALI_CTL_189__MR20_DATA_1_WIDTH 8U
  2903. #define LPDDR4__MR20_DATA_1__REG DENALI_CTL_189
  2904. #define LPDDR4__MR20_DATA_1__FLD LPDDR4__DENALI_CTL_189__MR20_DATA_1
  2905. #define LPDDR4__DENALI_CTL_189__MR22_DATA_F0_1_MASK 0x0000FF00U
  2906. #define LPDDR4__DENALI_CTL_189__MR22_DATA_F0_1_SHIFT 8U
  2907. #define LPDDR4__DENALI_CTL_189__MR22_DATA_F0_1_WIDTH 8U
  2908. #define LPDDR4__MR22_DATA_F0_1__REG DENALI_CTL_189
  2909. #define LPDDR4__MR22_DATA_F0_1__FLD LPDDR4__DENALI_CTL_189__MR22_DATA_F0_1
  2910. #define LPDDR4__DENALI_CTL_189__MR22_DATA_F1_1_MASK 0x00FF0000U
  2911. #define LPDDR4__DENALI_CTL_189__MR22_DATA_F1_1_SHIFT 16U
  2912. #define LPDDR4__DENALI_CTL_189__MR22_DATA_F1_1_WIDTH 8U
  2913. #define LPDDR4__MR22_DATA_F1_1__REG DENALI_CTL_189
  2914. #define LPDDR4__MR22_DATA_F1_1__FLD LPDDR4__DENALI_CTL_189__MR22_DATA_F1_1
  2915. #define LPDDR4__DENALI_CTL_189__MR22_DATA_F2_1_MASK 0xFF000000U
  2916. #define LPDDR4__DENALI_CTL_189__MR22_DATA_F2_1_SHIFT 24U
  2917. #define LPDDR4__DENALI_CTL_189__MR22_DATA_F2_1_WIDTH 8U
  2918. #define LPDDR4__MR22_DATA_F2_1__REG DENALI_CTL_189
  2919. #define LPDDR4__MR22_DATA_F2_1__FLD LPDDR4__DENALI_CTL_189__MR22_DATA_F2_1
  2920. #define LPDDR4__DENALI_CTL_190_READ_MASK 0x010101FFU
  2921. #define LPDDR4__DENALI_CTL_190_WRITE_MASK 0x010101FFU
  2922. #define LPDDR4__DENALI_CTL_190__MR23_DATA_MASK 0x000000FFU
  2923. #define LPDDR4__DENALI_CTL_190__MR23_DATA_SHIFT 0U
  2924. #define LPDDR4__DENALI_CTL_190__MR23_DATA_WIDTH 8U
  2925. #define LPDDR4__MR23_DATA__REG DENALI_CTL_190
  2926. #define LPDDR4__MR23_DATA__FLD LPDDR4__DENALI_CTL_190__MR23_DATA
  2927. #define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_MASK 0x00000100U
  2928. #define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_SHIFT 8U
  2929. #define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_WIDTH 1U
  2930. #define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_WOCLR 0U
  2931. #define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_WOSET 0U
  2932. #define LPDDR4__MR_FSP_DATA_VALID_F0__REG DENALI_CTL_190
  2933. #define LPDDR4__MR_FSP_DATA_VALID_F0__FLD LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0
  2934. #define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_MASK 0x00010000U
  2935. #define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_SHIFT 16U
  2936. #define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_WIDTH 1U
  2937. #define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_WOCLR 0U
  2938. #define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_WOSET 0U
  2939. #define LPDDR4__MR_FSP_DATA_VALID_F1__REG DENALI_CTL_190
  2940. #define LPDDR4__MR_FSP_DATA_VALID_F1__FLD LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1
  2941. #define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_MASK 0x01000000U
  2942. #define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_SHIFT 24U
  2943. #define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_WIDTH 1U
  2944. #define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_WOCLR 0U
  2945. #define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_WOSET 0U
  2946. #define LPDDR4__MR_FSP_DATA_VALID_F2__REG DENALI_CTL_190
  2947. #define LPDDR4__MR_FSP_DATA_VALID_F2__FLD LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2
  2948. #define LPDDR4__DENALI_CTL_191_READ_MASK 0x01010103U
  2949. #define LPDDR4__DENALI_CTL_191_WRITE_MASK 0x01010103U
  2950. #define LPDDR4__DENALI_CTL_191__RL3_SUPPORT_EN_MASK 0x00000003U
  2951. #define LPDDR4__DENALI_CTL_191__RL3_SUPPORT_EN_SHIFT 0U
  2952. #define LPDDR4__DENALI_CTL_191__RL3_SUPPORT_EN_WIDTH 2U
  2953. #define LPDDR4__RL3_SUPPORT_EN__REG DENALI_CTL_191
  2954. #define LPDDR4__RL3_SUPPORT_EN__FLD LPDDR4__DENALI_CTL_191__RL3_SUPPORT_EN
  2955. #define LPDDR4__DENALI_CTL_191__MC_RESERVED19_MASK 0x00000100U
  2956. #define LPDDR4__DENALI_CTL_191__MC_RESERVED19_SHIFT 8U
  2957. #define LPDDR4__DENALI_CTL_191__MC_RESERVED19_WIDTH 1U
  2958. #define LPDDR4__DENALI_CTL_191__MC_RESERVED19_WOCLR 0U
  2959. #define LPDDR4__DENALI_CTL_191__MC_RESERVED19_WOSET 0U
  2960. #define LPDDR4__MC_RESERVED19__REG DENALI_CTL_191
  2961. #define LPDDR4__MC_RESERVED19__FLD LPDDR4__DENALI_CTL_191__MC_RESERVED19
  2962. #define LPDDR4__DENALI_CTL_191__MC_RESERVED20_MASK 0x00010000U
  2963. #define LPDDR4__DENALI_CTL_191__MC_RESERVED20_SHIFT 16U
  2964. #define LPDDR4__DENALI_CTL_191__MC_RESERVED20_WIDTH 1U
  2965. #define LPDDR4__DENALI_CTL_191__MC_RESERVED20_WOCLR 0U
  2966. #define LPDDR4__DENALI_CTL_191__MC_RESERVED20_WOSET 0U
  2967. #define LPDDR4__MC_RESERVED20__REG DENALI_CTL_191
  2968. #define LPDDR4__MC_RESERVED20__FLD LPDDR4__DENALI_CTL_191__MC_RESERVED20
  2969. #define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_MASK 0x01000000U
  2970. #define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_SHIFT 24U
  2971. #define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_WIDTH 1U
  2972. #define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_WOCLR 0U
  2973. #define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_WOSET 0U
  2974. #define LPDDR4__FSP_PHY_UPDATE_MRW__REG DENALI_CTL_191
  2975. #define LPDDR4__FSP_PHY_UPDATE_MRW__FLD LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW
  2976. #define LPDDR4__DENALI_CTL_192_READ_MASK 0x01010101U
  2977. #define LPDDR4__DENALI_CTL_192_WRITE_MASK 0x01010101U
  2978. #define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_MASK 0x00000001U
  2979. #define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_SHIFT 0U
  2980. #define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_WIDTH 1U
  2981. #define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_WOCLR 0U
  2982. #define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_WOSET 0U
  2983. #define LPDDR4__DFS_ALWAYS_WRITE_FSP__REG DENALI_CTL_192
  2984. #define LPDDR4__DFS_ALWAYS_WRITE_FSP__FLD LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP
  2985. #define LPDDR4__DENALI_CTL_192__FSP_STATUS_MASK 0x00000100U
  2986. #define LPDDR4__DENALI_CTL_192__FSP_STATUS_SHIFT 8U
  2987. #define LPDDR4__DENALI_CTL_192__FSP_STATUS_WIDTH 1U
  2988. #define LPDDR4__DENALI_CTL_192__FSP_STATUS_WOCLR 0U
  2989. #define LPDDR4__DENALI_CTL_192__FSP_STATUS_WOSET 0U
  2990. #define LPDDR4__FSP_STATUS__REG DENALI_CTL_192
  2991. #define LPDDR4__FSP_STATUS__FLD LPDDR4__DENALI_CTL_192__FSP_STATUS
  2992. #define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_MASK 0x00010000U
  2993. #define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_SHIFT 16U
  2994. #define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_WIDTH 1U
  2995. #define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_WOCLR 0U
  2996. #define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_WOSET 0U
  2997. #define LPDDR4__FSP_OP_CURRENT__REG DENALI_CTL_192
  2998. #define LPDDR4__FSP_OP_CURRENT__FLD LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT
  2999. #define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_MASK 0x01000000U
  3000. #define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_SHIFT 24U
  3001. #define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_WIDTH 1U
  3002. #define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_WOCLR 0U
  3003. #define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_WOSET 0U
  3004. #define LPDDR4__FSP_WR_CURRENT__REG DENALI_CTL_192
  3005. #define LPDDR4__FSP_WR_CURRENT__FLD LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT
  3006. #define LPDDR4__DENALI_CTL_193_READ_MASK 0x03030101U
  3007. #define LPDDR4__DENALI_CTL_193_WRITE_MASK 0x03030101U
  3008. #define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_MASK 0x00000001U
  3009. #define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_SHIFT 0U
  3010. #define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_WIDTH 1U
  3011. #define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_WOCLR 0U
  3012. #define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_WOSET 0U
  3013. #define LPDDR4__FSP0_FRC_VALID__REG DENALI_CTL_193
  3014. #define LPDDR4__FSP0_FRC_VALID__FLD LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID
  3015. #define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_MASK 0x00000100U
  3016. #define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_SHIFT 8U
  3017. #define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_WIDTH 1U
  3018. #define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_WOCLR 0U
  3019. #define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_WOSET 0U
  3020. #define LPDDR4__FSP1_FRC_VALID__REG DENALI_CTL_193
  3021. #define LPDDR4__FSP1_FRC_VALID__FLD LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID
  3022. #define LPDDR4__DENALI_CTL_193__FSP0_FRC_MASK 0x00030000U
  3023. #define LPDDR4__DENALI_CTL_193__FSP0_FRC_SHIFT 16U
  3024. #define LPDDR4__DENALI_CTL_193__FSP0_FRC_WIDTH 2U
  3025. #define LPDDR4__FSP0_FRC__REG DENALI_CTL_193
  3026. #define LPDDR4__FSP0_FRC__FLD LPDDR4__DENALI_CTL_193__FSP0_FRC
  3027. #define LPDDR4__DENALI_CTL_193__FSP1_FRC_MASK 0x03000000U
  3028. #define LPDDR4__DENALI_CTL_193__FSP1_FRC_SHIFT 24U
  3029. #define LPDDR4__DENALI_CTL_193__FSP1_FRC_WIDTH 2U
  3030. #define LPDDR4__FSP1_FRC__REG DENALI_CTL_193
  3031. #define LPDDR4__FSP1_FRC__FLD LPDDR4__DENALI_CTL_193__FSP1_FRC
  3032. #define LPDDR4__DENALI_CTL_194_READ_MASK 0x013F0300U
  3033. #define LPDDR4__DENALI_CTL_194_WRITE_MASK 0x013F0300U
  3034. #define LPDDR4__DENALI_CTL_194__BIST_GO_MASK 0x00000001U
  3035. #define LPDDR4__DENALI_CTL_194__BIST_GO_SHIFT 0U
  3036. #define LPDDR4__DENALI_CTL_194__BIST_GO_WIDTH 1U
  3037. #define LPDDR4__DENALI_CTL_194__BIST_GO_WOCLR 0U
  3038. #define LPDDR4__DENALI_CTL_194__BIST_GO_WOSET 0U
  3039. #define LPDDR4__BIST_GO__REG DENALI_CTL_194
  3040. #define LPDDR4__BIST_GO__FLD LPDDR4__DENALI_CTL_194__BIST_GO
  3041. #define LPDDR4__DENALI_CTL_194__BIST_RESULT_MASK 0x00000300U
  3042. #define LPDDR4__DENALI_CTL_194__BIST_RESULT_SHIFT 8U
  3043. #define LPDDR4__DENALI_CTL_194__BIST_RESULT_WIDTH 2U
  3044. #define LPDDR4__BIST_RESULT__REG DENALI_CTL_194
  3045. #define LPDDR4__BIST_RESULT__FLD LPDDR4__DENALI_CTL_194__BIST_RESULT
  3046. #define LPDDR4__DENALI_CTL_194__ADDR_SPACE_MASK 0x003F0000U
  3047. #define LPDDR4__DENALI_CTL_194__ADDR_SPACE_SHIFT 16U
  3048. #define LPDDR4__DENALI_CTL_194__ADDR_SPACE_WIDTH 6U
  3049. #define LPDDR4__ADDR_SPACE__REG DENALI_CTL_194
  3050. #define LPDDR4__ADDR_SPACE__FLD LPDDR4__DENALI_CTL_194__ADDR_SPACE
  3051. #define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_MASK 0x01000000U
  3052. #define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_SHIFT 24U
  3053. #define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_WIDTH 1U
  3054. #define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_WOCLR 0U
  3055. #define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_WOSET 0U
  3056. #define LPDDR4__BIST_DATA_CHECK__REG DENALI_CTL_194
  3057. #define LPDDR4__BIST_DATA_CHECK__FLD LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK
  3058. #define LPDDR4__DENALI_CTL_195_READ_MASK 0x00000001U
  3059. #define LPDDR4__DENALI_CTL_195_WRITE_MASK 0x00000001U
  3060. #define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_MASK 0x00000001U
  3061. #define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_SHIFT 0U
  3062. #define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_WIDTH 1U
  3063. #define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_WOCLR 0U
  3064. #define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_WOSET 0U
  3065. #define LPDDR4__BIST_ADDR_CHECK__REG DENALI_CTL_195
  3066. #define LPDDR4__BIST_ADDR_CHECK__FLD LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK
  3067. #define LPDDR4__DENALI_CTL_196_READ_MASK 0xFFFFFFFFU
  3068. #define LPDDR4__DENALI_CTL_196_WRITE_MASK 0xFFFFFFFFU
  3069. #define LPDDR4__DENALI_CTL_196__BIST_START_ADDRESS_0_MASK 0xFFFFFFFFU
  3070. #define LPDDR4__DENALI_CTL_196__BIST_START_ADDRESS_0_SHIFT 0U
  3071. #define LPDDR4__DENALI_CTL_196__BIST_START_ADDRESS_0_WIDTH 32U
  3072. #define LPDDR4__BIST_START_ADDRESS_0__REG DENALI_CTL_196
  3073. #define LPDDR4__BIST_START_ADDRESS_0__FLD LPDDR4__DENALI_CTL_196__BIST_START_ADDRESS_0
  3074. #define LPDDR4__DENALI_CTL_197_READ_MASK 0x00000007U
  3075. #define LPDDR4__DENALI_CTL_197_WRITE_MASK 0x00000007U
  3076. #define LPDDR4__DENALI_CTL_197__BIST_START_ADDRESS_1_MASK 0x00000007U
  3077. #define LPDDR4__DENALI_CTL_197__BIST_START_ADDRESS_1_SHIFT 0U
  3078. #define LPDDR4__DENALI_CTL_197__BIST_START_ADDRESS_1_WIDTH 3U
  3079. #define LPDDR4__BIST_START_ADDRESS_1__REG DENALI_CTL_197
  3080. #define LPDDR4__BIST_START_ADDRESS_1__FLD LPDDR4__DENALI_CTL_197__BIST_START_ADDRESS_1
  3081. #define LPDDR4__DENALI_CTL_198_READ_MASK 0xFFFFFFFFU
  3082. #define LPDDR4__DENALI_CTL_198_WRITE_MASK 0xFFFFFFFFU
  3083. #define LPDDR4__DENALI_CTL_198__BIST_DATA_MASK_0_MASK 0xFFFFFFFFU
  3084. #define LPDDR4__DENALI_CTL_198__BIST_DATA_MASK_0_SHIFT 0U
  3085. #define LPDDR4__DENALI_CTL_198__BIST_DATA_MASK_0_WIDTH 32U
  3086. #define LPDDR4__BIST_DATA_MASK_0__REG DENALI_CTL_198
  3087. #define LPDDR4__BIST_DATA_MASK_0__FLD LPDDR4__DENALI_CTL_198__BIST_DATA_MASK_0
  3088. #define LPDDR4__DENALI_CTL_199_READ_MASK 0xFFFFFFFFU
  3089. #define LPDDR4__DENALI_CTL_199_WRITE_MASK 0xFFFFFFFFU
  3090. #define LPDDR4__DENALI_CTL_199__BIST_DATA_MASK_1_MASK 0xFFFFFFFFU
  3091. #define LPDDR4__DENALI_CTL_199__BIST_DATA_MASK_1_SHIFT 0U
  3092. #define LPDDR4__DENALI_CTL_199__BIST_DATA_MASK_1_WIDTH 32U
  3093. #define LPDDR4__BIST_DATA_MASK_1__REG DENALI_CTL_199
  3094. #define LPDDR4__BIST_DATA_MASK_1__FLD LPDDR4__DENALI_CTL_199__BIST_DATA_MASK_1
  3095. #define LPDDR4__DENALI_CTL_200_READ_MASK 0x00000007U
  3096. #define LPDDR4__DENALI_CTL_200_WRITE_MASK 0x00000007U
  3097. #define LPDDR4__DENALI_CTL_200__BIST_TEST_MODE_MASK 0x00000007U
  3098. #define LPDDR4__DENALI_CTL_200__BIST_TEST_MODE_SHIFT 0U
  3099. #define LPDDR4__DENALI_CTL_200__BIST_TEST_MODE_WIDTH 3U
  3100. #define LPDDR4__BIST_TEST_MODE__REG DENALI_CTL_200
  3101. #define LPDDR4__BIST_TEST_MODE__FLD LPDDR4__DENALI_CTL_200__BIST_TEST_MODE
  3102. #define LPDDR4__DENALI_CTL_201_READ_MASK 0xFFFFFFFFU
  3103. #define LPDDR4__DENALI_CTL_201_WRITE_MASK 0xFFFFFFFFU
  3104. #define LPDDR4__DENALI_CTL_201__BIST_DATA_PATTERN_0_MASK 0xFFFFFFFFU
  3105. #define LPDDR4__DENALI_CTL_201__BIST_DATA_PATTERN_0_SHIFT 0U
  3106. #define LPDDR4__DENALI_CTL_201__BIST_DATA_PATTERN_0_WIDTH 32U
  3107. #define LPDDR4__BIST_DATA_PATTERN_0__REG DENALI_CTL_201
  3108. #define LPDDR4__BIST_DATA_PATTERN_0__FLD LPDDR4__DENALI_CTL_201__BIST_DATA_PATTERN_0
  3109. #define LPDDR4__DENALI_CTL_202_READ_MASK 0xFFFFFFFFU
  3110. #define LPDDR4__DENALI_CTL_202_WRITE_MASK 0xFFFFFFFFU
  3111. #define LPDDR4__DENALI_CTL_202__BIST_DATA_PATTERN_1_MASK 0xFFFFFFFFU
  3112. #define LPDDR4__DENALI_CTL_202__BIST_DATA_PATTERN_1_SHIFT 0U
  3113. #define LPDDR4__DENALI_CTL_202__BIST_DATA_PATTERN_1_WIDTH 32U
  3114. #define LPDDR4__BIST_DATA_PATTERN_1__REG DENALI_CTL_202
  3115. #define LPDDR4__BIST_DATA_PATTERN_1__FLD LPDDR4__DENALI_CTL_202__BIST_DATA_PATTERN_1
  3116. #define LPDDR4__DENALI_CTL_203_READ_MASK 0xFFFFFFFFU
  3117. #define LPDDR4__DENALI_CTL_203_WRITE_MASK 0xFFFFFFFFU
  3118. #define LPDDR4__DENALI_CTL_203__BIST_DATA_PATTERN_2_MASK 0xFFFFFFFFU
  3119. #define LPDDR4__DENALI_CTL_203__BIST_DATA_PATTERN_2_SHIFT 0U
  3120. #define LPDDR4__DENALI_CTL_203__BIST_DATA_PATTERN_2_WIDTH 32U
  3121. #define LPDDR4__BIST_DATA_PATTERN_2__REG DENALI_CTL_203
  3122. #define LPDDR4__BIST_DATA_PATTERN_2__FLD LPDDR4__DENALI_CTL_203__BIST_DATA_PATTERN_2
  3123. #define LPDDR4__DENALI_CTL_204_READ_MASK 0xFFFFFFFFU
  3124. #define LPDDR4__DENALI_CTL_204_WRITE_MASK 0xFFFFFFFFU
  3125. #define LPDDR4__DENALI_CTL_204__BIST_DATA_PATTERN_3_MASK 0xFFFFFFFFU
  3126. #define LPDDR4__DENALI_CTL_204__BIST_DATA_PATTERN_3_SHIFT 0U
  3127. #define LPDDR4__DENALI_CTL_204__BIST_DATA_PATTERN_3_WIDTH 32U
  3128. #define LPDDR4__BIST_DATA_PATTERN_3__REG DENALI_CTL_204
  3129. #define LPDDR4__BIST_DATA_PATTERN_3__FLD LPDDR4__DENALI_CTL_204__BIST_DATA_PATTERN_3
  3130. #define LPDDR4__DENALI_CTL_205_READ_MASK 0x0FFF0100U
  3131. #define LPDDR4__DENALI_CTL_205_WRITE_MASK 0x0FFF0100U
  3132. #define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_MASK 0x00000001U
  3133. #define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_SHIFT 0U
  3134. #define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_WIDTH 1U
  3135. #define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_WOCLR 0U
  3136. #define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_WOSET 0U
  3137. #define LPDDR4__BIST_RET_STATE_EXIT__REG DENALI_CTL_205
  3138. #define LPDDR4__BIST_RET_STATE_EXIT__FLD LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT
  3139. #define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_MASK 0x00000100U
  3140. #define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_SHIFT 8U
  3141. #define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_WIDTH 1U
  3142. #define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_WOCLR 0U
  3143. #define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_WOSET 0U
  3144. #define LPDDR4__BIST_RET_STATE__REG DENALI_CTL_205
  3145. #define LPDDR4__BIST_RET_STATE__FLD LPDDR4__DENALI_CTL_205__BIST_RET_STATE
  3146. #define LPDDR4__DENALI_CTL_205__BIST_ERR_STOP_MASK 0x0FFF0000U
  3147. #define LPDDR4__DENALI_CTL_205__BIST_ERR_STOP_SHIFT 16U
  3148. #define LPDDR4__DENALI_CTL_205__BIST_ERR_STOP_WIDTH 12U
  3149. #define LPDDR4__BIST_ERR_STOP__REG DENALI_CTL_205
  3150. #define LPDDR4__BIST_ERR_STOP__FLD LPDDR4__DENALI_CTL_205__BIST_ERR_STOP
  3151. #define LPDDR4__DENALI_CTL_206_READ_MASK 0x07030FFFU
  3152. #define LPDDR4__DENALI_CTL_206_WRITE_MASK 0x07030FFFU
  3153. #define LPDDR4__DENALI_CTL_206__BIST_ERR_COUNT_MASK 0x00000FFFU
  3154. #define LPDDR4__DENALI_CTL_206__BIST_ERR_COUNT_SHIFT 0U
  3155. #define LPDDR4__DENALI_CTL_206__BIST_ERR_COUNT_WIDTH 12U
  3156. #define LPDDR4__BIST_ERR_COUNT__REG DENALI_CTL_206
  3157. #define LPDDR4__BIST_ERR_COUNT__FLD LPDDR4__DENALI_CTL_206__BIST_ERR_COUNT
  3158. #define LPDDR4__DENALI_CTL_206__ECC_ENABLE_MASK 0x00030000U
  3159. #define LPDDR4__DENALI_CTL_206__ECC_ENABLE_SHIFT 16U
  3160. #define LPDDR4__DENALI_CTL_206__ECC_ENABLE_WIDTH 2U
  3161. #define LPDDR4__ECC_ENABLE__REG DENALI_CTL_206
  3162. #define LPDDR4__ECC_ENABLE__FLD LPDDR4__DENALI_CTL_206__ECC_ENABLE
  3163. #define LPDDR4__DENALI_CTL_206__INLINE_ECC_BANK_OFFSET_MASK 0x07000000U
  3164. #define LPDDR4__DENALI_CTL_206__INLINE_ECC_BANK_OFFSET_SHIFT 24U
  3165. #define LPDDR4__DENALI_CTL_206__INLINE_ECC_BANK_OFFSET_WIDTH 3U
  3166. #define LPDDR4__INLINE_ECC_BANK_OFFSET__REG DENALI_CTL_206
  3167. #define LPDDR4__INLINE_ECC_BANK_OFFSET__FLD LPDDR4__DENALI_CTL_206__INLINE_ECC_BANK_OFFSET
  3168. #define LPDDR4__DENALI_CTL_207_READ_MASK 0x010F0101U
  3169. #define LPDDR4__DENALI_CTL_207_WRITE_MASK 0x010F0101U
  3170. #define LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN_MASK 0x00000001U
  3171. #define LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN_SHIFT 0U
  3172. #define LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN_WIDTH 1U
  3173. #define LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN_WOCLR 0U
  3174. #define LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN_WOSET 0U
  3175. #define LPDDR4__ECC_READ_CACHING_EN__REG DENALI_CTL_207
  3176. #define LPDDR4__ECC_READ_CACHING_EN__FLD LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN
  3177. #define LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN_MASK 0x00000100U
  3178. #define LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN_SHIFT 8U
  3179. #define LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN_WIDTH 1U
  3180. #define LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN_WOCLR 0U
  3181. #define LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN_WOSET 0U
  3182. #define LPDDR4__ECC_WRITE_COMBINING_EN__REG DENALI_CTL_207
  3183. #define LPDDR4__ECC_WRITE_COMBINING_EN__FLD LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN
  3184. #define LPDDR4__DENALI_CTL_207__MC_RESERVED21_MASK 0x000F0000U
  3185. #define LPDDR4__DENALI_CTL_207__MC_RESERVED21_SHIFT 16U
  3186. #define LPDDR4__DENALI_CTL_207__MC_RESERVED21_WIDTH 4U
  3187. #define LPDDR4__MC_RESERVED21__REG DENALI_CTL_207
  3188. #define LPDDR4__MC_RESERVED21__FLD LPDDR4__DENALI_CTL_207__MC_RESERVED21
  3189. #define LPDDR4__DENALI_CTL_207__MC_RESERVED22_MASK 0x01000000U
  3190. #define LPDDR4__DENALI_CTL_207__MC_RESERVED22_SHIFT 24U
  3191. #define LPDDR4__DENALI_CTL_207__MC_RESERVED22_WIDTH 1U
  3192. #define LPDDR4__DENALI_CTL_207__MC_RESERVED22_WOCLR 0U
  3193. #define LPDDR4__DENALI_CTL_207__MC_RESERVED22_WOSET 0U
  3194. #define LPDDR4__MC_RESERVED22__REG DENALI_CTL_207
  3195. #define LPDDR4__MC_RESERVED22__FLD LPDDR4__DENALI_CTL_207__MC_RESERVED22
  3196. #define LPDDR4__DENALI_CTL_208_READ_MASK 0x01FFFF01U
  3197. #define LPDDR4__DENALI_CTL_208_WRITE_MASK 0x01FFFF01U
  3198. #define LPDDR4__DENALI_CTL_208__FWC_MASK 0x00000001U
  3199. #define LPDDR4__DENALI_CTL_208__FWC_SHIFT 0U
  3200. #define LPDDR4__DENALI_CTL_208__FWC_WIDTH 1U
  3201. #define LPDDR4__DENALI_CTL_208__FWC_WOCLR 0U
  3202. #define LPDDR4__DENALI_CTL_208__FWC_WOSET 0U
  3203. #define LPDDR4__FWC__REG DENALI_CTL_208
  3204. #define LPDDR4__FWC__FLD LPDDR4__DENALI_CTL_208__FWC
  3205. #define LPDDR4__DENALI_CTL_208__XOR_CHECK_BITS_MASK 0x00FFFF00U
  3206. #define LPDDR4__DENALI_CTL_208__XOR_CHECK_BITS_SHIFT 8U
  3207. #define LPDDR4__DENALI_CTL_208__XOR_CHECK_BITS_WIDTH 16U
  3208. #define LPDDR4__XOR_CHECK_BITS__REG DENALI_CTL_208
  3209. #define LPDDR4__XOR_CHECK_BITS__FLD LPDDR4__DENALI_CTL_208__XOR_CHECK_BITS
  3210. #define LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN_MASK 0x01000000U
  3211. #define LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN_SHIFT 24U
  3212. #define LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN_WIDTH 1U
  3213. #define LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN_WOCLR 0U
  3214. #define LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN_WOSET 0U
  3215. #define LPDDR4__ECC_WRITEBACK_EN__REG DENALI_CTL_208
  3216. #define LPDDR4__ECC_WRITEBACK_EN__FLD LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN
  3217. #define LPDDR4__DENALI_CTL_209_READ_MASK 0x00000001U
  3218. #define LPDDR4__DENALI_CTL_209_WRITE_MASK 0x00000001U
  3219. #define LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR_MASK 0x00000001U
  3220. #define LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR_SHIFT 0U
  3221. #define LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR_WIDTH 1U
  3222. #define LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR_WOCLR 0U
  3223. #define LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR_WOSET 0U
  3224. #define LPDDR4__ECC_DISABLE_W_UC_ERR__REG DENALI_CTL_209
  3225. #define LPDDR4__ECC_DISABLE_W_UC_ERR__FLD LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR
  3226. #define LPDDR4__DENALI_CTL_210_READ_MASK 0xFFFFFFFFU
  3227. #define LPDDR4__DENALI_CTL_210_WRITE_MASK 0xFFFFFFFFU
  3228. #define LPDDR4__DENALI_CTL_210__ECC_U_ADDR_0_MASK 0xFFFFFFFFU
  3229. #define LPDDR4__DENALI_CTL_210__ECC_U_ADDR_0_SHIFT 0U
  3230. #define LPDDR4__DENALI_CTL_210__ECC_U_ADDR_0_WIDTH 32U
  3231. #define LPDDR4__ECC_U_ADDR_0__REG DENALI_CTL_210
  3232. #define LPDDR4__ECC_U_ADDR_0__FLD LPDDR4__DENALI_CTL_210__ECC_U_ADDR_0
  3233. #define LPDDR4__DENALI_CTL_211_READ_MASK 0x0000FF07U
  3234. #define LPDDR4__DENALI_CTL_211_WRITE_MASK 0x0000FF07U
  3235. #define LPDDR4__DENALI_CTL_211__ECC_U_ADDR_1_MASK 0x00000007U
  3236. #define LPDDR4__DENALI_CTL_211__ECC_U_ADDR_1_SHIFT 0U
  3237. #define LPDDR4__DENALI_CTL_211__ECC_U_ADDR_1_WIDTH 3U
  3238. #define LPDDR4__ECC_U_ADDR_1__REG DENALI_CTL_211
  3239. #define LPDDR4__ECC_U_ADDR_1__FLD LPDDR4__DENALI_CTL_211__ECC_U_ADDR_1
  3240. #define LPDDR4__DENALI_CTL_211__ECC_U_SYND_MASK 0x0000FF00U
  3241. #define LPDDR4__DENALI_CTL_211__ECC_U_SYND_SHIFT 8U
  3242. #define LPDDR4__DENALI_CTL_211__ECC_U_SYND_WIDTH 8U
  3243. #define LPDDR4__ECC_U_SYND__REG DENALI_CTL_211
  3244. #define LPDDR4__ECC_U_SYND__FLD LPDDR4__DENALI_CTL_211__ECC_U_SYND
  3245. #define LPDDR4__DENALI_CTL_212_READ_MASK 0xFFFFFFFFU
  3246. #define LPDDR4__DENALI_CTL_212_WRITE_MASK 0xFFFFFFFFU
  3247. #define LPDDR4__DENALI_CTL_212__ECC_U_DATA_0_MASK 0xFFFFFFFFU
  3248. #define LPDDR4__DENALI_CTL_212__ECC_U_DATA_0_SHIFT 0U
  3249. #define LPDDR4__DENALI_CTL_212__ECC_U_DATA_0_WIDTH 32U
  3250. #define LPDDR4__ECC_U_DATA_0__REG DENALI_CTL_212
  3251. #define LPDDR4__ECC_U_DATA_0__FLD LPDDR4__DENALI_CTL_212__ECC_U_DATA_0
  3252. #define LPDDR4__DENALI_CTL_213_READ_MASK 0xFFFFFFFFU
  3253. #define LPDDR4__DENALI_CTL_213_WRITE_MASK 0xFFFFFFFFU
  3254. #define LPDDR4__DENALI_CTL_213__ECC_U_DATA_1_MASK 0xFFFFFFFFU
  3255. #define LPDDR4__DENALI_CTL_213__ECC_U_DATA_1_SHIFT 0U
  3256. #define LPDDR4__DENALI_CTL_213__ECC_U_DATA_1_WIDTH 32U
  3257. #define LPDDR4__ECC_U_DATA_1__REG DENALI_CTL_213
  3258. #define LPDDR4__ECC_U_DATA_1__FLD LPDDR4__DENALI_CTL_213__ECC_U_DATA_1
  3259. #define LPDDR4__DENALI_CTL_214_READ_MASK 0xFFFFFFFFU
  3260. #define LPDDR4__DENALI_CTL_214_WRITE_MASK 0xFFFFFFFFU
  3261. #define LPDDR4__DENALI_CTL_214__ECC_C_ADDR_0_MASK 0xFFFFFFFFU
  3262. #define LPDDR4__DENALI_CTL_214__ECC_C_ADDR_0_SHIFT 0U
  3263. #define LPDDR4__DENALI_CTL_214__ECC_C_ADDR_0_WIDTH 32U
  3264. #define LPDDR4__ECC_C_ADDR_0__REG DENALI_CTL_214
  3265. #define LPDDR4__ECC_C_ADDR_0__FLD LPDDR4__DENALI_CTL_214__ECC_C_ADDR_0
  3266. #define LPDDR4__DENALI_CTL_215_READ_MASK 0x0000FF07U
  3267. #define LPDDR4__DENALI_CTL_215_WRITE_MASK 0x0000FF07U
  3268. #define LPDDR4__DENALI_CTL_215__ECC_C_ADDR_1_MASK 0x00000007U
  3269. #define LPDDR4__DENALI_CTL_215__ECC_C_ADDR_1_SHIFT 0U
  3270. #define LPDDR4__DENALI_CTL_215__ECC_C_ADDR_1_WIDTH 3U
  3271. #define LPDDR4__ECC_C_ADDR_1__REG DENALI_CTL_215
  3272. #define LPDDR4__ECC_C_ADDR_1__FLD LPDDR4__DENALI_CTL_215__ECC_C_ADDR_1
  3273. #define LPDDR4__DENALI_CTL_215__ECC_C_SYND_MASK 0x0000FF00U
  3274. #define LPDDR4__DENALI_CTL_215__ECC_C_SYND_SHIFT 8U
  3275. #define LPDDR4__DENALI_CTL_215__ECC_C_SYND_WIDTH 8U
  3276. #define LPDDR4__ECC_C_SYND__REG DENALI_CTL_215
  3277. #define LPDDR4__ECC_C_SYND__FLD LPDDR4__DENALI_CTL_215__ECC_C_SYND
  3278. #define LPDDR4__DENALI_CTL_216_READ_MASK 0xFFFFFFFFU
  3279. #define LPDDR4__DENALI_CTL_216_WRITE_MASK 0xFFFFFFFFU
  3280. #define LPDDR4__DENALI_CTL_216__ECC_C_DATA_0_MASK 0xFFFFFFFFU
  3281. #define LPDDR4__DENALI_CTL_216__ECC_C_DATA_0_SHIFT 0U
  3282. #define LPDDR4__DENALI_CTL_216__ECC_C_DATA_0_WIDTH 32U
  3283. #define LPDDR4__ECC_C_DATA_0__REG DENALI_CTL_216
  3284. #define LPDDR4__ECC_C_DATA_0__FLD LPDDR4__DENALI_CTL_216__ECC_C_DATA_0
  3285. #define LPDDR4__DENALI_CTL_217_READ_MASK 0xFFFFFFFFU
  3286. #define LPDDR4__DENALI_CTL_217_WRITE_MASK 0xFFFFFFFFU
  3287. #define LPDDR4__DENALI_CTL_217__ECC_C_DATA_1_MASK 0xFFFFFFFFU
  3288. #define LPDDR4__DENALI_CTL_217__ECC_C_DATA_1_SHIFT 0U
  3289. #define LPDDR4__DENALI_CTL_217__ECC_C_DATA_1_WIDTH 32U
  3290. #define LPDDR4__ECC_C_DATA_1__REG DENALI_CTL_217
  3291. #define LPDDR4__ECC_C_DATA_1__FLD LPDDR4__DENALI_CTL_217__ECC_C_DATA_1
  3292. #define LPDDR4__DENALI_CTL_218_READ_MASK 0x7FFF3F3FU
  3293. #define LPDDR4__DENALI_CTL_218_WRITE_MASK 0x7FFF3F3FU
  3294. #define LPDDR4__DENALI_CTL_218__ECC_U_ID_MASK 0x0000003FU
  3295. #define LPDDR4__DENALI_CTL_218__ECC_U_ID_SHIFT 0U
  3296. #define LPDDR4__DENALI_CTL_218__ECC_U_ID_WIDTH 6U
  3297. #define LPDDR4__ECC_U_ID__REG DENALI_CTL_218
  3298. #define LPDDR4__ECC_U_ID__FLD LPDDR4__DENALI_CTL_218__ECC_U_ID
  3299. #define LPDDR4__DENALI_CTL_218__ECC_C_ID_MASK 0x00003F00U
  3300. #define LPDDR4__DENALI_CTL_218__ECC_C_ID_SHIFT 8U
  3301. #define LPDDR4__DENALI_CTL_218__ECC_C_ID_WIDTH 6U
  3302. #define LPDDR4__ECC_C_ID__REG DENALI_CTL_218
  3303. #define LPDDR4__ECC_C_ID__FLD LPDDR4__DENALI_CTL_218__ECC_C_ID
  3304. #define LPDDR4__DENALI_CTL_218__NON_ECC_REGION_START_ADDR_0_MASK 0x7FFF0000U
  3305. #define LPDDR4__DENALI_CTL_218__NON_ECC_REGION_START_ADDR_0_SHIFT 16U
  3306. #define LPDDR4__DENALI_CTL_218__NON_ECC_REGION_START_ADDR_0_WIDTH 15U
  3307. #define LPDDR4__NON_ECC_REGION_START_ADDR_0__REG DENALI_CTL_218
  3308. #define LPDDR4__NON_ECC_REGION_START_ADDR_0__FLD LPDDR4__DENALI_CTL_218__NON_ECC_REGION_START_ADDR_0
  3309. #define LPDDR4__DENALI_CTL_219_READ_MASK 0x7FFF7FFFU
  3310. #define LPDDR4__DENALI_CTL_219_WRITE_MASK 0x7FFF7FFFU
  3311. #define LPDDR4__DENALI_CTL_219__NON_ECC_REGION_END_ADDR_0_MASK 0x00007FFFU
  3312. #define LPDDR4__DENALI_CTL_219__NON_ECC_REGION_END_ADDR_0_SHIFT 0U
  3313. #define LPDDR4__DENALI_CTL_219__NON_ECC_REGION_END_ADDR_0_WIDTH 15U
  3314. #define LPDDR4__NON_ECC_REGION_END_ADDR_0__REG DENALI_CTL_219
  3315. #define LPDDR4__NON_ECC_REGION_END_ADDR_0__FLD LPDDR4__DENALI_CTL_219__NON_ECC_REGION_END_ADDR_0
  3316. #define LPDDR4__DENALI_CTL_219__NON_ECC_REGION_START_ADDR_1_MASK 0x7FFF0000U
  3317. #define LPDDR4__DENALI_CTL_219__NON_ECC_REGION_START_ADDR_1_SHIFT 16U
  3318. #define LPDDR4__DENALI_CTL_219__NON_ECC_REGION_START_ADDR_1_WIDTH 15U
  3319. #define LPDDR4__NON_ECC_REGION_START_ADDR_1__REG DENALI_CTL_219
  3320. #define LPDDR4__NON_ECC_REGION_START_ADDR_1__FLD LPDDR4__DENALI_CTL_219__NON_ECC_REGION_START_ADDR_1
  3321. #define LPDDR4__DENALI_CTL_220_READ_MASK 0x7FFF7FFFU
  3322. #define LPDDR4__DENALI_CTL_220_WRITE_MASK 0x7FFF7FFFU
  3323. #define LPDDR4__DENALI_CTL_220__NON_ECC_REGION_END_ADDR_1_MASK 0x00007FFFU
  3324. #define LPDDR4__DENALI_CTL_220__NON_ECC_REGION_END_ADDR_1_SHIFT 0U
  3325. #define LPDDR4__DENALI_CTL_220__NON_ECC_REGION_END_ADDR_1_WIDTH 15U
  3326. #define LPDDR4__NON_ECC_REGION_END_ADDR_1__REG DENALI_CTL_220
  3327. #define LPDDR4__NON_ECC_REGION_END_ADDR_1__FLD LPDDR4__DENALI_CTL_220__NON_ECC_REGION_END_ADDR_1
  3328. #define LPDDR4__DENALI_CTL_220__NON_ECC_REGION_START_ADDR_2_MASK 0x7FFF0000U
  3329. #define LPDDR4__DENALI_CTL_220__NON_ECC_REGION_START_ADDR_2_SHIFT 16U
  3330. #define LPDDR4__DENALI_CTL_220__NON_ECC_REGION_START_ADDR_2_WIDTH 15U
  3331. #define LPDDR4__NON_ECC_REGION_START_ADDR_2__REG DENALI_CTL_220
  3332. #define LPDDR4__NON_ECC_REGION_START_ADDR_2__FLD LPDDR4__DENALI_CTL_220__NON_ECC_REGION_START_ADDR_2
  3333. #define LPDDR4__DENALI_CTL_221_READ_MASK 0x00077FFFU
  3334. #define LPDDR4__DENALI_CTL_221_WRITE_MASK 0x00077FFFU
  3335. #define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_END_ADDR_2_MASK 0x00007FFFU
  3336. #define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_END_ADDR_2_SHIFT 0U
  3337. #define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_END_ADDR_2_WIDTH 15U
  3338. #define LPDDR4__NON_ECC_REGION_END_ADDR_2__REG DENALI_CTL_221
  3339. #define LPDDR4__NON_ECC_REGION_END_ADDR_2__FLD LPDDR4__DENALI_CTL_221__NON_ECC_REGION_END_ADDR_2
  3340. #define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_ENABLE_MASK 0x00070000U
  3341. #define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_ENABLE_SHIFT 16U
  3342. #define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_ENABLE_WIDTH 3U
  3343. #define LPDDR4__NON_ECC_REGION_ENABLE__REG DENALI_CTL_221
  3344. #define LPDDR4__NON_ECC_REGION_ENABLE__FLD LPDDR4__DENALI_CTL_221__NON_ECC_REGION_ENABLE
  3345. #define LPDDR4__DENALI_CTL_221__ECC_SCRUB_START_MASK 0x01000000U
  3346. #define LPDDR4__DENALI_CTL_221__ECC_SCRUB_START_SHIFT 24U
  3347. #define LPDDR4__DENALI_CTL_221__ECC_SCRUB_START_WIDTH 1U
  3348. #define LPDDR4__DENALI_CTL_221__ECC_SCRUB_START_WOCLR 0U
  3349. #define LPDDR4__DENALI_CTL_221__ECC_SCRUB_START_WOSET 0U
  3350. #define LPDDR4__ECC_SCRUB_START__REG DENALI_CTL_221
  3351. #define LPDDR4__ECC_SCRUB_START__FLD LPDDR4__DENALI_CTL_221__ECC_SCRUB_START
  3352. #define LPDDR4__DENALI_CTL_222_READ_MASK 0x010FFF01U
  3353. #define LPDDR4__DENALI_CTL_222_WRITE_MASK 0x010FFF01U
  3354. #define LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS_MASK 0x00000001U
  3355. #define LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS_SHIFT 0U
  3356. #define LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS_WIDTH 1U
  3357. #define LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS_WOCLR 0U
  3358. #define LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS_WOSET 0U
  3359. #define LPDDR4__ECC_SCRUB_IN_PROGRESS__REG DENALI_CTL_222
  3360. #define LPDDR4__ECC_SCRUB_IN_PROGRESS__FLD LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS
  3361. #define LPDDR4__DENALI_CTL_222__ECC_SCRUB_LEN_MASK 0x000FFF00U
  3362. #define LPDDR4__DENALI_CTL_222__ECC_SCRUB_LEN_SHIFT 8U
  3363. #define LPDDR4__DENALI_CTL_222__ECC_SCRUB_LEN_WIDTH 12U
  3364. #define LPDDR4__ECC_SCRUB_LEN__REG DENALI_CTL_222
  3365. #define LPDDR4__ECC_SCRUB_LEN__FLD LPDDR4__DENALI_CTL_222__ECC_SCRUB_LEN
  3366. #define LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE_MASK 0x01000000U
  3367. #define LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE_SHIFT 24U
  3368. #define LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE_WIDTH 1U
  3369. #define LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE_WOCLR 0U
  3370. #define LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE_WOSET 0U
  3371. #define LPDDR4__ECC_SCRUB_MODE__REG DENALI_CTL_222
  3372. #define LPDDR4__ECC_SCRUB_MODE__FLD LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE
  3373. #define LPDDR4__DENALI_CTL_223_READ_MASK 0xFFFFFFFFU
  3374. #define LPDDR4__DENALI_CTL_223_WRITE_MASK 0xFFFFFFFFU
  3375. #define LPDDR4__DENALI_CTL_223__ECC_SCRUB_INTERVAL_MASK 0x0000FFFFU
  3376. #define LPDDR4__DENALI_CTL_223__ECC_SCRUB_INTERVAL_SHIFT 0U
  3377. #define LPDDR4__DENALI_CTL_223__ECC_SCRUB_INTERVAL_WIDTH 16U
  3378. #define LPDDR4__ECC_SCRUB_INTERVAL__REG DENALI_CTL_223
  3379. #define LPDDR4__ECC_SCRUB_INTERVAL__FLD LPDDR4__DENALI_CTL_223__ECC_SCRUB_INTERVAL
  3380. #define LPDDR4__DENALI_CTL_223__ECC_SCRUB_IDLE_CNT_MASK 0xFFFF0000U
  3381. #define LPDDR4__DENALI_CTL_223__ECC_SCRUB_IDLE_CNT_SHIFT 16U
  3382. #define LPDDR4__DENALI_CTL_223__ECC_SCRUB_IDLE_CNT_WIDTH 16U
  3383. #define LPDDR4__ECC_SCRUB_IDLE_CNT__REG DENALI_CTL_223
  3384. #define LPDDR4__ECC_SCRUB_IDLE_CNT__FLD LPDDR4__DENALI_CTL_223__ECC_SCRUB_IDLE_CNT
  3385. #define LPDDR4__DENALI_CTL_224_READ_MASK 0xFFFFFFFFU
  3386. #define LPDDR4__DENALI_CTL_224_WRITE_MASK 0xFFFFFFFFU
  3387. #define LPDDR4__DENALI_CTL_224__ECC_SCRUB_START_ADDR_0_MASK 0xFFFFFFFFU
  3388. #define LPDDR4__DENALI_CTL_224__ECC_SCRUB_START_ADDR_0_SHIFT 0U
  3389. #define LPDDR4__DENALI_CTL_224__ECC_SCRUB_START_ADDR_0_WIDTH 32U
  3390. #define LPDDR4__ECC_SCRUB_START_ADDR_0__REG DENALI_CTL_224
  3391. #define LPDDR4__ECC_SCRUB_START_ADDR_0__FLD LPDDR4__DENALI_CTL_224__ECC_SCRUB_START_ADDR_0
  3392. #define LPDDR4__DENALI_CTL_225_READ_MASK 0x00000007U
  3393. #define LPDDR4__DENALI_CTL_225_WRITE_MASK 0x00000007U
  3394. #define LPDDR4__DENALI_CTL_225__ECC_SCRUB_START_ADDR_1_MASK 0x00000007U
  3395. #define LPDDR4__DENALI_CTL_225__ECC_SCRUB_START_ADDR_1_SHIFT 0U
  3396. #define LPDDR4__DENALI_CTL_225__ECC_SCRUB_START_ADDR_1_WIDTH 3U
  3397. #define LPDDR4__ECC_SCRUB_START_ADDR_1__REG DENALI_CTL_225
  3398. #define LPDDR4__ECC_SCRUB_START_ADDR_1__FLD LPDDR4__DENALI_CTL_225__ECC_SCRUB_START_ADDR_1
  3399. #define LPDDR4__DENALI_CTL_226_READ_MASK 0xFFFFFFFFU
  3400. #define LPDDR4__DENALI_CTL_226_WRITE_MASK 0xFFFFFFFFU
  3401. #define LPDDR4__DENALI_CTL_226__ECC_SCRUB_END_ADDR_0_MASK 0xFFFFFFFFU
  3402. #define LPDDR4__DENALI_CTL_226__ECC_SCRUB_END_ADDR_0_SHIFT 0U
  3403. #define LPDDR4__DENALI_CTL_226__ECC_SCRUB_END_ADDR_0_WIDTH 32U
  3404. #define LPDDR4__ECC_SCRUB_END_ADDR_0__REG DENALI_CTL_226
  3405. #define LPDDR4__ECC_SCRUB_END_ADDR_0__FLD LPDDR4__DENALI_CTL_226__ECC_SCRUB_END_ADDR_0
  3406. #define LPDDR4__DENALI_CTL_227_READ_MASK 0x1F1F1F07U
  3407. #define LPDDR4__DENALI_CTL_227_WRITE_MASK 0x1F1F1F07U
  3408. #define LPDDR4__DENALI_CTL_227__ECC_SCRUB_END_ADDR_1_MASK 0x00000007U
  3409. #define LPDDR4__DENALI_CTL_227__ECC_SCRUB_END_ADDR_1_SHIFT 0U
  3410. #define LPDDR4__DENALI_CTL_227__ECC_SCRUB_END_ADDR_1_WIDTH 3U
  3411. #define LPDDR4__ECC_SCRUB_END_ADDR_1__REG DENALI_CTL_227
  3412. #define LPDDR4__ECC_SCRUB_END_ADDR_1__FLD LPDDR4__DENALI_CTL_227__ECC_SCRUB_END_ADDR_1
  3413. #define LPDDR4__DENALI_CTL_227__LONG_COUNT_MASK_MASK 0x00001F00U
  3414. #define LPDDR4__DENALI_CTL_227__LONG_COUNT_MASK_SHIFT 8U
  3415. #define LPDDR4__DENALI_CTL_227__LONG_COUNT_MASK_WIDTH 5U
  3416. #define LPDDR4__LONG_COUNT_MASK__REG DENALI_CTL_227
  3417. #define LPDDR4__LONG_COUNT_MASK__FLD LPDDR4__DENALI_CTL_227__LONG_COUNT_MASK
  3418. #define LPDDR4__DENALI_CTL_227__AREF_NORM_THRESHOLD_MASK 0x001F0000U
  3419. #define LPDDR4__DENALI_CTL_227__AREF_NORM_THRESHOLD_SHIFT 16U
  3420. #define LPDDR4__DENALI_CTL_227__AREF_NORM_THRESHOLD_WIDTH 5U
  3421. #define LPDDR4__AREF_NORM_THRESHOLD__REG DENALI_CTL_227
  3422. #define LPDDR4__AREF_NORM_THRESHOLD__FLD LPDDR4__DENALI_CTL_227__AREF_NORM_THRESHOLD
  3423. #define LPDDR4__DENALI_CTL_227__AREF_HIGH_THRESHOLD_MASK 0x1F000000U
  3424. #define LPDDR4__DENALI_CTL_227__AREF_HIGH_THRESHOLD_SHIFT 24U
  3425. #define LPDDR4__DENALI_CTL_227__AREF_HIGH_THRESHOLD_WIDTH 5U
  3426. #define LPDDR4__AREF_HIGH_THRESHOLD__REG DENALI_CTL_227
  3427. #define LPDDR4__AREF_HIGH_THRESHOLD__FLD LPDDR4__DENALI_CTL_227__AREF_HIGH_THRESHOLD
  3428. #define LPDDR4__DENALI_CTL_228_READ_MASK 0x000F1F1FU
  3429. #define LPDDR4__DENALI_CTL_228_WRITE_MASK 0x000F1F1FU
  3430. #define LPDDR4__DENALI_CTL_228__AREF_MAX_DEFICIT_MASK 0x0000001FU
  3431. #define LPDDR4__DENALI_CTL_228__AREF_MAX_DEFICIT_SHIFT 0U
  3432. #define LPDDR4__DENALI_CTL_228__AREF_MAX_DEFICIT_WIDTH 5U
  3433. #define LPDDR4__AREF_MAX_DEFICIT__REG DENALI_CTL_228
  3434. #define LPDDR4__AREF_MAX_DEFICIT__FLD LPDDR4__DENALI_CTL_228__AREF_MAX_DEFICIT
  3435. #define LPDDR4__DENALI_CTL_228__AREF_MAX_CREDIT_MASK 0x00001F00U
  3436. #define LPDDR4__DENALI_CTL_228__AREF_MAX_CREDIT_SHIFT 8U
  3437. #define LPDDR4__DENALI_CTL_228__AREF_MAX_CREDIT_WIDTH 5U
  3438. #define LPDDR4__AREF_MAX_CREDIT__REG DENALI_CTL_228
  3439. #define LPDDR4__AREF_MAX_CREDIT__FLD LPDDR4__DENALI_CTL_228__AREF_MAX_CREDIT
  3440. #define LPDDR4__DENALI_CTL_228__AREF_CMD_MAX_PER_TREFI_MASK 0x000F0000U
  3441. #define LPDDR4__DENALI_CTL_228__AREF_CMD_MAX_PER_TREFI_SHIFT 16U
  3442. #define LPDDR4__DENALI_CTL_228__AREF_CMD_MAX_PER_TREFI_WIDTH 4U
  3443. #define LPDDR4__AREF_CMD_MAX_PER_TREFI__REG DENALI_CTL_228
  3444. #define LPDDR4__AREF_CMD_MAX_PER_TREFI__FLD LPDDR4__DENALI_CTL_228__AREF_CMD_MAX_PER_TREFI
  3445. #define LPDDR4__DENALI_CTL_229_READ_MASK 0xFFFFFFFFU
  3446. #define LPDDR4__DENALI_CTL_229_WRITE_MASK 0xFFFFFFFFU
  3447. #define LPDDR4__DENALI_CTL_229__ZQ_CALSTART_NORM_THRESHOLD_F0_MASK 0x0000FFFFU
  3448. #define LPDDR4__DENALI_CTL_229__ZQ_CALSTART_NORM_THRESHOLD_F0_SHIFT 0U
  3449. #define LPDDR4__DENALI_CTL_229__ZQ_CALSTART_NORM_THRESHOLD_F0_WIDTH 16U
  3450. #define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F0__REG DENALI_CTL_229
  3451. #define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_229__ZQ_CALSTART_NORM_THRESHOLD_F0
  3452. #define LPDDR4__DENALI_CTL_229__ZQ_CALSTART_HIGH_THRESHOLD_F0_MASK 0xFFFF0000U
  3453. #define LPDDR4__DENALI_CTL_229__ZQ_CALSTART_HIGH_THRESHOLD_F0_SHIFT 16U
  3454. #define LPDDR4__DENALI_CTL_229__ZQ_CALSTART_HIGH_THRESHOLD_F0_WIDTH 16U
  3455. #define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F0__REG DENALI_CTL_229
  3456. #define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_229__ZQ_CALSTART_HIGH_THRESHOLD_F0
  3457. #define LPDDR4__DENALI_CTL_230_READ_MASK 0xFFFFFFFFU
  3458. #define LPDDR4__DENALI_CTL_230_WRITE_MASK 0xFFFFFFFFU
  3459. #define LPDDR4__DENALI_CTL_230__ZQ_CALLATCH_HIGH_THRESHOLD_F0_MASK 0x0000FFFFU
  3460. #define LPDDR4__DENALI_CTL_230__ZQ_CALLATCH_HIGH_THRESHOLD_F0_SHIFT 0U
  3461. #define LPDDR4__DENALI_CTL_230__ZQ_CALLATCH_HIGH_THRESHOLD_F0_WIDTH 16U
  3462. #define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F0__REG DENALI_CTL_230
  3463. #define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_230__ZQ_CALLATCH_HIGH_THRESHOLD_F0
  3464. #define LPDDR4__DENALI_CTL_230__ZQ_CS_NORM_THRESHOLD_F0_MASK 0xFFFF0000U
  3465. #define LPDDR4__DENALI_CTL_230__ZQ_CS_NORM_THRESHOLD_F0_SHIFT 16U
  3466. #define LPDDR4__DENALI_CTL_230__ZQ_CS_NORM_THRESHOLD_F0_WIDTH 16U
  3467. #define LPDDR4__ZQ_CS_NORM_THRESHOLD_F0__REG DENALI_CTL_230
  3468. #define LPDDR4__ZQ_CS_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_230__ZQ_CS_NORM_THRESHOLD_F0
  3469. #define LPDDR4__DENALI_CTL_231_READ_MASK 0xFFFFFFFFU
  3470. #define LPDDR4__DENALI_CTL_231_WRITE_MASK 0xFFFFFFFFU
  3471. #define LPDDR4__DENALI_CTL_231__ZQ_CS_HIGH_THRESHOLD_F0_MASK 0x0000FFFFU
  3472. #define LPDDR4__DENALI_CTL_231__ZQ_CS_HIGH_THRESHOLD_F0_SHIFT 0U
  3473. #define LPDDR4__DENALI_CTL_231__ZQ_CS_HIGH_THRESHOLD_F0_WIDTH 16U
  3474. #define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F0__REG DENALI_CTL_231
  3475. #define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_231__ZQ_CS_HIGH_THRESHOLD_F0
  3476. #define LPDDR4__DENALI_CTL_231__ZQ_CALSTART_TIMEOUT_F0_MASK 0xFFFF0000U
  3477. #define LPDDR4__DENALI_CTL_231__ZQ_CALSTART_TIMEOUT_F0_SHIFT 16U
  3478. #define LPDDR4__DENALI_CTL_231__ZQ_CALSTART_TIMEOUT_F0_WIDTH 16U
  3479. #define LPDDR4__ZQ_CALSTART_TIMEOUT_F0__REG DENALI_CTL_231
  3480. #define LPDDR4__ZQ_CALSTART_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_231__ZQ_CALSTART_TIMEOUT_F0
  3481. #define LPDDR4__DENALI_CTL_232_READ_MASK 0xFFFFFFFFU
  3482. #define LPDDR4__DENALI_CTL_232_WRITE_MASK 0xFFFFFFFFU
  3483. #define LPDDR4__DENALI_CTL_232__ZQ_CALLATCH_TIMEOUT_F0_MASK 0x0000FFFFU
  3484. #define LPDDR4__DENALI_CTL_232__ZQ_CALLATCH_TIMEOUT_F0_SHIFT 0U
  3485. #define LPDDR4__DENALI_CTL_232__ZQ_CALLATCH_TIMEOUT_F0_WIDTH 16U
  3486. #define LPDDR4__ZQ_CALLATCH_TIMEOUT_F0__REG DENALI_CTL_232
  3487. #define LPDDR4__ZQ_CALLATCH_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_232__ZQ_CALLATCH_TIMEOUT_F0
  3488. #define LPDDR4__DENALI_CTL_232__ZQ_CS_TIMEOUT_F0_MASK 0xFFFF0000U
  3489. #define LPDDR4__DENALI_CTL_232__ZQ_CS_TIMEOUT_F0_SHIFT 16U
  3490. #define LPDDR4__DENALI_CTL_232__ZQ_CS_TIMEOUT_F0_WIDTH 16U
  3491. #define LPDDR4__ZQ_CS_TIMEOUT_F0__REG DENALI_CTL_232
  3492. #define LPDDR4__ZQ_CS_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_232__ZQ_CS_TIMEOUT_F0
  3493. #define LPDDR4__DENALI_CTL_233_READ_MASK 0xFFFFFFFFU
  3494. #define LPDDR4__DENALI_CTL_233_WRITE_MASK 0xFFFFFFFFU
  3495. #define LPDDR4__DENALI_CTL_233__ZQ_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
  3496. #define LPDDR4__DENALI_CTL_233__ZQ_PROMOTE_THRESHOLD_F0_SHIFT 0U
  3497. #define LPDDR4__DENALI_CTL_233__ZQ_PROMOTE_THRESHOLD_F0_WIDTH 16U
  3498. #define LPDDR4__ZQ_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_233
  3499. #define LPDDR4__ZQ_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_233__ZQ_PROMOTE_THRESHOLD_F0
  3500. #define LPDDR4__DENALI_CTL_233__ZQ_CALSTART_NORM_THRESHOLD_F1_MASK 0xFFFF0000U
  3501. #define LPDDR4__DENALI_CTL_233__ZQ_CALSTART_NORM_THRESHOLD_F1_SHIFT 16U
  3502. #define LPDDR4__DENALI_CTL_233__ZQ_CALSTART_NORM_THRESHOLD_F1_WIDTH 16U
  3503. #define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F1__REG DENALI_CTL_233
  3504. #define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_233__ZQ_CALSTART_NORM_THRESHOLD_F1
  3505. #define LPDDR4__DENALI_CTL_234_READ_MASK 0xFFFFFFFFU
  3506. #define LPDDR4__DENALI_CTL_234_WRITE_MASK 0xFFFFFFFFU
  3507. #define LPDDR4__DENALI_CTL_234__ZQ_CALSTART_HIGH_THRESHOLD_F1_MASK 0x0000FFFFU
  3508. #define LPDDR4__DENALI_CTL_234__ZQ_CALSTART_HIGH_THRESHOLD_F1_SHIFT 0U
  3509. #define LPDDR4__DENALI_CTL_234__ZQ_CALSTART_HIGH_THRESHOLD_F1_WIDTH 16U
  3510. #define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F1__REG DENALI_CTL_234
  3511. #define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_234__ZQ_CALSTART_HIGH_THRESHOLD_F1
  3512. #define LPDDR4__DENALI_CTL_234__ZQ_CALLATCH_HIGH_THRESHOLD_F1_MASK 0xFFFF0000U
  3513. #define LPDDR4__DENALI_CTL_234__ZQ_CALLATCH_HIGH_THRESHOLD_F1_SHIFT 16U
  3514. #define LPDDR4__DENALI_CTL_234__ZQ_CALLATCH_HIGH_THRESHOLD_F1_WIDTH 16U
  3515. #define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F1__REG DENALI_CTL_234
  3516. #define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_234__ZQ_CALLATCH_HIGH_THRESHOLD_F1
  3517. #define LPDDR4__DENALI_CTL_235_READ_MASK 0xFFFFFFFFU
  3518. #define LPDDR4__DENALI_CTL_235_WRITE_MASK 0xFFFFFFFFU
  3519. #define LPDDR4__DENALI_CTL_235__ZQ_CS_NORM_THRESHOLD_F1_MASK 0x0000FFFFU
  3520. #define LPDDR4__DENALI_CTL_235__ZQ_CS_NORM_THRESHOLD_F1_SHIFT 0U
  3521. #define LPDDR4__DENALI_CTL_235__ZQ_CS_NORM_THRESHOLD_F1_WIDTH 16U
  3522. #define LPDDR4__ZQ_CS_NORM_THRESHOLD_F1__REG DENALI_CTL_235
  3523. #define LPDDR4__ZQ_CS_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_235__ZQ_CS_NORM_THRESHOLD_F1
  3524. #define LPDDR4__DENALI_CTL_235__ZQ_CS_HIGH_THRESHOLD_F1_MASK 0xFFFF0000U
  3525. #define LPDDR4__DENALI_CTL_235__ZQ_CS_HIGH_THRESHOLD_F1_SHIFT 16U
  3526. #define LPDDR4__DENALI_CTL_235__ZQ_CS_HIGH_THRESHOLD_F1_WIDTH 16U
  3527. #define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F1__REG DENALI_CTL_235
  3528. #define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_235__ZQ_CS_HIGH_THRESHOLD_F1
  3529. #define LPDDR4__DENALI_CTL_236_READ_MASK 0xFFFFFFFFU
  3530. #define LPDDR4__DENALI_CTL_236_WRITE_MASK 0xFFFFFFFFU
  3531. #define LPDDR4__DENALI_CTL_236__ZQ_CALSTART_TIMEOUT_F1_MASK 0x0000FFFFU
  3532. #define LPDDR4__DENALI_CTL_236__ZQ_CALSTART_TIMEOUT_F1_SHIFT 0U
  3533. #define LPDDR4__DENALI_CTL_236__ZQ_CALSTART_TIMEOUT_F1_WIDTH 16U
  3534. #define LPDDR4__ZQ_CALSTART_TIMEOUT_F1__REG DENALI_CTL_236
  3535. #define LPDDR4__ZQ_CALSTART_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_236__ZQ_CALSTART_TIMEOUT_F1
  3536. #define LPDDR4__DENALI_CTL_236__ZQ_CALLATCH_TIMEOUT_F1_MASK 0xFFFF0000U
  3537. #define LPDDR4__DENALI_CTL_236__ZQ_CALLATCH_TIMEOUT_F1_SHIFT 16U
  3538. #define LPDDR4__DENALI_CTL_236__ZQ_CALLATCH_TIMEOUT_F1_WIDTH 16U
  3539. #define LPDDR4__ZQ_CALLATCH_TIMEOUT_F1__REG DENALI_CTL_236
  3540. #define LPDDR4__ZQ_CALLATCH_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_236__ZQ_CALLATCH_TIMEOUT_F1
  3541. #define LPDDR4__DENALI_CTL_237_READ_MASK 0xFFFFFFFFU
  3542. #define LPDDR4__DENALI_CTL_237_WRITE_MASK 0xFFFFFFFFU
  3543. #define LPDDR4__DENALI_CTL_237__ZQ_CS_TIMEOUT_F1_MASK 0x0000FFFFU
  3544. #define LPDDR4__DENALI_CTL_237__ZQ_CS_TIMEOUT_F1_SHIFT 0U
  3545. #define LPDDR4__DENALI_CTL_237__ZQ_CS_TIMEOUT_F1_WIDTH 16U
  3546. #define LPDDR4__ZQ_CS_TIMEOUT_F1__REG DENALI_CTL_237
  3547. #define LPDDR4__ZQ_CS_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_237__ZQ_CS_TIMEOUT_F1
  3548. #define LPDDR4__DENALI_CTL_237__ZQ_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U
  3549. #define LPDDR4__DENALI_CTL_237__ZQ_PROMOTE_THRESHOLD_F1_SHIFT 16U
  3550. #define LPDDR4__DENALI_CTL_237__ZQ_PROMOTE_THRESHOLD_F1_WIDTH 16U
  3551. #define LPDDR4__ZQ_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_237
  3552. #define LPDDR4__ZQ_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_237__ZQ_PROMOTE_THRESHOLD_F1
  3553. #define LPDDR4__DENALI_CTL_238_READ_MASK 0xFFFFFFFFU
  3554. #define LPDDR4__DENALI_CTL_238_WRITE_MASK 0xFFFFFFFFU
  3555. #define LPDDR4__DENALI_CTL_238__ZQ_CALSTART_NORM_THRESHOLD_F2_MASK 0x0000FFFFU
  3556. #define LPDDR4__DENALI_CTL_238__ZQ_CALSTART_NORM_THRESHOLD_F2_SHIFT 0U
  3557. #define LPDDR4__DENALI_CTL_238__ZQ_CALSTART_NORM_THRESHOLD_F2_WIDTH 16U
  3558. #define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F2__REG DENALI_CTL_238
  3559. #define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_238__ZQ_CALSTART_NORM_THRESHOLD_F2
  3560. #define LPDDR4__DENALI_CTL_238__ZQ_CALSTART_HIGH_THRESHOLD_F2_MASK 0xFFFF0000U
  3561. #define LPDDR4__DENALI_CTL_238__ZQ_CALSTART_HIGH_THRESHOLD_F2_SHIFT 16U
  3562. #define LPDDR4__DENALI_CTL_238__ZQ_CALSTART_HIGH_THRESHOLD_F2_WIDTH 16U
  3563. #define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F2__REG DENALI_CTL_238
  3564. #define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_238__ZQ_CALSTART_HIGH_THRESHOLD_F2
  3565. #define LPDDR4__DENALI_CTL_239_READ_MASK 0xFFFFFFFFU
  3566. #define LPDDR4__DENALI_CTL_239_WRITE_MASK 0xFFFFFFFFU
  3567. #define LPDDR4__DENALI_CTL_239__ZQ_CALLATCH_HIGH_THRESHOLD_F2_MASK 0x0000FFFFU
  3568. #define LPDDR4__DENALI_CTL_239__ZQ_CALLATCH_HIGH_THRESHOLD_F2_SHIFT 0U
  3569. #define LPDDR4__DENALI_CTL_239__ZQ_CALLATCH_HIGH_THRESHOLD_F2_WIDTH 16U
  3570. #define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F2__REG DENALI_CTL_239
  3571. #define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_239__ZQ_CALLATCH_HIGH_THRESHOLD_F2
  3572. #define LPDDR4__DENALI_CTL_239__ZQ_CS_NORM_THRESHOLD_F2_MASK 0xFFFF0000U
  3573. #define LPDDR4__DENALI_CTL_239__ZQ_CS_NORM_THRESHOLD_F2_SHIFT 16U
  3574. #define LPDDR4__DENALI_CTL_239__ZQ_CS_NORM_THRESHOLD_F2_WIDTH 16U
  3575. #define LPDDR4__ZQ_CS_NORM_THRESHOLD_F2__REG DENALI_CTL_239
  3576. #define LPDDR4__ZQ_CS_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_239__ZQ_CS_NORM_THRESHOLD_F2
  3577. #define LPDDR4__DENALI_CTL_240_READ_MASK 0xFFFFFFFFU
  3578. #define LPDDR4__DENALI_CTL_240_WRITE_MASK 0xFFFFFFFFU
  3579. #define LPDDR4__DENALI_CTL_240__ZQ_CS_HIGH_THRESHOLD_F2_MASK 0x0000FFFFU
  3580. #define LPDDR4__DENALI_CTL_240__ZQ_CS_HIGH_THRESHOLD_F2_SHIFT 0U
  3581. #define LPDDR4__DENALI_CTL_240__ZQ_CS_HIGH_THRESHOLD_F2_WIDTH 16U
  3582. #define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F2__REG DENALI_CTL_240
  3583. #define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_240__ZQ_CS_HIGH_THRESHOLD_F2
  3584. #define LPDDR4__DENALI_CTL_240__ZQ_CALSTART_TIMEOUT_F2_MASK 0xFFFF0000U
  3585. #define LPDDR4__DENALI_CTL_240__ZQ_CALSTART_TIMEOUT_F2_SHIFT 16U
  3586. #define LPDDR4__DENALI_CTL_240__ZQ_CALSTART_TIMEOUT_F2_WIDTH 16U
  3587. #define LPDDR4__ZQ_CALSTART_TIMEOUT_F2__REG DENALI_CTL_240
  3588. #define LPDDR4__ZQ_CALSTART_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_240__ZQ_CALSTART_TIMEOUT_F2
  3589. #define LPDDR4__DENALI_CTL_241_READ_MASK 0xFFFFFFFFU
  3590. #define LPDDR4__DENALI_CTL_241_WRITE_MASK 0xFFFFFFFFU
  3591. #define LPDDR4__DENALI_CTL_241__ZQ_CALLATCH_TIMEOUT_F2_MASK 0x0000FFFFU
  3592. #define LPDDR4__DENALI_CTL_241__ZQ_CALLATCH_TIMEOUT_F2_SHIFT 0U
  3593. #define LPDDR4__DENALI_CTL_241__ZQ_CALLATCH_TIMEOUT_F2_WIDTH 16U
  3594. #define LPDDR4__ZQ_CALLATCH_TIMEOUT_F2__REG DENALI_CTL_241
  3595. #define LPDDR4__ZQ_CALLATCH_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_241__ZQ_CALLATCH_TIMEOUT_F2
  3596. #define LPDDR4__DENALI_CTL_241__ZQ_CS_TIMEOUT_F2_MASK 0xFFFF0000U
  3597. #define LPDDR4__DENALI_CTL_241__ZQ_CS_TIMEOUT_F2_SHIFT 16U
  3598. #define LPDDR4__DENALI_CTL_241__ZQ_CS_TIMEOUT_F2_WIDTH 16U
  3599. #define LPDDR4__ZQ_CS_TIMEOUT_F2__REG DENALI_CTL_241
  3600. #define LPDDR4__ZQ_CS_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_241__ZQ_CS_TIMEOUT_F2
  3601. #define LPDDR4__DENALI_CTL_242_READ_MASK 0x0007FFFFU
  3602. #define LPDDR4__DENALI_CTL_242_WRITE_MASK 0x0007FFFFU
  3603. #define LPDDR4__DENALI_CTL_242__ZQ_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
  3604. #define LPDDR4__DENALI_CTL_242__ZQ_PROMOTE_THRESHOLD_F2_SHIFT 0U
  3605. #define LPDDR4__DENALI_CTL_242__ZQ_PROMOTE_THRESHOLD_F2_WIDTH 16U
  3606. #define LPDDR4__ZQ_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_242
  3607. #define LPDDR4__ZQ_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_242__ZQ_PROMOTE_THRESHOLD_F2
  3608. #define LPDDR4__DENALI_CTL_242__MC_RESERVED23_MASK 0x00070000U
  3609. #define LPDDR4__DENALI_CTL_242__MC_RESERVED23_SHIFT 16U
  3610. #define LPDDR4__DENALI_CTL_242__MC_RESERVED23_WIDTH 3U
  3611. #define LPDDR4__MC_RESERVED23__REG DENALI_CTL_242
  3612. #define LPDDR4__MC_RESERVED23__FLD LPDDR4__DENALI_CTL_242__MC_RESERVED23
  3613. #define LPDDR4__DENALI_CTL_243_READ_MASK 0xFFFFFFFFU
  3614. #define LPDDR4__DENALI_CTL_243_WRITE_MASK 0xFFFFFFFFU
  3615. #define LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_TASK_ARB_F0_MASK 0x0000FFFFU
  3616. #define LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_TASK_ARB_F0_SHIFT 0U
  3617. #define LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_TASK_ARB_F0_WIDTH 16U
  3618. #define LPDDR4__WATCHDOG_THRESHOLD_TASK_ARB_F0__REG DENALI_CTL_243
  3619. #define LPDDR4__WATCHDOG_THRESHOLD_TASK_ARB_F0__FLD LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_TASK_ARB_F0
  3620. #define LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_BUS_ARB_F0_MASK 0xFFFF0000U
  3621. #define LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_BUS_ARB_F0_SHIFT 16U
  3622. #define LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_BUS_ARB_F0_WIDTH 16U
  3623. #define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F0__REG DENALI_CTL_243
  3624. #define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F0__FLD LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_BUS_ARB_F0
  3625. #define LPDDR4__DENALI_CTL_244_READ_MASK 0xFFFFFFFFU
  3626. #define LPDDR4__DENALI_CTL_244_WRITE_MASK 0xFFFFFFFFU
  3627. #define LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0_MASK 0x0000FFFFU
  3628. #define LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0_SHIFT 0U
  3629. #define LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0_WIDTH 16U
  3630. #define LPDDR4__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0__REG DENALI_CTL_244
  3631. #define LPDDR4__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0__FLD LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0
  3632. #define LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_SPLIT_F0_MASK 0xFFFF0000U
  3633. #define LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_SPLIT_F0_SHIFT 16U
  3634. #define LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_SPLIT_F0_WIDTH 16U
  3635. #define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F0__REG DENALI_CTL_244
  3636. #define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F0__FLD LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_SPLIT_F0
  3637. #define LPDDR4__DENALI_CTL_245_READ_MASK 0xFFFFFFFFU
  3638. #define LPDDR4__DENALI_CTL_245_WRITE_MASK 0xFFFFFFFFU
  3639. #define LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_STRATEGY_F0_MASK 0x0000FFFFU
  3640. #define LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_STRATEGY_F0_SHIFT 0U
  3641. #define LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_STRATEGY_F0_WIDTH 16U
  3642. #define LPDDR4__WATCHDOG_THRESHOLD_STRATEGY_F0__REG DENALI_CTL_245
  3643. #define LPDDR4__WATCHDOG_THRESHOLD_STRATEGY_F0__FLD LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_STRATEGY_F0
  3644. #define LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0_MASK 0xFFFF0000U
  3645. #define LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0_SHIFT 16U
  3646. #define LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0_WIDTH 16U
  3647. #define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0__REG DENALI_CTL_245
  3648. #define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0__FLD LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0
  3649. #define LPDDR4__DENALI_CTL_246_READ_MASK 0xFFFFFFFFU
  3650. #define LPDDR4__DENALI_CTL_246_WRITE_MASK 0xFFFFFFFFU
  3651. #define LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0_MASK 0x0000FFFFU
  3652. #define LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0_SHIFT 0U
  3653. #define LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0_WIDTH 16U
  3654. #define LPDDR4__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0__REG DENALI_CTL_246
  3655. #define LPDDR4__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0__FLD LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0
  3656. #define LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0_MASK 0xFFFF0000U
  3657. #define LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0_SHIFT 16U
  3658. #define LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0_WIDTH 16U
  3659. #define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0__REG DENALI_CTL_246
  3660. #define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0__FLD LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0
  3661. #define LPDDR4__DENALI_CTL_247_READ_MASK 0xFFFFFFFFU
  3662. #define LPDDR4__DENALI_CTL_247_WRITE_MASK 0xFFFFFFFFU
  3663. #define LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_TASK_ARB_F1_MASK 0x0000FFFFU
  3664. #define LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_TASK_ARB_F1_SHIFT 0U
  3665. #define LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_TASK_ARB_F1_WIDTH 16U
  3666. #define LPDDR4__WATCHDOG_THRESHOLD_TASK_ARB_F1__REG DENALI_CTL_247
  3667. #define LPDDR4__WATCHDOG_THRESHOLD_TASK_ARB_F1__FLD LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_TASK_ARB_F1
  3668. #define LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_BUS_ARB_F1_MASK 0xFFFF0000U
  3669. #define LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_BUS_ARB_F1_SHIFT 16U
  3670. #define LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_BUS_ARB_F1_WIDTH 16U
  3671. #define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F1__REG DENALI_CTL_247
  3672. #define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F1__FLD LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_BUS_ARB_F1
  3673. #define LPDDR4__DENALI_CTL_248_READ_MASK 0xFFFFFFFFU
  3674. #define LPDDR4__DENALI_CTL_248_WRITE_MASK 0xFFFFFFFFU
  3675. #define LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1_MASK 0x0000FFFFU
  3676. #define LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1_SHIFT 0U
  3677. #define LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1_WIDTH 16U
  3678. #define LPDDR4__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1__REG DENALI_CTL_248
  3679. #define LPDDR4__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1__FLD LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1
  3680. #define LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_SPLIT_F1_MASK 0xFFFF0000U
  3681. #define LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_SPLIT_F1_SHIFT 16U
  3682. #define LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_SPLIT_F1_WIDTH 16U
  3683. #define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F1__REG DENALI_CTL_248
  3684. #define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F1__FLD LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_SPLIT_F1
  3685. #define LPDDR4__DENALI_CTL_249_READ_MASK 0xFFFFFFFFU
  3686. #define LPDDR4__DENALI_CTL_249_WRITE_MASK 0xFFFFFFFFU
  3687. #define LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_STRATEGY_F1_MASK 0x0000FFFFU
  3688. #define LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_STRATEGY_F1_SHIFT 0U
  3689. #define LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_STRATEGY_F1_WIDTH 16U
  3690. #define LPDDR4__WATCHDOG_THRESHOLD_STRATEGY_F1__REG DENALI_CTL_249
  3691. #define LPDDR4__WATCHDOG_THRESHOLD_STRATEGY_F1__FLD LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_STRATEGY_F1
  3692. #define LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1_MASK 0xFFFF0000U
  3693. #define LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1_SHIFT 16U
  3694. #define LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1_WIDTH 16U
  3695. #define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1__REG DENALI_CTL_249
  3696. #define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1__FLD LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1
  3697. #define LPDDR4__DENALI_CTL_250_READ_MASK 0xFFFFFFFFU
  3698. #define LPDDR4__DENALI_CTL_250_WRITE_MASK 0xFFFFFFFFU
  3699. #define LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1_MASK 0x0000FFFFU
  3700. #define LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1_SHIFT 0U
  3701. #define LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1_WIDTH 16U
  3702. #define LPDDR4__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1__REG DENALI_CTL_250
  3703. #define LPDDR4__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1__FLD LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1
  3704. #define LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1_MASK 0xFFFF0000U
  3705. #define LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1_SHIFT 16U
  3706. #define LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1_WIDTH 16U
  3707. #define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1__REG DENALI_CTL_250
  3708. #define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1__FLD LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1
  3709. #define LPDDR4__DENALI_CTL_251_READ_MASK 0xFFFFFFFFU
  3710. #define LPDDR4__DENALI_CTL_251_WRITE_MASK 0xFFFFFFFFU
  3711. #define LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_TASK_ARB_F2_MASK 0x0000FFFFU
  3712. #define LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_TASK_ARB_F2_SHIFT 0U
  3713. #define LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_TASK_ARB_F2_WIDTH 16U
  3714. #define LPDDR4__WATCHDOG_THRESHOLD_TASK_ARB_F2__REG DENALI_CTL_251
  3715. #define LPDDR4__WATCHDOG_THRESHOLD_TASK_ARB_F2__FLD LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_TASK_ARB_F2
  3716. #define LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_BUS_ARB_F2_MASK 0xFFFF0000U
  3717. #define LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_BUS_ARB_F2_SHIFT 16U
  3718. #define LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_BUS_ARB_F2_WIDTH 16U
  3719. #define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F2__REG DENALI_CTL_251
  3720. #define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F2__FLD LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_BUS_ARB_F2
  3721. #define LPDDR4__DENALI_CTL_252_READ_MASK 0xFFFFFFFFU
  3722. #define LPDDR4__DENALI_CTL_252_WRITE_MASK 0xFFFFFFFFU
  3723. #define LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2_MASK 0x0000FFFFU
  3724. #define LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2_SHIFT 0U
  3725. #define LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2_WIDTH 16U
  3726. #define LPDDR4__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2__REG DENALI_CTL_252
  3727. #define LPDDR4__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2__FLD LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2
  3728. #define LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_SPLIT_F2_MASK 0xFFFF0000U
  3729. #define LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_SPLIT_F2_SHIFT 16U
  3730. #define LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_SPLIT_F2_WIDTH 16U
  3731. #define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F2__REG DENALI_CTL_252
  3732. #define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F2__FLD LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_SPLIT_F2
  3733. #define LPDDR4__DENALI_CTL_253_READ_MASK 0xFFFFFFFFU
  3734. #define LPDDR4__DENALI_CTL_253_WRITE_MASK 0xFFFFFFFFU
  3735. #define LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_STRATEGY_F2_MASK 0x0000FFFFU
  3736. #define LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_STRATEGY_F2_SHIFT 0U
  3737. #define LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_STRATEGY_F2_WIDTH 16U
  3738. #define LPDDR4__WATCHDOG_THRESHOLD_STRATEGY_F2__REG DENALI_CTL_253
  3739. #define LPDDR4__WATCHDOG_THRESHOLD_STRATEGY_F2__FLD LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_STRATEGY_F2
  3740. #define LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2_MASK 0xFFFF0000U
  3741. #define LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2_SHIFT 16U
  3742. #define LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2_WIDTH 16U
  3743. #define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2__REG DENALI_CTL_253
  3744. #define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2__FLD LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2
  3745. #define LPDDR4__DENALI_CTL_254_READ_MASK 0xFFFFFFFFU
  3746. #define LPDDR4__DENALI_CTL_254_WRITE_MASK 0xFFFFFFFFU
  3747. #define LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2_MASK 0x0000FFFFU
  3748. #define LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2_SHIFT 0U
  3749. #define LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2_WIDTH 16U
  3750. #define LPDDR4__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2__REG DENALI_CTL_254
  3751. #define LPDDR4__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2__FLD LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2
  3752. #define LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2_MASK 0xFFFF0000U
  3753. #define LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2_SHIFT 16U
  3754. #define LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2_WIDTH 16U
  3755. #define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2__REG DENALI_CTL_254
  3756. #define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2__FLD LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2
  3757. #define LPDDR4__DENALI_CTL_255_READ_MASK 0x0000FF00U
  3758. #define LPDDR4__DENALI_CTL_255_WRITE_MASK 0x0000FF00U
  3759. #define LPDDR4__DENALI_CTL_255__WATCHDOG_RELOAD_MASK 0x000000FFU
  3760. #define LPDDR4__DENALI_CTL_255__WATCHDOG_RELOAD_SHIFT 0U
  3761. #define LPDDR4__DENALI_CTL_255__WATCHDOG_RELOAD_WIDTH 8U
  3762. #define LPDDR4__WATCHDOG_RELOAD__REG DENALI_CTL_255
  3763. #define LPDDR4__WATCHDOG_RELOAD__FLD LPDDR4__DENALI_CTL_255__WATCHDOG_RELOAD
  3764. #define LPDDR4__DENALI_CTL_255__WATCHDOG_DIAGNOSTIC_MODE_MASK 0x0000FF00U
  3765. #define LPDDR4__DENALI_CTL_255__WATCHDOG_DIAGNOSTIC_MODE_SHIFT 8U
  3766. #define LPDDR4__DENALI_CTL_255__WATCHDOG_DIAGNOSTIC_MODE_WIDTH 8U
  3767. #define LPDDR4__WATCHDOG_DIAGNOSTIC_MODE__REG DENALI_CTL_255
  3768. #define LPDDR4__WATCHDOG_DIAGNOSTIC_MODE__FLD LPDDR4__DENALI_CTL_255__WATCHDOG_DIAGNOSTIC_MODE
  3769. #define LPDDR4__DENALI_CTL_256_READ_MASK 0x000FFFFFU
  3770. #define LPDDR4__DENALI_CTL_256_WRITE_MASK 0x000FFFFFU
  3771. #define LPDDR4__DENALI_CTL_256__TIMEOUT_TIMER_LOG_MASK 0x000FFFFFU
  3772. #define LPDDR4__DENALI_CTL_256__TIMEOUT_TIMER_LOG_SHIFT 0U
  3773. #define LPDDR4__DENALI_CTL_256__TIMEOUT_TIMER_LOG_WIDTH 20U
  3774. #define LPDDR4__TIMEOUT_TIMER_LOG__REG DENALI_CTL_256
  3775. #define LPDDR4__TIMEOUT_TIMER_LOG__FLD LPDDR4__DENALI_CTL_256__TIMEOUT_TIMER_LOG
  3776. #define LPDDR4__DENALI_CTL_257_READ_MASK 0x0FFF0FFFU
  3777. #define LPDDR4__DENALI_CTL_257_WRITE_MASK 0x0FFF0FFFU
  3778. #define LPDDR4__DENALI_CTL_257__ZQINIT_F0_MASK 0x00000FFFU
  3779. #define LPDDR4__DENALI_CTL_257__ZQINIT_F0_SHIFT 0U
  3780. #define LPDDR4__DENALI_CTL_257__ZQINIT_F0_WIDTH 12U
  3781. #define LPDDR4__ZQINIT_F0__REG DENALI_CTL_257
  3782. #define LPDDR4__ZQINIT_F0__FLD LPDDR4__DENALI_CTL_257__ZQINIT_F0
  3783. #define LPDDR4__DENALI_CTL_257__ZQCL_F0_MASK 0x0FFF0000U
  3784. #define LPDDR4__DENALI_CTL_257__ZQCL_F0_SHIFT 16U
  3785. #define LPDDR4__DENALI_CTL_257__ZQCL_F0_WIDTH 12U
  3786. #define LPDDR4__ZQCL_F0__REG DENALI_CTL_257
  3787. #define LPDDR4__ZQCL_F0__FLD LPDDR4__DENALI_CTL_257__ZQCL_F0
  3788. #define LPDDR4__DENALI_CTL_258_READ_MASK 0x0FFF0FFFU
  3789. #define LPDDR4__DENALI_CTL_258_WRITE_MASK 0x0FFF0FFFU
  3790. #define LPDDR4__DENALI_CTL_258__ZQCS_F0_MASK 0x00000FFFU
  3791. #define LPDDR4__DENALI_CTL_258__ZQCS_F0_SHIFT 0U
  3792. #define LPDDR4__DENALI_CTL_258__ZQCS_F0_WIDTH 12U
  3793. #define LPDDR4__ZQCS_F0__REG DENALI_CTL_258
  3794. #define LPDDR4__ZQCS_F0__FLD LPDDR4__DENALI_CTL_258__ZQCS_F0
  3795. #define LPDDR4__DENALI_CTL_258__TZQCAL_F0_MASK 0x0FFF0000U
  3796. #define LPDDR4__DENALI_CTL_258__TZQCAL_F0_SHIFT 16U
  3797. #define LPDDR4__DENALI_CTL_258__TZQCAL_F0_WIDTH 12U
  3798. #define LPDDR4__TZQCAL_F0__REG DENALI_CTL_258
  3799. #define LPDDR4__TZQCAL_F0__FLD LPDDR4__DENALI_CTL_258__TZQCAL_F0
  3800. #define LPDDR4__DENALI_CTL_259_READ_MASK 0x000FFF7FU
  3801. #define LPDDR4__DENALI_CTL_259_WRITE_MASK 0x000FFF7FU
  3802. #define LPDDR4__DENALI_CTL_259__TZQLAT_F0_MASK 0x0000007FU
  3803. #define LPDDR4__DENALI_CTL_259__TZQLAT_F0_SHIFT 0U
  3804. #define LPDDR4__DENALI_CTL_259__TZQLAT_F0_WIDTH 7U
  3805. #define LPDDR4__TZQLAT_F0__REG DENALI_CTL_259
  3806. #define LPDDR4__TZQLAT_F0__FLD LPDDR4__DENALI_CTL_259__TZQLAT_F0
  3807. #define LPDDR4__DENALI_CTL_259__ZQINIT_F1_MASK 0x000FFF00U
  3808. #define LPDDR4__DENALI_CTL_259__ZQINIT_F1_SHIFT 8U
  3809. #define LPDDR4__DENALI_CTL_259__ZQINIT_F1_WIDTH 12U
  3810. #define LPDDR4__ZQINIT_F1__REG DENALI_CTL_259
  3811. #define LPDDR4__ZQINIT_F1__FLD LPDDR4__DENALI_CTL_259__ZQINIT_F1
  3812. #define LPDDR4__DENALI_CTL_260_READ_MASK 0x0FFF0FFFU
  3813. #define LPDDR4__DENALI_CTL_260_WRITE_MASK 0x0FFF0FFFU
  3814. #define LPDDR4__DENALI_CTL_260__ZQCL_F1_MASK 0x00000FFFU
  3815. #define LPDDR4__DENALI_CTL_260__ZQCL_F1_SHIFT 0U
  3816. #define LPDDR4__DENALI_CTL_260__ZQCL_F1_WIDTH 12U
  3817. #define LPDDR4__ZQCL_F1__REG DENALI_CTL_260
  3818. #define LPDDR4__ZQCL_F1__FLD LPDDR4__DENALI_CTL_260__ZQCL_F1
  3819. #define LPDDR4__DENALI_CTL_260__ZQCS_F1_MASK 0x0FFF0000U
  3820. #define LPDDR4__DENALI_CTL_260__ZQCS_F1_SHIFT 16U
  3821. #define LPDDR4__DENALI_CTL_260__ZQCS_F1_WIDTH 12U
  3822. #define LPDDR4__ZQCS_F1__REG DENALI_CTL_260
  3823. #define LPDDR4__ZQCS_F1__FLD LPDDR4__DENALI_CTL_260__ZQCS_F1
  3824. #define LPDDR4__DENALI_CTL_261_READ_MASK 0x007F0FFFU
  3825. #define LPDDR4__DENALI_CTL_261_WRITE_MASK 0x007F0FFFU
  3826. #define LPDDR4__DENALI_CTL_261__TZQCAL_F1_MASK 0x00000FFFU
  3827. #define LPDDR4__DENALI_CTL_261__TZQCAL_F1_SHIFT 0U
  3828. #define LPDDR4__DENALI_CTL_261__TZQCAL_F1_WIDTH 12U
  3829. #define LPDDR4__TZQCAL_F1__REG DENALI_CTL_261
  3830. #define LPDDR4__TZQCAL_F1__FLD LPDDR4__DENALI_CTL_261__TZQCAL_F1
  3831. #define LPDDR4__DENALI_CTL_261__TZQLAT_F1_MASK 0x007F0000U
  3832. #define LPDDR4__DENALI_CTL_261__TZQLAT_F1_SHIFT 16U
  3833. #define LPDDR4__DENALI_CTL_261__TZQLAT_F1_WIDTH 7U
  3834. #define LPDDR4__TZQLAT_F1__REG DENALI_CTL_261
  3835. #define LPDDR4__TZQLAT_F1__FLD LPDDR4__DENALI_CTL_261__TZQLAT_F1
  3836. #define LPDDR4__DENALI_CTL_262_READ_MASK 0x0FFF0FFFU
  3837. #define LPDDR4__DENALI_CTL_262_WRITE_MASK 0x0FFF0FFFU
  3838. #define LPDDR4__DENALI_CTL_262__ZQINIT_F2_MASK 0x00000FFFU
  3839. #define LPDDR4__DENALI_CTL_262__ZQINIT_F2_SHIFT 0U
  3840. #define LPDDR4__DENALI_CTL_262__ZQINIT_F2_WIDTH 12U
  3841. #define LPDDR4__ZQINIT_F2__REG DENALI_CTL_262
  3842. #define LPDDR4__ZQINIT_F2__FLD LPDDR4__DENALI_CTL_262__ZQINIT_F2
  3843. #define LPDDR4__DENALI_CTL_262__ZQCL_F2_MASK 0x0FFF0000U
  3844. #define LPDDR4__DENALI_CTL_262__ZQCL_F2_SHIFT 16U
  3845. #define LPDDR4__DENALI_CTL_262__ZQCL_F2_WIDTH 12U
  3846. #define LPDDR4__ZQCL_F2__REG DENALI_CTL_262
  3847. #define LPDDR4__ZQCL_F2__FLD LPDDR4__DENALI_CTL_262__ZQCL_F2
  3848. #define LPDDR4__DENALI_CTL_263_READ_MASK 0x0FFF0FFFU
  3849. #define LPDDR4__DENALI_CTL_263_WRITE_MASK 0x0FFF0FFFU
  3850. #define LPDDR4__DENALI_CTL_263__ZQCS_F2_MASK 0x00000FFFU
  3851. #define LPDDR4__DENALI_CTL_263__ZQCS_F2_SHIFT 0U
  3852. #define LPDDR4__DENALI_CTL_263__ZQCS_F2_WIDTH 12U
  3853. #define LPDDR4__ZQCS_F2__REG DENALI_CTL_263
  3854. #define LPDDR4__ZQCS_F2__FLD LPDDR4__DENALI_CTL_263__ZQCS_F2
  3855. #define LPDDR4__DENALI_CTL_263__TZQCAL_F2_MASK 0x0FFF0000U
  3856. #define LPDDR4__DENALI_CTL_263__TZQCAL_F2_SHIFT 16U
  3857. #define LPDDR4__DENALI_CTL_263__TZQCAL_F2_WIDTH 12U
  3858. #define LPDDR4__TZQCAL_F2__REG DENALI_CTL_263
  3859. #define LPDDR4__TZQCAL_F2__FLD LPDDR4__DENALI_CTL_263__TZQCAL_F2
  3860. #define LPDDR4__DENALI_CTL_264_READ_MASK 0x0100037FU
  3861. #define LPDDR4__DENALI_CTL_264_WRITE_MASK 0x0100037FU
  3862. #define LPDDR4__DENALI_CTL_264__TZQLAT_F2_MASK 0x0000007FU
  3863. #define LPDDR4__DENALI_CTL_264__TZQLAT_F2_SHIFT 0U
  3864. #define LPDDR4__DENALI_CTL_264__TZQLAT_F2_WIDTH 7U
  3865. #define LPDDR4__TZQLAT_F2__REG DENALI_CTL_264
  3866. #define LPDDR4__TZQLAT_F2__FLD LPDDR4__DENALI_CTL_264__TZQLAT_F2
  3867. #define LPDDR4__DENALI_CTL_264__ZQ_SW_REQ_START_LATCH_MAP_MASK 0x00000300U
  3868. #define LPDDR4__DENALI_CTL_264__ZQ_SW_REQ_START_LATCH_MAP_SHIFT 8U
  3869. #define LPDDR4__DENALI_CTL_264__ZQ_SW_REQ_START_LATCH_MAP_WIDTH 2U
  3870. #define LPDDR4__ZQ_SW_REQ_START_LATCH_MAP__REG DENALI_CTL_264
  3871. #define LPDDR4__ZQ_SW_REQ_START_LATCH_MAP__FLD LPDDR4__DENALI_CTL_264__ZQ_SW_REQ_START_LATCH_MAP
  3872. #define LPDDR4__DENALI_CTL_264__ZQ_REQ_MASK 0x000F0000U
  3873. #define LPDDR4__DENALI_CTL_264__ZQ_REQ_SHIFT 16U
  3874. #define LPDDR4__DENALI_CTL_264__ZQ_REQ_WIDTH 4U
  3875. #define LPDDR4__ZQ_REQ__REG DENALI_CTL_264
  3876. #define LPDDR4__ZQ_REQ__FLD LPDDR4__DENALI_CTL_264__ZQ_REQ
  3877. #define LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING_MASK 0x01000000U
  3878. #define LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING_SHIFT 24U
  3879. #define LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING_WIDTH 1U
  3880. #define LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING_WOCLR 0U
  3881. #define LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING_WOSET 0U
  3882. #define LPDDR4__ZQ_REQ_PENDING__REG DENALI_CTL_264
  3883. #define LPDDR4__ZQ_REQ_PENDING__FLD LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING
  3884. #define LPDDR4__DENALI_CTL_265_READ_MASK 0x0FFF0FFFU
  3885. #define LPDDR4__DENALI_CTL_265_WRITE_MASK 0x0FFF0FFFU
  3886. #define LPDDR4__DENALI_CTL_265__ZQRESET_F0_MASK 0x00000FFFU
  3887. #define LPDDR4__DENALI_CTL_265__ZQRESET_F0_SHIFT 0U
  3888. #define LPDDR4__DENALI_CTL_265__ZQRESET_F0_WIDTH 12U
  3889. #define LPDDR4__ZQRESET_F0__REG DENALI_CTL_265
  3890. #define LPDDR4__ZQRESET_F0__FLD LPDDR4__DENALI_CTL_265__ZQRESET_F0
  3891. #define LPDDR4__DENALI_CTL_265__ZQRESET_F1_MASK 0x0FFF0000U
  3892. #define LPDDR4__DENALI_CTL_265__ZQRESET_F1_SHIFT 16U
  3893. #define LPDDR4__DENALI_CTL_265__ZQRESET_F1_WIDTH 12U
  3894. #define LPDDR4__ZQRESET_F1__REG DENALI_CTL_265
  3895. #define LPDDR4__ZQRESET_F1__FLD LPDDR4__DENALI_CTL_265__ZQRESET_F1
  3896. #define LPDDR4__DENALI_CTL_266_READ_MASK 0x01010FFFU
  3897. #define LPDDR4__DENALI_CTL_266_WRITE_MASK 0x01010FFFU
  3898. #define LPDDR4__DENALI_CTL_266__ZQRESET_F2_MASK 0x00000FFFU
  3899. #define LPDDR4__DENALI_CTL_266__ZQRESET_F2_SHIFT 0U
  3900. #define LPDDR4__DENALI_CTL_266__ZQRESET_F2_WIDTH 12U
  3901. #define LPDDR4__ZQRESET_F2__REG DENALI_CTL_266
  3902. #define LPDDR4__ZQRESET_F2__FLD LPDDR4__DENALI_CTL_266__ZQRESET_F2
  3903. #define LPDDR4__DENALI_CTL_266__NO_ZQ_INIT_MASK 0x00010000U
  3904. #define LPDDR4__DENALI_CTL_266__NO_ZQ_INIT_SHIFT 16U
  3905. #define LPDDR4__DENALI_CTL_266__NO_ZQ_INIT_WIDTH 1U
  3906. #define LPDDR4__DENALI_CTL_266__NO_ZQ_INIT_WOCLR 0U
  3907. #define LPDDR4__DENALI_CTL_266__NO_ZQ_INIT_WOSET 0U
  3908. #define LPDDR4__NO_ZQ_INIT__REG DENALI_CTL_266
  3909. #define LPDDR4__NO_ZQ_INIT__FLD LPDDR4__DENALI_CTL_266__NO_ZQ_INIT
  3910. #define LPDDR4__DENALI_CTL_266__ZQCS_ROTATE_MASK 0x01000000U
  3911. #define LPDDR4__DENALI_CTL_266__ZQCS_ROTATE_SHIFT 24U
  3912. #define LPDDR4__DENALI_CTL_266__ZQCS_ROTATE_WIDTH 1U
  3913. #define LPDDR4__DENALI_CTL_266__ZQCS_ROTATE_WOCLR 0U
  3914. #define LPDDR4__DENALI_CTL_266__ZQCS_ROTATE_WOSET 0U
  3915. #define LPDDR4__ZQCS_ROTATE__REG DENALI_CTL_266
  3916. #define LPDDR4__ZQCS_ROTATE__FLD LPDDR4__DENALI_CTL_266__ZQCS_ROTATE
  3917. #define LPDDR4__DENALI_CTL_267_READ_MASK 0x03030303U
  3918. #define LPDDR4__DENALI_CTL_267_WRITE_MASK 0x03030303U
  3919. #define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_0_MASK 0x00000003U
  3920. #define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_0_SHIFT 0U
  3921. #define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_0_WIDTH 2U
  3922. #define LPDDR4__ZQ_CAL_START_MAP_0__REG DENALI_CTL_267
  3923. #define LPDDR4__ZQ_CAL_START_MAP_0__FLD LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_0
  3924. #define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_0_MASK 0x00000300U
  3925. #define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_0_SHIFT 8U
  3926. #define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_0_WIDTH 2U
  3927. #define LPDDR4__ZQ_CAL_LATCH_MAP_0__REG DENALI_CTL_267
  3928. #define LPDDR4__ZQ_CAL_LATCH_MAP_0__FLD LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_0
  3929. #define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_1_MASK 0x00030000U
  3930. #define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_1_SHIFT 16U
  3931. #define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_1_WIDTH 2U
  3932. #define LPDDR4__ZQ_CAL_START_MAP_1__REG DENALI_CTL_267
  3933. #define LPDDR4__ZQ_CAL_START_MAP_1__FLD LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_1
  3934. #define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_1_MASK 0x03000000U
  3935. #define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_1_SHIFT 24U
  3936. #define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_1_WIDTH 2U
  3937. #define LPDDR4__ZQ_CAL_LATCH_MAP_1__REG DENALI_CTL_267
  3938. #define LPDDR4__ZQ_CAL_LATCH_MAP_1__FLD LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_1
  3939. #define LPDDR4__DENALI_CTL_268_READ_MASK 0x07070303U
  3940. #define LPDDR4__DENALI_CTL_268_WRITE_MASK 0x07070303U
  3941. #define LPDDR4__DENALI_CTL_268__BANK_DIFF_0_MASK 0x00000003U
  3942. #define LPDDR4__DENALI_CTL_268__BANK_DIFF_0_SHIFT 0U
  3943. #define LPDDR4__DENALI_CTL_268__BANK_DIFF_0_WIDTH 2U
  3944. #define LPDDR4__BANK_DIFF_0__REG DENALI_CTL_268
  3945. #define LPDDR4__BANK_DIFF_0__FLD LPDDR4__DENALI_CTL_268__BANK_DIFF_0
  3946. #define LPDDR4__DENALI_CTL_268__BANK_DIFF_1_MASK 0x00000300U
  3947. #define LPDDR4__DENALI_CTL_268__BANK_DIFF_1_SHIFT 8U
  3948. #define LPDDR4__DENALI_CTL_268__BANK_DIFF_1_WIDTH 2U
  3949. #define LPDDR4__BANK_DIFF_1__REG DENALI_CTL_268
  3950. #define LPDDR4__BANK_DIFF_1__FLD LPDDR4__DENALI_CTL_268__BANK_DIFF_1
  3951. #define LPDDR4__DENALI_CTL_268__ROW_DIFF_0_MASK 0x00070000U
  3952. #define LPDDR4__DENALI_CTL_268__ROW_DIFF_0_SHIFT 16U
  3953. #define LPDDR4__DENALI_CTL_268__ROW_DIFF_0_WIDTH 3U
  3954. #define LPDDR4__ROW_DIFF_0__REG DENALI_CTL_268
  3955. #define LPDDR4__ROW_DIFF_0__FLD LPDDR4__DENALI_CTL_268__ROW_DIFF_0
  3956. #define LPDDR4__DENALI_CTL_268__ROW_DIFF_1_MASK 0x07000000U
  3957. #define LPDDR4__DENALI_CTL_268__ROW_DIFF_1_SHIFT 24U
  3958. #define LPDDR4__DENALI_CTL_268__ROW_DIFF_1_WIDTH 3U
  3959. #define LPDDR4__ROW_DIFF_1__REG DENALI_CTL_268
  3960. #define LPDDR4__ROW_DIFF_1__FLD LPDDR4__DENALI_CTL_268__ROW_DIFF_1
  3961. #define LPDDR4__DENALI_CTL_269_READ_MASK 0xFFFF0F0FU
  3962. #define LPDDR4__DENALI_CTL_269_WRITE_MASK 0xFFFF0F0FU
  3963. #define LPDDR4__DENALI_CTL_269__COL_DIFF_0_MASK 0x0000000FU
  3964. #define LPDDR4__DENALI_CTL_269__COL_DIFF_0_SHIFT 0U
  3965. #define LPDDR4__DENALI_CTL_269__COL_DIFF_0_WIDTH 4U
  3966. #define LPDDR4__COL_DIFF_0__REG DENALI_CTL_269
  3967. #define LPDDR4__COL_DIFF_0__FLD LPDDR4__DENALI_CTL_269__COL_DIFF_0
  3968. #define LPDDR4__DENALI_CTL_269__COL_DIFF_1_MASK 0x00000F00U
  3969. #define LPDDR4__DENALI_CTL_269__COL_DIFF_1_SHIFT 8U
  3970. #define LPDDR4__DENALI_CTL_269__COL_DIFF_1_WIDTH 4U
  3971. #define LPDDR4__COL_DIFF_1__REG DENALI_CTL_269
  3972. #define LPDDR4__COL_DIFF_1__FLD LPDDR4__DENALI_CTL_269__COL_DIFF_1
  3973. #define LPDDR4__DENALI_CTL_269__CS_VAL_LOWER_0_MASK 0xFFFF0000U
  3974. #define LPDDR4__DENALI_CTL_269__CS_VAL_LOWER_0_SHIFT 16U
  3975. #define LPDDR4__DENALI_CTL_269__CS_VAL_LOWER_0_WIDTH 16U
  3976. #define LPDDR4__CS_VAL_LOWER_0__REG DENALI_CTL_269
  3977. #define LPDDR4__CS_VAL_LOWER_0__FLD LPDDR4__DENALI_CTL_269__CS_VAL_LOWER_0
  3978. #define LPDDR4__DENALI_CTL_270_READ_MASK 0x0007FFFFU
  3979. #define LPDDR4__DENALI_CTL_270_WRITE_MASK 0x0007FFFFU
  3980. #define LPDDR4__DENALI_CTL_270__CS_VAL_UPPER_0_MASK 0x0000FFFFU
  3981. #define LPDDR4__DENALI_CTL_270__CS_VAL_UPPER_0_SHIFT 0U
  3982. #define LPDDR4__DENALI_CTL_270__CS_VAL_UPPER_0_WIDTH 16U
  3983. #define LPDDR4__CS_VAL_UPPER_0__REG DENALI_CTL_270
  3984. #define LPDDR4__CS_VAL_UPPER_0__FLD LPDDR4__DENALI_CTL_270__CS_VAL_UPPER_0
  3985. #define LPDDR4__DENALI_CTL_270__ROW_START_VAL_0_MASK 0x00070000U
  3986. #define LPDDR4__DENALI_CTL_270__ROW_START_VAL_0_SHIFT 16U
  3987. #define LPDDR4__DENALI_CTL_270__ROW_START_VAL_0_WIDTH 3U
  3988. #define LPDDR4__ROW_START_VAL_0__REG DENALI_CTL_270
  3989. #define LPDDR4__ROW_START_VAL_0__FLD LPDDR4__DENALI_CTL_270__ROW_START_VAL_0
  3990. #define LPDDR4__DENALI_CTL_271_READ_MASK 0xFFFFFFFFU
  3991. #define LPDDR4__DENALI_CTL_271_WRITE_MASK 0xFFFFFFFFU
  3992. #define LPDDR4__DENALI_CTL_271__CS_VAL_LOWER_1_MASK 0x0000FFFFU
  3993. #define LPDDR4__DENALI_CTL_271__CS_VAL_LOWER_1_SHIFT 0U
  3994. #define LPDDR4__DENALI_CTL_271__CS_VAL_LOWER_1_WIDTH 16U
  3995. #define LPDDR4__CS_VAL_LOWER_1__REG DENALI_CTL_271
  3996. #define LPDDR4__CS_VAL_LOWER_1__FLD LPDDR4__DENALI_CTL_271__CS_VAL_LOWER_1
  3997. #define LPDDR4__DENALI_CTL_271__CS_VAL_UPPER_1_MASK 0xFFFF0000U
  3998. #define LPDDR4__DENALI_CTL_271__CS_VAL_UPPER_1_SHIFT 16U
  3999. #define LPDDR4__DENALI_CTL_271__CS_VAL_UPPER_1_WIDTH 16U
  4000. #define LPDDR4__CS_VAL_UPPER_1__REG DENALI_CTL_271
  4001. #define LPDDR4__CS_VAL_UPPER_1__FLD LPDDR4__DENALI_CTL_271__CS_VAL_UPPER_1
  4002. #define LPDDR4__DENALI_CTL_272_READ_MASK 0xFFFF0307U
  4003. #define LPDDR4__DENALI_CTL_272_WRITE_MASK 0xFFFF0307U
  4004. #define LPDDR4__DENALI_CTL_272__ROW_START_VAL_1_MASK 0x00000007U
  4005. #define LPDDR4__DENALI_CTL_272__ROW_START_VAL_1_SHIFT 0U
  4006. #define LPDDR4__DENALI_CTL_272__ROW_START_VAL_1_WIDTH 3U
  4007. #define LPDDR4__ROW_START_VAL_1__REG DENALI_CTL_272
  4008. #define LPDDR4__ROW_START_VAL_1__FLD LPDDR4__DENALI_CTL_272__ROW_START_VAL_1
  4009. #define LPDDR4__DENALI_CTL_272__CS_MAP_NON_POW2_MASK 0x00000300U
  4010. #define LPDDR4__DENALI_CTL_272__CS_MAP_NON_POW2_SHIFT 8U
  4011. #define LPDDR4__DENALI_CTL_272__CS_MAP_NON_POW2_WIDTH 2U
  4012. #define LPDDR4__CS_MAP_NON_POW2__REG DENALI_CTL_272
  4013. #define LPDDR4__CS_MAP_NON_POW2__FLD LPDDR4__DENALI_CTL_272__CS_MAP_NON_POW2
  4014. #define LPDDR4__DENALI_CTL_272__CS_MSK_0_MASK 0xFFFF0000U
  4015. #define LPDDR4__DENALI_CTL_272__CS_MSK_0_SHIFT 16U
  4016. #define LPDDR4__DENALI_CTL_272__CS_MSK_0_WIDTH 16U
  4017. #define LPDDR4__CS_MSK_0__REG DENALI_CTL_272
  4018. #define LPDDR4__CS_MSK_0__FLD LPDDR4__DENALI_CTL_272__CS_MSK_0
  4019. #define LPDDR4__DENALI_CTL_273_READ_MASK 0x1F01FFFFU
  4020. #define LPDDR4__DENALI_CTL_273_WRITE_MASK 0x1F01FFFFU
  4021. #define LPDDR4__DENALI_CTL_273__CS_MSK_1_MASK 0x0000FFFFU
  4022. #define LPDDR4__DENALI_CTL_273__CS_MSK_1_SHIFT 0U
  4023. #define LPDDR4__DENALI_CTL_273__CS_MSK_1_WIDTH 16U
  4024. #define LPDDR4__CS_MSK_1__REG DENALI_CTL_273
  4025. #define LPDDR4__CS_MSK_1__FLD LPDDR4__DENALI_CTL_273__CS_MSK_1
  4026. #define LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN_MASK 0x00010000U
  4027. #define LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN_SHIFT 16U
  4028. #define LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN_WIDTH 1U
  4029. #define LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN_WOCLR 0U
  4030. #define LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN_WOSET 0U
  4031. #define LPDDR4__CS_LOWER_ADDR_EN__REG DENALI_CTL_273
  4032. #define LPDDR4__CS_LOWER_ADDR_EN__FLD LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN
  4033. #define LPDDR4__DENALI_CTL_273__MC_RESERVED24_MASK 0x1F000000U
  4034. #define LPDDR4__DENALI_CTL_273__MC_RESERVED24_SHIFT 24U
  4035. #define LPDDR4__DENALI_CTL_273__MC_RESERVED24_WIDTH 5U
  4036. #define LPDDR4__MC_RESERVED24__REG DENALI_CTL_273
  4037. #define LPDDR4__MC_RESERVED24__FLD LPDDR4__DENALI_CTL_273__MC_RESERVED24
  4038. #define LPDDR4__DENALI_CTL_274_READ_MASK 0xFFFF1F01U
  4039. #define LPDDR4__DENALI_CTL_274_WRITE_MASK 0xFFFF1F01U
  4040. #define LPDDR4__DENALI_CTL_274__MC_RESERVED25_MASK 0x00000001U
  4041. #define LPDDR4__DENALI_CTL_274__MC_RESERVED25_SHIFT 0U
  4042. #define LPDDR4__DENALI_CTL_274__MC_RESERVED25_WIDTH 1U
  4043. #define LPDDR4__DENALI_CTL_274__MC_RESERVED25_WOCLR 0U
  4044. #define LPDDR4__DENALI_CTL_274__MC_RESERVED25_WOSET 0U
  4045. #define LPDDR4__MC_RESERVED25__REG DENALI_CTL_274
  4046. #define LPDDR4__MC_RESERVED25__FLD LPDDR4__DENALI_CTL_274__MC_RESERVED25
  4047. #define LPDDR4__DENALI_CTL_274__APREBIT_MASK 0x00001F00U
  4048. #define LPDDR4__DENALI_CTL_274__APREBIT_SHIFT 8U
  4049. #define LPDDR4__DENALI_CTL_274__APREBIT_WIDTH 5U
  4050. #define LPDDR4__APREBIT__REG DENALI_CTL_274
  4051. #define LPDDR4__APREBIT__FLD LPDDR4__DENALI_CTL_274__APREBIT
  4052. #define LPDDR4__DENALI_CTL_274__AGE_COUNT_MASK 0x00FF0000U
  4053. #define LPDDR4__DENALI_CTL_274__AGE_COUNT_SHIFT 16U
  4054. #define LPDDR4__DENALI_CTL_274__AGE_COUNT_WIDTH 8U
  4055. #define LPDDR4__AGE_COUNT__REG DENALI_CTL_274
  4056. #define LPDDR4__AGE_COUNT__FLD LPDDR4__DENALI_CTL_274__AGE_COUNT
  4057. #define LPDDR4__DENALI_CTL_274__COMMAND_AGE_COUNT_MASK 0xFF000000U
  4058. #define LPDDR4__DENALI_CTL_274__COMMAND_AGE_COUNT_SHIFT 24U
  4059. #define LPDDR4__DENALI_CTL_274__COMMAND_AGE_COUNT_WIDTH 8U
  4060. #define LPDDR4__COMMAND_AGE_COUNT__REG DENALI_CTL_274
  4061. #define LPDDR4__COMMAND_AGE_COUNT__FLD LPDDR4__DENALI_CTL_274__COMMAND_AGE_COUNT
  4062. #define LPDDR4__DENALI_CTL_275_READ_MASK 0x01010101U
  4063. #define LPDDR4__DENALI_CTL_275_WRITE_MASK 0x01010101U
  4064. #define LPDDR4__DENALI_CTL_275__ADDR_CMP_EN_MASK 0x00000001U
  4065. #define LPDDR4__DENALI_CTL_275__ADDR_CMP_EN_SHIFT 0U
  4066. #define LPDDR4__DENALI_CTL_275__ADDR_CMP_EN_WIDTH 1U
  4067. #define LPDDR4__DENALI_CTL_275__ADDR_CMP_EN_WOCLR 0U
  4068. #define LPDDR4__DENALI_CTL_275__ADDR_CMP_EN_WOSET 0U
  4069. #define LPDDR4__ADDR_CMP_EN__REG DENALI_CTL_275
  4070. #define LPDDR4__ADDR_CMP_EN__FLD LPDDR4__DENALI_CTL_275__ADDR_CMP_EN
  4071. #define LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS_MASK 0x00000100U
  4072. #define LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS_SHIFT 8U
  4073. #define LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS_WIDTH 1U
  4074. #define LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS_WOCLR 0U
  4075. #define LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS_WOSET 0U
  4076. #define LPDDR4__ADDR_COLLISION_MPM_DIS__REG DENALI_CTL_275
  4077. #define LPDDR4__ADDR_COLLISION_MPM_DIS__FLD LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS
  4078. #define LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN_MASK 0x00010000U
  4079. #define LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN_SHIFT 16U
  4080. #define LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN_WIDTH 1U
  4081. #define LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN_WOCLR 0U
  4082. #define LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN_WOSET 0U
  4083. #define LPDDR4__BANK_SPLIT_EN__REG DENALI_CTL_275
  4084. #define LPDDR4__BANK_SPLIT_EN__FLD LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN
  4085. #define LPDDR4__DENALI_CTL_275__PLACEMENT_EN_MASK 0x01000000U
  4086. #define LPDDR4__DENALI_CTL_275__PLACEMENT_EN_SHIFT 24U
  4087. #define LPDDR4__DENALI_CTL_275__PLACEMENT_EN_WIDTH 1U
  4088. #define LPDDR4__DENALI_CTL_275__PLACEMENT_EN_WOCLR 0U
  4089. #define LPDDR4__DENALI_CTL_275__PLACEMENT_EN_WOSET 0U
  4090. #define LPDDR4__PLACEMENT_EN__REG DENALI_CTL_275
  4091. #define LPDDR4__PLACEMENT_EN__FLD LPDDR4__DENALI_CTL_275__PLACEMENT_EN
  4092. #define LPDDR4__DENALI_CTL_276_READ_MASK 0x01010101U
  4093. #define LPDDR4__DENALI_CTL_276_WRITE_MASK 0x01010101U
  4094. #define LPDDR4__DENALI_CTL_276__PRIORITY_EN_MASK 0x00000001U
  4095. #define LPDDR4__DENALI_CTL_276__PRIORITY_EN_SHIFT 0U
  4096. #define LPDDR4__DENALI_CTL_276__PRIORITY_EN_WIDTH 1U
  4097. #define LPDDR4__DENALI_CTL_276__PRIORITY_EN_WOCLR 0U
  4098. #define LPDDR4__DENALI_CTL_276__PRIORITY_EN_WOSET 0U
  4099. #define LPDDR4__PRIORITY_EN__REG DENALI_CTL_276
  4100. #define LPDDR4__PRIORITY_EN__FLD LPDDR4__DENALI_CTL_276__PRIORITY_EN
  4101. #define LPDDR4__DENALI_CTL_276__RW_SAME_EN_MASK 0x00000100U
  4102. #define LPDDR4__DENALI_CTL_276__RW_SAME_EN_SHIFT 8U
  4103. #define LPDDR4__DENALI_CTL_276__RW_SAME_EN_WIDTH 1U
  4104. #define LPDDR4__DENALI_CTL_276__RW_SAME_EN_WOCLR 0U
  4105. #define LPDDR4__DENALI_CTL_276__RW_SAME_EN_WOSET 0U
  4106. #define LPDDR4__RW_SAME_EN__REG DENALI_CTL_276
  4107. #define LPDDR4__RW_SAME_EN__FLD LPDDR4__DENALI_CTL_276__RW_SAME_EN
  4108. #define LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN_MASK 0x00010000U
  4109. #define LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN_SHIFT 16U
  4110. #define LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN_WIDTH 1U
  4111. #define LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN_WOCLR 0U
  4112. #define LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN_WOSET 0U
  4113. #define LPDDR4__RW_SAME_PAGE_EN__REG DENALI_CTL_276
  4114. #define LPDDR4__RW_SAME_PAGE_EN__FLD LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN
  4115. #define LPDDR4__DENALI_CTL_276__CS_SAME_EN_MASK 0x01000000U
  4116. #define LPDDR4__DENALI_CTL_276__CS_SAME_EN_SHIFT 24U
  4117. #define LPDDR4__DENALI_CTL_276__CS_SAME_EN_WIDTH 1U
  4118. #define LPDDR4__DENALI_CTL_276__CS_SAME_EN_WOCLR 0U
  4119. #define LPDDR4__DENALI_CTL_276__CS_SAME_EN_WOSET 0U
  4120. #define LPDDR4__CS_SAME_EN__REG DENALI_CTL_276
  4121. #define LPDDR4__CS_SAME_EN__FLD LPDDR4__DENALI_CTL_276__CS_SAME_EN
  4122. #define LPDDR4__DENALI_CTL_277_READ_MASK 0x011F0301U
  4123. #define LPDDR4__DENALI_CTL_277_WRITE_MASK 0x011F0301U
  4124. #define LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN_MASK 0x00000001U
  4125. #define LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN_SHIFT 0U
  4126. #define LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN_WIDTH 1U
  4127. #define LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN_WOCLR 0U
  4128. #define LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN_WOSET 0U
  4129. #define LPDDR4__W2R_SPLIT_EN__REG DENALI_CTL_277
  4130. #define LPDDR4__W2R_SPLIT_EN__FLD LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN
  4131. #define LPDDR4__DENALI_CTL_277__DISABLE_RW_GROUP_W_BNK_CONFLICT_MASK 0x00000300U
  4132. #define LPDDR4__DENALI_CTL_277__DISABLE_RW_GROUP_W_BNK_CONFLICT_SHIFT 8U
  4133. #define LPDDR4__DENALI_CTL_277__DISABLE_RW_GROUP_W_BNK_CONFLICT_WIDTH 2U
  4134. #define LPDDR4__DISABLE_RW_GROUP_W_BNK_CONFLICT__REG DENALI_CTL_277
  4135. #define LPDDR4__DISABLE_RW_GROUP_W_BNK_CONFLICT__FLD LPDDR4__DENALI_CTL_277__DISABLE_RW_GROUP_W_BNK_CONFLICT
  4136. #define LPDDR4__DENALI_CTL_277__NUM_Q_ENTRIES_ACT_DISABLE_MASK 0x001F0000U
  4137. #define LPDDR4__DENALI_CTL_277__NUM_Q_ENTRIES_ACT_DISABLE_SHIFT 16U
  4138. #define LPDDR4__DENALI_CTL_277__NUM_Q_ENTRIES_ACT_DISABLE_WIDTH 5U
  4139. #define LPDDR4__NUM_Q_ENTRIES_ACT_DISABLE__REG DENALI_CTL_277
  4140. #define LPDDR4__NUM_Q_ENTRIES_ACT_DISABLE__FLD LPDDR4__DENALI_CTL_277__NUM_Q_ENTRIES_ACT_DISABLE
  4141. #define LPDDR4__DENALI_CTL_277__SWAP_EN_MASK 0x01000000U
  4142. #define LPDDR4__DENALI_CTL_277__SWAP_EN_SHIFT 24U
  4143. #define LPDDR4__DENALI_CTL_277__SWAP_EN_WIDTH 1U
  4144. #define LPDDR4__DENALI_CTL_277__SWAP_EN_WOCLR 0U
  4145. #define LPDDR4__DENALI_CTL_277__SWAP_EN_WOSET 0U
  4146. #define LPDDR4__SWAP_EN__REG DENALI_CTL_277
  4147. #define LPDDR4__SWAP_EN__FLD LPDDR4__DENALI_CTL_277__SWAP_EN
  4148. #define LPDDR4__DENALI_CTL_278_READ_MASK 0x01030301U
  4149. #define LPDDR4__DENALI_CTL_278_WRITE_MASK 0x01030301U
  4150. #define LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE_MASK 0x00000001U
  4151. #define LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE_SHIFT 0U
  4152. #define LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE_WIDTH 1U
  4153. #define LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE_WOCLR 0U
  4154. #define LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE_WOSET 0U
  4155. #define LPDDR4__DISABLE_RD_INTERLEAVE__REG DENALI_CTL_278
  4156. #define LPDDR4__DISABLE_RD_INTERLEAVE__FLD LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE
  4157. #define LPDDR4__DENALI_CTL_278__INHIBIT_DRAM_CMD_MASK 0x00000300U
  4158. #define LPDDR4__DENALI_CTL_278__INHIBIT_DRAM_CMD_SHIFT 8U
  4159. #define LPDDR4__DENALI_CTL_278__INHIBIT_DRAM_CMD_WIDTH 2U
  4160. #define LPDDR4__INHIBIT_DRAM_CMD__REG DENALI_CTL_278
  4161. #define LPDDR4__INHIBIT_DRAM_CMD__FLD LPDDR4__DENALI_CTL_278__INHIBIT_DRAM_CMD
  4162. #define LPDDR4__DENALI_CTL_278__CS_MAP_MASK 0x00030000U
  4163. #define LPDDR4__DENALI_CTL_278__CS_MAP_SHIFT 16U
  4164. #define LPDDR4__DENALI_CTL_278__CS_MAP_WIDTH 2U
  4165. #define LPDDR4__CS_MAP__REG DENALI_CTL_278
  4166. #define LPDDR4__CS_MAP__FLD LPDDR4__DENALI_CTL_278__CS_MAP
  4167. #define LPDDR4__DENALI_CTL_278__REDUC_MASK 0x01000000U
  4168. #define LPDDR4__DENALI_CTL_278__REDUC_SHIFT 24U
  4169. #define LPDDR4__DENALI_CTL_278__REDUC_WIDTH 1U
  4170. #define LPDDR4__DENALI_CTL_278__REDUC_WOCLR 0U
  4171. #define LPDDR4__DENALI_CTL_278__REDUC_WOSET 0U
  4172. #define LPDDR4__REDUC__REG DENALI_CTL_278
  4173. #define LPDDR4__REDUC__FLD LPDDR4__DENALI_CTL_278__REDUC
  4174. #define LPDDR4__DENALI_CTL_279_READ_MASK 0x0003FFFFU
  4175. #define LPDDR4__DENALI_CTL_279_WRITE_MASK 0x0003FFFFU
  4176. #define LPDDR4__DENALI_CTL_279__FAULT_FIFO_PROTECTION_EN_MASK 0x0003FFFFU
  4177. #define LPDDR4__DENALI_CTL_279__FAULT_FIFO_PROTECTION_EN_SHIFT 0U
  4178. #define LPDDR4__DENALI_CTL_279__FAULT_FIFO_PROTECTION_EN_WIDTH 18U
  4179. #define LPDDR4__FAULT_FIFO_PROTECTION_EN__REG DENALI_CTL_279
  4180. #define LPDDR4__FAULT_FIFO_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_279__FAULT_FIFO_PROTECTION_EN
  4181. #define LPDDR4__DENALI_CTL_280_READ_MASK 0x0003FFFFU
  4182. #define LPDDR4__DENALI_CTL_280_WRITE_MASK 0x0003FFFFU
  4183. #define LPDDR4__DENALI_CTL_280__FAULT_FIFO_PROTECTION_STATUS_MASK 0x0003FFFFU
  4184. #define LPDDR4__DENALI_CTL_280__FAULT_FIFO_PROTECTION_STATUS_SHIFT 0U
  4185. #define LPDDR4__DENALI_CTL_280__FAULT_FIFO_PROTECTION_STATUS_WIDTH 18U
  4186. #define LPDDR4__FAULT_FIFO_PROTECTION_STATUS__REG DENALI_CTL_280
  4187. #define LPDDR4__FAULT_FIFO_PROTECTION_STATUS__FLD LPDDR4__DENALI_CTL_280__FAULT_FIFO_PROTECTION_STATUS
  4188. #define LPDDR4__DENALI_CTL_281_READ_MASK 0x0103FFFFU
  4189. #define LPDDR4__DENALI_CTL_281_WRITE_MASK 0x0103FFFFU
  4190. #define LPDDR4__DENALI_CTL_281__FAULT_FIFO_PROTECTION_INJECTION_EN_MASK 0x0003FFFFU
  4191. #define LPDDR4__DENALI_CTL_281__FAULT_FIFO_PROTECTION_INJECTION_EN_SHIFT 0U
  4192. #define LPDDR4__DENALI_CTL_281__FAULT_FIFO_PROTECTION_INJECTION_EN_WIDTH 18U
  4193. #define LPDDR4__FAULT_FIFO_PROTECTION_INJECTION_EN__REG DENALI_CTL_281
  4194. #define LPDDR4__FAULT_FIFO_PROTECTION_INJECTION_EN__FLD LPDDR4__DENALI_CTL_281__FAULT_FIFO_PROTECTION_INJECTION_EN
  4195. #define LPDDR4__DENALI_CTL_281__WRITE_ADDR_CHAN_PARITY_EN_MASK 0x01000000U
  4196. #define LPDDR4__DENALI_CTL_281__WRITE_ADDR_CHAN_PARITY_EN_SHIFT 24U
  4197. #define LPDDR4__DENALI_CTL_281__WRITE_ADDR_CHAN_PARITY_EN_WIDTH 1U
  4198. #define LPDDR4__DENALI_CTL_281__WRITE_ADDR_CHAN_PARITY_EN_WOCLR 0U
  4199. #define LPDDR4__DENALI_CTL_281__WRITE_ADDR_CHAN_PARITY_EN_WOSET 0U
  4200. #define LPDDR4__WRITE_ADDR_CHAN_PARITY_EN__REG DENALI_CTL_281
  4201. #define LPDDR4__WRITE_ADDR_CHAN_PARITY_EN__FLD LPDDR4__DENALI_CTL_281__WRITE_ADDR_CHAN_PARITY_EN
  4202. #define LPDDR4__DENALI_CTL_282_READ_MASK 0x01010103U
  4203. #define LPDDR4__DENALI_CTL_282_WRITE_MASK 0x01010103U
  4204. #define LPDDR4__DENALI_CTL_282__WRITE_DATA_CHAN_PARITY_EN_MASK 0x00000003U
  4205. #define LPDDR4__DENALI_CTL_282__WRITE_DATA_CHAN_PARITY_EN_SHIFT 0U
  4206. #define LPDDR4__DENALI_CTL_282__WRITE_DATA_CHAN_PARITY_EN_WIDTH 2U
  4207. #define LPDDR4__WRITE_DATA_CHAN_PARITY_EN__REG DENALI_CTL_282
  4208. #define LPDDR4__WRITE_DATA_CHAN_PARITY_EN__FLD LPDDR4__DENALI_CTL_282__WRITE_DATA_CHAN_PARITY_EN
  4209. #define LPDDR4__DENALI_CTL_282__WRITE_RESP_CHAN_PARITY_EN_MASK 0x00000100U
  4210. #define LPDDR4__DENALI_CTL_282__WRITE_RESP_CHAN_PARITY_EN_SHIFT 8U
  4211. #define LPDDR4__DENALI_CTL_282__WRITE_RESP_CHAN_PARITY_EN_WIDTH 1U
  4212. #define LPDDR4__DENALI_CTL_282__WRITE_RESP_CHAN_PARITY_EN_WOCLR 0U
  4213. #define LPDDR4__DENALI_CTL_282__WRITE_RESP_CHAN_PARITY_EN_WOSET 0U
  4214. #define LPDDR4__WRITE_RESP_CHAN_PARITY_EN__REG DENALI_CTL_282
  4215. #define LPDDR4__WRITE_RESP_CHAN_PARITY_EN__FLD LPDDR4__DENALI_CTL_282__WRITE_RESP_CHAN_PARITY_EN
  4216. #define LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN_MASK 0x00010000U
  4217. #define LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN_SHIFT 16U
  4218. #define LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN_WIDTH 1U
  4219. #define LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN_WOCLR 0U
  4220. #define LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN_WOSET 0U
  4221. #define LPDDR4__READ_ADDR_CHAN_PARITY_EN__REG DENALI_CTL_282
  4222. #define LPDDR4__READ_ADDR_CHAN_PARITY_EN__FLD LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN
  4223. #define LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN_MASK 0x01000000U
  4224. #define LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN_SHIFT 24U
  4225. #define LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN_WIDTH 1U
  4226. #define LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN_WOCLR 0U
  4227. #define LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN_WOSET 0U
  4228. #define LPDDR4__READ_DATA_CHAN_PARITY_EN__REG DENALI_CTL_282
  4229. #define LPDDR4__READ_DATA_CHAN_PARITY_EN__FLD LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN
  4230. #define LPDDR4__DENALI_CTL_283_READ_MASK 0x01010101U
  4231. #define LPDDR4__DENALI_CTL_283_WRITE_MASK 0x01010101U
  4232. #define LPDDR4__DENALI_CTL_283__MC_RESERVED26_MASK 0x00000001U
  4233. #define LPDDR4__DENALI_CTL_283__MC_RESERVED26_SHIFT 0U
  4234. #define LPDDR4__DENALI_CTL_283__MC_RESERVED26_WIDTH 1U
  4235. #define LPDDR4__DENALI_CTL_283__MC_RESERVED26_WOCLR 0U
  4236. #define LPDDR4__DENALI_CTL_283__MC_RESERVED26_WOSET 0U
  4237. #define LPDDR4__MC_RESERVED26__REG DENALI_CTL_283
  4238. #define LPDDR4__MC_RESERVED26__FLD LPDDR4__DENALI_CTL_283__MC_RESERVED26
  4239. #define LPDDR4__DENALI_CTL_283__MC_RESERVED27_MASK 0x00000100U
  4240. #define LPDDR4__DENALI_CTL_283__MC_RESERVED27_SHIFT 8U
  4241. #define LPDDR4__DENALI_CTL_283__MC_RESERVED27_WIDTH 1U
  4242. #define LPDDR4__DENALI_CTL_283__MC_RESERVED27_WOCLR 0U
  4243. #define LPDDR4__DENALI_CTL_283__MC_RESERVED27_WOSET 0U
  4244. #define LPDDR4__MC_RESERVED27__REG DENALI_CTL_283
  4245. #define LPDDR4__MC_RESERVED27__FLD LPDDR4__DENALI_CTL_283__MC_RESERVED27
  4246. #define LPDDR4__DENALI_CTL_283__WRITE_PARITY_ERR_BRESP_EN_MASK 0x00010000U
  4247. #define LPDDR4__DENALI_CTL_283__WRITE_PARITY_ERR_BRESP_EN_SHIFT 16U
  4248. #define LPDDR4__DENALI_CTL_283__WRITE_PARITY_ERR_BRESP_EN_WIDTH 1U
  4249. #define LPDDR4__DENALI_CTL_283__WRITE_PARITY_ERR_BRESP_EN_WOCLR 0U
  4250. #define LPDDR4__DENALI_CTL_283__WRITE_PARITY_ERR_BRESP_EN_WOSET 0U
  4251. #define LPDDR4__WRITE_PARITY_ERR_BRESP_EN__REG DENALI_CTL_283
  4252. #define LPDDR4__WRITE_PARITY_ERR_BRESP_EN__FLD LPDDR4__DENALI_CTL_283__WRITE_PARITY_ERR_BRESP_EN
  4253. #define LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN_MASK 0x01000000U
  4254. #define LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN_SHIFT 24U
  4255. #define LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN_WIDTH 1U
  4256. #define LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN_WOCLR 0U
  4257. #define LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN_WOSET 0U
  4258. #define LPDDR4__READ_PARITY_ERR_RRESP_EN__REG DENALI_CTL_283
  4259. #define LPDDR4__READ_PARITY_ERR_RRESP_EN__FLD LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN
  4260. #define LPDDR4__DENALI_CTL_284_READ_MASK 0x01010101U
  4261. #define LPDDR4__DENALI_CTL_284_WRITE_MASK 0x01010101U
  4262. #define LPDDR4__DENALI_CTL_284__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN_MASK 0x00000001U
  4263. #define LPDDR4__DENALI_CTL_284__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN_SHIFT 0U
  4264. #define LPDDR4__DENALI_CTL_284__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN_WIDTH 1U
  4265. #define LPDDR4__DENALI_CTL_284__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN_WOCLR 0U
  4266. #define LPDDR4__DENALI_CTL_284__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN_WOSET 0U
  4267. #define LPDDR4__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN__REG DENALI_CTL_284
  4268. #define LPDDR4__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN__FLD LPDDR4__DENALI_CTL_284__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN
  4269. #define LPDDR4__DENALI_CTL_284__WRITE_DATA_CHAN_TRIGGER_PARITY_EN_MASK 0x00000100U
  4270. #define LPDDR4__DENALI_CTL_284__WRITE_DATA_CHAN_TRIGGER_PARITY_EN_SHIFT 8U
  4271. #define LPDDR4__DENALI_CTL_284__WRITE_DATA_CHAN_TRIGGER_PARITY_EN_WIDTH 1U
  4272. #define LPDDR4__DENALI_CTL_284__WRITE_DATA_CHAN_TRIGGER_PARITY_EN_WOCLR 0U
  4273. #define LPDDR4__DENALI_CTL_284__WRITE_DATA_CHAN_TRIGGER_PARITY_EN_WOSET 0U
  4274. #define LPDDR4__WRITE_DATA_CHAN_TRIGGER_PARITY_EN__REG DENALI_CTL_284
  4275. #define LPDDR4__WRITE_DATA_CHAN_TRIGGER_PARITY_EN__FLD LPDDR4__DENALI_CTL_284__WRITE_DATA_CHAN_TRIGGER_PARITY_EN
  4276. #define LPDDR4__DENALI_CTL_284__WRITE_RESP_CHAN_CORRUPT_PARITY_EN_MASK 0x00010000U
  4277. #define LPDDR4__DENALI_CTL_284__WRITE_RESP_CHAN_CORRUPT_PARITY_EN_SHIFT 16U
  4278. #define LPDDR4__DENALI_CTL_284__WRITE_RESP_CHAN_CORRUPT_PARITY_EN_WIDTH 1U
  4279. #define LPDDR4__DENALI_CTL_284__WRITE_RESP_CHAN_CORRUPT_PARITY_EN_WOCLR 0U
  4280. #define LPDDR4__DENALI_CTL_284__WRITE_RESP_CHAN_CORRUPT_PARITY_EN_WOSET 0U
  4281. #define LPDDR4__WRITE_RESP_CHAN_CORRUPT_PARITY_EN__REG DENALI_CTL_284
  4282. #define LPDDR4__WRITE_RESP_CHAN_CORRUPT_PARITY_EN__FLD LPDDR4__DENALI_CTL_284__WRITE_RESP_CHAN_CORRUPT_PARITY_EN
  4283. #define LPDDR4__DENALI_CTL_284__READ_ADDR_CHAN_TRIGGER_PARITY_EN_MASK 0x01000000U
  4284. #define LPDDR4__DENALI_CTL_284__READ_ADDR_CHAN_TRIGGER_PARITY_EN_SHIFT 24U
  4285. #define LPDDR4__DENALI_CTL_284__READ_ADDR_CHAN_TRIGGER_PARITY_EN_WIDTH 1U
  4286. #define LPDDR4__DENALI_CTL_284__READ_ADDR_CHAN_TRIGGER_PARITY_EN_WOCLR 0U
  4287. #define LPDDR4__DENALI_CTL_284__READ_ADDR_CHAN_TRIGGER_PARITY_EN_WOSET 0U
  4288. #define LPDDR4__READ_ADDR_CHAN_TRIGGER_PARITY_EN__REG DENALI_CTL_284
  4289. #define LPDDR4__READ_ADDR_CHAN_TRIGGER_PARITY_EN__FLD LPDDR4__DENALI_CTL_284__READ_ADDR_CHAN_TRIGGER_PARITY_EN
  4290. #define LPDDR4__DENALI_CTL_285_READ_MASK 0x01010101U
  4291. #define LPDDR4__DENALI_CTL_285_WRITE_MASK 0x01010101U
  4292. #define LPDDR4__DENALI_CTL_285__READ_DATA_CHAN_CORRUPT_PARITY_EN_MASK 0x00000001U
  4293. #define LPDDR4__DENALI_CTL_285__READ_DATA_CHAN_CORRUPT_PARITY_EN_SHIFT 0U
  4294. #define LPDDR4__DENALI_CTL_285__READ_DATA_CHAN_CORRUPT_PARITY_EN_WIDTH 1U
  4295. #define LPDDR4__DENALI_CTL_285__READ_DATA_CHAN_CORRUPT_PARITY_EN_WOCLR 0U
  4296. #define LPDDR4__DENALI_CTL_285__READ_DATA_CHAN_CORRUPT_PARITY_EN_WOSET 0U
  4297. #define LPDDR4__READ_DATA_CHAN_CORRUPT_PARITY_EN__REG DENALI_CTL_285
  4298. #define LPDDR4__READ_DATA_CHAN_CORRUPT_PARITY_EN__FLD LPDDR4__DENALI_CTL_285__READ_DATA_CHAN_CORRUPT_PARITY_EN
  4299. #define LPDDR4__DENALI_CTL_285__ECC_AXI_ERROR_RESPONSE_INHIBIT_MASK 0x00000100U
  4300. #define LPDDR4__DENALI_CTL_285__ECC_AXI_ERROR_RESPONSE_INHIBIT_SHIFT 8U
  4301. #define LPDDR4__DENALI_CTL_285__ECC_AXI_ERROR_RESPONSE_INHIBIT_WIDTH 1U
  4302. #define LPDDR4__DENALI_CTL_285__ECC_AXI_ERROR_RESPONSE_INHIBIT_WOCLR 0U
  4303. #define LPDDR4__DENALI_CTL_285__ECC_AXI_ERROR_RESPONSE_INHIBIT_WOSET 0U
  4304. #define LPDDR4__ECC_AXI_ERROR_RESPONSE_INHIBIT__REG DENALI_CTL_285
  4305. #define LPDDR4__ECC_AXI_ERROR_RESPONSE_INHIBIT__FLD LPDDR4__DENALI_CTL_285__ECC_AXI_ERROR_RESPONSE_INHIBIT
  4306. #define LPDDR4__DENALI_CTL_285__WRITE_PARITY_ERR_CORRUPT_ECC_EN_MASK 0x00010000U
  4307. #define LPDDR4__DENALI_CTL_285__WRITE_PARITY_ERR_CORRUPT_ECC_EN_SHIFT 16U
  4308. #define LPDDR4__DENALI_CTL_285__WRITE_PARITY_ERR_CORRUPT_ECC_EN_WIDTH 1U
  4309. #define LPDDR4__DENALI_CTL_285__WRITE_PARITY_ERR_CORRUPT_ECC_EN_WOCLR 0U
  4310. #define LPDDR4__DENALI_CTL_285__WRITE_PARITY_ERR_CORRUPT_ECC_EN_WOSET 0U
  4311. #define LPDDR4__WRITE_PARITY_ERR_CORRUPT_ECC_EN__REG DENALI_CTL_285
  4312. #define LPDDR4__WRITE_PARITY_ERR_CORRUPT_ECC_EN__FLD LPDDR4__DENALI_CTL_285__WRITE_PARITY_ERR_CORRUPT_ECC_EN
  4313. #define LPDDR4__DENALI_CTL_285__ENHANCED_PARITY_PROTECTION_EN_MASK 0x01000000U
  4314. #define LPDDR4__DENALI_CTL_285__ENHANCED_PARITY_PROTECTION_EN_SHIFT 24U
  4315. #define LPDDR4__DENALI_CTL_285__ENHANCED_PARITY_PROTECTION_EN_WIDTH 1U
  4316. #define LPDDR4__DENALI_CTL_285__ENHANCED_PARITY_PROTECTION_EN_WOCLR 0U
  4317. #define LPDDR4__DENALI_CTL_285__ENHANCED_PARITY_PROTECTION_EN_WOSET 0U
  4318. #define LPDDR4__ENHANCED_PARITY_PROTECTION_EN__REG DENALI_CTL_285
  4319. #define LPDDR4__ENHANCED_PARITY_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_285__ENHANCED_PARITY_PROTECTION_EN
  4320. #define LPDDR4__DENALI_CTL_286_READ_MASK 0x0F0F0F07U
  4321. #define LPDDR4__DENALI_CTL_286_WRITE_MASK 0x0F0F0F07U
  4322. #define LPDDR4__DENALI_CTL_286__MEMDATA_RATIO_0_MASK 0x00000007U
  4323. #define LPDDR4__DENALI_CTL_286__MEMDATA_RATIO_0_SHIFT 0U
  4324. #define LPDDR4__DENALI_CTL_286__MEMDATA_RATIO_0_WIDTH 3U
  4325. #define LPDDR4__MEMDATA_RATIO_0__REG DENALI_CTL_286
  4326. #define LPDDR4__MEMDATA_RATIO_0__FLD LPDDR4__DENALI_CTL_286__MEMDATA_RATIO_0
  4327. #define LPDDR4__DENALI_CTL_286__DEVICE0_BYTE0_CS0_MASK 0x00000F00U
  4328. #define LPDDR4__DENALI_CTL_286__DEVICE0_BYTE0_CS0_SHIFT 8U
  4329. #define LPDDR4__DENALI_CTL_286__DEVICE0_BYTE0_CS0_WIDTH 4U
  4330. #define LPDDR4__DEVICE0_BYTE0_CS0__REG DENALI_CTL_286
  4331. #define LPDDR4__DEVICE0_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_286__DEVICE0_BYTE0_CS0
  4332. #define LPDDR4__DENALI_CTL_286__DEVICE1_BYTE0_CS0_MASK 0x000F0000U
  4333. #define LPDDR4__DENALI_CTL_286__DEVICE1_BYTE0_CS0_SHIFT 16U
  4334. #define LPDDR4__DENALI_CTL_286__DEVICE1_BYTE0_CS0_WIDTH 4U
  4335. #define LPDDR4__DEVICE1_BYTE0_CS0__REG DENALI_CTL_286
  4336. #define LPDDR4__DEVICE1_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_286__DEVICE1_BYTE0_CS0
  4337. #define LPDDR4__DENALI_CTL_286__DEVICE2_BYTE0_CS0_MASK 0x0F000000U
  4338. #define LPDDR4__DENALI_CTL_286__DEVICE2_BYTE0_CS0_SHIFT 24U
  4339. #define LPDDR4__DENALI_CTL_286__DEVICE2_BYTE0_CS0_WIDTH 4U
  4340. #define LPDDR4__DEVICE2_BYTE0_CS0__REG DENALI_CTL_286
  4341. #define LPDDR4__DEVICE2_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_286__DEVICE2_BYTE0_CS0
  4342. #define LPDDR4__DENALI_CTL_287_READ_MASK 0x0F0F070FU
  4343. #define LPDDR4__DENALI_CTL_287_WRITE_MASK 0x0F0F070FU
  4344. #define LPDDR4__DENALI_CTL_287__DEVICE3_BYTE0_CS0_MASK 0x0000000FU
  4345. #define LPDDR4__DENALI_CTL_287__DEVICE3_BYTE0_CS0_SHIFT 0U
  4346. #define LPDDR4__DENALI_CTL_287__DEVICE3_BYTE0_CS0_WIDTH 4U
  4347. #define LPDDR4__DEVICE3_BYTE0_CS0__REG DENALI_CTL_287
  4348. #define LPDDR4__DEVICE3_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_287__DEVICE3_BYTE0_CS0
  4349. #define LPDDR4__DENALI_CTL_287__MEMDATA_RATIO_1_MASK 0x00000700U
  4350. #define LPDDR4__DENALI_CTL_287__MEMDATA_RATIO_1_SHIFT 8U
  4351. #define LPDDR4__DENALI_CTL_287__MEMDATA_RATIO_1_WIDTH 3U
  4352. #define LPDDR4__MEMDATA_RATIO_1__REG DENALI_CTL_287
  4353. #define LPDDR4__MEMDATA_RATIO_1__FLD LPDDR4__DENALI_CTL_287__MEMDATA_RATIO_1
  4354. #define LPDDR4__DENALI_CTL_287__DEVICE0_BYTE0_CS1_MASK 0x000F0000U
  4355. #define LPDDR4__DENALI_CTL_287__DEVICE0_BYTE0_CS1_SHIFT 16U
  4356. #define LPDDR4__DENALI_CTL_287__DEVICE0_BYTE0_CS1_WIDTH 4U
  4357. #define LPDDR4__DEVICE0_BYTE0_CS1__REG DENALI_CTL_287
  4358. #define LPDDR4__DEVICE0_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_287__DEVICE0_BYTE0_CS1
  4359. #define LPDDR4__DENALI_CTL_287__DEVICE1_BYTE0_CS1_MASK 0x0F000000U
  4360. #define LPDDR4__DENALI_CTL_287__DEVICE1_BYTE0_CS1_SHIFT 24U
  4361. #define LPDDR4__DENALI_CTL_287__DEVICE1_BYTE0_CS1_WIDTH 4U
  4362. #define LPDDR4__DEVICE1_BYTE0_CS1__REG DENALI_CTL_287
  4363. #define LPDDR4__DEVICE1_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_287__DEVICE1_BYTE0_CS1
  4364. #define LPDDR4__DENALI_CTL_288_READ_MASK 0x011F0F0FU
  4365. #define LPDDR4__DENALI_CTL_288_WRITE_MASK 0x011F0F0FU
  4366. #define LPDDR4__DENALI_CTL_288__DEVICE2_BYTE0_CS1_MASK 0x0000000FU
  4367. #define LPDDR4__DENALI_CTL_288__DEVICE2_BYTE0_CS1_SHIFT 0U
  4368. #define LPDDR4__DENALI_CTL_288__DEVICE2_BYTE0_CS1_WIDTH 4U
  4369. #define LPDDR4__DEVICE2_BYTE0_CS1__REG DENALI_CTL_288
  4370. #define LPDDR4__DEVICE2_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_288__DEVICE2_BYTE0_CS1
  4371. #define LPDDR4__DENALI_CTL_288__DEVICE3_BYTE0_CS1_MASK 0x00000F00U
  4372. #define LPDDR4__DENALI_CTL_288__DEVICE3_BYTE0_CS1_SHIFT 8U
  4373. #define LPDDR4__DENALI_CTL_288__DEVICE3_BYTE0_CS1_WIDTH 4U
  4374. #define LPDDR4__DEVICE3_BYTE0_CS1__REG DENALI_CTL_288
  4375. #define LPDDR4__DEVICE3_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_288__DEVICE3_BYTE0_CS1
  4376. #define LPDDR4__DENALI_CTL_288__Q_FULLNESS_MASK 0x001F0000U
  4377. #define LPDDR4__DENALI_CTL_288__Q_FULLNESS_SHIFT 16U
  4378. #define LPDDR4__DENALI_CTL_288__Q_FULLNESS_WIDTH 5U
  4379. #define LPDDR4__Q_FULLNESS__REG DENALI_CTL_288
  4380. #define LPDDR4__Q_FULLNESS__FLD LPDDR4__DENALI_CTL_288__Q_FULLNESS
  4381. #define LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT_MASK 0x01000000U
  4382. #define LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT_SHIFT 24U
  4383. #define LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT_WIDTH 1U
  4384. #define LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT_WOCLR 0U
  4385. #define LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT_WOSET 0U
  4386. #define LPDDR4__IN_ORDER_ACCEPT__REG DENALI_CTL_288
  4387. #define LPDDR4__IN_ORDER_ACCEPT__FLD LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT
  4388. #define LPDDR4__DENALI_CTL_289_READ_MASK 0x01000103U
  4389. #define LPDDR4__DENALI_CTL_289_WRITE_MASK 0x01000103U
  4390. #define LPDDR4__DENALI_CTL_289__WR_ORDER_REQ_MASK 0x00000003U
  4391. #define LPDDR4__DENALI_CTL_289__WR_ORDER_REQ_SHIFT 0U
  4392. #define LPDDR4__DENALI_CTL_289__WR_ORDER_REQ_WIDTH 2U
  4393. #define LPDDR4__WR_ORDER_REQ__REG DENALI_CTL_289
  4394. #define LPDDR4__WR_ORDER_REQ__FLD LPDDR4__DENALI_CTL_289__WR_ORDER_REQ
  4395. #define LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY_MASK 0x00000100U
  4396. #define LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY_SHIFT 8U
  4397. #define LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY_WIDTH 1U
  4398. #define LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY_WOCLR 0U
  4399. #define LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY_WOSET 0U
  4400. #define LPDDR4__CONTROLLER_BUSY__REG DENALI_CTL_289
  4401. #define LPDDR4__CONTROLLER_BUSY__FLD LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY
  4402. #define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_MASK 0x00010000U
  4403. #define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_SHIFT 16U
  4404. #define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_WIDTH 1U
  4405. #define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_WOCLR 0U
  4406. #define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_WOSET 0U
  4407. #define LPDDR4__CTRLUPD_REQ__REG DENALI_CTL_289
  4408. #define LPDDR4__CTRLUPD_REQ__FLD LPDDR4__DENALI_CTL_289__CTRLUPD_REQ
  4409. #define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN_MASK 0x01000000U
  4410. #define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN_SHIFT 24U
  4411. #define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN_WIDTH 1U
  4412. #define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN_WOCLR 0U
  4413. #define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN_WOSET 0U
  4414. #define LPDDR4__CTRLUPD_REQ_PER_AREF_EN__REG DENALI_CTL_289
  4415. #define LPDDR4__CTRLUPD_REQ_PER_AREF_EN__FLD LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN
  4416. #define LPDDR4__DENALI_CTL_290_READ_MASK 0x03030301U
  4417. #define LPDDR4__DENALI_CTL_290_WRITE_MASK 0x03030301U
  4418. #define LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE_MASK 0x00000001U
  4419. #define LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE_SHIFT 0U
  4420. #define LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE_WIDTH 1U
  4421. #define LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE_WOCLR 0U
  4422. #define LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE_WOSET 0U
  4423. #define LPDDR4__CTRLUPD_AREF_HP_ENABLE__REG DENALI_CTL_290
  4424. #define LPDDR4__CTRLUPD_AREF_HP_ENABLE__FLD LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE
  4425. #define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F0_MASK 0x00000300U
  4426. #define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F0_SHIFT 8U
  4427. #define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F0_WIDTH 2U
  4428. #define LPDDR4__PREAMBLE_SUPPORT_F0__REG DENALI_CTL_290
  4429. #define LPDDR4__PREAMBLE_SUPPORT_F0__FLD LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F0
  4430. #define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F1_MASK 0x00030000U
  4431. #define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F1_SHIFT 16U
  4432. #define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F1_WIDTH 2U
  4433. #define LPDDR4__PREAMBLE_SUPPORT_F1__REG DENALI_CTL_290
  4434. #define LPDDR4__PREAMBLE_SUPPORT_F1__FLD LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F1
  4435. #define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F2_MASK 0x03000000U
  4436. #define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F2_SHIFT 24U
  4437. #define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F2_WIDTH 2U
  4438. #define LPDDR4__PREAMBLE_SUPPORT_F2__REG DENALI_CTL_290
  4439. #define LPDDR4__PREAMBLE_SUPPORT_F2__FLD LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F2
  4440. #define LPDDR4__DENALI_CTL_291_READ_MASK 0x1F010101U
  4441. #define LPDDR4__DENALI_CTL_291_WRITE_MASK 0x1F010101U
  4442. #define LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN_MASK 0x00000001U
  4443. #define LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN_SHIFT 0U
  4444. #define LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN_WIDTH 1U
  4445. #define LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN_WOCLR 0U
  4446. #define LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN_WOSET 0U
  4447. #define LPDDR4__RD_PREAMBLE_TRAINING_EN__REG DENALI_CTL_291
  4448. #define LPDDR4__RD_PREAMBLE_TRAINING_EN__FLD LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN
  4449. #define LPDDR4__DENALI_CTL_291__WR_DBI_EN_MASK 0x00000100U
  4450. #define LPDDR4__DENALI_CTL_291__WR_DBI_EN_SHIFT 8U
  4451. #define LPDDR4__DENALI_CTL_291__WR_DBI_EN_WIDTH 1U
  4452. #define LPDDR4__DENALI_CTL_291__WR_DBI_EN_WOCLR 0U
  4453. #define LPDDR4__DENALI_CTL_291__WR_DBI_EN_WOSET 0U
  4454. #define LPDDR4__WR_DBI_EN__REG DENALI_CTL_291
  4455. #define LPDDR4__WR_DBI_EN__FLD LPDDR4__DENALI_CTL_291__WR_DBI_EN
  4456. #define LPDDR4__DENALI_CTL_291__RD_DBI_EN_MASK 0x00010000U
  4457. #define LPDDR4__DENALI_CTL_291__RD_DBI_EN_SHIFT 16U
  4458. #define LPDDR4__DENALI_CTL_291__RD_DBI_EN_WIDTH 1U
  4459. #define LPDDR4__DENALI_CTL_291__RD_DBI_EN_WOCLR 0U
  4460. #define LPDDR4__DENALI_CTL_291__RD_DBI_EN_WOSET 0U
  4461. #define LPDDR4__RD_DBI_EN__REG DENALI_CTL_291
  4462. #define LPDDR4__RD_DBI_EN__FLD LPDDR4__DENALI_CTL_291__RD_DBI_EN
  4463. #define LPDDR4__DENALI_CTL_291__DFI_ERROR_MASK 0x1F000000U
  4464. #define LPDDR4__DENALI_CTL_291__DFI_ERROR_SHIFT 24U
  4465. #define LPDDR4__DENALI_CTL_291__DFI_ERROR_WIDTH 5U
  4466. #define LPDDR4__DFI_ERROR__REG DENALI_CTL_291
  4467. #define LPDDR4__DFI_ERROR__FLD LPDDR4__DENALI_CTL_291__DFI_ERROR
  4468. #define LPDDR4__DENALI_CTL_292_READ_MASK 0x000FFFFFU
  4469. #define LPDDR4__DENALI_CTL_292_WRITE_MASK 0x000FFFFFU
  4470. #define LPDDR4__DENALI_CTL_292__DFI_ERROR_INFO_MASK 0x000FFFFFU
  4471. #define LPDDR4__DENALI_CTL_292__DFI_ERROR_INFO_SHIFT 0U
  4472. #define LPDDR4__DENALI_CTL_292__DFI_ERROR_INFO_WIDTH 20U
  4473. #define LPDDR4__DFI_ERROR_INFO__REG DENALI_CTL_292
  4474. #define LPDDR4__DFI_ERROR_INFO__FLD LPDDR4__DENALI_CTL_292__DFI_ERROR_INFO
  4475. #define LPDDR4__DENALI_CTL_292__MC_RESERVED28_MASK 0x01000000U
  4476. #define LPDDR4__DENALI_CTL_292__MC_RESERVED28_SHIFT 24U
  4477. #define LPDDR4__DENALI_CTL_292__MC_RESERVED28_WIDTH 1U
  4478. #define LPDDR4__DENALI_CTL_292__MC_RESERVED28_WOCLR 0U
  4479. #define LPDDR4__DENALI_CTL_292__MC_RESERVED28_WOSET 0U
  4480. #define LPDDR4__MC_RESERVED28__REG DENALI_CTL_292
  4481. #define LPDDR4__MC_RESERVED28__FLD LPDDR4__DENALI_CTL_292__MC_RESERVED28
  4482. #define LPDDR4__DENALI_CTL_293_READ_MASK 0xFFFFFFFFU
  4483. #define LPDDR4__DENALI_CTL_293_WRITE_MASK 0xFFFFFFFFU
  4484. #define LPDDR4__DENALI_CTL_293__INT_STATUS_0_MASK 0xFFFFFFFFU
  4485. #define LPDDR4__DENALI_CTL_293__INT_STATUS_0_SHIFT 0U
  4486. #define LPDDR4__DENALI_CTL_293__INT_STATUS_0_WIDTH 32U
  4487. #define LPDDR4__INT_STATUS_0__REG DENALI_CTL_293
  4488. #define LPDDR4__INT_STATUS_0__FLD LPDDR4__DENALI_CTL_293__INT_STATUS_0
  4489. #define LPDDR4__DENALI_CTL_294_READ_MASK 0x00001FFFU
  4490. #define LPDDR4__DENALI_CTL_294_WRITE_MASK 0x00001FFFU
  4491. #define LPDDR4__DENALI_CTL_294__INT_STATUS_1_MASK 0x00001FFFU
  4492. #define LPDDR4__DENALI_CTL_294__INT_STATUS_1_SHIFT 0U
  4493. #define LPDDR4__DENALI_CTL_294__INT_STATUS_1_WIDTH 13U
  4494. #define LPDDR4__INT_STATUS_1__REG DENALI_CTL_294
  4495. #define LPDDR4__INT_STATUS_1__FLD LPDDR4__DENALI_CTL_294__INT_STATUS_1
  4496. #define LPDDR4__DENALI_CTL_295__INT_ACK_0_MASK 0xFFFFFFFFU
  4497. #define LPDDR4__DENALI_CTL_295__INT_ACK_0_SHIFT 0U
  4498. #define LPDDR4__DENALI_CTL_295__INT_ACK_0_WIDTH 32U
  4499. #define LPDDR4__INT_ACK_0__REG DENALI_CTL_295
  4500. #define LPDDR4__INT_ACK_0__FLD LPDDR4__DENALI_CTL_295__INT_ACK_0
  4501. #define LPDDR4__DENALI_CTL_296__INT_ACK_1_MASK 0x00000FFFU
  4502. #define LPDDR4__DENALI_CTL_296__INT_ACK_1_SHIFT 0U
  4503. #define LPDDR4__DENALI_CTL_296__INT_ACK_1_WIDTH 12U
  4504. #define LPDDR4__INT_ACK_1__REG DENALI_CTL_296
  4505. #define LPDDR4__INT_ACK_1__FLD LPDDR4__DENALI_CTL_296__INT_ACK_1
  4506. #define LPDDR4__DENALI_CTL_297_READ_MASK 0xFFFFFFFFU
  4507. #define LPDDR4__DENALI_CTL_297_WRITE_MASK 0xFFFFFFFFU
  4508. #define LPDDR4__DENALI_CTL_297__INT_MASK_0_MASK 0xFFFFFFFFU
  4509. #define LPDDR4__DENALI_CTL_297__INT_MASK_0_SHIFT 0U
  4510. #define LPDDR4__DENALI_CTL_297__INT_MASK_0_WIDTH 32U
  4511. #define LPDDR4__INT_MASK_0__REG DENALI_CTL_297
  4512. #define LPDDR4__INT_MASK_0__FLD LPDDR4__DENALI_CTL_297__INT_MASK_0
  4513. #define LPDDR4__DENALI_CTL_298_READ_MASK 0x00001FFFU
  4514. #define LPDDR4__DENALI_CTL_298_WRITE_MASK 0x00001FFFU
  4515. #define LPDDR4__DENALI_CTL_298__INT_MASK_1_MASK 0x00001FFFU
  4516. #define LPDDR4__DENALI_CTL_298__INT_MASK_1_SHIFT 0U
  4517. #define LPDDR4__DENALI_CTL_298__INT_MASK_1_WIDTH 13U
  4518. #define LPDDR4__INT_MASK_1__REG DENALI_CTL_298
  4519. #define LPDDR4__INT_MASK_1__FLD LPDDR4__DENALI_CTL_298__INT_MASK_1
  4520. #define LPDDR4__DENALI_CTL_299_READ_MASK 0xFFFFFFFFU
  4521. #define LPDDR4__DENALI_CTL_299_WRITE_MASK 0xFFFFFFFFU
  4522. #define LPDDR4__DENALI_CTL_299__OUT_OF_RANGE_ADDR_0_MASK 0xFFFFFFFFU
  4523. #define LPDDR4__DENALI_CTL_299__OUT_OF_RANGE_ADDR_0_SHIFT 0U
  4524. #define LPDDR4__DENALI_CTL_299__OUT_OF_RANGE_ADDR_0_WIDTH 32U
  4525. #define LPDDR4__OUT_OF_RANGE_ADDR_0__REG DENALI_CTL_299
  4526. #define LPDDR4__OUT_OF_RANGE_ADDR_0__FLD LPDDR4__DENALI_CTL_299__OUT_OF_RANGE_ADDR_0
  4527. #define LPDDR4__DENALI_CTL_300_READ_MASK 0x7F0FFF07U
  4528. #define LPDDR4__DENALI_CTL_300_WRITE_MASK 0x7F0FFF07U
  4529. #define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_ADDR_1_MASK 0x00000007U
  4530. #define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_ADDR_1_SHIFT 0U
  4531. #define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_ADDR_1_WIDTH 3U
  4532. #define LPDDR4__OUT_OF_RANGE_ADDR_1__REG DENALI_CTL_300
  4533. #define LPDDR4__OUT_OF_RANGE_ADDR_1__FLD LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_ADDR_1
  4534. #define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_LENGTH_MASK 0x000FFF00U
  4535. #define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_LENGTH_SHIFT 8U
  4536. #define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_LENGTH_WIDTH 12U
  4537. #define LPDDR4__OUT_OF_RANGE_LENGTH__REG DENALI_CTL_300
  4538. #define LPDDR4__OUT_OF_RANGE_LENGTH__FLD LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_LENGTH
  4539. #define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_TYPE_MASK 0x7F000000U
  4540. #define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_TYPE_SHIFT 24U
  4541. #define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_TYPE_WIDTH 7U
  4542. #define LPDDR4__OUT_OF_RANGE_TYPE__REG DENALI_CTL_300
  4543. #define LPDDR4__OUT_OF_RANGE_TYPE__FLD LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_TYPE
  4544. #define LPDDR4__DENALI_CTL_301_READ_MASK 0x0000003FU
  4545. #define LPDDR4__DENALI_CTL_301_WRITE_MASK 0x0000003FU
  4546. #define LPDDR4__DENALI_CTL_301__OUT_OF_RANGE_SOURCE_ID_MASK 0x0000003FU
  4547. #define LPDDR4__DENALI_CTL_301__OUT_OF_RANGE_SOURCE_ID_SHIFT 0U
  4548. #define LPDDR4__DENALI_CTL_301__OUT_OF_RANGE_SOURCE_ID_WIDTH 6U
  4549. #define LPDDR4__OUT_OF_RANGE_SOURCE_ID__REG DENALI_CTL_301
  4550. #define LPDDR4__OUT_OF_RANGE_SOURCE_ID__FLD LPDDR4__DENALI_CTL_301__OUT_OF_RANGE_SOURCE_ID
  4551. #define LPDDR4__DENALI_CTL_302_READ_MASK 0xFFFFFFFFU
  4552. #define LPDDR4__DENALI_CTL_302_WRITE_MASK 0xFFFFFFFFU
  4553. #define LPDDR4__DENALI_CTL_302__BIST_EXP_DATA_0_MASK 0xFFFFFFFFU
  4554. #define LPDDR4__DENALI_CTL_302__BIST_EXP_DATA_0_SHIFT 0U
  4555. #define LPDDR4__DENALI_CTL_302__BIST_EXP_DATA_0_WIDTH 32U
  4556. #define LPDDR4__BIST_EXP_DATA_0__REG DENALI_CTL_302
  4557. #define LPDDR4__BIST_EXP_DATA_0__FLD LPDDR4__DENALI_CTL_302__BIST_EXP_DATA_0
  4558. #define LPDDR4__DENALI_CTL_303_READ_MASK 0xFFFFFFFFU
  4559. #define LPDDR4__DENALI_CTL_303_WRITE_MASK 0xFFFFFFFFU
  4560. #define LPDDR4__DENALI_CTL_303__BIST_EXP_DATA_1_MASK 0xFFFFFFFFU
  4561. #define LPDDR4__DENALI_CTL_303__BIST_EXP_DATA_1_SHIFT 0U
  4562. #define LPDDR4__DENALI_CTL_303__BIST_EXP_DATA_1_WIDTH 32U
  4563. #define LPDDR4__BIST_EXP_DATA_1__REG DENALI_CTL_303
  4564. #define LPDDR4__BIST_EXP_DATA_1__FLD LPDDR4__DENALI_CTL_303__BIST_EXP_DATA_1
  4565. #define LPDDR4__DENALI_CTL_304_READ_MASK 0xFFFFFFFFU
  4566. #define LPDDR4__DENALI_CTL_304_WRITE_MASK 0xFFFFFFFFU
  4567. #define LPDDR4__DENALI_CTL_304__BIST_EXP_DATA_2_MASK 0xFFFFFFFFU
  4568. #define LPDDR4__DENALI_CTL_304__BIST_EXP_DATA_2_SHIFT 0U
  4569. #define LPDDR4__DENALI_CTL_304__BIST_EXP_DATA_2_WIDTH 32U
  4570. #define LPDDR4__BIST_EXP_DATA_2__REG DENALI_CTL_304
  4571. #define LPDDR4__BIST_EXP_DATA_2__FLD LPDDR4__DENALI_CTL_304__BIST_EXP_DATA_2
  4572. #define LPDDR4__DENALI_CTL_305_READ_MASK 0xFFFFFFFFU
  4573. #define LPDDR4__DENALI_CTL_305_WRITE_MASK 0xFFFFFFFFU
  4574. #define LPDDR4__DENALI_CTL_305__BIST_EXP_DATA_3_MASK 0xFFFFFFFFU
  4575. #define LPDDR4__DENALI_CTL_305__BIST_EXP_DATA_3_SHIFT 0U
  4576. #define LPDDR4__DENALI_CTL_305__BIST_EXP_DATA_3_WIDTH 32U
  4577. #define LPDDR4__BIST_EXP_DATA_3__REG DENALI_CTL_305
  4578. #define LPDDR4__BIST_EXP_DATA_3__FLD LPDDR4__DENALI_CTL_305__BIST_EXP_DATA_3
  4579. #define LPDDR4__DENALI_CTL_306_READ_MASK 0xFFFFFFFFU
  4580. #define LPDDR4__DENALI_CTL_306_WRITE_MASK 0xFFFFFFFFU
  4581. #define LPDDR4__DENALI_CTL_306__BIST_FAIL_DATA_0_MASK 0xFFFFFFFFU
  4582. #define LPDDR4__DENALI_CTL_306__BIST_FAIL_DATA_0_SHIFT 0U
  4583. #define LPDDR4__DENALI_CTL_306__BIST_FAIL_DATA_0_WIDTH 32U
  4584. #define LPDDR4__BIST_FAIL_DATA_0__REG DENALI_CTL_306
  4585. #define LPDDR4__BIST_FAIL_DATA_0__FLD LPDDR4__DENALI_CTL_306__BIST_FAIL_DATA_0
  4586. #define LPDDR4__DENALI_CTL_307_READ_MASK 0xFFFFFFFFU
  4587. #define LPDDR4__DENALI_CTL_307_WRITE_MASK 0xFFFFFFFFU
  4588. #define LPDDR4__DENALI_CTL_307__BIST_FAIL_DATA_1_MASK 0xFFFFFFFFU
  4589. #define LPDDR4__DENALI_CTL_307__BIST_FAIL_DATA_1_SHIFT 0U
  4590. #define LPDDR4__DENALI_CTL_307__BIST_FAIL_DATA_1_WIDTH 32U
  4591. #define LPDDR4__BIST_FAIL_DATA_1__REG DENALI_CTL_307
  4592. #define LPDDR4__BIST_FAIL_DATA_1__FLD LPDDR4__DENALI_CTL_307__BIST_FAIL_DATA_1
  4593. #define LPDDR4__DENALI_CTL_308_READ_MASK 0xFFFFFFFFU
  4594. #define LPDDR4__DENALI_CTL_308_WRITE_MASK 0xFFFFFFFFU
  4595. #define LPDDR4__DENALI_CTL_308__BIST_FAIL_DATA_2_MASK 0xFFFFFFFFU
  4596. #define LPDDR4__DENALI_CTL_308__BIST_FAIL_DATA_2_SHIFT 0U
  4597. #define LPDDR4__DENALI_CTL_308__BIST_FAIL_DATA_2_WIDTH 32U
  4598. #define LPDDR4__BIST_FAIL_DATA_2__REG DENALI_CTL_308
  4599. #define LPDDR4__BIST_FAIL_DATA_2__FLD LPDDR4__DENALI_CTL_308__BIST_FAIL_DATA_2
  4600. #define LPDDR4__DENALI_CTL_309_READ_MASK 0xFFFFFFFFU
  4601. #define LPDDR4__DENALI_CTL_309_WRITE_MASK 0xFFFFFFFFU
  4602. #define LPDDR4__DENALI_CTL_309__BIST_FAIL_DATA_3_MASK 0xFFFFFFFFU
  4603. #define LPDDR4__DENALI_CTL_309__BIST_FAIL_DATA_3_SHIFT 0U
  4604. #define LPDDR4__DENALI_CTL_309__BIST_FAIL_DATA_3_WIDTH 32U
  4605. #define LPDDR4__BIST_FAIL_DATA_3__REG DENALI_CTL_309
  4606. #define LPDDR4__BIST_FAIL_DATA_3__FLD LPDDR4__DENALI_CTL_309__BIST_FAIL_DATA_3
  4607. #define LPDDR4__DENALI_CTL_310_READ_MASK 0xFFFFFFFFU
  4608. #define LPDDR4__DENALI_CTL_310_WRITE_MASK 0xFFFFFFFFU
  4609. #define LPDDR4__DENALI_CTL_310__BIST_FAIL_ADDR_0_MASK 0xFFFFFFFFU
  4610. #define LPDDR4__DENALI_CTL_310__BIST_FAIL_ADDR_0_SHIFT 0U
  4611. #define LPDDR4__DENALI_CTL_310__BIST_FAIL_ADDR_0_WIDTH 32U
  4612. #define LPDDR4__BIST_FAIL_ADDR_0__REG DENALI_CTL_310
  4613. #define LPDDR4__BIST_FAIL_ADDR_0__FLD LPDDR4__DENALI_CTL_310__BIST_FAIL_ADDR_0
  4614. #define LPDDR4__DENALI_CTL_311_READ_MASK 0x00000007U
  4615. #define LPDDR4__DENALI_CTL_311_WRITE_MASK 0x00000007U
  4616. #define LPDDR4__DENALI_CTL_311__BIST_FAIL_ADDR_1_MASK 0x00000007U
  4617. #define LPDDR4__DENALI_CTL_311__BIST_FAIL_ADDR_1_SHIFT 0U
  4618. #define LPDDR4__DENALI_CTL_311__BIST_FAIL_ADDR_1_WIDTH 3U
  4619. #define LPDDR4__BIST_FAIL_ADDR_1__REG DENALI_CTL_311
  4620. #define LPDDR4__BIST_FAIL_ADDR_1__FLD LPDDR4__DENALI_CTL_311__BIST_FAIL_ADDR_1
  4621. #define LPDDR4__DENALI_CTL_312_READ_MASK 0xFFFFFFFFU
  4622. #define LPDDR4__DENALI_CTL_312_WRITE_MASK 0xFFFFFFFFU
  4623. #define LPDDR4__DENALI_CTL_312__PORT_CMD_ERROR_ADDR_0_MASK 0xFFFFFFFFU
  4624. #define LPDDR4__DENALI_CTL_312__PORT_CMD_ERROR_ADDR_0_SHIFT 0U
  4625. #define LPDDR4__DENALI_CTL_312__PORT_CMD_ERROR_ADDR_0_WIDTH 32U
  4626. #define LPDDR4__PORT_CMD_ERROR_ADDR_0__REG DENALI_CTL_312
  4627. #define LPDDR4__PORT_CMD_ERROR_ADDR_0__FLD LPDDR4__DENALI_CTL_312__PORT_CMD_ERROR_ADDR_0
  4628. #define LPDDR4__DENALI_CTL_313_READ_MASK 0x03033F07U
  4629. #define LPDDR4__DENALI_CTL_313_WRITE_MASK 0x03033F07U
  4630. #define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ADDR_1_MASK 0x00000007U
  4631. #define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ADDR_1_SHIFT 0U
  4632. #define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ADDR_1_WIDTH 3U
  4633. #define LPDDR4__PORT_CMD_ERROR_ADDR_1__REG DENALI_CTL_313
  4634. #define LPDDR4__PORT_CMD_ERROR_ADDR_1__FLD LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ADDR_1
  4635. #define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ID_MASK 0x00003F00U
  4636. #define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ID_SHIFT 8U
  4637. #define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ID_WIDTH 6U
  4638. #define LPDDR4__PORT_CMD_ERROR_ID__REG DENALI_CTL_313
  4639. #define LPDDR4__PORT_CMD_ERROR_ID__FLD LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ID
  4640. #define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_TYPE_MASK 0x00030000U
  4641. #define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_TYPE_SHIFT 16U
  4642. #define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_TYPE_WIDTH 2U
  4643. #define LPDDR4__PORT_CMD_ERROR_TYPE__REG DENALI_CTL_313
  4644. #define LPDDR4__PORT_CMD_ERROR_TYPE__FLD LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_TYPE
  4645. #define LPDDR4__DENALI_CTL_313__ODT_RD_MAP_CS0_MASK 0x03000000U
  4646. #define LPDDR4__DENALI_CTL_313__ODT_RD_MAP_CS0_SHIFT 24U
  4647. #define LPDDR4__DENALI_CTL_313__ODT_RD_MAP_CS0_WIDTH 2U
  4648. #define LPDDR4__ODT_RD_MAP_CS0__REG DENALI_CTL_313
  4649. #define LPDDR4__ODT_RD_MAP_CS0__FLD LPDDR4__DENALI_CTL_313__ODT_RD_MAP_CS0
  4650. #define LPDDR4__DENALI_CTL_314_READ_MASK 0xFF030303U
  4651. #define LPDDR4__DENALI_CTL_314_WRITE_MASK 0xFF030303U
  4652. #define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS0_MASK 0x00000003U
  4653. #define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS0_SHIFT 0U
  4654. #define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS0_WIDTH 2U
  4655. #define LPDDR4__ODT_WR_MAP_CS0__REG DENALI_CTL_314
  4656. #define LPDDR4__ODT_WR_MAP_CS0__FLD LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS0
  4657. #define LPDDR4__DENALI_CTL_314__ODT_RD_MAP_CS1_MASK 0x00000300U
  4658. #define LPDDR4__DENALI_CTL_314__ODT_RD_MAP_CS1_SHIFT 8U
  4659. #define LPDDR4__DENALI_CTL_314__ODT_RD_MAP_CS1_WIDTH 2U
  4660. #define LPDDR4__ODT_RD_MAP_CS1__REG DENALI_CTL_314
  4661. #define LPDDR4__ODT_RD_MAP_CS1__FLD LPDDR4__DENALI_CTL_314__ODT_RD_MAP_CS1
  4662. #define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS1_MASK 0x00030000U
  4663. #define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS1_SHIFT 16U
  4664. #define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS1_WIDTH 2U
  4665. #define LPDDR4__ODT_WR_MAP_CS1__REG DENALI_CTL_314
  4666. #define LPDDR4__ODT_WR_MAP_CS1__FLD LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS1
  4667. #define LPDDR4__DENALI_CTL_314__TODTL_2CMD_F0_MASK 0xFF000000U
  4668. #define LPDDR4__DENALI_CTL_314__TODTL_2CMD_F0_SHIFT 24U
  4669. #define LPDDR4__DENALI_CTL_314__TODTL_2CMD_F0_WIDTH 8U
  4670. #define LPDDR4__TODTL_2CMD_F0__REG DENALI_CTL_314
  4671. #define LPDDR4__TODTL_2CMD_F0__FLD LPDDR4__DENALI_CTL_314__TODTL_2CMD_F0
  4672. #define LPDDR4__DENALI_CTL_315_READ_MASK 0x0FFF0F0FU
  4673. #define LPDDR4__DENALI_CTL_315_WRITE_MASK 0x0FFF0F0FU
  4674. #define LPDDR4__DENALI_CTL_315__TODTH_WR_F0_MASK 0x0000000FU
  4675. #define LPDDR4__DENALI_CTL_315__TODTH_WR_F0_SHIFT 0U
  4676. #define LPDDR4__DENALI_CTL_315__TODTH_WR_F0_WIDTH 4U
  4677. #define LPDDR4__TODTH_WR_F0__REG DENALI_CTL_315
  4678. #define LPDDR4__TODTH_WR_F0__FLD LPDDR4__DENALI_CTL_315__TODTH_WR_F0
  4679. #define LPDDR4__DENALI_CTL_315__TODTH_RD_F0_MASK 0x00000F00U
  4680. #define LPDDR4__DENALI_CTL_315__TODTH_RD_F0_SHIFT 8U
  4681. #define LPDDR4__DENALI_CTL_315__TODTH_RD_F0_WIDTH 4U
  4682. #define LPDDR4__TODTH_RD_F0__REG DENALI_CTL_315
  4683. #define LPDDR4__TODTH_RD_F0__FLD LPDDR4__DENALI_CTL_315__TODTH_RD_F0
  4684. #define LPDDR4__DENALI_CTL_315__TODTL_2CMD_F1_MASK 0x00FF0000U
  4685. #define LPDDR4__DENALI_CTL_315__TODTL_2CMD_F1_SHIFT 16U
  4686. #define LPDDR4__DENALI_CTL_315__TODTL_2CMD_F1_WIDTH 8U
  4687. #define LPDDR4__TODTL_2CMD_F1__REG DENALI_CTL_315
  4688. #define LPDDR4__TODTL_2CMD_F1__FLD LPDDR4__DENALI_CTL_315__TODTL_2CMD_F1
  4689. #define LPDDR4__DENALI_CTL_315__TODTH_WR_F1_MASK 0x0F000000U
  4690. #define LPDDR4__DENALI_CTL_315__TODTH_WR_F1_SHIFT 24U
  4691. #define LPDDR4__DENALI_CTL_315__TODTH_WR_F1_WIDTH 4U
  4692. #define LPDDR4__TODTH_WR_F1__REG DENALI_CTL_315
  4693. #define LPDDR4__TODTH_WR_F1__FLD LPDDR4__DENALI_CTL_315__TODTH_WR_F1
  4694. #define LPDDR4__DENALI_CTL_316_READ_MASK 0x0F0FFF0FU
  4695. #define LPDDR4__DENALI_CTL_316_WRITE_MASK 0x0F0FFF0FU
  4696. #define LPDDR4__DENALI_CTL_316__TODTH_RD_F1_MASK 0x0000000FU
  4697. #define LPDDR4__DENALI_CTL_316__TODTH_RD_F1_SHIFT 0U
  4698. #define LPDDR4__DENALI_CTL_316__TODTH_RD_F1_WIDTH 4U
  4699. #define LPDDR4__TODTH_RD_F1__REG DENALI_CTL_316
  4700. #define LPDDR4__TODTH_RD_F1__FLD LPDDR4__DENALI_CTL_316__TODTH_RD_F1
  4701. #define LPDDR4__DENALI_CTL_316__TODTL_2CMD_F2_MASK 0x0000FF00U
  4702. #define LPDDR4__DENALI_CTL_316__TODTL_2CMD_F2_SHIFT 8U
  4703. #define LPDDR4__DENALI_CTL_316__TODTL_2CMD_F2_WIDTH 8U
  4704. #define LPDDR4__TODTL_2CMD_F2__REG DENALI_CTL_316
  4705. #define LPDDR4__TODTL_2CMD_F2__FLD LPDDR4__DENALI_CTL_316__TODTL_2CMD_F2
  4706. #define LPDDR4__DENALI_CTL_316__TODTH_WR_F2_MASK 0x000F0000U
  4707. #define LPDDR4__DENALI_CTL_316__TODTH_WR_F2_SHIFT 16U
  4708. #define LPDDR4__DENALI_CTL_316__TODTH_WR_F2_WIDTH 4U
  4709. #define LPDDR4__TODTH_WR_F2__REG DENALI_CTL_316
  4710. #define LPDDR4__TODTH_WR_F2__FLD LPDDR4__DENALI_CTL_316__TODTH_WR_F2
  4711. #define LPDDR4__DENALI_CTL_316__TODTH_RD_F2_MASK 0x0F000000U
  4712. #define LPDDR4__DENALI_CTL_316__TODTH_RD_F2_SHIFT 24U
  4713. #define LPDDR4__DENALI_CTL_316__TODTH_RD_F2_WIDTH 4U
  4714. #define LPDDR4__TODTH_RD_F2__REG DENALI_CTL_316
  4715. #define LPDDR4__TODTH_RD_F2__FLD LPDDR4__DENALI_CTL_316__TODTH_RD_F2
  4716. #define LPDDR4__DENALI_CTL_317_READ_MASK 0x01010101U
  4717. #define LPDDR4__DENALI_CTL_317_WRITE_MASK 0x01010101U
  4718. #define LPDDR4__DENALI_CTL_317__ODT_EN_F0_MASK 0x00000001U
  4719. #define LPDDR4__DENALI_CTL_317__ODT_EN_F0_SHIFT 0U
  4720. #define LPDDR4__DENALI_CTL_317__ODT_EN_F0_WIDTH 1U
  4721. #define LPDDR4__DENALI_CTL_317__ODT_EN_F0_WOCLR 0U
  4722. #define LPDDR4__DENALI_CTL_317__ODT_EN_F0_WOSET 0U
  4723. #define LPDDR4__ODT_EN_F0__REG DENALI_CTL_317
  4724. #define LPDDR4__ODT_EN_F0__FLD LPDDR4__DENALI_CTL_317__ODT_EN_F0
  4725. #define LPDDR4__DENALI_CTL_317__ODT_EN_F1_MASK 0x00000100U
  4726. #define LPDDR4__DENALI_CTL_317__ODT_EN_F1_SHIFT 8U
  4727. #define LPDDR4__DENALI_CTL_317__ODT_EN_F1_WIDTH 1U
  4728. #define LPDDR4__DENALI_CTL_317__ODT_EN_F1_WOCLR 0U
  4729. #define LPDDR4__DENALI_CTL_317__ODT_EN_F1_WOSET 0U
  4730. #define LPDDR4__ODT_EN_F1__REG DENALI_CTL_317
  4731. #define LPDDR4__ODT_EN_F1__FLD LPDDR4__DENALI_CTL_317__ODT_EN_F1
  4732. #define LPDDR4__DENALI_CTL_317__ODT_EN_F2_MASK 0x00010000U
  4733. #define LPDDR4__DENALI_CTL_317__ODT_EN_F2_SHIFT 16U
  4734. #define LPDDR4__DENALI_CTL_317__ODT_EN_F2_WIDTH 1U
  4735. #define LPDDR4__DENALI_CTL_317__ODT_EN_F2_WOCLR 0U
  4736. #define LPDDR4__DENALI_CTL_317__ODT_EN_F2_WOSET 0U
  4737. #define LPDDR4__ODT_EN_F2__REG DENALI_CTL_317
  4738. #define LPDDR4__ODT_EN_F2__FLD LPDDR4__DENALI_CTL_317__ODT_EN_F2
  4739. #define LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD_MASK 0x01000000U
  4740. #define LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD_SHIFT 24U
  4741. #define LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD_WIDTH 1U
  4742. #define LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD_WOCLR 0U
  4743. #define LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD_WOSET 0U
  4744. #define LPDDR4__EN_ODT_ASSERT_EXCEPT_RD__REG DENALI_CTL_317
  4745. #define LPDDR4__EN_ODT_ASSERT_EXCEPT_RD__FLD LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD
  4746. #define LPDDR4__DENALI_CTL_318_READ_MASK 0x3F3F3F3FU
  4747. #define LPDDR4__DENALI_CTL_318_WRITE_MASK 0x3F3F3F3FU
  4748. #define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F0_MASK 0x0000003FU
  4749. #define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F0_SHIFT 0U
  4750. #define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F0_WIDTH 6U
  4751. #define LPDDR4__WR_TO_ODTH_F0__REG DENALI_CTL_318
  4752. #define LPDDR4__WR_TO_ODTH_F0__FLD LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F0
  4753. #define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F1_MASK 0x00003F00U
  4754. #define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F1_SHIFT 8U
  4755. #define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F1_WIDTH 6U
  4756. #define LPDDR4__WR_TO_ODTH_F1__REG DENALI_CTL_318
  4757. #define LPDDR4__WR_TO_ODTH_F1__FLD LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F1
  4758. #define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F2_MASK 0x003F0000U
  4759. #define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F2_SHIFT 16U
  4760. #define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F2_WIDTH 6U
  4761. #define LPDDR4__WR_TO_ODTH_F2__REG DENALI_CTL_318
  4762. #define LPDDR4__WR_TO_ODTH_F2__FLD LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F2
  4763. #define LPDDR4__DENALI_CTL_318__RD_TO_ODTH_F0_MASK 0x3F000000U
  4764. #define LPDDR4__DENALI_CTL_318__RD_TO_ODTH_F0_SHIFT 24U
  4765. #define LPDDR4__DENALI_CTL_318__RD_TO_ODTH_F0_WIDTH 6U
  4766. #define LPDDR4__RD_TO_ODTH_F0__REG DENALI_CTL_318
  4767. #define LPDDR4__RD_TO_ODTH_F0__FLD LPDDR4__DENALI_CTL_318__RD_TO_ODTH_F0
  4768. #define LPDDR4__DENALI_CTL_319_READ_MASK 0x1F1F3F3FU
  4769. #define LPDDR4__DENALI_CTL_319_WRITE_MASK 0x1F1F3F3FU
  4770. #define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F1_MASK 0x0000003FU
  4771. #define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F1_SHIFT 0U
  4772. #define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F1_WIDTH 6U
  4773. #define LPDDR4__RD_TO_ODTH_F1__REG DENALI_CTL_319
  4774. #define LPDDR4__RD_TO_ODTH_F1__FLD LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F1
  4775. #define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F2_MASK 0x00003F00U
  4776. #define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F2_SHIFT 8U
  4777. #define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F2_WIDTH 6U
  4778. #define LPDDR4__RD_TO_ODTH_F2__REG DENALI_CTL_319
  4779. #define LPDDR4__RD_TO_ODTH_F2__FLD LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F2
  4780. #define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F0_MASK 0x001F0000U
  4781. #define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F0_SHIFT 16U
  4782. #define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F0_WIDTH 5U
  4783. #define LPDDR4__RW2MRW_DLY_F0__REG DENALI_CTL_319
  4784. #define LPDDR4__RW2MRW_DLY_F0__FLD LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F0
  4785. #define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F1_MASK 0x1F000000U
  4786. #define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F1_SHIFT 24U
  4787. #define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F1_WIDTH 5U
  4788. #define LPDDR4__RW2MRW_DLY_F1__REG DENALI_CTL_319
  4789. #define LPDDR4__RW2MRW_DLY_F1__FLD LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F1
  4790. #define LPDDR4__DENALI_CTL_320_READ_MASK 0x1F1F1F1FU
  4791. #define LPDDR4__DENALI_CTL_320_WRITE_MASK 0x1F1F1F1FU
  4792. #define LPDDR4__DENALI_CTL_320__RW2MRW_DLY_F2_MASK 0x0000001FU
  4793. #define LPDDR4__DENALI_CTL_320__RW2MRW_DLY_F2_SHIFT 0U
  4794. #define LPDDR4__DENALI_CTL_320__RW2MRW_DLY_F2_WIDTH 5U
  4795. #define LPDDR4__RW2MRW_DLY_F2__REG DENALI_CTL_320
  4796. #define LPDDR4__RW2MRW_DLY_F2__FLD LPDDR4__DENALI_CTL_320__RW2MRW_DLY_F2
  4797. #define LPDDR4__DENALI_CTL_320__R2R_DIFFCS_DLY_F0_MASK 0x00001F00U
  4798. #define LPDDR4__DENALI_CTL_320__R2R_DIFFCS_DLY_F0_SHIFT 8U
  4799. #define LPDDR4__DENALI_CTL_320__R2R_DIFFCS_DLY_F0_WIDTH 5U
  4800. #define LPDDR4__R2R_DIFFCS_DLY_F0__REG DENALI_CTL_320
  4801. #define LPDDR4__R2R_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_320__R2R_DIFFCS_DLY_F0
  4802. #define LPDDR4__DENALI_CTL_320__R2W_DIFFCS_DLY_F0_MASK 0x001F0000U
  4803. #define LPDDR4__DENALI_CTL_320__R2W_DIFFCS_DLY_F0_SHIFT 16U
  4804. #define LPDDR4__DENALI_CTL_320__R2W_DIFFCS_DLY_F0_WIDTH 5U
  4805. #define LPDDR4__R2W_DIFFCS_DLY_F0__REG DENALI_CTL_320
  4806. #define LPDDR4__R2W_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_320__R2W_DIFFCS_DLY_F0
  4807. #define LPDDR4__DENALI_CTL_320__W2R_DIFFCS_DLY_F0_MASK 0x1F000000U
  4808. #define LPDDR4__DENALI_CTL_320__W2R_DIFFCS_DLY_F0_SHIFT 24U
  4809. #define LPDDR4__DENALI_CTL_320__W2R_DIFFCS_DLY_F0_WIDTH 5U
  4810. #define LPDDR4__W2R_DIFFCS_DLY_F0__REG DENALI_CTL_320
  4811. #define LPDDR4__W2R_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_320__W2R_DIFFCS_DLY_F0
  4812. #define LPDDR4__DENALI_CTL_321_READ_MASK 0x1F1F1F1FU
  4813. #define LPDDR4__DENALI_CTL_321_WRITE_MASK 0x1F1F1F1FU
  4814. #define LPDDR4__DENALI_CTL_321__W2W_DIFFCS_DLY_F0_MASK 0x0000001FU
  4815. #define LPDDR4__DENALI_CTL_321__W2W_DIFFCS_DLY_F0_SHIFT 0U
  4816. #define LPDDR4__DENALI_CTL_321__W2W_DIFFCS_DLY_F0_WIDTH 5U
  4817. #define LPDDR4__W2W_DIFFCS_DLY_F0__REG DENALI_CTL_321
  4818. #define LPDDR4__W2W_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_321__W2W_DIFFCS_DLY_F0
  4819. #define LPDDR4__DENALI_CTL_321__R2R_DIFFCS_DLY_F1_MASK 0x00001F00U
  4820. #define LPDDR4__DENALI_CTL_321__R2R_DIFFCS_DLY_F1_SHIFT 8U
  4821. #define LPDDR4__DENALI_CTL_321__R2R_DIFFCS_DLY_F1_WIDTH 5U
  4822. #define LPDDR4__R2R_DIFFCS_DLY_F1__REG DENALI_CTL_321
  4823. #define LPDDR4__R2R_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_321__R2R_DIFFCS_DLY_F1
  4824. #define LPDDR4__DENALI_CTL_321__R2W_DIFFCS_DLY_F1_MASK 0x001F0000U
  4825. #define LPDDR4__DENALI_CTL_321__R2W_DIFFCS_DLY_F1_SHIFT 16U
  4826. #define LPDDR4__DENALI_CTL_321__R2W_DIFFCS_DLY_F1_WIDTH 5U
  4827. #define LPDDR4__R2W_DIFFCS_DLY_F1__REG DENALI_CTL_321
  4828. #define LPDDR4__R2W_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_321__R2W_DIFFCS_DLY_F1
  4829. #define LPDDR4__DENALI_CTL_321__W2R_DIFFCS_DLY_F1_MASK 0x1F000000U
  4830. #define LPDDR4__DENALI_CTL_321__W2R_DIFFCS_DLY_F1_SHIFT 24U
  4831. #define LPDDR4__DENALI_CTL_321__W2R_DIFFCS_DLY_F1_WIDTH 5U
  4832. #define LPDDR4__W2R_DIFFCS_DLY_F1__REG DENALI_CTL_321
  4833. #define LPDDR4__W2R_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_321__W2R_DIFFCS_DLY_F1
  4834. #define LPDDR4__DENALI_CTL_322_READ_MASK 0x1F1F1F1FU
  4835. #define LPDDR4__DENALI_CTL_322_WRITE_MASK 0x1F1F1F1FU
  4836. #define LPDDR4__DENALI_CTL_322__W2W_DIFFCS_DLY_F1_MASK 0x0000001FU
  4837. #define LPDDR4__DENALI_CTL_322__W2W_DIFFCS_DLY_F1_SHIFT 0U
  4838. #define LPDDR4__DENALI_CTL_322__W2W_DIFFCS_DLY_F1_WIDTH 5U
  4839. #define LPDDR4__W2W_DIFFCS_DLY_F1__REG DENALI_CTL_322
  4840. #define LPDDR4__W2W_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_322__W2W_DIFFCS_DLY_F1
  4841. #define LPDDR4__DENALI_CTL_322__R2R_DIFFCS_DLY_F2_MASK 0x00001F00U
  4842. #define LPDDR4__DENALI_CTL_322__R2R_DIFFCS_DLY_F2_SHIFT 8U
  4843. #define LPDDR4__DENALI_CTL_322__R2R_DIFFCS_DLY_F2_WIDTH 5U
  4844. #define LPDDR4__R2R_DIFFCS_DLY_F2__REG DENALI_CTL_322
  4845. #define LPDDR4__R2R_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_322__R2R_DIFFCS_DLY_F2
  4846. #define LPDDR4__DENALI_CTL_322__R2W_DIFFCS_DLY_F2_MASK 0x001F0000U
  4847. #define LPDDR4__DENALI_CTL_322__R2W_DIFFCS_DLY_F2_SHIFT 16U
  4848. #define LPDDR4__DENALI_CTL_322__R2W_DIFFCS_DLY_F2_WIDTH 5U
  4849. #define LPDDR4__R2W_DIFFCS_DLY_F2__REG DENALI_CTL_322
  4850. #define LPDDR4__R2W_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_322__R2W_DIFFCS_DLY_F2
  4851. #define LPDDR4__DENALI_CTL_322__W2R_DIFFCS_DLY_F2_MASK 0x1F000000U
  4852. #define LPDDR4__DENALI_CTL_322__W2R_DIFFCS_DLY_F2_SHIFT 24U
  4853. #define LPDDR4__DENALI_CTL_322__W2R_DIFFCS_DLY_F2_WIDTH 5U
  4854. #define LPDDR4__W2R_DIFFCS_DLY_F2__REG DENALI_CTL_322
  4855. #define LPDDR4__W2R_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_322__W2R_DIFFCS_DLY_F2
  4856. #define LPDDR4__DENALI_CTL_323_READ_MASK 0x1F1F1F1FU
  4857. #define LPDDR4__DENALI_CTL_323_WRITE_MASK 0x1F1F1F1FU
  4858. #define LPDDR4__DENALI_CTL_323__W2W_DIFFCS_DLY_F2_MASK 0x0000001FU
  4859. #define LPDDR4__DENALI_CTL_323__W2W_DIFFCS_DLY_F2_SHIFT 0U
  4860. #define LPDDR4__DENALI_CTL_323__W2W_DIFFCS_DLY_F2_WIDTH 5U
  4861. #define LPDDR4__W2W_DIFFCS_DLY_F2__REG DENALI_CTL_323
  4862. #define LPDDR4__W2W_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_323__W2W_DIFFCS_DLY_F2
  4863. #define LPDDR4__DENALI_CTL_323__R2R_SAMECS_DLY_MASK 0x00001F00U
  4864. #define LPDDR4__DENALI_CTL_323__R2R_SAMECS_DLY_SHIFT 8U
  4865. #define LPDDR4__DENALI_CTL_323__R2R_SAMECS_DLY_WIDTH 5U
  4866. #define LPDDR4__R2R_SAMECS_DLY__REG DENALI_CTL_323
  4867. #define LPDDR4__R2R_SAMECS_DLY__FLD LPDDR4__DENALI_CTL_323__R2R_SAMECS_DLY
  4868. #define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F0_MASK 0x001F0000U
  4869. #define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F0_SHIFT 16U
  4870. #define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F0_WIDTH 5U
  4871. #define LPDDR4__R2W_SAMECS_DLY_F0__REG DENALI_CTL_323
  4872. #define LPDDR4__R2W_SAMECS_DLY_F0__FLD LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F0
  4873. #define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F1_MASK 0x1F000000U
  4874. #define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F1_SHIFT 24U
  4875. #define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F1_WIDTH 5U
  4876. #define LPDDR4__R2W_SAMECS_DLY_F1__REG DENALI_CTL_323
  4877. #define LPDDR4__R2W_SAMECS_DLY_F1__FLD LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F1
  4878. #define LPDDR4__DENALI_CTL_324_READ_MASK 0x0F1F1F1FU
  4879. #define LPDDR4__DENALI_CTL_324_WRITE_MASK 0x0F1F1F1FU
  4880. #define LPDDR4__DENALI_CTL_324__R2W_SAMECS_DLY_F2_MASK 0x0000001FU
  4881. #define LPDDR4__DENALI_CTL_324__R2W_SAMECS_DLY_F2_SHIFT 0U
  4882. #define LPDDR4__DENALI_CTL_324__R2W_SAMECS_DLY_F2_WIDTH 5U
  4883. #define LPDDR4__R2W_SAMECS_DLY_F2__REG DENALI_CTL_324
  4884. #define LPDDR4__R2W_SAMECS_DLY_F2__FLD LPDDR4__DENALI_CTL_324__R2W_SAMECS_DLY_F2
  4885. #define LPDDR4__DENALI_CTL_324__W2R_SAMECS_DLY_MASK 0x00001F00U
  4886. #define LPDDR4__DENALI_CTL_324__W2R_SAMECS_DLY_SHIFT 8U
  4887. #define LPDDR4__DENALI_CTL_324__W2R_SAMECS_DLY_WIDTH 5U
  4888. #define LPDDR4__W2R_SAMECS_DLY__REG DENALI_CTL_324
  4889. #define LPDDR4__W2R_SAMECS_DLY__FLD LPDDR4__DENALI_CTL_324__W2R_SAMECS_DLY
  4890. #define LPDDR4__DENALI_CTL_324__W2W_SAMECS_DLY_MASK 0x001F0000U
  4891. #define LPDDR4__DENALI_CTL_324__W2W_SAMECS_DLY_SHIFT 16U
  4892. #define LPDDR4__DENALI_CTL_324__W2W_SAMECS_DLY_WIDTH 5U
  4893. #define LPDDR4__W2W_SAMECS_DLY__REG DENALI_CTL_324
  4894. #define LPDDR4__W2W_SAMECS_DLY__FLD LPDDR4__DENALI_CTL_324__W2W_SAMECS_DLY
  4895. #define LPDDR4__DENALI_CTL_324__TDQSCK_MAX_F0_MASK 0x0F000000U
  4896. #define LPDDR4__DENALI_CTL_324__TDQSCK_MAX_F0_SHIFT 24U
  4897. #define LPDDR4__DENALI_CTL_324__TDQSCK_MAX_F0_WIDTH 4U
  4898. #define LPDDR4__TDQSCK_MAX_F0__REG DENALI_CTL_324
  4899. #define LPDDR4__TDQSCK_MAX_F0__FLD LPDDR4__DENALI_CTL_324__TDQSCK_MAX_F0
  4900. #define LPDDR4__DENALI_CTL_325_READ_MASK 0x0F070F07U
  4901. #define LPDDR4__DENALI_CTL_325_WRITE_MASK 0x0F070F07U
  4902. #define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F0_MASK 0x00000007U
  4903. #define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F0_SHIFT 0U
  4904. #define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F0_WIDTH 3U
  4905. #define LPDDR4__TDQSCK_MIN_F0__REG DENALI_CTL_325
  4906. #define LPDDR4__TDQSCK_MIN_F0__FLD LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F0
  4907. #define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F1_MASK 0x00000F00U
  4908. #define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F1_SHIFT 8U
  4909. #define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F1_WIDTH 4U
  4910. #define LPDDR4__TDQSCK_MAX_F1__REG DENALI_CTL_325
  4911. #define LPDDR4__TDQSCK_MAX_F1__FLD LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F1
  4912. #define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F1_MASK 0x00070000U
  4913. #define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F1_SHIFT 16U
  4914. #define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F1_WIDTH 3U
  4915. #define LPDDR4__TDQSCK_MIN_F1__REG DENALI_CTL_325
  4916. #define LPDDR4__TDQSCK_MIN_F1__FLD LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F1
  4917. #define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F2_MASK 0x0F000000U
  4918. #define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F2_SHIFT 24U
  4919. #define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F2_WIDTH 4U
  4920. #define LPDDR4__TDQSCK_MAX_F2__REG DENALI_CTL_325
  4921. #define LPDDR4__TDQSCK_MAX_F2__FLD LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F2
  4922. #define LPDDR4__DENALI_CTL_326_READ_MASK 0x00000707U
  4923. #define LPDDR4__DENALI_CTL_326_WRITE_MASK 0x00000707U
  4924. #define LPDDR4__DENALI_CTL_326__TDQSCK_MIN_F2_MASK 0x00000007U
  4925. #define LPDDR4__DENALI_CTL_326__TDQSCK_MIN_F2_SHIFT 0U
  4926. #define LPDDR4__DENALI_CTL_326__TDQSCK_MIN_F2_WIDTH 3U
  4927. #define LPDDR4__TDQSCK_MIN_F2__REG DENALI_CTL_326
  4928. #define LPDDR4__TDQSCK_MIN_F2__FLD LPDDR4__DENALI_CTL_326__TDQSCK_MIN_F2
  4929. #define LPDDR4__DENALI_CTL_326__SW_LEVELING_MODE_MASK 0x00000700U
  4930. #define LPDDR4__DENALI_CTL_326__SW_LEVELING_MODE_SHIFT 8U
  4931. #define LPDDR4__DENALI_CTL_326__SW_LEVELING_MODE_WIDTH 3U
  4932. #define LPDDR4__SW_LEVELING_MODE__REG DENALI_CTL_326
  4933. #define LPDDR4__SW_LEVELING_MODE__FLD LPDDR4__DENALI_CTL_326__SW_LEVELING_MODE
  4934. #define LPDDR4__DENALI_CTL_326__SWLVL_LOAD_MASK 0x00010000U
  4935. #define LPDDR4__DENALI_CTL_326__SWLVL_LOAD_SHIFT 16U
  4936. #define LPDDR4__DENALI_CTL_326__SWLVL_LOAD_WIDTH 1U
  4937. #define LPDDR4__DENALI_CTL_326__SWLVL_LOAD_WOCLR 0U
  4938. #define LPDDR4__DENALI_CTL_326__SWLVL_LOAD_WOSET 0U
  4939. #define LPDDR4__SWLVL_LOAD__REG DENALI_CTL_326
  4940. #define LPDDR4__SWLVL_LOAD__FLD LPDDR4__DENALI_CTL_326__SWLVL_LOAD
  4941. #define LPDDR4__DENALI_CTL_326__SWLVL_START_MASK 0x01000000U
  4942. #define LPDDR4__DENALI_CTL_326__SWLVL_START_SHIFT 24U
  4943. #define LPDDR4__DENALI_CTL_326__SWLVL_START_WIDTH 1U
  4944. #define LPDDR4__DENALI_CTL_326__SWLVL_START_WOCLR 0U
  4945. #define LPDDR4__DENALI_CTL_326__SWLVL_START_WOSET 0U
  4946. #define LPDDR4__SWLVL_START__REG DENALI_CTL_326
  4947. #define LPDDR4__SWLVL_START__FLD LPDDR4__DENALI_CTL_326__SWLVL_START
  4948. #define LPDDR4__DENALI_CTL_327_READ_MASK 0x01010100U
  4949. #define LPDDR4__DENALI_CTL_327_WRITE_MASK 0x01010100U
  4950. #define LPDDR4__DENALI_CTL_327__SWLVL_EXIT_MASK 0x00000001U
  4951. #define LPDDR4__DENALI_CTL_327__SWLVL_EXIT_SHIFT 0U
  4952. #define LPDDR4__DENALI_CTL_327__SWLVL_EXIT_WIDTH 1U
  4953. #define LPDDR4__DENALI_CTL_327__SWLVL_EXIT_WOCLR 0U
  4954. #define LPDDR4__DENALI_CTL_327__SWLVL_EXIT_WOSET 0U
  4955. #define LPDDR4__SWLVL_EXIT__REG DENALI_CTL_327
  4956. #define LPDDR4__SWLVL_EXIT__FLD LPDDR4__DENALI_CTL_327__SWLVL_EXIT
  4957. #define LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE_MASK 0x00000100U
  4958. #define LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE_SHIFT 8U
  4959. #define LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE_WIDTH 1U
  4960. #define LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE_WOCLR 0U
  4961. #define LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE_WOSET 0U
  4962. #define LPDDR4__SWLVL_OP_DONE__REG DENALI_CTL_327
  4963. #define LPDDR4__SWLVL_OP_DONE__FLD LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE
  4964. #define LPDDR4__DENALI_CTL_327__SWLVL_RESP_0_MASK 0x00010000U
  4965. #define LPDDR4__DENALI_CTL_327__SWLVL_RESP_0_SHIFT 16U
  4966. #define LPDDR4__DENALI_CTL_327__SWLVL_RESP_0_WIDTH 1U
  4967. #define LPDDR4__DENALI_CTL_327__SWLVL_RESP_0_WOCLR 0U
  4968. #define LPDDR4__DENALI_CTL_327__SWLVL_RESP_0_WOSET 0U
  4969. #define LPDDR4__SWLVL_RESP_0__REG DENALI_CTL_327
  4970. #define LPDDR4__SWLVL_RESP_0__FLD LPDDR4__DENALI_CTL_327__SWLVL_RESP_0
  4971. #define LPDDR4__DENALI_CTL_327__SWLVL_RESP_1_MASK 0x01000000U
  4972. #define LPDDR4__DENALI_CTL_327__SWLVL_RESP_1_SHIFT 24U
  4973. #define LPDDR4__DENALI_CTL_327__SWLVL_RESP_1_WIDTH 1U
  4974. #define LPDDR4__DENALI_CTL_327__SWLVL_RESP_1_WOCLR 0U
  4975. #define LPDDR4__DENALI_CTL_327__SWLVL_RESP_1_WOSET 0U
  4976. #define LPDDR4__SWLVL_RESP_1__REG DENALI_CTL_327
  4977. #define LPDDR4__SWLVL_RESP_1__FLD LPDDR4__DENALI_CTL_327__SWLVL_RESP_1
  4978. #define LPDDR4__DENALI_CTL_328_READ_MASK 0x00010101U
  4979. #define LPDDR4__DENALI_CTL_328_WRITE_MASK 0x00010101U
  4980. #define LPDDR4__DENALI_CTL_328__SWLVL_RESP_2_MASK 0x00000001U
  4981. #define LPDDR4__DENALI_CTL_328__SWLVL_RESP_2_SHIFT 0U
  4982. #define LPDDR4__DENALI_CTL_328__SWLVL_RESP_2_WIDTH 1U
  4983. #define LPDDR4__DENALI_CTL_328__SWLVL_RESP_2_WOCLR 0U
  4984. #define LPDDR4__DENALI_CTL_328__SWLVL_RESP_2_WOSET 0U
  4985. #define LPDDR4__SWLVL_RESP_2__REG DENALI_CTL_328
  4986. #define LPDDR4__SWLVL_RESP_2__FLD LPDDR4__DENALI_CTL_328__SWLVL_RESP_2
  4987. #define LPDDR4__DENALI_CTL_328__SWLVL_RESP_3_MASK 0x00000100U
  4988. #define LPDDR4__DENALI_CTL_328__SWLVL_RESP_3_SHIFT 8U
  4989. #define LPDDR4__DENALI_CTL_328__SWLVL_RESP_3_WIDTH 1U
  4990. #define LPDDR4__DENALI_CTL_328__SWLVL_RESP_3_WOCLR 0U
  4991. #define LPDDR4__DENALI_CTL_328__SWLVL_RESP_3_WOSET 0U
  4992. #define LPDDR4__SWLVL_RESP_3__REG DENALI_CTL_328
  4993. #define LPDDR4__SWLVL_RESP_3__FLD LPDDR4__DENALI_CTL_328__SWLVL_RESP_3
  4994. #define LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN_MASK 0x00010000U
  4995. #define LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN_SHIFT 16U
  4996. #define LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN_WIDTH 1U
  4997. #define LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN_WOCLR 0U
  4998. #define LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN_WOSET 0U
  4999. #define LPDDR4__PHYUPD_APPEND_EN__REG DENALI_CTL_328
  5000. #define LPDDR4__PHYUPD_APPEND_EN__FLD LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN
  5001. #define LPDDR4__DENALI_CTL_328__WRLVL_REQ_MASK 0x01000000U
  5002. #define LPDDR4__DENALI_CTL_328__WRLVL_REQ_SHIFT 24U
  5003. #define LPDDR4__DENALI_CTL_328__WRLVL_REQ_WIDTH 1U
  5004. #define LPDDR4__DENALI_CTL_328__WRLVL_REQ_WOCLR 0U
  5005. #define LPDDR4__DENALI_CTL_328__WRLVL_REQ_WOSET 0U
  5006. #define LPDDR4__WRLVL_REQ__REG DENALI_CTL_328
  5007. #define LPDDR4__WRLVL_REQ__FLD LPDDR4__DENALI_CTL_328__WRLVL_REQ
  5008. #define LPDDR4__DENALI_CTL_329_READ_MASK 0x013F3F01U
  5009. #define LPDDR4__DENALI_CTL_329_WRITE_MASK 0x013F3F01U
  5010. #define LPDDR4__DENALI_CTL_329__WRLVL_CS_MASK 0x00000001U
  5011. #define LPDDR4__DENALI_CTL_329__WRLVL_CS_SHIFT 0U
  5012. #define LPDDR4__DENALI_CTL_329__WRLVL_CS_WIDTH 1U
  5013. #define LPDDR4__DENALI_CTL_329__WRLVL_CS_WOCLR 0U
  5014. #define LPDDR4__DENALI_CTL_329__WRLVL_CS_WOSET 0U
  5015. #define LPDDR4__WRLVL_CS__REG DENALI_CTL_329
  5016. #define LPDDR4__WRLVL_CS__FLD LPDDR4__DENALI_CTL_329__WRLVL_CS
  5017. #define LPDDR4__DENALI_CTL_329__WLDQSEN_MASK 0x00003F00U
  5018. #define LPDDR4__DENALI_CTL_329__WLDQSEN_SHIFT 8U
  5019. #define LPDDR4__DENALI_CTL_329__WLDQSEN_WIDTH 6U
  5020. #define LPDDR4__WLDQSEN__REG DENALI_CTL_329
  5021. #define LPDDR4__WLDQSEN__FLD LPDDR4__DENALI_CTL_329__WLDQSEN
  5022. #define LPDDR4__DENALI_CTL_329__WLMRD_MASK 0x003F0000U
  5023. #define LPDDR4__DENALI_CTL_329__WLMRD_SHIFT 16U
  5024. #define LPDDR4__DENALI_CTL_329__WLMRD_WIDTH 6U
  5025. #define LPDDR4__WLMRD__REG DENALI_CTL_329
  5026. #define LPDDR4__WLMRD__FLD LPDDR4__DENALI_CTL_329__WLMRD
  5027. #define LPDDR4__DENALI_CTL_329__WRLVL_EN_MASK 0x01000000U
  5028. #define LPDDR4__DENALI_CTL_329__WRLVL_EN_SHIFT 24U
  5029. #define LPDDR4__DENALI_CTL_329__WRLVL_EN_WIDTH 1U
  5030. #define LPDDR4__DENALI_CTL_329__WRLVL_EN_WOCLR 0U
  5031. #define LPDDR4__DENALI_CTL_329__WRLVL_EN_WOSET 0U
  5032. #define LPDDR4__WRLVL_EN__REG DENALI_CTL_329
  5033. #define LPDDR4__WRLVL_EN__FLD LPDDR4__DENALI_CTL_329__WRLVL_EN
  5034. #define LPDDR4__DENALI_CTL_330_READ_MASK 0x0F010101U
  5035. #define LPDDR4__DENALI_CTL_330_WRITE_MASK 0x0F010101U
  5036. #define LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE_MASK 0x00000001U
  5037. #define LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE_SHIFT 0U
  5038. #define LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE_WIDTH 1U
  5039. #define LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE_WOCLR 0U
  5040. #define LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE_WOSET 0U
  5041. #define LPDDR4__DFI_PHY_WRLVL_MODE__REG DENALI_CTL_330
  5042. #define LPDDR4__DFI_PHY_WRLVL_MODE__FLD LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE
  5043. #define LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC_MASK 0x00000100U
  5044. #define LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC_SHIFT 8U
  5045. #define LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC_WIDTH 1U
  5046. #define LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC_WOCLR 0U
  5047. #define LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC_WOSET 0U
  5048. #define LPDDR4__WRLVL_PERIODIC__REG DENALI_CTL_330
  5049. #define LPDDR4__WRLVL_PERIODIC__FLD LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC
  5050. #define LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT_MASK 0x00010000U
  5051. #define LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT_SHIFT 16U
  5052. #define LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT_WIDTH 1U
  5053. #define LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT_WOCLR 0U
  5054. #define LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT_WOSET 0U
  5055. #define LPDDR4__WRLVL_ON_SREF_EXIT__REG DENALI_CTL_330
  5056. #define LPDDR4__WRLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT
  5057. #define LPDDR4__DENALI_CTL_330__WRLVL_RESP_MASK_MASK 0x0F000000U
  5058. #define LPDDR4__DENALI_CTL_330__WRLVL_RESP_MASK_SHIFT 24U
  5059. #define LPDDR4__DENALI_CTL_330__WRLVL_RESP_MASK_WIDTH 4U
  5060. #define LPDDR4__WRLVL_RESP_MASK__REG DENALI_CTL_330
  5061. #define LPDDR4__WRLVL_RESP_MASK__FLD LPDDR4__DENALI_CTL_330__WRLVL_RESP_MASK
  5062. #define LPDDR4__DENALI_CTL_331_READ_MASK 0x07030101U
  5063. #define LPDDR4__DENALI_CTL_331_WRITE_MASK 0x07030101U
  5064. #define LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN_MASK 0x00000001U
  5065. #define LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN_SHIFT 0U
  5066. #define LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN_WIDTH 1U
  5067. #define LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN_WOCLR 0U
  5068. #define LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN_WOSET 0U
  5069. #define LPDDR4__WRLVL_AREF_EN__REG DENALI_CTL_331
  5070. #define LPDDR4__WRLVL_AREF_EN__FLD LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN
  5071. #define LPDDR4__DENALI_CTL_331__WRLVL_ROTATE_MASK 0x00000100U
  5072. #define LPDDR4__DENALI_CTL_331__WRLVL_ROTATE_SHIFT 8U
  5073. #define LPDDR4__DENALI_CTL_331__WRLVL_ROTATE_WIDTH 1U
  5074. #define LPDDR4__DENALI_CTL_331__WRLVL_ROTATE_WOCLR 0U
  5075. #define LPDDR4__DENALI_CTL_331__WRLVL_ROTATE_WOSET 0U
  5076. #define LPDDR4__WRLVL_ROTATE__REG DENALI_CTL_331
  5077. #define LPDDR4__WRLVL_ROTATE__FLD LPDDR4__DENALI_CTL_331__WRLVL_ROTATE
  5078. #define LPDDR4__DENALI_CTL_331__WRLVL_CS_MAP_MASK 0x00030000U
  5079. #define LPDDR4__DENALI_CTL_331__WRLVL_CS_MAP_SHIFT 16U
  5080. #define LPDDR4__DENALI_CTL_331__WRLVL_CS_MAP_WIDTH 2U
  5081. #define LPDDR4__WRLVL_CS_MAP__REG DENALI_CTL_331
  5082. #define LPDDR4__WRLVL_CS_MAP__FLD LPDDR4__DENALI_CTL_331__WRLVL_CS_MAP
  5083. #define LPDDR4__DENALI_CTL_331__WRLVL_ERROR_STATUS_MASK 0x07000000U
  5084. #define LPDDR4__DENALI_CTL_331__WRLVL_ERROR_STATUS_SHIFT 24U
  5085. #define LPDDR4__DENALI_CTL_331__WRLVL_ERROR_STATUS_WIDTH 3U
  5086. #define LPDDR4__WRLVL_ERROR_STATUS__REG DENALI_CTL_331
  5087. #define LPDDR4__WRLVL_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_331__WRLVL_ERROR_STATUS
  5088. #define LPDDR4__DENALI_CTL_332_READ_MASK 0xFFFFFFFFU
  5089. #define LPDDR4__DENALI_CTL_332_WRITE_MASK 0xFFFFFFFFU
  5090. #define LPDDR4__DENALI_CTL_332__WRLVL_NORM_THRESHOLD_F0_MASK 0x0000FFFFU
  5091. #define LPDDR4__DENALI_CTL_332__WRLVL_NORM_THRESHOLD_F0_SHIFT 0U
  5092. #define LPDDR4__DENALI_CTL_332__WRLVL_NORM_THRESHOLD_F0_WIDTH 16U
  5093. #define LPDDR4__WRLVL_NORM_THRESHOLD_F0__REG DENALI_CTL_332
  5094. #define LPDDR4__WRLVL_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_332__WRLVL_NORM_THRESHOLD_F0
  5095. #define LPDDR4__DENALI_CTL_332__WRLVL_HIGH_THRESHOLD_F0_MASK 0xFFFF0000U
  5096. #define LPDDR4__DENALI_CTL_332__WRLVL_HIGH_THRESHOLD_F0_SHIFT 16U
  5097. #define LPDDR4__DENALI_CTL_332__WRLVL_HIGH_THRESHOLD_F0_WIDTH 16U
  5098. #define LPDDR4__WRLVL_HIGH_THRESHOLD_F0__REG DENALI_CTL_332
  5099. #define LPDDR4__WRLVL_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_332__WRLVL_HIGH_THRESHOLD_F0
  5100. #define LPDDR4__DENALI_CTL_333_READ_MASK 0xFFFFFFFFU
  5101. #define LPDDR4__DENALI_CTL_333_WRITE_MASK 0xFFFFFFFFU
  5102. #define LPDDR4__DENALI_CTL_333__WRLVL_TIMEOUT_F0_MASK 0x0000FFFFU
  5103. #define LPDDR4__DENALI_CTL_333__WRLVL_TIMEOUT_F0_SHIFT 0U
  5104. #define LPDDR4__DENALI_CTL_333__WRLVL_TIMEOUT_F0_WIDTH 16U
  5105. #define LPDDR4__WRLVL_TIMEOUT_F0__REG DENALI_CTL_333
  5106. #define LPDDR4__WRLVL_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_333__WRLVL_TIMEOUT_F0
  5107. #define LPDDR4__DENALI_CTL_333__WRLVL_SW_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U
  5108. #define LPDDR4__DENALI_CTL_333__WRLVL_SW_PROMOTE_THRESHOLD_F0_SHIFT 16U
  5109. #define LPDDR4__DENALI_CTL_333__WRLVL_SW_PROMOTE_THRESHOLD_F0_WIDTH 16U
  5110. #define LPDDR4__WRLVL_SW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_333
  5111. #define LPDDR4__WRLVL_SW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_333__WRLVL_SW_PROMOTE_THRESHOLD_F0
  5112. #define LPDDR4__DENALI_CTL_334_READ_MASK 0xFFFFFFFFU
  5113. #define LPDDR4__DENALI_CTL_334_WRITE_MASK 0xFFFFFFFFU
  5114. #define LPDDR4__DENALI_CTL_334__WRLVL_DFI_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
  5115. #define LPDDR4__DENALI_CTL_334__WRLVL_DFI_PROMOTE_THRESHOLD_F0_SHIFT 0U
  5116. #define LPDDR4__DENALI_CTL_334__WRLVL_DFI_PROMOTE_THRESHOLD_F0_WIDTH 16U
  5117. #define LPDDR4__WRLVL_DFI_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_334
  5118. #define LPDDR4__WRLVL_DFI_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_334__WRLVL_DFI_PROMOTE_THRESHOLD_F0
  5119. #define LPDDR4__DENALI_CTL_334__WRLVL_NORM_THRESHOLD_F1_MASK 0xFFFF0000U
  5120. #define LPDDR4__DENALI_CTL_334__WRLVL_NORM_THRESHOLD_F1_SHIFT 16U
  5121. #define LPDDR4__DENALI_CTL_334__WRLVL_NORM_THRESHOLD_F1_WIDTH 16U
  5122. #define LPDDR4__WRLVL_NORM_THRESHOLD_F1__REG DENALI_CTL_334
  5123. #define LPDDR4__WRLVL_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_334__WRLVL_NORM_THRESHOLD_F1
  5124. #define LPDDR4__DENALI_CTL_335_READ_MASK 0xFFFFFFFFU
  5125. #define LPDDR4__DENALI_CTL_335_WRITE_MASK 0xFFFFFFFFU
  5126. #define LPDDR4__DENALI_CTL_335__WRLVL_HIGH_THRESHOLD_F1_MASK 0x0000FFFFU
  5127. #define LPDDR4__DENALI_CTL_335__WRLVL_HIGH_THRESHOLD_F1_SHIFT 0U
  5128. #define LPDDR4__DENALI_CTL_335__WRLVL_HIGH_THRESHOLD_F1_WIDTH 16U
  5129. #define LPDDR4__WRLVL_HIGH_THRESHOLD_F1__REG DENALI_CTL_335
  5130. #define LPDDR4__WRLVL_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_335__WRLVL_HIGH_THRESHOLD_F1
  5131. #define LPDDR4__DENALI_CTL_335__WRLVL_TIMEOUT_F1_MASK 0xFFFF0000U
  5132. #define LPDDR4__DENALI_CTL_335__WRLVL_TIMEOUT_F1_SHIFT 16U
  5133. #define LPDDR4__DENALI_CTL_335__WRLVL_TIMEOUT_F1_WIDTH 16U
  5134. #define LPDDR4__WRLVL_TIMEOUT_F1__REG DENALI_CTL_335
  5135. #define LPDDR4__WRLVL_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_335__WRLVL_TIMEOUT_F1
  5136. #define LPDDR4__DENALI_CTL_336_READ_MASK 0xFFFFFFFFU
  5137. #define LPDDR4__DENALI_CTL_336_WRITE_MASK 0xFFFFFFFFU
  5138. #define LPDDR4__DENALI_CTL_336__WRLVL_SW_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU
  5139. #define LPDDR4__DENALI_CTL_336__WRLVL_SW_PROMOTE_THRESHOLD_F1_SHIFT 0U
  5140. #define LPDDR4__DENALI_CTL_336__WRLVL_SW_PROMOTE_THRESHOLD_F1_WIDTH 16U
  5141. #define LPDDR4__WRLVL_SW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_336
  5142. #define LPDDR4__WRLVL_SW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_336__WRLVL_SW_PROMOTE_THRESHOLD_F1
  5143. #define LPDDR4__DENALI_CTL_336__WRLVL_DFI_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U
  5144. #define LPDDR4__DENALI_CTL_336__WRLVL_DFI_PROMOTE_THRESHOLD_F1_SHIFT 16U
  5145. #define LPDDR4__DENALI_CTL_336__WRLVL_DFI_PROMOTE_THRESHOLD_F1_WIDTH 16U
  5146. #define LPDDR4__WRLVL_DFI_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_336
  5147. #define LPDDR4__WRLVL_DFI_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_336__WRLVL_DFI_PROMOTE_THRESHOLD_F1
  5148. #define LPDDR4__DENALI_CTL_337_READ_MASK 0xFFFFFFFFU
  5149. #define LPDDR4__DENALI_CTL_337_WRITE_MASK 0xFFFFFFFFU
  5150. #define LPDDR4__DENALI_CTL_337__WRLVL_NORM_THRESHOLD_F2_MASK 0x0000FFFFU
  5151. #define LPDDR4__DENALI_CTL_337__WRLVL_NORM_THRESHOLD_F2_SHIFT 0U
  5152. #define LPDDR4__DENALI_CTL_337__WRLVL_NORM_THRESHOLD_F2_WIDTH 16U
  5153. #define LPDDR4__WRLVL_NORM_THRESHOLD_F2__REG DENALI_CTL_337
  5154. #define LPDDR4__WRLVL_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_337__WRLVL_NORM_THRESHOLD_F2
  5155. #define LPDDR4__DENALI_CTL_337__WRLVL_HIGH_THRESHOLD_F2_MASK 0xFFFF0000U
  5156. #define LPDDR4__DENALI_CTL_337__WRLVL_HIGH_THRESHOLD_F2_SHIFT 16U
  5157. #define LPDDR4__DENALI_CTL_337__WRLVL_HIGH_THRESHOLD_F2_WIDTH 16U
  5158. #define LPDDR4__WRLVL_HIGH_THRESHOLD_F2__REG DENALI_CTL_337
  5159. #define LPDDR4__WRLVL_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_337__WRLVL_HIGH_THRESHOLD_F2
  5160. #define LPDDR4__DENALI_CTL_338_READ_MASK 0xFFFFFFFFU
  5161. #define LPDDR4__DENALI_CTL_338_WRITE_MASK 0xFFFFFFFFU
  5162. #define LPDDR4__DENALI_CTL_338__WRLVL_TIMEOUT_F2_MASK 0x0000FFFFU
  5163. #define LPDDR4__DENALI_CTL_338__WRLVL_TIMEOUT_F2_SHIFT 0U
  5164. #define LPDDR4__DENALI_CTL_338__WRLVL_TIMEOUT_F2_WIDTH 16U
  5165. #define LPDDR4__WRLVL_TIMEOUT_F2__REG DENALI_CTL_338
  5166. #define LPDDR4__WRLVL_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_338__WRLVL_TIMEOUT_F2
  5167. #define LPDDR4__DENALI_CTL_338__WRLVL_SW_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U
  5168. #define LPDDR4__DENALI_CTL_338__WRLVL_SW_PROMOTE_THRESHOLD_F2_SHIFT 16U
  5169. #define LPDDR4__DENALI_CTL_338__WRLVL_SW_PROMOTE_THRESHOLD_F2_WIDTH 16U
  5170. #define LPDDR4__WRLVL_SW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_338
  5171. #define LPDDR4__WRLVL_SW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_338__WRLVL_SW_PROMOTE_THRESHOLD_F2
  5172. #define LPDDR4__DENALI_CTL_339_READ_MASK 0x0000FFFFU
  5173. #define LPDDR4__DENALI_CTL_339_WRITE_MASK 0x0000FFFFU
  5174. #define LPDDR4__DENALI_CTL_339__WRLVL_DFI_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
  5175. #define LPDDR4__DENALI_CTL_339__WRLVL_DFI_PROMOTE_THRESHOLD_F2_SHIFT 0U
  5176. #define LPDDR4__DENALI_CTL_339__WRLVL_DFI_PROMOTE_THRESHOLD_F2_WIDTH 16U
  5177. #define LPDDR4__WRLVL_DFI_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_339
  5178. #define LPDDR4__WRLVL_DFI_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_339__WRLVL_DFI_PROMOTE_THRESHOLD_F2
  5179. #define LPDDR4__DENALI_CTL_339__RDLVL_REQ_MASK 0x00010000U
  5180. #define LPDDR4__DENALI_CTL_339__RDLVL_REQ_SHIFT 16U
  5181. #define LPDDR4__DENALI_CTL_339__RDLVL_REQ_WIDTH 1U
  5182. #define LPDDR4__DENALI_CTL_339__RDLVL_REQ_WOCLR 0U
  5183. #define LPDDR4__DENALI_CTL_339__RDLVL_REQ_WOSET 0U
  5184. #define LPDDR4__RDLVL_REQ__REG DENALI_CTL_339
  5185. #define LPDDR4__RDLVL_REQ__FLD LPDDR4__DENALI_CTL_339__RDLVL_REQ
  5186. #define LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ_MASK 0x01000000U
  5187. #define LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ_SHIFT 24U
  5188. #define LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ_WIDTH 1U
  5189. #define LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ_WOCLR 0U
  5190. #define LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ_WOSET 0U
  5191. #define LPDDR4__RDLVL_GATE_REQ__REG DENALI_CTL_339
  5192. #define LPDDR4__RDLVL_GATE_REQ__FLD LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ
  5193. #define LPDDR4__DENALI_CTL_340_READ_MASK 0x010F0F01U
  5194. #define LPDDR4__DENALI_CTL_340_WRITE_MASK 0x010F0F01U
  5195. #define LPDDR4__DENALI_CTL_340__RDLVL_CS_MASK 0x00000001U
  5196. #define LPDDR4__DENALI_CTL_340__RDLVL_CS_SHIFT 0U
  5197. #define LPDDR4__DENALI_CTL_340__RDLVL_CS_WIDTH 1U
  5198. #define LPDDR4__DENALI_CTL_340__RDLVL_CS_WOCLR 0U
  5199. #define LPDDR4__DENALI_CTL_340__RDLVL_CS_WOSET 0U
  5200. #define LPDDR4__RDLVL_CS__REG DENALI_CTL_340
  5201. #define LPDDR4__RDLVL_CS__FLD LPDDR4__DENALI_CTL_340__RDLVL_CS
  5202. #define LPDDR4__DENALI_CTL_340__RDLVL_SEQ_EN_MASK 0x00000F00U
  5203. #define LPDDR4__DENALI_CTL_340__RDLVL_SEQ_EN_SHIFT 8U
  5204. #define LPDDR4__DENALI_CTL_340__RDLVL_SEQ_EN_WIDTH 4U
  5205. #define LPDDR4__RDLVL_SEQ_EN__REG DENALI_CTL_340
  5206. #define LPDDR4__RDLVL_SEQ_EN__FLD LPDDR4__DENALI_CTL_340__RDLVL_SEQ_EN
  5207. #define LPDDR4__DENALI_CTL_340__RDLVL_GATE_SEQ_EN_MASK 0x000F0000U
  5208. #define LPDDR4__DENALI_CTL_340__RDLVL_GATE_SEQ_EN_SHIFT 16U
  5209. #define LPDDR4__DENALI_CTL_340__RDLVL_GATE_SEQ_EN_WIDTH 4U
  5210. #define LPDDR4__RDLVL_GATE_SEQ_EN__REG DENALI_CTL_340
  5211. #define LPDDR4__RDLVL_GATE_SEQ_EN__FLD LPDDR4__DENALI_CTL_340__RDLVL_GATE_SEQ_EN
  5212. #define LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE_MASK 0x01000000U
  5213. #define LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE_SHIFT 24U
  5214. #define LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE_WIDTH 1U
  5215. #define LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE_WOCLR 0U
  5216. #define LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE_WOSET 0U
  5217. #define LPDDR4__DFI_PHY_RDLVL_MODE__REG DENALI_CTL_340
  5218. #define LPDDR4__DFI_PHY_RDLVL_MODE__FLD LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE
  5219. #define LPDDR4__DENALI_CTL_341_READ_MASK 0x01010101U
  5220. #define LPDDR4__DENALI_CTL_341_WRITE_MASK 0x01010101U
  5221. #define LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE_MASK 0x00000001U
  5222. #define LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE_SHIFT 0U
  5223. #define LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE_WIDTH 1U
  5224. #define LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE_WOCLR 0U
  5225. #define LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE_WOSET 0U
  5226. #define LPDDR4__DFI_PHY_RDLVL_GATE_MODE__REG DENALI_CTL_341
  5227. #define LPDDR4__DFI_PHY_RDLVL_GATE_MODE__FLD LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE
  5228. #define LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC_MASK 0x00000100U
  5229. #define LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC_SHIFT 8U
  5230. #define LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC_WIDTH 1U
  5231. #define LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC_WOCLR 0U
  5232. #define LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC_WOSET 0U
  5233. #define LPDDR4__RDLVL_PERIODIC__REG DENALI_CTL_341
  5234. #define LPDDR4__RDLVL_PERIODIC__FLD LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC
  5235. #define LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT_MASK 0x00010000U
  5236. #define LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT_SHIFT 16U
  5237. #define LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT_WIDTH 1U
  5238. #define LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT_WOCLR 0U
  5239. #define LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT_WOSET 0U
  5240. #define LPDDR4__RDLVL_ON_SREF_EXIT__REG DENALI_CTL_341
  5241. #define LPDDR4__RDLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT
  5242. #define LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC_MASK 0x01000000U
  5243. #define LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC_SHIFT 24U
  5244. #define LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC_WIDTH 1U
  5245. #define LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC_WOCLR 0U
  5246. #define LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC_WOSET 0U
  5247. #define LPDDR4__RDLVL_GATE_PERIODIC__REG DENALI_CTL_341
  5248. #define LPDDR4__RDLVL_GATE_PERIODIC__FLD LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC
  5249. #define LPDDR4__DENALI_CTL_342_READ_MASK 0x01010101U
  5250. #define LPDDR4__DENALI_CTL_342_WRITE_MASK 0x01010101U
  5251. #define LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT_MASK 0x00000001U
  5252. #define LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT_SHIFT 0U
  5253. #define LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT_WIDTH 1U
  5254. #define LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT_WOCLR 0U
  5255. #define LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT_WOSET 0U
  5256. #define LPDDR4__RDLVL_GATE_ON_SREF_EXIT__REG DENALI_CTL_342
  5257. #define LPDDR4__RDLVL_GATE_ON_SREF_EXIT__FLD LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT
  5258. #define LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN_MASK 0x00000100U
  5259. #define LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN_SHIFT 8U
  5260. #define LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN_WIDTH 1U
  5261. #define LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN_WOCLR 0U
  5262. #define LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN_WOSET 0U
  5263. #define LPDDR4__RDLVL_AREF_EN__REG DENALI_CTL_342
  5264. #define LPDDR4__RDLVL_AREF_EN__FLD LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN
  5265. #define LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN_MASK 0x00010000U
  5266. #define LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN_SHIFT 16U
  5267. #define LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN_WIDTH 1U
  5268. #define LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN_WOCLR 0U
  5269. #define LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN_WOSET 0U
  5270. #define LPDDR4__RDLVL_GATE_AREF_EN__REG DENALI_CTL_342
  5271. #define LPDDR4__RDLVL_GATE_AREF_EN__FLD LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN
  5272. #define LPDDR4__DENALI_CTL_342__MC_RESERVED29_MASK 0x01000000U
  5273. #define LPDDR4__DENALI_CTL_342__MC_RESERVED29_SHIFT 24U
  5274. #define LPDDR4__DENALI_CTL_342__MC_RESERVED29_WIDTH 1U
  5275. #define LPDDR4__DENALI_CTL_342__MC_RESERVED29_WOCLR 0U
  5276. #define LPDDR4__DENALI_CTL_342__MC_RESERVED29_WOSET 0U
  5277. #define LPDDR4__MC_RESERVED29__REG DENALI_CTL_342
  5278. #define LPDDR4__MC_RESERVED29__FLD LPDDR4__DENALI_CTL_342__MC_RESERVED29
  5279. #define LPDDR4__DENALI_CTL_343_READ_MASK 0x03030101U
  5280. #define LPDDR4__DENALI_CTL_343_WRITE_MASK 0x03030101U
  5281. #define LPDDR4__DENALI_CTL_343__RDLVL_ROTATE_MASK 0x00000001U
  5282. #define LPDDR4__DENALI_CTL_343__RDLVL_ROTATE_SHIFT 0U
  5283. #define LPDDR4__DENALI_CTL_343__RDLVL_ROTATE_WIDTH 1U
  5284. #define LPDDR4__DENALI_CTL_343__RDLVL_ROTATE_WOCLR 0U
  5285. #define LPDDR4__DENALI_CTL_343__RDLVL_ROTATE_WOSET 0U
  5286. #define LPDDR4__RDLVL_ROTATE__REG DENALI_CTL_343
  5287. #define LPDDR4__RDLVL_ROTATE__FLD LPDDR4__DENALI_CTL_343__RDLVL_ROTATE
  5288. #define LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE_MASK 0x00000100U
  5289. #define LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE_SHIFT 8U
  5290. #define LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE_WIDTH 1U
  5291. #define LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE_WOCLR 0U
  5292. #define LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE_WOSET 0U
  5293. #define LPDDR4__RDLVL_GATE_ROTATE__REG DENALI_CTL_343
  5294. #define LPDDR4__RDLVL_GATE_ROTATE__FLD LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE
  5295. #define LPDDR4__DENALI_CTL_343__RDLVL_CS_MAP_MASK 0x00030000U
  5296. #define LPDDR4__DENALI_CTL_343__RDLVL_CS_MAP_SHIFT 16U
  5297. #define LPDDR4__DENALI_CTL_343__RDLVL_CS_MAP_WIDTH 2U
  5298. #define LPDDR4__RDLVL_CS_MAP__REG DENALI_CTL_343
  5299. #define LPDDR4__RDLVL_CS_MAP__FLD LPDDR4__DENALI_CTL_343__RDLVL_CS_MAP
  5300. #define LPDDR4__DENALI_CTL_343__RDLVL_GATE_CS_MAP_MASK 0x03000000U
  5301. #define LPDDR4__DENALI_CTL_343__RDLVL_GATE_CS_MAP_SHIFT 24U
  5302. #define LPDDR4__DENALI_CTL_343__RDLVL_GATE_CS_MAP_WIDTH 2U
  5303. #define LPDDR4__RDLVL_GATE_CS_MAP__REG DENALI_CTL_343
  5304. #define LPDDR4__RDLVL_GATE_CS_MAP__FLD LPDDR4__DENALI_CTL_343__RDLVL_GATE_CS_MAP
  5305. #define LPDDR4__DENALI_CTL_344_READ_MASK 0xFFFFFFFFU
  5306. #define LPDDR4__DENALI_CTL_344_WRITE_MASK 0xFFFFFFFFU
  5307. #define LPDDR4__DENALI_CTL_344__RDLVL_NORM_THRESHOLD_F0_MASK 0x0000FFFFU
  5308. #define LPDDR4__DENALI_CTL_344__RDLVL_NORM_THRESHOLD_F0_SHIFT 0U
  5309. #define LPDDR4__DENALI_CTL_344__RDLVL_NORM_THRESHOLD_F0_WIDTH 16U
  5310. #define LPDDR4__RDLVL_NORM_THRESHOLD_F0__REG DENALI_CTL_344
  5311. #define LPDDR4__RDLVL_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_344__RDLVL_NORM_THRESHOLD_F0
  5312. #define LPDDR4__DENALI_CTL_344__RDLVL_HIGH_THRESHOLD_F0_MASK 0xFFFF0000U
  5313. #define LPDDR4__DENALI_CTL_344__RDLVL_HIGH_THRESHOLD_F0_SHIFT 16U
  5314. #define LPDDR4__DENALI_CTL_344__RDLVL_HIGH_THRESHOLD_F0_WIDTH 16U
  5315. #define LPDDR4__RDLVL_HIGH_THRESHOLD_F0__REG DENALI_CTL_344
  5316. #define LPDDR4__RDLVL_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_344__RDLVL_HIGH_THRESHOLD_F0
  5317. #define LPDDR4__DENALI_CTL_345_READ_MASK 0xFFFFFFFFU
  5318. #define LPDDR4__DENALI_CTL_345_WRITE_MASK 0xFFFFFFFFU
  5319. #define LPDDR4__DENALI_CTL_345__RDLVL_TIMEOUT_F0_MASK 0x0000FFFFU
  5320. #define LPDDR4__DENALI_CTL_345__RDLVL_TIMEOUT_F0_SHIFT 0U
  5321. #define LPDDR4__DENALI_CTL_345__RDLVL_TIMEOUT_F0_WIDTH 16U
  5322. #define LPDDR4__RDLVL_TIMEOUT_F0__REG DENALI_CTL_345
  5323. #define LPDDR4__RDLVL_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_345__RDLVL_TIMEOUT_F0
  5324. #define LPDDR4__DENALI_CTL_345__RDLVL_SW_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U
  5325. #define LPDDR4__DENALI_CTL_345__RDLVL_SW_PROMOTE_THRESHOLD_F0_SHIFT 16U
  5326. #define LPDDR4__DENALI_CTL_345__RDLVL_SW_PROMOTE_THRESHOLD_F0_WIDTH 16U
  5327. #define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_345
  5328. #define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_345__RDLVL_SW_PROMOTE_THRESHOLD_F0
  5329. #define LPDDR4__DENALI_CTL_346_READ_MASK 0xFFFFFFFFU
  5330. #define LPDDR4__DENALI_CTL_346_WRITE_MASK 0xFFFFFFFFU
  5331. #define LPDDR4__DENALI_CTL_346__RDLVL_DFI_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
  5332. #define LPDDR4__DENALI_CTL_346__RDLVL_DFI_PROMOTE_THRESHOLD_F0_SHIFT 0U
  5333. #define LPDDR4__DENALI_CTL_346__RDLVL_DFI_PROMOTE_THRESHOLD_F0_WIDTH 16U
  5334. #define LPDDR4__RDLVL_DFI_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_346
  5335. #define LPDDR4__RDLVL_DFI_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_346__RDLVL_DFI_PROMOTE_THRESHOLD_F0
  5336. #define LPDDR4__DENALI_CTL_346__RDLVL_GATE_NORM_THRESHOLD_F0_MASK 0xFFFF0000U
  5337. #define LPDDR4__DENALI_CTL_346__RDLVL_GATE_NORM_THRESHOLD_F0_SHIFT 16U
  5338. #define LPDDR4__DENALI_CTL_346__RDLVL_GATE_NORM_THRESHOLD_F0_WIDTH 16U
  5339. #define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F0__REG DENALI_CTL_346
  5340. #define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_346__RDLVL_GATE_NORM_THRESHOLD_F0
  5341. #define LPDDR4__DENALI_CTL_347_READ_MASK 0xFFFFFFFFU
  5342. #define LPDDR4__DENALI_CTL_347_WRITE_MASK 0xFFFFFFFFU
  5343. #define LPDDR4__DENALI_CTL_347__RDLVL_GATE_HIGH_THRESHOLD_F0_MASK 0x0000FFFFU
  5344. #define LPDDR4__DENALI_CTL_347__RDLVL_GATE_HIGH_THRESHOLD_F0_SHIFT 0U
  5345. #define LPDDR4__DENALI_CTL_347__RDLVL_GATE_HIGH_THRESHOLD_F0_WIDTH 16U
  5346. #define LPDDR4__RDLVL_GATE_HIGH_THRESHOLD_F0__REG DENALI_CTL_347
  5347. #define LPDDR4__RDLVL_GATE_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_347__RDLVL_GATE_HIGH_THRESHOLD_F0
  5348. #define LPDDR4__DENALI_CTL_347__RDLVL_GATE_TIMEOUT_F0_MASK 0xFFFF0000U
  5349. #define LPDDR4__DENALI_CTL_347__RDLVL_GATE_TIMEOUT_F0_SHIFT 16U
  5350. #define LPDDR4__DENALI_CTL_347__RDLVL_GATE_TIMEOUT_F0_WIDTH 16U
  5351. #define LPDDR4__RDLVL_GATE_TIMEOUT_F0__REG DENALI_CTL_347
  5352. #define LPDDR4__RDLVL_GATE_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_347__RDLVL_GATE_TIMEOUT_F0
  5353. #define LPDDR4__DENALI_CTL_348_READ_MASK 0xFFFFFFFFU
  5354. #define LPDDR4__DENALI_CTL_348_WRITE_MASK 0xFFFFFFFFU
  5355. #define LPDDR4__DENALI_CTL_348__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
  5356. #define LPDDR4__DENALI_CTL_348__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0_SHIFT 0U
  5357. #define LPDDR4__DENALI_CTL_348__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0_WIDTH 16U
  5358. #define LPDDR4__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_348
  5359. #define LPDDR4__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_348__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0
  5360. #define LPDDR4__DENALI_CTL_348__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U
  5361. #define LPDDR4__DENALI_CTL_348__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0_SHIFT 16U
  5362. #define LPDDR4__DENALI_CTL_348__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0_WIDTH 16U
  5363. #define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_348
  5364. #define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_348__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0
  5365. #define LPDDR4__DENALI_CTL_349_READ_MASK 0xFFFFFFFFU
  5366. #define LPDDR4__DENALI_CTL_349_WRITE_MASK 0xFFFFFFFFU
  5367. #define LPDDR4__DENALI_CTL_349__RDLVL_NORM_THRESHOLD_F1_MASK 0x0000FFFFU
  5368. #define LPDDR4__DENALI_CTL_349__RDLVL_NORM_THRESHOLD_F1_SHIFT 0U
  5369. #define LPDDR4__DENALI_CTL_349__RDLVL_NORM_THRESHOLD_F1_WIDTH 16U
  5370. #define LPDDR4__RDLVL_NORM_THRESHOLD_F1__REG DENALI_CTL_349
  5371. #define LPDDR4__RDLVL_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_349__RDLVL_NORM_THRESHOLD_F1
  5372. #define LPDDR4__DENALI_CTL_349__RDLVL_HIGH_THRESHOLD_F1_MASK 0xFFFF0000U
  5373. #define LPDDR4__DENALI_CTL_349__RDLVL_HIGH_THRESHOLD_F1_SHIFT 16U
  5374. #define LPDDR4__DENALI_CTL_349__RDLVL_HIGH_THRESHOLD_F1_WIDTH 16U
  5375. #define LPDDR4__RDLVL_HIGH_THRESHOLD_F1__REG DENALI_CTL_349
  5376. #define LPDDR4__RDLVL_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_349__RDLVL_HIGH_THRESHOLD_F1
  5377. #define LPDDR4__DENALI_CTL_350_READ_MASK 0xFFFFFFFFU
  5378. #define LPDDR4__DENALI_CTL_350_WRITE_MASK 0xFFFFFFFFU
  5379. #define LPDDR4__DENALI_CTL_350__RDLVL_TIMEOUT_F1_MASK 0x0000FFFFU
  5380. #define LPDDR4__DENALI_CTL_350__RDLVL_TIMEOUT_F1_SHIFT 0U
  5381. #define LPDDR4__DENALI_CTL_350__RDLVL_TIMEOUT_F1_WIDTH 16U
  5382. #define LPDDR4__RDLVL_TIMEOUT_F1__REG DENALI_CTL_350
  5383. #define LPDDR4__RDLVL_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_350__RDLVL_TIMEOUT_F1
  5384. #define LPDDR4__DENALI_CTL_350__RDLVL_SW_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U
  5385. #define LPDDR4__DENALI_CTL_350__RDLVL_SW_PROMOTE_THRESHOLD_F1_SHIFT 16U
  5386. #define LPDDR4__DENALI_CTL_350__RDLVL_SW_PROMOTE_THRESHOLD_F1_WIDTH 16U
  5387. #define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_350
  5388. #define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_350__RDLVL_SW_PROMOTE_THRESHOLD_F1
  5389. #define LPDDR4__DENALI_CTL_351_READ_MASK 0xFFFFFFFFU
  5390. #define LPDDR4__DENALI_CTL_351_WRITE_MASK 0xFFFFFFFFU
  5391. #define LPDDR4__DENALI_CTL_351__RDLVL_DFI_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU
  5392. #define LPDDR4__DENALI_CTL_351__RDLVL_DFI_PROMOTE_THRESHOLD_F1_SHIFT 0U
  5393. #define LPDDR4__DENALI_CTL_351__RDLVL_DFI_PROMOTE_THRESHOLD_F1_WIDTH 16U
  5394. #define LPDDR4__RDLVL_DFI_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_351
  5395. #define LPDDR4__RDLVL_DFI_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_351__RDLVL_DFI_PROMOTE_THRESHOLD_F1
  5396. #define LPDDR4__DENALI_CTL_351__RDLVL_GATE_NORM_THRESHOLD_F1_MASK 0xFFFF0000U
  5397. #define LPDDR4__DENALI_CTL_351__RDLVL_GATE_NORM_THRESHOLD_F1_SHIFT 16U
  5398. #define LPDDR4__DENALI_CTL_351__RDLVL_GATE_NORM_THRESHOLD_F1_WIDTH 16U
  5399. #define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F1__REG DENALI_CTL_351
  5400. #define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_351__RDLVL_GATE_NORM_THRESHOLD_F1
  5401. #define LPDDR4__DENALI_CTL_352_READ_MASK 0xFFFFFFFFU
  5402. #define LPDDR4__DENALI_CTL_352_WRITE_MASK 0xFFFFFFFFU
  5403. #define LPDDR4__DENALI_CTL_352__RDLVL_GATE_HIGH_THRESHOLD_F1_MASK 0x0000FFFFU
  5404. #define LPDDR4__DENALI_CTL_352__RDLVL_GATE_HIGH_THRESHOLD_F1_SHIFT 0U
  5405. #define LPDDR4__DENALI_CTL_352__RDLVL_GATE_HIGH_THRESHOLD_F1_WIDTH 16U
  5406. #define LPDDR4__RDLVL_GATE_HIGH_THRESHOLD_F1__REG DENALI_CTL_352
  5407. #define LPDDR4__RDLVL_GATE_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_352__RDLVL_GATE_HIGH_THRESHOLD_F1
  5408. #define LPDDR4__DENALI_CTL_352__RDLVL_GATE_TIMEOUT_F1_MASK 0xFFFF0000U
  5409. #define LPDDR4__DENALI_CTL_352__RDLVL_GATE_TIMEOUT_F1_SHIFT 16U
  5410. #define LPDDR4__DENALI_CTL_352__RDLVL_GATE_TIMEOUT_F1_WIDTH 16U
  5411. #define LPDDR4__RDLVL_GATE_TIMEOUT_F1__REG DENALI_CTL_352
  5412. #define LPDDR4__RDLVL_GATE_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_352__RDLVL_GATE_TIMEOUT_F1
  5413. #define LPDDR4__DENALI_CTL_353_READ_MASK 0xFFFFFFFFU
  5414. #define LPDDR4__DENALI_CTL_353_WRITE_MASK 0xFFFFFFFFU
  5415. #define LPDDR4__DENALI_CTL_353__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU
  5416. #define LPDDR4__DENALI_CTL_353__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1_SHIFT 0U
  5417. #define LPDDR4__DENALI_CTL_353__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1_WIDTH 16U
  5418. #define LPDDR4__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_353
  5419. #define LPDDR4__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_353__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1
  5420. #define LPDDR4__DENALI_CTL_353__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U
  5421. #define LPDDR4__DENALI_CTL_353__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1_SHIFT 16U
  5422. #define LPDDR4__DENALI_CTL_353__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1_WIDTH 16U
  5423. #define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_353
  5424. #define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_353__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1
  5425. #define LPDDR4__DENALI_CTL_354_READ_MASK 0xFFFFFFFFU
  5426. #define LPDDR4__DENALI_CTL_354_WRITE_MASK 0xFFFFFFFFU
  5427. #define LPDDR4__DENALI_CTL_354__RDLVL_NORM_THRESHOLD_F2_MASK 0x0000FFFFU
  5428. #define LPDDR4__DENALI_CTL_354__RDLVL_NORM_THRESHOLD_F2_SHIFT 0U
  5429. #define LPDDR4__DENALI_CTL_354__RDLVL_NORM_THRESHOLD_F2_WIDTH 16U
  5430. #define LPDDR4__RDLVL_NORM_THRESHOLD_F2__REG DENALI_CTL_354
  5431. #define LPDDR4__RDLVL_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_354__RDLVL_NORM_THRESHOLD_F2
  5432. #define LPDDR4__DENALI_CTL_354__RDLVL_HIGH_THRESHOLD_F2_MASK 0xFFFF0000U
  5433. #define LPDDR4__DENALI_CTL_354__RDLVL_HIGH_THRESHOLD_F2_SHIFT 16U
  5434. #define LPDDR4__DENALI_CTL_354__RDLVL_HIGH_THRESHOLD_F2_WIDTH 16U
  5435. #define LPDDR4__RDLVL_HIGH_THRESHOLD_F2__REG DENALI_CTL_354
  5436. #define LPDDR4__RDLVL_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_354__RDLVL_HIGH_THRESHOLD_F2
  5437. #define LPDDR4__DENALI_CTL_355_READ_MASK 0xFFFFFFFFU
  5438. #define LPDDR4__DENALI_CTL_355_WRITE_MASK 0xFFFFFFFFU
  5439. #define LPDDR4__DENALI_CTL_355__RDLVL_TIMEOUT_F2_MASK 0x0000FFFFU
  5440. #define LPDDR4__DENALI_CTL_355__RDLVL_TIMEOUT_F2_SHIFT 0U
  5441. #define LPDDR4__DENALI_CTL_355__RDLVL_TIMEOUT_F2_WIDTH 16U
  5442. #define LPDDR4__RDLVL_TIMEOUT_F2__REG DENALI_CTL_355
  5443. #define LPDDR4__RDLVL_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_355__RDLVL_TIMEOUT_F2
  5444. #define LPDDR4__DENALI_CTL_355__RDLVL_SW_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U
  5445. #define LPDDR4__DENALI_CTL_355__RDLVL_SW_PROMOTE_THRESHOLD_F2_SHIFT 16U
  5446. #define LPDDR4__DENALI_CTL_355__RDLVL_SW_PROMOTE_THRESHOLD_F2_WIDTH 16U
  5447. #define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_355
  5448. #define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_355__RDLVL_SW_PROMOTE_THRESHOLD_F2
  5449. #define LPDDR4__DENALI_CTL_356_READ_MASK 0xFFFFFFFFU
  5450. #define LPDDR4__DENALI_CTL_356_WRITE_MASK 0xFFFFFFFFU
  5451. #define LPDDR4__DENALI_CTL_356__RDLVL_DFI_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
  5452. #define LPDDR4__DENALI_CTL_356__RDLVL_DFI_PROMOTE_THRESHOLD_F2_SHIFT 0U
  5453. #define LPDDR4__DENALI_CTL_356__RDLVL_DFI_PROMOTE_THRESHOLD_F2_WIDTH 16U
  5454. #define LPDDR4__RDLVL_DFI_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_356
  5455. #define LPDDR4__RDLVL_DFI_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_356__RDLVL_DFI_PROMOTE_THRESHOLD_F2
  5456. #define LPDDR4__DENALI_CTL_356__RDLVL_GATE_NORM_THRESHOLD_F2_MASK 0xFFFF0000U
  5457. #define LPDDR4__DENALI_CTL_356__RDLVL_GATE_NORM_THRESHOLD_F2_SHIFT 16U
  5458. #define LPDDR4__DENALI_CTL_356__RDLVL_GATE_NORM_THRESHOLD_F2_WIDTH 16U
  5459. #define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F2__REG DENALI_CTL_356
  5460. #define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_356__RDLVL_GATE_NORM_THRESHOLD_F2
  5461. #define LPDDR4__DENALI_CTL_357_READ_MASK 0xFFFFFFFFU
  5462. #define LPDDR4__DENALI_CTL_357_WRITE_MASK 0xFFFFFFFFU
  5463. #define LPDDR4__DENALI_CTL_357__RDLVL_GATE_HIGH_THRESHOLD_F2_MASK 0x0000FFFFU
  5464. #define LPDDR4__DENALI_CTL_357__RDLVL_GATE_HIGH_THRESHOLD_F2_SHIFT 0U
  5465. #define LPDDR4__DENALI_CTL_357__RDLVL_GATE_HIGH_THRESHOLD_F2_WIDTH 16U
  5466. #define LPDDR4__RDLVL_GATE_HIGH_THRESHOLD_F2__REG DENALI_CTL_357
  5467. #define LPDDR4__RDLVL_GATE_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_357__RDLVL_GATE_HIGH_THRESHOLD_F2
  5468. #define LPDDR4__DENALI_CTL_357__RDLVL_GATE_TIMEOUT_F2_MASK 0xFFFF0000U
  5469. #define LPDDR4__DENALI_CTL_357__RDLVL_GATE_TIMEOUT_F2_SHIFT 16U
  5470. #define LPDDR4__DENALI_CTL_357__RDLVL_GATE_TIMEOUT_F2_WIDTH 16U
  5471. #define LPDDR4__RDLVL_GATE_TIMEOUT_F2__REG DENALI_CTL_357
  5472. #define LPDDR4__RDLVL_GATE_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_357__RDLVL_GATE_TIMEOUT_F2
  5473. #define LPDDR4__DENALI_CTL_358_READ_MASK 0xFFFFFFFFU
  5474. #define LPDDR4__DENALI_CTL_358_WRITE_MASK 0xFFFFFFFFU
  5475. #define LPDDR4__DENALI_CTL_358__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
  5476. #define LPDDR4__DENALI_CTL_358__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2_SHIFT 0U
  5477. #define LPDDR4__DENALI_CTL_358__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2_WIDTH 16U
  5478. #define LPDDR4__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_358
  5479. #define LPDDR4__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_358__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2
  5480. #define LPDDR4__DENALI_CTL_358__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U
  5481. #define LPDDR4__DENALI_CTL_358__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2_SHIFT 16U
  5482. #define LPDDR4__DENALI_CTL_358__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2_WIDTH 16U
  5483. #define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_358
  5484. #define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_358__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2
  5485. #define LPDDR4__DENALI_CTL_359_READ_MASK 0x00000100U
  5486. #define LPDDR4__DENALI_CTL_359_WRITE_MASK 0x00000100U
  5487. #define LPDDR4__DENALI_CTL_359__CALVL_REQ_MASK 0x00000001U
  5488. #define LPDDR4__DENALI_CTL_359__CALVL_REQ_SHIFT 0U
  5489. #define LPDDR4__DENALI_CTL_359__CALVL_REQ_WIDTH 1U
  5490. #define LPDDR4__DENALI_CTL_359__CALVL_REQ_WOCLR 0U
  5491. #define LPDDR4__DENALI_CTL_359__CALVL_REQ_WOSET 0U
  5492. #define LPDDR4__CALVL_REQ__REG DENALI_CTL_359
  5493. #define LPDDR4__CALVL_REQ__FLD LPDDR4__DENALI_CTL_359__CALVL_REQ
  5494. #define LPDDR4__DENALI_CTL_359__CALVL_CS_MASK 0x00000100U
  5495. #define LPDDR4__DENALI_CTL_359__CALVL_CS_SHIFT 8U
  5496. #define LPDDR4__DENALI_CTL_359__CALVL_CS_WIDTH 1U
  5497. #define LPDDR4__DENALI_CTL_359__CALVL_CS_WOCLR 0U
  5498. #define LPDDR4__DENALI_CTL_359__CALVL_CS_WOSET 0U
  5499. #define LPDDR4__CALVL_CS__REG DENALI_CTL_359
  5500. #define LPDDR4__CALVL_CS__FLD LPDDR4__DENALI_CTL_359__CALVL_CS
  5501. #define LPDDR4__DENALI_CTL_360_READ_MASK 0x000FFFFFU
  5502. #define LPDDR4__DENALI_CTL_360_WRITE_MASK 0x000FFFFFU
  5503. #define LPDDR4__DENALI_CTL_360__CALVL_PAT_0_MASK 0x000FFFFFU
  5504. #define LPDDR4__DENALI_CTL_360__CALVL_PAT_0_SHIFT 0U
  5505. #define LPDDR4__DENALI_CTL_360__CALVL_PAT_0_WIDTH 20U
  5506. #define LPDDR4__CALVL_PAT_0__REG DENALI_CTL_360
  5507. #define LPDDR4__CALVL_PAT_0__FLD LPDDR4__DENALI_CTL_360__CALVL_PAT_0
  5508. #define LPDDR4__DENALI_CTL_361_READ_MASK 0x000FFFFFU
  5509. #define LPDDR4__DENALI_CTL_361_WRITE_MASK 0x000FFFFFU
  5510. #define LPDDR4__DENALI_CTL_361__CALVL_BG_PAT_0_MASK 0x000FFFFFU
  5511. #define LPDDR4__DENALI_CTL_361__CALVL_BG_PAT_0_SHIFT 0U
  5512. #define LPDDR4__DENALI_CTL_361__CALVL_BG_PAT_0_WIDTH 20U
  5513. #define LPDDR4__CALVL_BG_PAT_0__REG DENALI_CTL_361
  5514. #define LPDDR4__CALVL_BG_PAT_0__FLD LPDDR4__DENALI_CTL_361__CALVL_BG_PAT_0
  5515. #define LPDDR4__DENALI_CTL_362_READ_MASK 0x000FFFFFU
  5516. #define LPDDR4__DENALI_CTL_362_WRITE_MASK 0x000FFFFFU
  5517. #define LPDDR4__DENALI_CTL_362__CALVL_PAT_1_MASK 0x000FFFFFU
  5518. #define LPDDR4__DENALI_CTL_362__CALVL_PAT_1_SHIFT 0U
  5519. #define LPDDR4__DENALI_CTL_362__CALVL_PAT_1_WIDTH 20U
  5520. #define LPDDR4__CALVL_PAT_1__REG DENALI_CTL_362
  5521. #define LPDDR4__CALVL_PAT_1__FLD LPDDR4__DENALI_CTL_362__CALVL_PAT_1
  5522. #define LPDDR4__DENALI_CTL_363_READ_MASK 0x000FFFFFU
  5523. #define LPDDR4__DENALI_CTL_363_WRITE_MASK 0x000FFFFFU
  5524. #define LPDDR4__DENALI_CTL_363__CALVL_BG_PAT_1_MASK 0x000FFFFFU
  5525. #define LPDDR4__DENALI_CTL_363__CALVL_BG_PAT_1_SHIFT 0U
  5526. #define LPDDR4__DENALI_CTL_363__CALVL_BG_PAT_1_WIDTH 20U
  5527. #define LPDDR4__CALVL_BG_PAT_1__REG DENALI_CTL_363
  5528. #define LPDDR4__CALVL_BG_PAT_1__FLD LPDDR4__DENALI_CTL_363__CALVL_BG_PAT_1
  5529. #define LPDDR4__DENALI_CTL_364_READ_MASK 0x000FFFFFU
  5530. #define LPDDR4__DENALI_CTL_364_WRITE_MASK 0x000FFFFFU
  5531. #define LPDDR4__DENALI_CTL_364__CALVL_PAT_2_MASK 0x000FFFFFU
  5532. #define LPDDR4__DENALI_CTL_364__CALVL_PAT_2_SHIFT 0U
  5533. #define LPDDR4__DENALI_CTL_364__CALVL_PAT_2_WIDTH 20U
  5534. #define LPDDR4__CALVL_PAT_2__REG DENALI_CTL_364
  5535. #define LPDDR4__CALVL_PAT_2__FLD LPDDR4__DENALI_CTL_364__CALVL_PAT_2
  5536. #define LPDDR4__DENALI_CTL_365_READ_MASK 0x000FFFFFU
  5537. #define LPDDR4__DENALI_CTL_365_WRITE_MASK 0x000FFFFFU
  5538. #define LPDDR4__DENALI_CTL_365__CALVL_BG_PAT_2_MASK 0x000FFFFFU
  5539. #define LPDDR4__DENALI_CTL_365__CALVL_BG_PAT_2_SHIFT 0U
  5540. #define LPDDR4__DENALI_CTL_365__CALVL_BG_PAT_2_WIDTH 20U
  5541. #define LPDDR4__CALVL_BG_PAT_2__REG DENALI_CTL_365
  5542. #define LPDDR4__CALVL_BG_PAT_2__FLD LPDDR4__DENALI_CTL_365__CALVL_BG_PAT_2
  5543. #define LPDDR4__DENALI_CTL_366_READ_MASK 0x000FFFFFU
  5544. #define LPDDR4__DENALI_CTL_366_WRITE_MASK 0x000FFFFFU
  5545. #define LPDDR4__DENALI_CTL_366__CALVL_PAT_3_MASK 0x000FFFFFU
  5546. #define LPDDR4__DENALI_CTL_366__CALVL_PAT_3_SHIFT 0U
  5547. #define LPDDR4__DENALI_CTL_366__CALVL_PAT_3_WIDTH 20U
  5548. #define LPDDR4__CALVL_PAT_3__REG DENALI_CTL_366
  5549. #define LPDDR4__CALVL_PAT_3__FLD LPDDR4__DENALI_CTL_366__CALVL_PAT_3
  5550. #define LPDDR4__DENALI_CTL_367_READ_MASK 0x010FFFFFU
  5551. #define LPDDR4__DENALI_CTL_367_WRITE_MASK 0x010FFFFFU
  5552. #define LPDDR4__DENALI_CTL_367__CALVL_BG_PAT_3_MASK 0x000FFFFFU
  5553. #define LPDDR4__DENALI_CTL_367__CALVL_BG_PAT_3_SHIFT 0U
  5554. #define LPDDR4__DENALI_CTL_367__CALVL_BG_PAT_3_WIDTH 20U
  5555. #define LPDDR4__CALVL_BG_PAT_3__REG DENALI_CTL_367
  5556. #define LPDDR4__CALVL_BG_PAT_3__FLD LPDDR4__DENALI_CTL_367__CALVL_BG_PAT_3
  5557. #define LPDDR4__DENALI_CTL_367__MC_RESERVED30_MASK 0x01000000U
  5558. #define LPDDR4__DENALI_CTL_367__MC_RESERVED30_SHIFT 24U
  5559. #define LPDDR4__DENALI_CTL_367__MC_RESERVED30_WIDTH 1U
  5560. #define LPDDR4__DENALI_CTL_367__MC_RESERVED30_WOCLR 0U
  5561. #define LPDDR4__DENALI_CTL_367__MC_RESERVED30_WOSET 0U
  5562. #define LPDDR4__MC_RESERVED30__REG DENALI_CTL_367
  5563. #define LPDDR4__MC_RESERVED30__FLD LPDDR4__DENALI_CTL_367__MC_RESERVED30
  5564. #define LPDDR4__DENALI_CTL_368_READ_MASK 0x0101030FU
  5565. #define LPDDR4__DENALI_CTL_368_WRITE_MASK 0x0101030FU
  5566. #define LPDDR4__DENALI_CTL_368__MC_RESERVED31_MASK 0x0000000FU
  5567. #define LPDDR4__DENALI_CTL_368__MC_RESERVED31_SHIFT 0U
  5568. #define LPDDR4__DENALI_CTL_368__MC_RESERVED31_WIDTH 4U
  5569. #define LPDDR4__MC_RESERVED31__REG DENALI_CTL_368
  5570. #define LPDDR4__MC_RESERVED31__FLD LPDDR4__DENALI_CTL_368__MC_RESERVED31
  5571. #define LPDDR4__DENALI_CTL_368__CALVL_SEQ_EN_MASK 0x00000300U
  5572. #define LPDDR4__DENALI_CTL_368__CALVL_SEQ_EN_SHIFT 8U
  5573. #define LPDDR4__DENALI_CTL_368__CALVL_SEQ_EN_WIDTH 2U
  5574. #define LPDDR4__CALVL_SEQ_EN__REG DENALI_CTL_368
  5575. #define LPDDR4__CALVL_SEQ_EN__FLD LPDDR4__DENALI_CTL_368__CALVL_SEQ_EN
  5576. #define LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE_MASK 0x00010000U
  5577. #define LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE_SHIFT 16U
  5578. #define LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE_WIDTH 1U
  5579. #define LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE_WOCLR 0U
  5580. #define LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE_WOSET 0U
  5581. #define LPDDR4__DFI_PHY_CALVL_MODE__REG DENALI_CTL_368
  5582. #define LPDDR4__DFI_PHY_CALVL_MODE__FLD LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE
  5583. #define LPDDR4__DENALI_CTL_368__CALVL_PERIODIC_MASK 0x01000000U
  5584. #define LPDDR4__DENALI_CTL_368__CALVL_PERIODIC_SHIFT 24U
  5585. #define LPDDR4__DENALI_CTL_368__CALVL_PERIODIC_WIDTH 1U
  5586. #define LPDDR4__DENALI_CTL_368__CALVL_PERIODIC_WOCLR 0U
  5587. #define LPDDR4__DENALI_CTL_368__CALVL_PERIODIC_WOSET 0U
  5588. #define LPDDR4__CALVL_PERIODIC__REG DENALI_CTL_368
  5589. #define LPDDR4__CALVL_PERIODIC__FLD LPDDR4__DENALI_CTL_368__CALVL_PERIODIC
  5590. #define LPDDR4__DENALI_CTL_369_READ_MASK 0x03010101U
  5591. #define LPDDR4__DENALI_CTL_369_WRITE_MASK 0x03010101U
  5592. #define LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT_MASK 0x00000001U
  5593. #define LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT_SHIFT 0U
  5594. #define LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT_WIDTH 1U
  5595. #define LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT_WOCLR 0U
  5596. #define LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT_WOSET 0U
  5597. #define LPDDR4__CALVL_ON_SREF_EXIT__REG DENALI_CTL_369
  5598. #define LPDDR4__CALVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT
  5599. #define LPDDR4__DENALI_CTL_369__CALVL_AREF_EN_MASK 0x00000100U
  5600. #define LPDDR4__DENALI_CTL_369__CALVL_AREF_EN_SHIFT 8U
  5601. #define LPDDR4__DENALI_CTL_369__CALVL_AREF_EN_WIDTH 1U
  5602. #define LPDDR4__DENALI_CTL_369__CALVL_AREF_EN_WOCLR 0U
  5603. #define LPDDR4__DENALI_CTL_369__CALVL_AREF_EN_WOSET 0U
  5604. #define LPDDR4__CALVL_AREF_EN__REG DENALI_CTL_369
  5605. #define LPDDR4__CALVL_AREF_EN__FLD LPDDR4__DENALI_CTL_369__CALVL_AREF_EN
  5606. #define LPDDR4__DENALI_CTL_369__CALVL_ROTATE_MASK 0x00010000U
  5607. #define LPDDR4__DENALI_CTL_369__CALVL_ROTATE_SHIFT 16U
  5608. #define LPDDR4__DENALI_CTL_369__CALVL_ROTATE_WIDTH 1U
  5609. #define LPDDR4__DENALI_CTL_369__CALVL_ROTATE_WOCLR 0U
  5610. #define LPDDR4__DENALI_CTL_369__CALVL_ROTATE_WOSET 0U
  5611. #define LPDDR4__CALVL_ROTATE__REG DENALI_CTL_369
  5612. #define LPDDR4__CALVL_ROTATE__FLD LPDDR4__DENALI_CTL_369__CALVL_ROTATE
  5613. #define LPDDR4__DENALI_CTL_369__CALVL_CS_MAP_MASK 0x03000000U
  5614. #define LPDDR4__DENALI_CTL_369__CALVL_CS_MAP_SHIFT 24U
  5615. #define LPDDR4__DENALI_CTL_369__CALVL_CS_MAP_WIDTH 2U
  5616. #define LPDDR4__CALVL_CS_MAP__REG DENALI_CTL_369
  5617. #define LPDDR4__CALVL_CS_MAP__FLD LPDDR4__DENALI_CTL_369__CALVL_CS_MAP
  5618. #define LPDDR4__DENALI_CTL_370_READ_MASK 0xFFFFFFFFU
  5619. #define LPDDR4__DENALI_CTL_370_WRITE_MASK 0xFFFFFFFFU
  5620. #define LPDDR4__DENALI_CTL_370__CALVL_NORM_THRESHOLD_F0_MASK 0x0000FFFFU
  5621. #define LPDDR4__DENALI_CTL_370__CALVL_NORM_THRESHOLD_F0_SHIFT 0U
  5622. #define LPDDR4__DENALI_CTL_370__CALVL_NORM_THRESHOLD_F0_WIDTH 16U
  5623. #define LPDDR4__CALVL_NORM_THRESHOLD_F0__REG DENALI_CTL_370
  5624. #define LPDDR4__CALVL_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_370__CALVL_NORM_THRESHOLD_F0
  5625. #define LPDDR4__DENALI_CTL_370__CALVL_HIGH_THRESHOLD_F0_MASK 0xFFFF0000U
  5626. #define LPDDR4__DENALI_CTL_370__CALVL_HIGH_THRESHOLD_F0_SHIFT 16U
  5627. #define LPDDR4__DENALI_CTL_370__CALVL_HIGH_THRESHOLD_F0_WIDTH 16U
  5628. #define LPDDR4__CALVL_HIGH_THRESHOLD_F0__REG DENALI_CTL_370
  5629. #define LPDDR4__CALVL_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_370__CALVL_HIGH_THRESHOLD_F0
  5630. #define LPDDR4__DENALI_CTL_371_READ_MASK 0xFFFFFFFFU
  5631. #define LPDDR4__DENALI_CTL_371_WRITE_MASK 0xFFFFFFFFU
  5632. #define LPDDR4__DENALI_CTL_371__CALVL_TIMEOUT_F0_MASK 0x0000FFFFU
  5633. #define LPDDR4__DENALI_CTL_371__CALVL_TIMEOUT_F0_SHIFT 0U
  5634. #define LPDDR4__DENALI_CTL_371__CALVL_TIMEOUT_F0_WIDTH 16U
  5635. #define LPDDR4__CALVL_TIMEOUT_F0__REG DENALI_CTL_371
  5636. #define LPDDR4__CALVL_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_371__CALVL_TIMEOUT_F0
  5637. #define LPDDR4__DENALI_CTL_371__CALVL_SW_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U
  5638. #define LPDDR4__DENALI_CTL_371__CALVL_SW_PROMOTE_THRESHOLD_F0_SHIFT 16U
  5639. #define LPDDR4__DENALI_CTL_371__CALVL_SW_PROMOTE_THRESHOLD_F0_WIDTH 16U
  5640. #define LPDDR4__CALVL_SW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_371
  5641. #define LPDDR4__CALVL_SW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_371__CALVL_SW_PROMOTE_THRESHOLD_F0
  5642. #define LPDDR4__DENALI_CTL_372_READ_MASK 0xFFFFFFFFU
  5643. #define LPDDR4__DENALI_CTL_372_WRITE_MASK 0xFFFFFFFFU
  5644. #define LPDDR4__DENALI_CTL_372__CALVL_DFI_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
  5645. #define LPDDR4__DENALI_CTL_372__CALVL_DFI_PROMOTE_THRESHOLD_F0_SHIFT 0U
  5646. #define LPDDR4__DENALI_CTL_372__CALVL_DFI_PROMOTE_THRESHOLD_F0_WIDTH 16U
  5647. #define LPDDR4__CALVL_DFI_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_372
  5648. #define LPDDR4__CALVL_DFI_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_372__CALVL_DFI_PROMOTE_THRESHOLD_F0
  5649. #define LPDDR4__DENALI_CTL_372__CALVL_NORM_THRESHOLD_F1_MASK 0xFFFF0000U
  5650. #define LPDDR4__DENALI_CTL_372__CALVL_NORM_THRESHOLD_F1_SHIFT 16U
  5651. #define LPDDR4__DENALI_CTL_372__CALVL_NORM_THRESHOLD_F1_WIDTH 16U
  5652. #define LPDDR4__CALVL_NORM_THRESHOLD_F1__REG DENALI_CTL_372
  5653. #define LPDDR4__CALVL_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_372__CALVL_NORM_THRESHOLD_F1
  5654. #define LPDDR4__DENALI_CTL_373_READ_MASK 0xFFFFFFFFU
  5655. #define LPDDR4__DENALI_CTL_373_WRITE_MASK 0xFFFFFFFFU
  5656. #define LPDDR4__DENALI_CTL_373__CALVL_HIGH_THRESHOLD_F1_MASK 0x0000FFFFU
  5657. #define LPDDR4__DENALI_CTL_373__CALVL_HIGH_THRESHOLD_F1_SHIFT 0U
  5658. #define LPDDR4__DENALI_CTL_373__CALVL_HIGH_THRESHOLD_F1_WIDTH 16U
  5659. #define LPDDR4__CALVL_HIGH_THRESHOLD_F1__REG DENALI_CTL_373
  5660. #define LPDDR4__CALVL_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_373__CALVL_HIGH_THRESHOLD_F1
  5661. #define LPDDR4__DENALI_CTL_373__CALVL_TIMEOUT_F1_MASK 0xFFFF0000U
  5662. #define LPDDR4__DENALI_CTL_373__CALVL_TIMEOUT_F1_SHIFT 16U
  5663. #define LPDDR4__DENALI_CTL_373__CALVL_TIMEOUT_F1_WIDTH 16U
  5664. #define LPDDR4__CALVL_TIMEOUT_F1__REG DENALI_CTL_373
  5665. #define LPDDR4__CALVL_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_373__CALVL_TIMEOUT_F1
  5666. #define LPDDR4__DENALI_CTL_374_READ_MASK 0xFFFFFFFFU
  5667. #define LPDDR4__DENALI_CTL_374_WRITE_MASK 0xFFFFFFFFU
  5668. #define LPDDR4__DENALI_CTL_374__CALVL_SW_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU
  5669. #define LPDDR4__DENALI_CTL_374__CALVL_SW_PROMOTE_THRESHOLD_F1_SHIFT 0U
  5670. #define LPDDR4__DENALI_CTL_374__CALVL_SW_PROMOTE_THRESHOLD_F1_WIDTH 16U
  5671. #define LPDDR4__CALVL_SW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_374
  5672. #define LPDDR4__CALVL_SW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_374__CALVL_SW_PROMOTE_THRESHOLD_F1
  5673. #define LPDDR4__DENALI_CTL_374__CALVL_DFI_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U
  5674. #define LPDDR4__DENALI_CTL_374__CALVL_DFI_PROMOTE_THRESHOLD_F1_SHIFT 16U
  5675. #define LPDDR4__DENALI_CTL_374__CALVL_DFI_PROMOTE_THRESHOLD_F1_WIDTH 16U
  5676. #define LPDDR4__CALVL_DFI_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_374
  5677. #define LPDDR4__CALVL_DFI_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_374__CALVL_DFI_PROMOTE_THRESHOLD_F1
  5678. #define LPDDR4__DENALI_CTL_375_READ_MASK 0xFFFFFFFFU
  5679. #define LPDDR4__DENALI_CTL_375_WRITE_MASK 0xFFFFFFFFU
  5680. #define LPDDR4__DENALI_CTL_375__CALVL_NORM_THRESHOLD_F2_MASK 0x0000FFFFU
  5681. #define LPDDR4__DENALI_CTL_375__CALVL_NORM_THRESHOLD_F2_SHIFT 0U
  5682. #define LPDDR4__DENALI_CTL_375__CALVL_NORM_THRESHOLD_F2_WIDTH 16U
  5683. #define LPDDR4__CALVL_NORM_THRESHOLD_F2__REG DENALI_CTL_375
  5684. #define LPDDR4__CALVL_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_375__CALVL_NORM_THRESHOLD_F2
  5685. #define LPDDR4__DENALI_CTL_375__CALVL_HIGH_THRESHOLD_F2_MASK 0xFFFF0000U
  5686. #define LPDDR4__DENALI_CTL_375__CALVL_HIGH_THRESHOLD_F2_SHIFT 16U
  5687. #define LPDDR4__DENALI_CTL_375__CALVL_HIGH_THRESHOLD_F2_WIDTH 16U
  5688. #define LPDDR4__CALVL_HIGH_THRESHOLD_F2__REG DENALI_CTL_375
  5689. #define LPDDR4__CALVL_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_375__CALVL_HIGH_THRESHOLD_F2
  5690. #define LPDDR4__DENALI_CTL_376_READ_MASK 0xFFFFFFFFU
  5691. #define LPDDR4__DENALI_CTL_376_WRITE_MASK 0xFFFFFFFFU
  5692. #define LPDDR4__DENALI_CTL_376__CALVL_TIMEOUT_F2_MASK 0x0000FFFFU
  5693. #define LPDDR4__DENALI_CTL_376__CALVL_TIMEOUT_F2_SHIFT 0U
  5694. #define LPDDR4__DENALI_CTL_376__CALVL_TIMEOUT_F2_WIDTH 16U
  5695. #define LPDDR4__CALVL_TIMEOUT_F2__REG DENALI_CTL_376
  5696. #define LPDDR4__CALVL_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_376__CALVL_TIMEOUT_F2
  5697. #define LPDDR4__DENALI_CTL_376__CALVL_SW_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U
  5698. #define LPDDR4__DENALI_CTL_376__CALVL_SW_PROMOTE_THRESHOLD_F2_SHIFT 16U
  5699. #define LPDDR4__DENALI_CTL_376__CALVL_SW_PROMOTE_THRESHOLD_F2_WIDTH 16U
  5700. #define LPDDR4__CALVL_SW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_376
  5701. #define LPDDR4__CALVL_SW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_376__CALVL_SW_PROMOTE_THRESHOLD_F2
  5702. #define LPDDR4__DENALI_CTL_377_READ_MASK 0x0101FFFFU
  5703. #define LPDDR4__DENALI_CTL_377_WRITE_MASK 0x0101FFFFU
  5704. #define LPDDR4__DENALI_CTL_377__CALVL_DFI_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
  5705. #define LPDDR4__DENALI_CTL_377__CALVL_DFI_PROMOTE_THRESHOLD_F2_SHIFT 0U
  5706. #define LPDDR4__DENALI_CTL_377__CALVL_DFI_PROMOTE_THRESHOLD_F2_WIDTH 16U
  5707. #define LPDDR4__CALVL_DFI_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_377
  5708. #define LPDDR4__CALVL_DFI_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_377__CALVL_DFI_PROMOTE_THRESHOLD_F2
  5709. #define LPDDR4__DENALI_CTL_377__AXI0_ALL_STROBES_USED_ENABLE_MASK 0x00010000U
  5710. #define LPDDR4__DENALI_CTL_377__AXI0_ALL_STROBES_USED_ENABLE_SHIFT 16U
  5711. #define LPDDR4__DENALI_CTL_377__AXI0_ALL_STROBES_USED_ENABLE_WIDTH 1U
  5712. #define LPDDR4__DENALI_CTL_377__AXI0_ALL_STROBES_USED_ENABLE_WOCLR 0U
  5713. #define LPDDR4__DENALI_CTL_377__AXI0_ALL_STROBES_USED_ENABLE_WOSET 0U
  5714. #define LPDDR4__AXI0_ALL_STROBES_USED_ENABLE__REG DENALI_CTL_377
  5715. #define LPDDR4__AXI0_ALL_STROBES_USED_ENABLE__FLD LPDDR4__DENALI_CTL_377__AXI0_ALL_STROBES_USED_ENABLE
  5716. #define LPDDR4__DENALI_CTL_377__AXI0_FIXED_PORT_PRIORITY_ENABLE_MASK 0x01000000U
  5717. #define LPDDR4__DENALI_CTL_377__AXI0_FIXED_PORT_PRIORITY_ENABLE_SHIFT 24U
  5718. #define LPDDR4__DENALI_CTL_377__AXI0_FIXED_PORT_PRIORITY_ENABLE_WIDTH 1U
  5719. #define LPDDR4__DENALI_CTL_377__AXI0_FIXED_PORT_PRIORITY_ENABLE_WOCLR 0U
  5720. #define LPDDR4__DENALI_CTL_377__AXI0_FIXED_PORT_PRIORITY_ENABLE_WOSET 0U
  5721. #define LPDDR4__AXI0_FIXED_PORT_PRIORITY_ENABLE__REG DENALI_CTL_377
  5722. #define LPDDR4__AXI0_FIXED_PORT_PRIORITY_ENABLE__FLD LPDDR4__DENALI_CTL_377__AXI0_FIXED_PORT_PRIORITY_ENABLE
  5723. #define LPDDR4__DENALI_CTL_378_READ_MASK 0x00000707U
  5724. #define LPDDR4__DENALI_CTL_378_WRITE_MASK 0x00000707U
  5725. #define LPDDR4__DENALI_CTL_378__AXI0_R_PRIORITY_MASK 0x00000007U
  5726. #define LPDDR4__DENALI_CTL_378__AXI0_R_PRIORITY_SHIFT 0U
  5727. #define LPDDR4__DENALI_CTL_378__AXI0_R_PRIORITY_WIDTH 3U
  5728. #define LPDDR4__AXI0_R_PRIORITY__REG DENALI_CTL_378
  5729. #define LPDDR4__AXI0_R_PRIORITY__FLD LPDDR4__DENALI_CTL_378__AXI0_R_PRIORITY
  5730. #define LPDDR4__DENALI_CTL_378__AXI0_W_PRIORITY_MASK 0x00000700U
  5731. #define LPDDR4__DENALI_CTL_378__AXI0_W_PRIORITY_SHIFT 8U
  5732. #define LPDDR4__DENALI_CTL_378__AXI0_W_PRIORITY_WIDTH 3U
  5733. #define LPDDR4__AXI0_W_PRIORITY__REG DENALI_CTL_378
  5734. #define LPDDR4__AXI0_W_PRIORITY__FLD LPDDR4__DENALI_CTL_378__AXI0_W_PRIORITY
  5735. #define LPDDR4__DENALI_CTL_379_READ_MASK 0xFFFFFFFFU
  5736. #define LPDDR4__DENALI_CTL_379_WRITE_MASK 0xFFFFFFFFU
  5737. #define LPDDR4__DENALI_CTL_379__PARITY_ERROR_ADDRESS_0_MASK 0xFFFFFFFFU
  5738. #define LPDDR4__DENALI_CTL_379__PARITY_ERROR_ADDRESS_0_SHIFT 0U
  5739. #define LPDDR4__DENALI_CTL_379__PARITY_ERROR_ADDRESS_0_WIDTH 32U
  5740. #define LPDDR4__PARITY_ERROR_ADDRESS_0__REG DENALI_CTL_379
  5741. #define LPDDR4__PARITY_ERROR_ADDRESS_0__FLD LPDDR4__DENALI_CTL_379__PARITY_ERROR_ADDRESS_0
  5742. #define LPDDR4__DENALI_CTL_380_READ_MASK 0x1FFF3F07U
  5743. #define LPDDR4__DENALI_CTL_380_WRITE_MASK 0x1FFF3F07U
  5744. #define LPDDR4__DENALI_CTL_380__PARITY_ERROR_ADDRESS_1_MASK 0x00000007U
  5745. #define LPDDR4__DENALI_CTL_380__PARITY_ERROR_ADDRESS_1_SHIFT 0U
  5746. #define LPDDR4__DENALI_CTL_380__PARITY_ERROR_ADDRESS_1_WIDTH 3U
  5747. #define LPDDR4__PARITY_ERROR_ADDRESS_1__REG DENALI_CTL_380
  5748. #define LPDDR4__PARITY_ERROR_ADDRESS_1__FLD LPDDR4__DENALI_CTL_380__PARITY_ERROR_ADDRESS_1
  5749. #define LPDDR4__DENALI_CTL_380__PARITY_ERROR_MASTER_ID_MASK 0x00003F00U
  5750. #define LPDDR4__DENALI_CTL_380__PARITY_ERROR_MASTER_ID_SHIFT 8U
  5751. #define LPDDR4__DENALI_CTL_380__PARITY_ERROR_MASTER_ID_WIDTH 6U
  5752. #define LPDDR4__PARITY_ERROR_MASTER_ID__REG DENALI_CTL_380
  5753. #define LPDDR4__PARITY_ERROR_MASTER_ID__FLD LPDDR4__DENALI_CTL_380__PARITY_ERROR_MASTER_ID
  5754. #define LPDDR4__DENALI_CTL_380__PARITY_ERROR_BUS_CHANNEL_MASK 0x1FFF0000U
  5755. #define LPDDR4__DENALI_CTL_380__PARITY_ERROR_BUS_CHANNEL_SHIFT 16U
  5756. #define LPDDR4__DENALI_CTL_380__PARITY_ERROR_BUS_CHANNEL_WIDTH 13U
  5757. #define LPDDR4__PARITY_ERROR_BUS_CHANNEL__REG DENALI_CTL_380
  5758. #define LPDDR4__PARITY_ERROR_BUS_CHANNEL__FLD LPDDR4__DENALI_CTL_380__PARITY_ERROR_BUS_CHANNEL
  5759. #define LPDDR4__DENALI_CTL_381_READ_MASK 0xFFFFFFFFU
  5760. #define LPDDR4__DENALI_CTL_381_WRITE_MASK 0xFFFFFFFFU
  5761. #define LPDDR4__DENALI_CTL_381__PARITY_ERROR_WRITE_DATA_0_MASK 0xFFFFFFFFU
  5762. #define LPDDR4__DENALI_CTL_381__PARITY_ERROR_WRITE_DATA_0_SHIFT 0U
  5763. #define LPDDR4__DENALI_CTL_381__PARITY_ERROR_WRITE_DATA_0_WIDTH 32U
  5764. #define LPDDR4__PARITY_ERROR_WRITE_DATA_0__REG DENALI_CTL_381
  5765. #define LPDDR4__PARITY_ERROR_WRITE_DATA_0__FLD LPDDR4__DENALI_CTL_381__PARITY_ERROR_WRITE_DATA_0
  5766. #define LPDDR4__DENALI_CTL_382_READ_MASK 0xFFFFFFFFU
  5767. #define LPDDR4__DENALI_CTL_382_WRITE_MASK 0xFFFFFFFFU
  5768. #define LPDDR4__DENALI_CTL_382__PARITY_ERROR_WRITE_DATA_1_MASK 0xFFFFFFFFU
  5769. #define LPDDR4__DENALI_CTL_382__PARITY_ERROR_WRITE_DATA_1_SHIFT 0U
  5770. #define LPDDR4__DENALI_CTL_382__PARITY_ERROR_WRITE_DATA_1_WIDTH 32U
  5771. #define LPDDR4__PARITY_ERROR_WRITE_DATA_1__REG DENALI_CTL_382
  5772. #define LPDDR4__PARITY_ERROR_WRITE_DATA_1__FLD LPDDR4__DENALI_CTL_382__PARITY_ERROR_WRITE_DATA_1
  5773. #define LPDDR4__DENALI_CTL_383_READ_MASK 0xFFFFFFFFU
  5774. #define LPDDR4__DENALI_CTL_383_WRITE_MASK 0xFFFFFFFFU
  5775. #define LPDDR4__DENALI_CTL_383__PARITY_ERROR_WRITE_DATA_2_MASK 0xFFFFFFFFU
  5776. #define LPDDR4__DENALI_CTL_383__PARITY_ERROR_WRITE_DATA_2_SHIFT 0U
  5777. #define LPDDR4__DENALI_CTL_383__PARITY_ERROR_WRITE_DATA_2_WIDTH 32U
  5778. #define LPDDR4__PARITY_ERROR_WRITE_DATA_2__REG DENALI_CTL_383
  5779. #define LPDDR4__PARITY_ERROR_WRITE_DATA_2__FLD LPDDR4__DENALI_CTL_383__PARITY_ERROR_WRITE_DATA_2
  5780. #define LPDDR4__DENALI_CTL_384_READ_MASK 0xFFFFFFFFU
  5781. #define LPDDR4__DENALI_CTL_384_WRITE_MASK 0xFFFFFFFFU
  5782. #define LPDDR4__DENALI_CTL_384__PARITY_ERROR_WRITE_DATA_3_MASK 0xFFFFFFFFU
  5783. #define LPDDR4__DENALI_CTL_384__PARITY_ERROR_WRITE_DATA_3_SHIFT 0U
  5784. #define LPDDR4__DENALI_CTL_384__PARITY_ERROR_WRITE_DATA_3_WIDTH 32U
  5785. #define LPDDR4__PARITY_ERROR_WRITE_DATA_3__REG DENALI_CTL_384
  5786. #define LPDDR4__PARITY_ERROR_WRITE_DATA_3__FLD LPDDR4__DENALI_CTL_384__PARITY_ERROR_WRITE_DATA_3
  5787. #define LPDDR4__DENALI_CTL_385_READ_MASK 0x0103FFFFU
  5788. #define LPDDR4__DENALI_CTL_385_WRITE_MASK 0x0103FFFFU
  5789. #define LPDDR4__DENALI_CTL_385__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR_MASK 0x0000FFFFU
  5790. #define LPDDR4__DENALI_CTL_385__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR_SHIFT 0U
  5791. #define LPDDR4__DENALI_CTL_385__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR_WIDTH 16U
  5792. #define LPDDR4__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR__REG DENALI_CTL_385
  5793. #define LPDDR4__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR__FLD LPDDR4__DENALI_CTL_385__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR
  5794. #define LPDDR4__DENALI_CTL_385__CKE_STATUS_MASK 0x00030000U
  5795. #define LPDDR4__DENALI_CTL_385__CKE_STATUS_SHIFT 16U
  5796. #define LPDDR4__DENALI_CTL_385__CKE_STATUS_WIDTH 2U
  5797. #define LPDDR4__CKE_STATUS__REG DENALI_CTL_385
  5798. #define LPDDR4__CKE_STATUS__FLD LPDDR4__DENALI_CTL_385__CKE_STATUS
  5799. #define LPDDR4__DENALI_CTL_385__MEM_RST_VALID_MASK 0x01000000U
  5800. #define LPDDR4__DENALI_CTL_385__MEM_RST_VALID_SHIFT 24U
  5801. #define LPDDR4__DENALI_CTL_385__MEM_RST_VALID_WIDTH 1U
  5802. #define LPDDR4__DENALI_CTL_385__MEM_RST_VALID_WOCLR 0U
  5803. #define LPDDR4__DENALI_CTL_385__MEM_RST_VALID_WOSET 0U
  5804. #define LPDDR4__MEM_RST_VALID__REG DENALI_CTL_385
  5805. #define LPDDR4__MEM_RST_VALID__FLD LPDDR4__DENALI_CTL_385__MEM_RST_VALID
  5806. #define LPDDR4__DENALI_CTL_386_READ_MASK 0x7FFFFFFFU
  5807. #define LPDDR4__DENALI_CTL_386_WRITE_MASK 0x7FFFFFFFU
  5808. #define LPDDR4__DENALI_CTL_386__DLL_RST_DELAY_MASK 0x0000FFFFU
  5809. #define LPDDR4__DENALI_CTL_386__DLL_RST_DELAY_SHIFT 0U
  5810. #define LPDDR4__DENALI_CTL_386__DLL_RST_DELAY_WIDTH 16U
  5811. #define LPDDR4__DLL_RST_DELAY__REG DENALI_CTL_386
  5812. #define LPDDR4__DLL_RST_DELAY__FLD LPDDR4__DENALI_CTL_386__DLL_RST_DELAY
  5813. #define LPDDR4__DENALI_CTL_386__DLL_RST_ADJ_DLY_MASK 0x00FF0000U
  5814. #define LPDDR4__DENALI_CTL_386__DLL_RST_ADJ_DLY_SHIFT 16U
  5815. #define LPDDR4__DENALI_CTL_386__DLL_RST_ADJ_DLY_WIDTH 8U
  5816. #define LPDDR4__DLL_RST_ADJ_DLY__REG DENALI_CTL_386
  5817. #define LPDDR4__DLL_RST_ADJ_DLY__FLD LPDDR4__DENALI_CTL_386__DLL_RST_ADJ_DLY
  5818. #define LPDDR4__DENALI_CTL_386__TDFI_PHY_WRLAT_MASK 0x7F000000U
  5819. #define LPDDR4__DENALI_CTL_386__TDFI_PHY_WRLAT_SHIFT 24U
  5820. #define LPDDR4__DENALI_CTL_386__TDFI_PHY_WRLAT_WIDTH 7U
  5821. #define LPDDR4__TDFI_PHY_WRLAT__REG DENALI_CTL_386
  5822. #define LPDDR4__TDFI_PHY_WRLAT__FLD LPDDR4__DENALI_CTL_386__TDFI_PHY_WRLAT
  5823. #define LPDDR4__DENALI_CTL_387_READ_MASK 0x7F7F7F7FU
  5824. #define LPDDR4__DENALI_CTL_387_WRITE_MASK 0x7F7F7F7FU
  5825. #define LPDDR4__DENALI_CTL_387__UPDATE_ERROR_STATUS_MASK 0x0000007FU
  5826. #define LPDDR4__DENALI_CTL_387__UPDATE_ERROR_STATUS_SHIFT 0U
  5827. #define LPDDR4__DENALI_CTL_387__UPDATE_ERROR_STATUS_WIDTH 7U
  5828. #define LPDDR4__UPDATE_ERROR_STATUS__REG DENALI_CTL_387
  5829. #define LPDDR4__UPDATE_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_387__UPDATE_ERROR_STATUS
  5830. #define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F0_MASK 0x00007F00U
  5831. #define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F0_SHIFT 8U
  5832. #define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F0_WIDTH 7U
  5833. #define LPDDR4__TDFI_PHY_RDLAT_F0__REG DENALI_CTL_387
  5834. #define LPDDR4__TDFI_PHY_RDLAT_F0__FLD LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F0
  5835. #define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F1_MASK 0x007F0000U
  5836. #define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F1_SHIFT 16U
  5837. #define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F1_WIDTH 7U
  5838. #define LPDDR4__TDFI_PHY_RDLAT_F1__REG DENALI_CTL_387
  5839. #define LPDDR4__TDFI_PHY_RDLAT_F1__FLD LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F1
  5840. #define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F2_MASK 0x7F000000U
  5841. #define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F2_SHIFT 24U
  5842. #define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F2_WIDTH 7U
  5843. #define LPDDR4__TDFI_PHY_RDLAT_F2__REG DENALI_CTL_387
  5844. #define LPDDR4__TDFI_PHY_RDLAT_F2__FLD LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F2
  5845. #define LPDDR4__DENALI_CTL_388_READ_MASK 0x00FF037FU
  5846. #define LPDDR4__DENALI_CTL_388_WRITE_MASK 0x00FF037FU
  5847. #define LPDDR4__DENALI_CTL_388__TDFI_RDDATA_EN_MASK 0x0000007FU
  5848. #define LPDDR4__DENALI_CTL_388__TDFI_RDDATA_EN_SHIFT 0U
  5849. #define LPDDR4__DENALI_CTL_388__TDFI_RDDATA_EN_WIDTH 7U
  5850. #define LPDDR4__TDFI_RDDATA_EN__REG DENALI_CTL_388
  5851. #define LPDDR4__TDFI_RDDATA_EN__FLD LPDDR4__DENALI_CTL_388__TDFI_RDDATA_EN
  5852. #define LPDDR4__DENALI_CTL_388__DRAM_CLK_DISABLE_MASK 0x00000300U
  5853. #define LPDDR4__DENALI_CTL_388__DRAM_CLK_DISABLE_SHIFT 8U
  5854. #define LPDDR4__DENALI_CTL_388__DRAM_CLK_DISABLE_WIDTH 2U
  5855. #define LPDDR4__DRAM_CLK_DISABLE__REG DENALI_CTL_388
  5856. #define LPDDR4__DRAM_CLK_DISABLE__FLD LPDDR4__DENALI_CTL_388__DRAM_CLK_DISABLE
  5857. #define LPDDR4__DENALI_CTL_388__TDFI_CTRLUPD_MIN_MASK 0x00FF0000U
  5858. #define LPDDR4__DENALI_CTL_388__TDFI_CTRLUPD_MIN_SHIFT 16U
  5859. #define LPDDR4__DENALI_CTL_388__TDFI_CTRLUPD_MIN_WIDTH 8U
  5860. #define LPDDR4__TDFI_CTRLUPD_MIN__REG DENALI_CTL_388
  5861. #define LPDDR4__TDFI_CTRLUPD_MIN__FLD LPDDR4__DENALI_CTL_388__TDFI_CTRLUPD_MIN
  5862. #define LPDDR4__DENALI_CTL_389_READ_MASK 0x001FFFFFU
  5863. #define LPDDR4__DENALI_CTL_389_WRITE_MASK 0x001FFFFFU
  5864. #define LPDDR4__DENALI_CTL_389__TDFI_CTRLUPD_MAX_F0_MASK 0x001FFFFFU
  5865. #define LPDDR4__DENALI_CTL_389__TDFI_CTRLUPD_MAX_F0_SHIFT 0U
  5866. #define LPDDR4__DENALI_CTL_389__TDFI_CTRLUPD_MAX_F0_WIDTH 21U
  5867. #define LPDDR4__TDFI_CTRLUPD_MAX_F0__REG DENALI_CTL_389
  5868. #define LPDDR4__TDFI_CTRLUPD_MAX_F0__FLD LPDDR4__DENALI_CTL_389__TDFI_CTRLUPD_MAX_F0
  5869. #define LPDDR4__DENALI_CTL_390_READ_MASK 0xFFFFFFFFU
  5870. #define LPDDR4__DENALI_CTL_390_WRITE_MASK 0xFFFFFFFFU
  5871. #define LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_TYPE0_F0_MASK 0xFFFFFFFFU
  5872. #define LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_TYPE0_F0_SHIFT 0U
  5873. #define LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_TYPE0_F0_WIDTH 32U
  5874. #define LPDDR4__TDFI_PHYUPD_TYPE0_F0__REG DENALI_CTL_390
  5875. #define LPDDR4__TDFI_PHYUPD_TYPE0_F0__FLD LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_TYPE0_F0
  5876. #define LPDDR4__DENALI_CTL_391_READ_MASK 0xFFFFFFFFU
  5877. #define LPDDR4__DENALI_CTL_391_WRITE_MASK 0xFFFFFFFFU
  5878. #define LPDDR4__DENALI_CTL_391__TDFI_PHYUPD_TYPE1_F0_MASK 0xFFFFFFFFU
  5879. #define LPDDR4__DENALI_CTL_391__TDFI_PHYUPD_TYPE1_F0_SHIFT 0U
  5880. #define LPDDR4__DENALI_CTL_391__TDFI_PHYUPD_TYPE1_F0_WIDTH 32U
  5881. #define LPDDR4__TDFI_PHYUPD_TYPE1_F0__REG DENALI_CTL_391
  5882. #define LPDDR4__TDFI_PHYUPD_TYPE1_F0__FLD LPDDR4__DENALI_CTL_391__TDFI_PHYUPD_TYPE1_F0
  5883. #define LPDDR4__DENALI_CTL_392_READ_MASK 0xFFFFFFFFU
  5884. #define LPDDR4__DENALI_CTL_392_WRITE_MASK 0xFFFFFFFFU
  5885. #define LPDDR4__DENALI_CTL_392__TDFI_PHYUPD_TYPE2_F0_MASK 0xFFFFFFFFU
  5886. #define LPDDR4__DENALI_CTL_392__TDFI_PHYUPD_TYPE2_F0_SHIFT 0U
  5887. #define LPDDR4__DENALI_CTL_392__TDFI_PHYUPD_TYPE2_F0_WIDTH 32U
  5888. #define LPDDR4__TDFI_PHYUPD_TYPE2_F0__REG DENALI_CTL_392
  5889. #define LPDDR4__TDFI_PHYUPD_TYPE2_F0__FLD LPDDR4__DENALI_CTL_392__TDFI_PHYUPD_TYPE2_F0
  5890. #define LPDDR4__DENALI_CTL_393_READ_MASK 0xFFFFFFFFU
  5891. #define LPDDR4__DENALI_CTL_393_WRITE_MASK 0xFFFFFFFFU
  5892. #define LPDDR4__DENALI_CTL_393__TDFI_PHYUPD_TYPE3_F0_MASK 0xFFFFFFFFU
  5893. #define LPDDR4__DENALI_CTL_393__TDFI_PHYUPD_TYPE3_F0_SHIFT 0U
  5894. #define LPDDR4__DENALI_CTL_393__TDFI_PHYUPD_TYPE3_F0_WIDTH 32U
  5895. #define LPDDR4__TDFI_PHYUPD_TYPE3_F0__REG DENALI_CTL_393
  5896. #define LPDDR4__TDFI_PHYUPD_TYPE3_F0__FLD LPDDR4__DENALI_CTL_393__TDFI_PHYUPD_TYPE3_F0
  5897. #define LPDDR4__DENALI_CTL_394_READ_MASK 0x007FFFFFU
  5898. #define LPDDR4__DENALI_CTL_394_WRITE_MASK 0x007FFFFFU
  5899. #define LPDDR4__DENALI_CTL_394__TDFI_PHYUPD_RESP_F0_MASK 0x007FFFFFU
  5900. #define LPDDR4__DENALI_CTL_394__TDFI_PHYUPD_RESP_F0_SHIFT 0U
  5901. #define LPDDR4__DENALI_CTL_394__TDFI_PHYUPD_RESP_F0_WIDTH 23U
  5902. #define LPDDR4__TDFI_PHYUPD_RESP_F0__REG DENALI_CTL_394
  5903. #define LPDDR4__TDFI_PHYUPD_RESP_F0__FLD LPDDR4__DENALI_CTL_394__TDFI_PHYUPD_RESP_F0
  5904. #define LPDDR4__DENALI_CTL_395_READ_MASK 0xFFFFFFFFU
  5905. #define LPDDR4__DENALI_CTL_395_WRITE_MASK 0xFFFFFFFFU
  5906. #define LPDDR4__DENALI_CTL_395__TDFI_CTRLUPD_INTERVAL_F0_MASK 0xFFFFFFFFU
  5907. #define LPDDR4__DENALI_CTL_395__TDFI_CTRLUPD_INTERVAL_F0_SHIFT 0U
  5908. #define LPDDR4__DENALI_CTL_395__TDFI_CTRLUPD_INTERVAL_F0_WIDTH 32U
  5909. #define LPDDR4__TDFI_CTRLUPD_INTERVAL_F0__REG DENALI_CTL_395
  5910. #define LPDDR4__TDFI_CTRLUPD_INTERVAL_F0__FLD LPDDR4__DENALI_CTL_395__TDFI_CTRLUPD_INTERVAL_F0
  5911. #define LPDDR4__DENALI_CTL_396_READ_MASK 0x00007F7FU
  5912. #define LPDDR4__DENALI_CTL_396_WRITE_MASK 0x00007F7FU
  5913. #define LPDDR4__DENALI_CTL_396__RDLAT_ADJ_F0_MASK 0x0000007FU
  5914. #define LPDDR4__DENALI_CTL_396__RDLAT_ADJ_F0_SHIFT 0U
  5915. #define LPDDR4__DENALI_CTL_396__RDLAT_ADJ_F0_WIDTH 7U
  5916. #define LPDDR4__RDLAT_ADJ_F0__REG DENALI_CTL_396
  5917. #define LPDDR4__RDLAT_ADJ_F0__FLD LPDDR4__DENALI_CTL_396__RDLAT_ADJ_F0
  5918. #define LPDDR4__DENALI_CTL_396__WRLAT_ADJ_F0_MASK 0x00007F00U
  5919. #define LPDDR4__DENALI_CTL_396__WRLAT_ADJ_F0_SHIFT 8U
  5920. #define LPDDR4__DENALI_CTL_396__WRLAT_ADJ_F0_WIDTH 7U
  5921. #define LPDDR4__WRLAT_ADJ_F0__REG DENALI_CTL_396
  5922. #define LPDDR4__WRLAT_ADJ_F0__FLD LPDDR4__DENALI_CTL_396__WRLAT_ADJ_F0
  5923. #define LPDDR4__DENALI_CTL_397_READ_MASK 0x001FFFFFU
  5924. #define LPDDR4__DENALI_CTL_397_WRITE_MASK 0x001FFFFFU
  5925. #define LPDDR4__DENALI_CTL_397__TDFI_CTRLUPD_MAX_F1_MASK 0x001FFFFFU
  5926. #define LPDDR4__DENALI_CTL_397__TDFI_CTRLUPD_MAX_F1_SHIFT 0U
  5927. #define LPDDR4__DENALI_CTL_397__TDFI_CTRLUPD_MAX_F1_WIDTH 21U
  5928. #define LPDDR4__TDFI_CTRLUPD_MAX_F1__REG DENALI_CTL_397
  5929. #define LPDDR4__TDFI_CTRLUPD_MAX_F1__FLD LPDDR4__DENALI_CTL_397__TDFI_CTRLUPD_MAX_F1
  5930. #define LPDDR4__DENALI_CTL_398_READ_MASK 0xFFFFFFFFU
  5931. #define LPDDR4__DENALI_CTL_398_WRITE_MASK 0xFFFFFFFFU
  5932. #define LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE0_F1_MASK 0xFFFFFFFFU
  5933. #define LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE0_F1_SHIFT 0U
  5934. #define LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE0_F1_WIDTH 32U
  5935. #define LPDDR4__TDFI_PHYUPD_TYPE0_F1__REG DENALI_CTL_398
  5936. #define LPDDR4__TDFI_PHYUPD_TYPE0_F1__FLD LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE0_F1
  5937. #define LPDDR4__DENALI_CTL_399_READ_MASK 0xFFFFFFFFU
  5938. #define LPDDR4__DENALI_CTL_399_WRITE_MASK 0xFFFFFFFFU
  5939. #define LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_TYPE1_F1_MASK 0xFFFFFFFFU
  5940. #define LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_TYPE1_F1_SHIFT 0U
  5941. #define LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_TYPE1_F1_WIDTH 32U
  5942. #define LPDDR4__TDFI_PHYUPD_TYPE1_F1__REG DENALI_CTL_399
  5943. #define LPDDR4__TDFI_PHYUPD_TYPE1_F1__FLD LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_TYPE1_F1
  5944. #define LPDDR4__DENALI_CTL_400_READ_MASK 0xFFFFFFFFU
  5945. #define LPDDR4__DENALI_CTL_400_WRITE_MASK 0xFFFFFFFFU
  5946. #define LPDDR4__DENALI_CTL_400__TDFI_PHYUPD_TYPE2_F1_MASK 0xFFFFFFFFU
  5947. #define LPDDR4__DENALI_CTL_400__TDFI_PHYUPD_TYPE2_F1_SHIFT 0U
  5948. #define LPDDR4__DENALI_CTL_400__TDFI_PHYUPD_TYPE2_F1_WIDTH 32U
  5949. #define LPDDR4__TDFI_PHYUPD_TYPE2_F1__REG DENALI_CTL_400
  5950. #define LPDDR4__TDFI_PHYUPD_TYPE2_F1__FLD LPDDR4__DENALI_CTL_400__TDFI_PHYUPD_TYPE2_F1
  5951. #define LPDDR4__DENALI_CTL_401_READ_MASK 0xFFFFFFFFU
  5952. #define LPDDR4__DENALI_CTL_401_WRITE_MASK 0xFFFFFFFFU
  5953. #define LPDDR4__DENALI_CTL_401__TDFI_PHYUPD_TYPE3_F1_MASK 0xFFFFFFFFU
  5954. #define LPDDR4__DENALI_CTL_401__TDFI_PHYUPD_TYPE3_F1_SHIFT 0U
  5955. #define LPDDR4__DENALI_CTL_401__TDFI_PHYUPD_TYPE3_F1_WIDTH 32U
  5956. #define LPDDR4__TDFI_PHYUPD_TYPE3_F1__REG DENALI_CTL_401
  5957. #define LPDDR4__TDFI_PHYUPD_TYPE3_F1__FLD LPDDR4__DENALI_CTL_401__TDFI_PHYUPD_TYPE3_F1
  5958. #define LPDDR4__DENALI_CTL_402_READ_MASK 0x007FFFFFU
  5959. #define LPDDR4__DENALI_CTL_402_WRITE_MASK 0x007FFFFFU
  5960. #define LPDDR4__DENALI_CTL_402__TDFI_PHYUPD_RESP_F1_MASK 0x007FFFFFU
  5961. #define LPDDR4__DENALI_CTL_402__TDFI_PHYUPD_RESP_F1_SHIFT 0U
  5962. #define LPDDR4__DENALI_CTL_402__TDFI_PHYUPD_RESP_F1_WIDTH 23U
  5963. #define LPDDR4__TDFI_PHYUPD_RESP_F1__REG DENALI_CTL_402
  5964. #define LPDDR4__TDFI_PHYUPD_RESP_F1__FLD LPDDR4__DENALI_CTL_402__TDFI_PHYUPD_RESP_F1
  5965. #define LPDDR4__DENALI_CTL_403_READ_MASK 0xFFFFFFFFU
  5966. #define LPDDR4__DENALI_CTL_403_WRITE_MASK 0xFFFFFFFFU
  5967. #define LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_INTERVAL_F1_MASK 0xFFFFFFFFU
  5968. #define LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_INTERVAL_F1_SHIFT 0U
  5969. #define LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_INTERVAL_F1_WIDTH 32U
  5970. #define LPDDR4__TDFI_CTRLUPD_INTERVAL_F1__REG DENALI_CTL_403
  5971. #define LPDDR4__TDFI_CTRLUPD_INTERVAL_F1__FLD LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_INTERVAL_F1
  5972. #define LPDDR4__DENALI_CTL_404_READ_MASK 0x00007F7FU
  5973. #define LPDDR4__DENALI_CTL_404_WRITE_MASK 0x00007F7FU
  5974. #define LPDDR4__DENALI_CTL_404__RDLAT_ADJ_F1_MASK 0x0000007FU
  5975. #define LPDDR4__DENALI_CTL_404__RDLAT_ADJ_F1_SHIFT 0U
  5976. #define LPDDR4__DENALI_CTL_404__RDLAT_ADJ_F1_WIDTH 7U
  5977. #define LPDDR4__RDLAT_ADJ_F1__REG DENALI_CTL_404
  5978. #define LPDDR4__RDLAT_ADJ_F1__FLD LPDDR4__DENALI_CTL_404__RDLAT_ADJ_F1
  5979. #define LPDDR4__DENALI_CTL_404__WRLAT_ADJ_F1_MASK 0x00007F00U
  5980. #define LPDDR4__DENALI_CTL_404__WRLAT_ADJ_F1_SHIFT 8U
  5981. #define LPDDR4__DENALI_CTL_404__WRLAT_ADJ_F1_WIDTH 7U
  5982. #define LPDDR4__WRLAT_ADJ_F1__REG DENALI_CTL_404
  5983. #define LPDDR4__WRLAT_ADJ_F1__FLD LPDDR4__DENALI_CTL_404__WRLAT_ADJ_F1
  5984. #define LPDDR4__DENALI_CTL_405_READ_MASK 0x001FFFFFU
  5985. #define LPDDR4__DENALI_CTL_405_WRITE_MASK 0x001FFFFFU
  5986. #define LPDDR4__DENALI_CTL_405__TDFI_CTRLUPD_MAX_F2_MASK 0x001FFFFFU
  5987. #define LPDDR4__DENALI_CTL_405__TDFI_CTRLUPD_MAX_F2_SHIFT 0U
  5988. #define LPDDR4__DENALI_CTL_405__TDFI_CTRLUPD_MAX_F2_WIDTH 21U
  5989. #define LPDDR4__TDFI_CTRLUPD_MAX_F2__REG DENALI_CTL_405
  5990. #define LPDDR4__TDFI_CTRLUPD_MAX_F2__FLD LPDDR4__DENALI_CTL_405__TDFI_CTRLUPD_MAX_F2
  5991. #define LPDDR4__DENALI_CTL_406_READ_MASK 0xFFFFFFFFU
  5992. #define LPDDR4__DENALI_CTL_406_WRITE_MASK 0xFFFFFFFFU
  5993. #define LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE0_F2_MASK 0xFFFFFFFFU
  5994. #define LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE0_F2_SHIFT 0U
  5995. #define LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE0_F2_WIDTH 32U
  5996. #define LPDDR4__TDFI_PHYUPD_TYPE0_F2__REG DENALI_CTL_406
  5997. #define LPDDR4__TDFI_PHYUPD_TYPE0_F2__FLD LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE0_F2
  5998. #define LPDDR4__DENALI_CTL_407_READ_MASK 0xFFFFFFFFU
  5999. #define LPDDR4__DENALI_CTL_407_WRITE_MASK 0xFFFFFFFFU
  6000. #define LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE1_F2_MASK 0xFFFFFFFFU
  6001. #define LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE1_F2_SHIFT 0U
  6002. #define LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE1_F2_WIDTH 32U
  6003. #define LPDDR4__TDFI_PHYUPD_TYPE1_F2__REG DENALI_CTL_407
  6004. #define LPDDR4__TDFI_PHYUPD_TYPE1_F2__FLD LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE1_F2
  6005. #define LPDDR4__DENALI_CTL_408_READ_MASK 0xFFFFFFFFU
  6006. #define LPDDR4__DENALI_CTL_408_WRITE_MASK 0xFFFFFFFFU
  6007. #define LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_TYPE2_F2_MASK 0xFFFFFFFFU
  6008. #define LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_TYPE2_F2_SHIFT 0U
  6009. #define LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_TYPE2_F2_WIDTH 32U
  6010. #define LPDDR4__TDFI_PHYUPD_TYPE2_F2__REG DENALI_CTL_408
  6011. #define LPDDR4__TDFI_PHYUPD_TYPE2_F2__FLD LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_TYPE2_F2
  6012. #define LPDDR4__DENALI_CTL_409_READ_MASK 0xFFFFFFFFU
  6013. #define LPDDR4__DENALI_CTL_409_WRITE_MASK 0xFFFFFFFFU
  6014. #define LPDDR4__DENALI_CTL_409__TDFI_PHYUPD_TYPE3_F2_MASK 0xFFFFFFFFU
  6015. #define LPDDR4__DENALI_CTL_409__TDFI_PHYUPD_TYPE3_F2_SHIFT 0U
  6016. #define LPDDR4__DENALI_CTL_409__TDFI_PHYUPD_TYPE3_F2_WIDTH 32U
  6017. #define LPDDR4__TDFI_PHYUPD_TYPE3_F2__REG DENALI_CTL_409
  6018. #define LPDDR4__TDFI_PHYUPD_TYPE3_F2__FLD LPDDR4__DENALI_CTL_409__TDFI_PHYUPD_TYPE3_F2
  6019. #define LPDDR4__DENALI_CTL_410_READ_MASK 0x007FFFFFU
  6020. #define LPDDR4__DENALI_CTL_410_WRITE_MASK 0x007FFFFFU
  6021. #define LPDDR4__DENALI_CTL_410__TDFI_PHYUPD_RESP_F2_MASK 0x007FFFFFU
  6022. #define LPDDR4__DENALI_CTL_410__TDFI_PHYUPD_RESP_F2_SHIFT 0U
  6023. #define LPDDR4__DENALI_CTL_410__TDFI_PHYUPD_RESP_F2_WIDTH 23U
  6024. #define LPDDR4__TDFI_PHYUPD_RESP_F2__REG DENALI_CTL_410
  6025. #define LPDDR4__TDFI_PHYUPD_RESP_F2__FLD LPDDR4__DENALI_CTL_410__TDFI_PHYUPD_RESP_F2
  6026. #define LPDDR4__DENALI_CTL_411_READ_MASK 0xFFFFFFFFU
  6027. #define LPDDR4__DENALI_CTL_411_WRITE_MASK 0xFFFFFFFFU
  6028. #define LPDDR4__DENALI_CTL_411__TDFI_CTRLUPD_INTERVAL_F2_MASK 0xFFFFFFFFU
  6029. #define LPDDR4__DENALI_CTL_411__TDFI_CTRLUPD_INTERVAL_F2_SHIFT 0U
  6030. #define LPDDR4__DENALI_CTL_411__TDFI_CTRLUPD_INTERVAL_F2_WIDTH 32U
  6031. #define LPDDR4__TDFI_CTRLUPD_INTERVAL_F2__REG DENALI_CTL_411
  6032. #define LPDDR4__TDFI_CTRLUPD_INTERVAL_F2__FLD LPDDR4__DENALI_CTL_411__TDFI_CTRLUPD_INTERVAL_F2
  6033. #define LPDDR4__DENALI_CTL_412_READ_MASK 0x0F0F7F7FU
  6034. #define LPDDR4__DENALI_CTL_412_WRITE_MASK 0x0F0F7F7FU
  6035. #define LPDDR4__DENALI_CTL_412__RDLAT_ADJ_F2_MASK 0x0000007FU
  6036. #define LPDDR4__DENALI_CTL_412__RDLAT_ADJ_F2_SHIFT 0U
  6037. #define LPDDR4__DENALI_CTL_412__RDLAT_ADJ_F2_WIDTH 7U
  6038. #define LPDDR4__RDLAT_ADJ_F2__REG DENALI_CTL_412
  6039. #define LPDDR4__RDLAT_ADJ_F2__FLD LPDDR4__DENALI_CTL_412__RDLAT_ADJ_F2
  6040. #define LPDDR4__DENALI_CTL_412__WRLAT_ADJ_F2_MASK 0x00007F00U
  6041. #define LPDDR4__DENALI_CTL_412__WRLAT_ADJ_F2_SHIFT 8U
  6042. #define LPDDR4__DENALI_CTL_412__WRLAT_ADJ_F2_WIDTH 7U
  6043. #define LPDDR4__WRLAT_ADJ_F2__REG DENALI_CTL_412
  6044. #define LPDDR4__WRLAT_ADJ_F2__FLD LPDDR4__DENALI_CTL_412__WRLAT_ADJ_F2
  6045. #define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F0_MASK 0x000F0000U
  6046. #define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F0_SHIFT 16U
  6047. #define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F0_WIDTH 4U
  6048. #define LPDDR4__TDFI_CTRL_DELAY_F0__REG DENALI_CTL_412
  6049. #define LPDDR4__TDFI_CTRL_DELAY_F0__FLD LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F0
  6050. #define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F1_MASK 0x0F000000U
  6051. #define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F1_SHIFT 24U
  6052. #define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F1_WIDTH 4U
  6053. #define LPDDR4__TDFI_CTRL_DELAY_F1__REG DENALI_CTL_412
  6054. #define LPDDR4__TDFI_CTRL_DELAY_F1__FLD LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F1
  6055. #define LPDDR4__DENALI_CTL_413_READ_MASK 0xFF0F0F0FU
  6056. #define LPDDR4__DENALI_CTL_413_WRITE_MASK 0xFF0F0F0FU
  6057. #define LPDDR4__DENALI_CTL_413__TDFI_CTRL_DELAY_F2_MASK 0x0000000FU
  6058. #define LPDDR4__DENALI_CTL_413__TDFI_CTRL_DELAY_F2_SHIFT 0U
  6059. #define LPDDR4__DENALI_CTL_413__TDFI_CTRL_DELAY_F2_WIDTH 4U
  6060. #define LPDDR4__TDFI_CTRL_DELAY_F2__REG DENALI_CTL_413
  6061. #define LPDDR4__TDFI_CTRL_DELAY_F2__FLD LPDDR4__DENALI_CTL_413__TDFI_CTRL_DELAY_F2
  6062. #define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE_MASK 0x00000F00U
  6063. #define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE_SHIFT 8U
  6064. #define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE_WIDTH 4U
  6065. #define LPDDR4__TDFI_DRAM_CLK_DISABLE__REG DENALI_CTL_413
  6066. #define LPDDR4__TDFI_DRAM_CLK_DISABLE__FLD LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE
  6067. #define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE_MASK 0x000F0000U
  6068. #define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE_SHIFT 16U
  6069. #define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE_WIDTH 4U
  6070. #define LPDDR4__TDFI_DRAM_CLK_ENABLE__REG DENALI_CTL_413
  6071. #define LPDDR4__TDFI_DRAM_CLK_ENABLE__FLD LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE
  6072. #define LPDDR4__DENALI_CTL_413__TDFI_WRLVL_EN_MASK 0xFF000000U
  6073. #define LPDDR4__DENALI_CTL_413__TDFI_WRLVL_EN_SHIFT 24U
  6074. #define LPDDR4__DENALI_CTL_413__TDFI_WRLVL_EN_WIDTH 8U
  6075. #define LPDDR4__TDFI_WRLVL_EN__REG DENALI_CTL_413
  6076. #define LPDDR4__TDFI_WRLVL_EN__FLD LPDDR4__DENALI_CTL_413__TDFI_WRLVL_EN
  6077. #define LPDDR4__DENALI_CTL_414_READ_MASK 0x000003FFU
  6078. #define LPDDR4__DENALI_CTL_414_WRITE_MASK 0x000003FFU
  6079. #define LPDDR4__DENALI_CTL_414__TDFI_WRLVL_WW_MASK 0x000003FFU
  6080. #define LPDDR4__DENALI_CTL_414__TDFI_WRLVL_WW_SHIFT 0U
  6081. #define LPDDR4__DENALI_CTL_414__TDFI_WRLVL_WW_WIDTH 10U
  6082. #define LPDDR4__TDFI_WRLVL_WW__REG DENALI_CTL_414
  6083. #define LPDDR4__TDFI_WRLVL_WW__FLD LPDDR4__DENALI_CTL_414__TDFI_WRLVL_WW
  6084. #define LPDDR4__DENALI_CTL_415_READ_MASK 0xFFFFFFFFU
  6085. #define LPDDR4__DENALI_CTL_415_WRITE_MASK 0xFFFFFFFFU
  6086. #define LPDDR4__DENALI_CTL_415__TDFI_WRLVL_RESP_MASK 0xFFFFFFFFU
  6087. #define LPDDR4__DENALI_CTL_415__TDFI_WRLVL_RESP_SHIFT 0U
  6088. #define LPDDR4__DENALI_CTL_415__TDFI_WRLVL_RESP_WIDTH 32U
  6089. #define LPDDR4__TDFI_WRLVL_RESP__REG DENALI_CTL_415
  6090. #define LPDDR4__TDFI_WRLVL_RESP__FLD LPDDR4__DENALI_CTL_415__TDFI_WRLVL_RESP
  6091. #define LPDDR4__DENALI_CTL_416_READ_MASK 0xFFFFFFFFU
  6092. #define LPDDR4__DENALI_CTL_416_WRITE_MASK 0xFFFFFFFFU
  6093. #define LPDDR4__DENALI_CTL_416__TDFI_WRLVL_MAX_MASK 0xFFFFFFFFU
  6094. #define LPDDR4__DENALI_CTL_416__TDFI_WRLVL_MAX_SHIFT 0U
  6095. #define LPDDR4__DENALI_CTL_416__TDFI_WRLVL_MAX_WIDTH 32U
  6096. #define LPDDR4__TDFI_WRLVL_MAX__REG DENALI_CTL_416
  6097. #define LPDDR4__TDFI_WRLVL_MAX__FLD LPDDR4__DENALI_CTL_416__TDFI_WRLVL_MAX
  6098. #define LPDDR4__DENALI_CTL_417_READ_MASK 0x0003FFFFU
  6099. #define LPDDR4__DENALI_CTL_417_WRITE_MASK 0x0003FFFFU
  6100. #define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_EN_MASK 0x000000FFU
  6101. #define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_EN_SHIFT 0U
  6102. #define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_EN_WIDTH 8U
  6103. #define LPDDR4__TDFI_RDLVL_EN__REG DENALI_CTL_417
  6104. #define LPDDR4__TDFI_RDLVL_EN__FLD LPDDR4__DENALI_CTL_417__TDFI_RDLVL_EN
  6105. #define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_RR_MASK 0x0003FF00U
  6106. #define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_RR_SHIFT 8U
  6107. #define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_RR_WIDTH 10U
  6108. #define LPDDR4__TDFI_RDLVL_RR__REG DENALI_CTL_417
  6109. #define LPDDR4__TDFI_RDLVL_RR__FLD LPDDR4__DENALI_CTL_417__TDFI_RDLVL_RR
  6110. #define LPDDR4__DENALI_CTL_418_READ_MASK 0xFFFFFFFFU
  6111. #define LPDDR4__DENALI_CTL_418_WRITE_MASK 0xFFFFFFFFU
  6112. #define LPDDR4__DENALI_CTL_418__TDFI_RDLVL_RESP_MASK 0xFFFFFFFFU
  6113. #define LPDDR4__DENALI_CTL_418__TDFI_RDLVL_RESP_SHIFT 0U
  6114. #define LPDDR4__DENALI_CTL_418__TDFI_RDLVL_RESP_WIDTH 32U
  6115. #define LPDDR4__TDFI_RDLVL_RESP__REG DENALI_CTL_418
  6116. #define LPDDR4__TDFI_RDLVL_RESP__FLD LPDDR4__DENALI_CTL_418__TDFI_RDLVL_RESP
  6117. #define LPDDR4__DENALI_CTL_419_READ_MASK 0x000101FFU
  6118. #define LPDDR4__DENALI_CTL_419_WRITE_MASK 0x000101FFU
  6119. #define LPDDR4__DENALI_CTL_419__RDLVL_RESP_MASK_MASK 0x000000FFU
  6120. #define LPDDR4__DENALI_CTL_419__RDLVL_RESP_MASK_SHIFT 0U
  6121. #define LPDDR4__DENALI_CTL_419__RDLVL_RESP_MASK_WIDTH 8U
  6122. #define LPDDR4__RDLVL_RESP_MASK__REG DENALI_CTL_419
  6123. #define LPDDR4__RDLVL_RESP_MASK__FLD LPDDR4__DENALI_CTL_419__RDLVL_RESP_MASK
  6124. #define LPDDR4__DENALI_CTL_419__RDLVL_EN_MASK 0x00000100U
  6125. #define LPDDR4__DENALI_CTL_419__RDLVL_EN_SHIFT 8U
  6126. #define LPDDR4__DENALI_CTL_419__RDLVL_EN_WIDTH 1U
  6127. #define LPDDR4__DENALI_CTL_419__RDLVL_EN_WOCLR 0U
  6128. #define LPDDR4__DENALI_CTL_419__RDLVL_EN_WOSET 0U
  6129. #define LPDDR4__RDLVL_EN__REG DENALI_CTL_419
  6130. #define LPDDR4__RDLVL_EN__FLD LPDDR4__DENALI_CTL_419__RDLVL_EN
  6131. #define LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN_MASK 0x00010000U
  6132. #define LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN_SHIFT 16U
  6133. #define LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN_WIDTH 1U
  6134. #define LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN_WOCLR 0U
  6135. #define LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN_WOSET 0U
  6136. #define LPDDR4__RDLVL_GATE_EN__REG DENALI_CTL_419
  6137. #define LPDDR4__RDLVL_GATE_EN__FLD LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN
  6138. #define LPDDR4__DENALI_CTL_420_READ_MASK 0xFFFFFFFFU
  6139. #define LPDDR4__DENALI_CTL_420_WRITE_MASK 0xFFFFFFFFU
  6140. #define LPDDR4__DENALI_CTL_420__TDFI_RDLVL_MAX_MASK 0xFFFFFFFFU
  6141. #define LPDDR4__DENALI_CTL_420__TDFI_RDLVL_MAX_SHIFT 0U
  6142. #define LPDDR4__DENALI_CTL_420__TDFI_RDLVL_MAX_WIDTH 32U
  6143. #define LPDDR4__TDFI_RDLVL_MAX__REG DENALI_CTL_420
  6144. #define LPDDR4__TDFI_RDLVL_MAX__FLD LPDDR4__DENALI_CTL_420__TDFI_RDLVL_MAX
  6145. #define LPDDR4__DENALI_CTL_421_READ_MASK 0x00FF0707U
  6146. #define LPDDR4__DENALI_CTL_421_WRITE_MASK 0x00FF0707U
  6147. #define LPDDR4__DENALI_CTL_421__RDLVL_ERROR_STATUS_MASK 0x00000007U
  6148. #define LPDDR4__DENALI_CTL_421__RDLVL_ERROR_STATUS_SHIFT 0U
  6149. #define LPDDR4__DENALI_CTL_421__RDLVL_ERROR_STATUS_WIDTH 3U
  6150. #define LPDDR4__RDLVL_ERROR_STATUS__REG DENALI_CTL_421
  6151. #define LPDDR4__RDLVL_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_421__RDLVL_ERROR_STATUS
  6152. #define LPDDR4__DENALI_CTL_421__RDLVL_GATE_ERROR_STATUS_MASK 0x00000700U
  6153. #define LPDDR4__DENALI_CTL_421__RDLVL_GATE_ERROR_STATUS_SHIFT 8U
  6154. #define LPDDR4__DENALI_CTL_421__RDLVL_GATE_ERROR_STATUS_WIDTH 3U
  6155. #define LPDDR4__RDLVL_GATE_ERROR_STATUS__REG DENALI_CTL_421
  6156. #define LPDDR4__RDLVL_GATE_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_421__RDLVL_GATE_ERROR_STATUS
  6157. #define LPDDR4__DENALI_CTL_421__TDFI_CALVL_EN_MASK 0x00FF0000U
  6158. #define LPDDR4__DENALI_CTL_421__TDFI_CALVL_EN_SHIFT 16U
  6159. #define LPDDR4__DENALI_CTL_421__TDFI_CALVL_EN_WIDTH 8U
  6160. #define LPDDR4__TDFI_CALVL_EN__REG DENALI_CTL_421
  6161. #define LPDDR4__TDFI_CALVL_EN__FLD LPDDR4__DENALI_CTL_421__TDFI_CALVL_EN
  6162. #define LPDDR4__DENALI_CTL_422_READ_MASK 0x03FF03FFU
  6163. #define LPDDR4__DENALI_CTL_422_WRITE_MASK 0x03FF03FFU
  6164. #define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CC_F0_MASK 0x000003FFU
  6165. #define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CC_F0_SHIFT 0U
  6166. #define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CC_F0_WIDTH 10U
  6167. #define LPDDR4__TDFI_CALVL_CC_F0__REG DENALI_CTL_422
  6168. #define LPDDR4__TDFI_CALVL_CC_F0__FLD LPDDR4__DENALI_CTL_422__TDFI_CALVL_CC_F0
  6169. #define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CAPTURE_F0_MASK 0x03FF0000U
  6170. #define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CAPTURE_F0_SHIFT 16U
  6171. #define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CAPTURE_F0_WIDTH 10U
  6172. #define LPDDR4__TDFI_CALVL_CAPTURE_F0__REG DENALI_CTL_422
  6173. #define LPDDR4__TDFI_CALVL_CAPTURE_F0__FLD LPDDR4__DENALI_CTL_422__TDFI_CALVL_CAPTURE_F0
  6174. #define LPDDR4__DENALI_CTL_423_READ_MASK 0x03FF03FFU
  6175. #define LPDDR4__DENALI_CTL_423_WRITE_MASK 0x03FF03FFU
  6176. #define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CC_F1_MASK 0x000003FFU
  6177. #define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CC_F1_SHIFT 0U
  6178. #define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CC_F1_WIDTH 10U
  6179. #define LPDDR4__TDFI_CALVL_CC_F1__REG DENALI_CTL_423
  6180. #define LPDDR4__TDFI_CALVL_CC_F1__FLD LPDDR4__DENALI_CTL_423__TDFI_CALVL_CC_F1
  6181. #define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CAPTURE_F1_MASK 0x03FF0000U
  6182. #define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CAPTURE_F1_SHIFT 16U
  6183. #define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CAPTURE_F1_WIDTH 10U
  6184. #define LPDDR4__TDFI_CALVL_CAPTURE_F1__REG DENALI_CTL_423
  6185. #define LPDDR4__TDFI_CALVL_CAPTURE_F1__FLD LPDDR4__DENALI_CTL_423__TDFI_CALVL_CAPTURE_F1
  6186. #define LPDDR4__DENALI_CTL_424_READ_MASK 0x03FF03FFU
  6187. #define LPDDR4__DENALI_CTL_424_WRITE_MASK 0x03FF03FFU
  6188. #define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CC_F2_MASK 0x000003FFU
  6189. #define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CC_F2_SHIFT 0U
  6190. #define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CC_F2_WIDTH 10U
  6191. #define LPDDR4__TDFI_CALVL_CC_F2__REG DENALI_CTL_424
  6192. #define LPDDR4__TDFI_CALVL_CC_F2__FLD LPDDR4__DENALI_CTL_424__TDFI_CALVL_CC_F2
  6193. #define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CAPTURE_F2_MASK 0x03FF0000U
  6194. #define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CAPTURE_F2_SHIFT 16U
  6195. #define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CAPTURE_F2_WIDTH 10U
  6196. #define LPDDR4__TDFI_CALVL_CAPTURE_F2__REG DENALI_CTL_424
  6197. #define LPDDR4__TDFI_CALVL_CAPTURE_F2__FLD LPDDR4__DENALI_CTL_424__TDFI_CALVL_CAPTURE_F2
  6198. #define LPDDR4__DENALI_CTL_425_READ_MASK 0xFFFFFFFFU
  6199. #define LPDDR4__DENALI_CTL_425_WRITE_MASK 0xFFFFFFFFU
  6200. #define LPDDR4__DENALI_CTL_425__TDFI_CALVL_RESP_MASK 0xFFFFFFFFU
  6201. #define LPDDR4__DENALI_CTL_425__TDFI_CALVL_RESP_SHIFT 0U
  6202. #define LPDDR4__DENALI_CTL_425__TDFI_CALVL_RESP_WIDTH 32U
  6203. #define LPDDR4__TDFI_CALVL_RESP__REG DENALI_CTL_425
  6204. #define LPDDR4__TDFI_CALVL_RESP__FLD LPDDR4__DENALI_CTL_425__TDFI_CALVL_RESP
  6205. #define LPDDR4__DENALI_CTL_426_READ_MASK 0xFFFFFFFFU
  6206. #define LPDDR4__DENALI_CTL_426_WRITE_MASK 0xFFFFFFFFU
  6207. #define LPDDR4__DENALI_CTL_426__TDFI_CALVL_MAX_MASK 0xFFFFFFFFU
  6208. #define LPDDR4__DENALI_CTL_426__TDFI_CALVL_MAX_SHIFT 0U
  6209. #define LPDDR4__DENALI_CTL_426__TDFI_CALVL_MAX_WIDTH 32U
  6210. #define LPDDR4__TDFI_CALVL_MAX__REG DENALI_CTL_426
  6211. #define LPDDR4__TDFI_CALVL_MAX__FLD LPDDR4__DENALI_CTL_426__TDFI_CALVL_MAX
  6212. #define LPDDR4__DENALI_CTL_427_READ_MASK 0x070F0101U
  6213. #define LPDDR4__DENALI_CTL_427_WRITE_MASK 0x070F0101U
  6214. #define LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK_MASK 0x00000001U
  6215. #define LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK_SHIFT 0U
  6216. #define LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK_WIDTH 1U
  6217. #define LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK_WOCLR 0U
  6218. #define LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK_WOSET 0U
  6219. #define LPDDR4__CALVL_RESP_MASK__REG DENALI_CTL_427
  6220. #define LPDDR4__CALVL_RESP_MASK__FLD LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK
  6221. #define LPDDR4__DENALI_CTL_427__CALVL_EN_MASK 0x00000100U
  6222. #define LPDDR4__DENALI_CTL_427__CALVL_EN_SHIFT 8U
  6223. #define LPDDR4__DENALI_CTL_427__CALVL_EN_WIDTH 1U
  6224. #define LPDDR4__DENALI_CTL_427__CALVL_EN_WOCLR 0U
  6225. #define LPDDR4__DENALI_CTL_427__CALVL_EN_WOSET 0U
  6226. #define LPDDR4__CALVL_EN__REG DENALI_CTL_427
  6227. #define LPDDR4__CALVL_EN__FLD LPDDR4__DENALI_CTL_427__CALVL_EN
  6228. #define LPDDR4__DENALI_CTL_427__CALVL_ERROR_STATUS_MASK 0x000F0000U
  6229. #define LPDDR4__DENALI_CTL_427__CALVL_ERROR_STATUS_SHIFT 16U
  6230. #define LPDDR4__DENALI_CTL_427__CALVL_ERROR_STATUS_WIDTH 4U
  6231. #define LPDDR4__CALVL_ERROR_STATUS__REG DENALI_CTL_427
  6232. #define LPDDR4__CALVL_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_427__CALVL_ERROR_STATUS
  6233. #define LPDDR4__DENALI_CTL_427__TDFI_PHY_WRDATA_F0_MASK 0x07000000U
  6234. #define LPDDR4__DENALI_CTL_427__TDFI_PHY_WRDATA_F0_SHIFT 24U
  6235. #define LPDDR4__DENALI_CTL_427__TDFI_PHY_WRDATA_F0_WIDTH 3U
  6236. #define LPDDR4__TDFI_PHY_WRDATA_F0__REG DENALI_CTL_427
  6237. #define LPDDR4__TDFI_PHY_WRDATA_F0__FLD LPDDR4__DENALI_CTL_427__TDFI_PHY_WRDATA_F0
  6238. #define LPDDR4__DENALI_CTL_428_READ_MASK 0x7F7F0707U
  6239. #define LPDDR4__DENALI_CTL_428_WRITE_MASK 0x7F7F0707U
  6240. #define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F1_MASK 0x00000007U
  6241. #define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F1_SHIFT 0U
  6242. #define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F1_WIDTH 3U
  6243. #define LPDDR4__TDFI_PHY_WRDATA_F1__REG DENALI_CTL_428
  6244. #define LPDDR4__TDFI_PHY_WRDATA_F1__FLD LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F1
  6245. #define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F2_MASK 0x00000700U
  6246. #define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F2_SHIFT 8U
  6247. #define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F2_WIDTH 3U
  6248. #define LPDDR4__TDFI_PHY_WRDATA_F2__REG DENALI_CTL_428
  6249. #define LPDDR4__TDFI_PHY_WRDATA_F2__FLD LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F2
  6250. #define LPDDR4__DENALI_CTL_428__TDFI_RDCSLAT_F0_MASK 0x007F0000U
  6251. #define LPDDR4__DENALI_CTL_428__TDFI_RDCSLAT_F0_SHIFT 16U
  6252. #define LPDDR4__DENALI_CTL_428__TDFI_RDCSLAT_F0_WIDTH 7U
  6253. #define LPDDR4__TDFI_RDCSLAT_F0__REG DENALI_CTL_428
  6254. #define LPDDR4__TDFI_RDCSLAT_F0__FLD LPDDR4__DENALI_CTL_428__TDFI_RDCSLAT_F0
  6255. #define LPDDR4__DENALI_CTL_428__TDFI_WRCSLAT_F0_MASK 0x7F000000U
  6256. #define LPDDR4__DENALI_CTL_428__TDFI_WRCSLAT_F0_SHIFT 24U
  6257. #define LPDDR4__DENALI_CTL_428__TDFI_WRCSLAT_F0_WIDTH 7U
  6258. #define LPDDR4__TDFI_WRCSLAT_F0__REG DENALI_CTL_428
  6259. #define LPDDR4__TDFI_WRCSLAT_F0__FLD LPDDR4__DENALI_CTL_428__TDFI_WRCSLAT_F0
  6260. #define LPDDR4__DENALI_CTL_429_READ_MASK 0x7F7F7F7FU
  6261. #define LPDDR4__DENALI_CTL_429_WRITE_MASK 0x7F7F7F7FU
  6262. #define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F1_MASK 0x0000007FU
  6263. #define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F1_SHIFT 0U
  6264. #define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F1_WIDTH 7U
  6265. #define LPDDR4__TDFI_RDCSLAT_F1__REG DENALI_CTL_429
  6266. #define LPDDR4__TDFI_RDCSLAT_F1__FLD LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F1
  6267. #define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F1_MASK 0x00007F00U
  6268. #define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F1_SHIFT 8U
  6269. #define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F1_WIDTH 7U
  6270. #define LPDDR4__TDFI_WRCSLAT_F1__REG DENALI_CTL_429
  6271. #define LPDDR4__TDFI_WRCSLAT_F1__FLD LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F1
  6272. #define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F2_MASK 0x007F0000U
  6273. #define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F2_SHIFT 16U
  6274. #define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F2_WIDTH 7U
  6275. #define LPDDR4__TDFI_RDCSLAT_F2__REG DENALI_CTL_429
  6276. #define LPDDR4__TDFI_RDCSLAT_F2__FLD LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F2
  6277. #define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F2_MASK 0x7F000000U
  6278. #define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F2_SHIFT 24U
  6279. #define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F2_WIDTH 7U
  6280. #define LPDDR4__TDFI_WRCSLAT_F2__REG DENALI_CTL_429
  6281. #define LPDDR4__TDFI_WRCSLAT_F2__FLD LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F2
  6282. #define LPDDR4__DENALI_CTL_430_READ_MASK 0x010101FFU
  6283. #define LPDDR4__DENALI_CTL_430_WRITE_MASK 0x010101FFU
  6284. #define LPDDR4__DENALI_CTL_430__TDFI_WRDATA_DELAY_MASK 0x000000FFU
  6285. #define LPDDR4__DENALI_CTL_430__TDFI_WRDATA_DELAY_SHIFT 0U
  6286. #define LPDDR4__DENALI_CTL_430__TDFI_WRDATA_DELAY_WIDTH 8U
  6287. #define LPDDR4__TDFI_WRDATA_DELAY__REG DENALI_CTL_430
  6288. #define LPDDR4__TDFI_WRDATA_DELAY__FLD LPDDR4__DENALI_CTL_430__TDFI_WRDATA_DELAY
  6289. #define LPDDR4__DENALI_CTL_430__EN_1T_TIMING_MASK 0x00000100U
  6290. #define LPDDR4__DENALI_CTL_430__EN_1T_TIMING_SHIFT 8U
  6291. #define LPDDR4__DENALI_CTL_430__EN_1T_TIMING_WIDTH 1U
  6292. #define LPDDR4__DENALI_CTL_430__EN_1T_TIMING_WOCLR 0U
  6293. #define LPDDR4__DENALI_CTL_430__EN_1T_TIMING_WOSET 0U
  6294. #define LPDDR4__EN_1T_TIMING__REG DENALI_CTL_430
  6295. #define LPDDR4__EN_1T_TIMING__FLD LPDDR4__DENALI_CTL_430__EN_1T_TIMING
  6296. #define LPDDR4__DENALI_CTL_430__DISABLE_MEMORY_MASKED_WRITE_MASK 0x00010000U
  6297. #define LPDDR4__DENALI_CTL_430__DISABLE_MEMORY_MASKED_WRITE_SHIFT 16U
  6298. #define LPDDR4__DENALI_CTL_430__DISABLE_MEMORY_MASKED_WRITE_WIDTH 1U
  6299. #define LPDDR4__DENALI_CTL_430__DISABLE_MEMORY_MASKED_WRITE_WOCLR 0U
  6300. #define LPDDR4__DENALI_CTL_430__DISABLE_MEMORY_MASKED_WRITE_WOSET 0U
  6301. #define LPDDR4__DISABLE_MEMORY_MASKED_WRITE__REG DENALI_CTL_430
  6302. #define LPDDR4__DISABLE_MEMORY_MASKED_WRITE__FLD LPDDR4__DENALI_CTL_430__DISABLE_MEMORY_MASKED_WRITE
  6303. #define LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE_MASK 0x01000000U
  6304. #define LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE_SHIFT 24U
  6305. #define LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE_WIDTH 1U
  6306. #define LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE_WOCLR 0U
  6307. #define LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE_WOSET 0U
  6308. #define LPDDR4__BL_ON_FLY_ENABLE__REG DENALI_CTL_430
  6309. #define LPDDR4__BL_ON_FLY_ENABLE__FLD LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE
  6310. #define LPDDR4__DENALI_CTL_431_READ_MASK 0x07070701U
  6311. #define LPDDR4__DENALI_CTL_431_WRITE_MASK 0x07070701U
  6312. #define LPDDR4__DENALI_CTL_431__MC_RESERVED32_MASK 0x00000001U
  6313. #define LPDDR4__DENALI_CTL_431__MC_RESERVED32_SHIFT 0U
  6314. #define LPDDR4__DENALI_CTL_431__MC_RESERVED32_WIDTH 1U
  6315. #define LPDDR4__DENALI_CTL_431__MC_RESERVED32_WOCLR 0U
  6316. #define LPDDR4__DENALI_CTL_431__MC_RESERVED32_WOSET 0U
  6317. #define LPDDR4__MC_RESERVED32__REG DENALI_CTL_431
  6318. #define LPDDR4__MC_RESERVED32__FLD LPDDR4__DENALI_CTL_431__MC_RESERVED32
  6319. #define LPDDR4__DENALI_CTL_431__MC_RESERVED33_MASK 0x00000700U
  6320. #define LPDDR4__DENALI_CTL_431__MC_RESERVED33_SHIFT 8U
  6321. #define LPDDR4__DENALI_CTL_431__MC_RESERVED33_WIDTH 3U
  6322. #define LPDDR4__MC_RESERVED33__REG DENALI_CTL_431
  6323. #define LPDDR4__MC_RESERVED33__FLD LPDDR4__DENALI_CTL_431__MC_RESERVED33
  6324. #define LPDDR4__DENALI_CTL_431__MC_RESERVED34_MASK 0x00070000U
  6325. #define LPDDR4__DENALI_CTL_431__MC_RESERVED34_SHIFT 16U
  6326. #define LPDDR4__DENALI_CTL_431__MC_RESERVED34_WIDTH 3U
  6327. #define LPDDR4__MC_RESERVED34__REG DENALI_CTL_431
  6328. #define LPDDR4__MC_RESERVED34__FLD LPDDR4__DENALI_CTL_431__MC_RESERVED34
  6329. #define LPDDR4__DENALI_CTL_431__MC_RESERVED35_MASK 0x07000000U
  6330. #define LPDDR4__DENALI_CTL_431__MC_RESERVED35_SHIFT 24U
  6331. #define LPDDR4__DENALI_CTL_431__MC_RESERVED35_WIDTH 3U
  6332. #define LPDDR4__MC_RESERVED35__REG DENALI_CTL_431
  6333. #define LPDDR4__MC_RESERVED35__FLD LPDDR4__DENALI_CTL_431__MC_RESERVED35
  6334. #define LPDDR4__DENALI_CTL_432_READ_MASK 0x0F070707U
  6335. #define LPDDR4__DENALI_CTL_432_WRITE_MASK 0x0F070707U
  6336. #define LPDDR4__DENALI_CTL_432__MC_RESERVED36_MASK 0x00000007U
  6337. #define LPDDR4__DENALI_CTL_432__MC_RESERVED36_SHIFT 0U
  6338. #define LPDDR4__DENALI_CTL_432__MC_RESERVED36_WIDTH 3U
  6339. #define LPDDR4__MC_RESERVED36__REG DENALI_CTL_432
  6340. #define LPDDR4__MC_RESERVED36__FLD LPDDR4__DENALI_CTL_432__MC_RESERVED36
  6341. #define LPDDR4__DENALI_CTL_432__MC_RESERVED37_MASK 0x00000700U
  6342. #define LPDDR4__DENALI_CTL_432__MC_RESERVED37_SHIFT 8U
  6343. #define LPDDR4__DENALI_CTL_432__MC_RESERVED37_WIDTH 3U
  6344. #define LPDDR4__MC_RESERVED37__REG DENALI_CTL_432
  6345. #define LPDDR4__MC_RESERVED37__FLD LPDDR4__DENALI_CTL_432__MC_RESERVED37
  6346. #define LPDDR4__DENALI_CTL_432__MC_RESERVED38_MASK 0x00070000U
  6347. #define LPDDR4__DENALI_CTL_432__MC_RESERVED38_SHIFT 16U
  6348. #define LPDDR4__DENALI_CTL_432__MC_RESERVED38_WIDTH 3U
  6349. #define LPDDR4__MC_RESERVED38__REG DENALI_CTL_432
  6350. #define LPDDR4__MC_RESERVED38__FLD LPDDR4__DENALI_CTL_432__MC_RESERVED38
  6351. #define LPDDR4__DENALI_CTL_432__MC_RESERVED39_MASK 0x0F000000U
  6352. #define LPDDR4__DENALI_CTL_432__MC_RESERVED39_SHIFT 24U
  6353. #define LPDDR4__DENALI_CTL_432__MC_RESERVED39_WIDTH 4U
  6354. #define LPDDR4__MC_RESERVED39__REG DENALI_CTL_432
  6355. #define LPDDR4__MC_RESERVED39__FLD LPDDR4__DENALI_CTL_432__MC_RESERVED39
  6356. #define LPDDR4__DENALI_CTL_433_READ_MASK 0x0F0F0F0FU
  6357. #define LPDDR4__DENALI_CTL_433_WRITE_MASK 0x0F0F0F0FU
  6358. #define LPDDR4__DENALI_CTL_433__MC_RESERVED40_MASK 0x0000000FU
  6359. #define LPDDR4__DENALI_CTL_433__MC_RESERVED40_SHIFT 0U
  6360. #define LPDDR4__DENALI_CTL_433__MC_RESERVED40_WIDTH 4U
  6361. #define LPDDR4__MC_RESERVED40__REG DENALI_CTL_433
  6362. #define LPDDR4__MC_RESERVED40__FLD LPDDR4__DENALI_CTL_433__MC_RESERVED40
  6363. #define LPDDR4__DENALI_CTL_433__MC_RESERVED41_MASK 0x00000F00U
  6364. #define LPDDR4__DENALI_CTL_433__MC_RESERVED41_SHIFT 8U
  6365. #define LPDDR4__DENALI_CTL_433__MC_RESERVED41_WIDTH 4U
  6366. #define LPDDR4__MC_RESERVED41__REG DENALI_CTL_433
  6367. #define LPDDR4__MC_RESERVED41__FLD LPDDR4__DENALI_CTL_433__MC_RESERVED41
  6368. #define LPDDR4__DENALI_CTL_433__MC_RESERVED42_MASK 0x000F0000U
  6369. #define LPDDR4__DENALI_CTL_433__MC_RESERVED42_SHIFT 16U
  6370. #define LPDDR4__DENALI_CTL_433__MC_RESERVED42_WIDTH 4U
  6371. #define LPDDR4__MC_RESERVED42__REG DENALI_CTL_433
  6372. #define LPDDR4__MC_RESERVED42__FLD LPDDR4__DENALI_CTL_433__MC_RESERVED42
  6373. #define LPDDR4__DENALI_CTL_433__MC_RESERVED43_MASK 0x0F000000U
  6374. #define LPDDR4__DENALI_CTL_433__MC_RESERVED43_SHIFT 24U
  6375. #define LPDDR4__DENALI_CTL_433__MC_RESERVED43_WIDTH 4U
  6376. #define LPDDR4__MC_RESERVED43__REG DENALI_CTL_433
  6377. #define LPDDR4__MC_RESERVED43__FLD LPDDR4__DENALI_CTL_433__MC_RESERVED43
  6378. #define LPDDR4__DENALI_CTL_434_READ_MASK 0x0F0F0F0FU
  6379. #define LPDDR4__DENALI_CTL_434_WRITE_MASK 0x0F0F0F0FU
  6380. #define LPDDR4__DENALI_CTL_434__MC_RESERVED44_MASK 0x0000000FU
  6381. #define LPDDR4__DENALI_CTL_434__MC_RESERVED44_SHIFT 0U
  6382. #define LPDDR4__DENALI_CTL_434__MC_RESERVED44_WIDTH 4U
  6383. #define LPDDR4__MC_RESERVED44__REG DENALI_CTL_434
  6384. #define LPDDR4__MC_RESERVED44__FLD LPDDR4__DENALI_CTL_434__MC_RESERVED44
  6385. #define LPDDR4__DENALI_CTL_434__MC_RESERVED45_MASK 0x00000F00U
  6386. #define LPDDR4__DENALI_CTL_434__MC_RESERVED45_SHIFT 8U
  6387. #define LPDDR4__DENALI_CTL_434__MC_RESERVED45_WIDTH 4U
  6388. #define LPDDR4__MC_RESERVED45__REG DENALI_CTL_434
  6389. #define LPDDR4__MC_RESERVED45__FLD LPDDR4__DENALI_CTL_434__MC_RESERVED45
  6390. #define LPDDR4__DENALI_CTL_434__MC_RESERVED46_MASK 0x000F0000U
  6391. #define LPDDR4__DENALI_CTL_434__MC_RESERVED46_SHIFT 16U
  6392. #define LPDDR4__DENALI_CTL_434__MC_RESERVED46_WIDTH 4U
  6393. #define LPDDR4__MC_RESERVED46__REG DENALI_CTL_434
  6394. #define LPDDR4__MC_RESERVED46__FLD LPDDR4__DENALI_CTL_434__MC_RESERVED46
  6395. #define LPDDR4__DENALI_CTL_434__MC_RESERVED47_MASK 0x0F000000U
  6396. #define LPDDR4__DENALI_CTL_434__MC_RESERVED47_SHIFT 24U
  6397. #define LPDDR4__DENALI_CTL_434__MC_RESERVED47_WIDTH 4U
  6398. #define LPDDR4__MC_RESERVED47__REG DENALI_CTL_434
  6399. #define LPDDR4__MC_RESERVED47__FLD LPDDR4__DENALI_CTL_434__MC_RESERVED47
  6400. #define LPDDR4__DENALI_CTL_435_READ_MASK 0x0F0F0F0FU
  6401. #define LPDDR4__DENALI_CTL_435_WRITE_MASK 0x0F0F0F0FU
  6402. #define LPDDR4__DENALI_CTL_435__MC_RESERVED48_MASK 0x0000000FU
  6403. #define LPDDR4__DENALI_CTL_435__MC_RESERVED48_SHIFT 0U
  6404. #define LPDDR4__DENALI_CTL_435__MC_RESERVED48_WIDTH 4U
  6405. #define LPDDR4__MC_RESERVED48__REG DENALI_CTL_435
  6406. #define LPDDR4__MC_RESERVED48__FLD LPDDR4__DENALI_CTL_435__MC_RESERVED48
  6407. #define LPDDR4__DENALI_CTL_435__MC_RESERVED49_MASK 0x00000F00U
  6408. #define LPDDR4__DENALI_CTL_435__MC_RESERVED49_SHIFT 8U
  6409. #define LPDDR4__DENALI_CTL_435__MC_RESERVED49_WIDTH 4U
  6410. #define LPDDR4__MC_RESERVED49__REG DENALI_CTL_435
  6411. #define LPDDR4__MC_RESERVED49__FLD LPDDR4__DENALI_CTL_435__MC_RESERVED49
  6412. #define LPDDR4__DENALI_CTL_435__MC_RESERVED50_MASK 0x000F0000U
  6413. #define LPDDR4__DENALI_CTL_435__MC_RESERVED50_SHIFT 16U
  6414. #define LPDDR4__DENALI_CTL_435__MC_RESERVED50_WIDTH 4U
  6415. #define LPDDR4__MC_RESERVED50__REG DENALI_CTL_435
  6416. #define LPDDR4__MC_RESERVED50__FLD LPDDR4__DENALI_CTL_435__MC_RESERVED50
  6417. #define LPDDR4__DENALI_CTL_435__MC_RESERVED51_MASK 0x0F000000U
  6418. #define LPDDR4__DENALI_CTL_435__MC_RESERVED51_SHIFT 24U
  6419. #define LPDDR4__DENALI_CTL_435__MC_RESERVED51_WIDTH 4U
  6420. #define LPDDR4__MC_RESERVED51__REG DENALI_CTL_435
  6421. #define LPDDR4__MC_RESERVED51__FLD LPDDR4__DENALI_CTL_435__MC_RESERVED51
  6422. #define LPDDR4__DENALI_CTL_436_READ_MASK 0x0F0F0F0FU
  6423. #define LPDDR4__DENALI_CTL_436_WRITE_MASK 0x0F0F0F0FU
  6424. #define LPDDR4__DENALI_CTL_436__MC_RESERVED52_MASK 0x0000000FU
  6425. #define LPDDR4__DENALI_CTL_436__MC_RESERVED52_SHIFT 0U
  6426. #define LPDDR4__DENALI_CTL_436__MC_RESERVED52_WIDTH 4U
  6427. #define LPDDR4__MC_RESERVED52__REG DENALI_CTL_436
  6428. #define LPDDR4__MC_RESERVED52__FLD LPDDR4__DENALI_CTL_436__MC_RESERVED52
  6429. #define LPDDR4__DENALI_CTL_436__MC_RESERVED53_MASK 0x00000F00U
  6430. #define LPDDR4__DENALI_CTL_436__MC_RESERVED53_SHIFT 8U
  6431. #define LPDDR4__DENALI_CTL_436__MC_RESERVED53_WIDTH 4U
  6432. #define LPDDR4__MC_RESERVED53__REG DENALI_CTL_436
  6433. #define LPDDR4__MC_RESERVED53__FLD LPDDR4__DENALI_CTL_436__MC_RESERVED53
  6434. #define LPDDR4__DENALI_CTL_436__MC_RESERVED54_MASK 0x000F0000U
  6435. #define LPDDR4__DENALI_CTL_436__MC_RESERVED54_SHIFT 16U
  6436. #define LPDDR4__DENALI_CTL_436__MC_RESERVED54_WIDTH 4U
  6437. #define LPDDR4__MC_RESERVED54__REG DENALI_CTL_436
  6438. #define LPDDR4__MC_RESERVED54__FLD LPDDR4__DENALI_CTL_436__MC_RESERVED54
  6439. #define LPDDR4__DENALI_CTL_436__MC_RESERVED55_MASK 0x0F000000U
  6440. #define LPDDR4__DENALI_CTL_436__MC_RESERVED55_SHIFT 24U
  6441. #define LPDDR4__DENALI_CTL_436__MC_RESERVED55_WIDTH 4U
  6442. #define LPDDR4__MC_RESERVED55__REG DENALI_CTL_436
  6443. #define LPDDR4__MC_RESERVED55__FLD LPDDR4__DENALI_CTL_436__MC_RESERVED55
  6444. #define LPDDR4__DENALI_CTL_437_READ_MASK 0xFF0F0F0FU
  6445. #define LPDDR4__DENALI_CTL_437_WRITE_MASK 0xFF0F0F0FU
  6446. #define LPDDR4__DENALI_CTL_437__MC_RESERVED56_MASK 0x0000000FU
  6447. #define LPDDR4__DENALI_CTL_437__MC_RESERVED56_SHIFT 0U
  6448. #define LPDDR4__DENALI_CTL_437__MC_RESERVED56_WIDTH 4U
  6449. #define LPDDR4__MC_RESERVED56__REG DENALI_CTL_437
  6450. #define LPDDR4__MC_RESERVED56__FLD LPDDR4__DENALI_CTL_437__MC_RESERVED56
  6451. #define LPDDR4__DENALI_CTL_437__MC_RESERVED57_MASK 0x00000F00U
  6452. #define LPDDR4__DENALI_CTL_437__MC_RESERVED57_SHIFT 8U
  6453. #define LPDDR4__DENALI_CTL_437__MC_RESERVED57_WIDTH 4U
  6454. #define LPDDR4__MC_RESERVED57__REG DENALI_CTL_437
  6455. #define LPDDR4__MC_RESERVED57__FLD LPDDR4__DENALI_CTL_437__MC_RESERVED57
  6456. #define LPDDR4__DENALI_CTL_437__MC_RESERVED58_MASK 0x000F0000U
  6457. #define LPDDR4__DENALI_CTL_437__MC_RESERVED58_SHIFT 16U
  6458. #define LPDDR4__DENALI_CTL_437__MC_RESERVED58_WIDTH 4U
  6459. #define LPDDR4__MC_RESERVED58__REG DENALI_CTL_437
  6460. #define LPDDR4__MC_RESERVED58__FLD LPDDR4__DENALI_CTL_437__MC_RESERVED58
  6461. #define LPDDR4__DENALI_CTL_437__GLOBAL_ERROR_INFO_MASK 0xFF000000U
  6462. #define LPDDR4__DENALI_CTL_437__GLOBAL_ERROR_INFO_SHIFT 24U
  6463. #define LPDDR4__DENALI_CTL_437__GLOBAL_ERROR_INFO_WIDTH 8U
  6464. #define LPDDR4__GLOBAL_ERROR_INFO__REG DENALI_CTL_437
  6465. #define LPDDR4__GLOBAL_ERROR_INFO__FLD LPDDR4__DENALI_CTL_437__GLOBAL_ERROR_INFO
  6466. #define LPDDR4__DENALI_CTL_438_READ_MASK 0xFFFF03FFU
  6467. #define LPDDR4__DENALI_CTL_438_WRITE_MASK 0xFFFF03FFU
  6468. #define LPDDR4__DENALI_CTL_438__GLOBAL_ERROR_MASK_MASK 0x000000FFU
  6469. #define LPDDR4__DENALI_CTL_438__GLOBAL_ERROR_MASK_SHIFT 0U
  6470. #define LPDDR4__DENALI_CTL_438__GLOBAL_ERROR_MASK_WIDTH 8U
  6471. #define LPDDR4__GLOBAL_ERROR_MASK__REG DENALI_CTL_438
  6472. #define LPDDR4__GLOBAL_ERROR_MASK__FLD LPDDR4__DENALI_CTL_438__GLOBAL_ERROR_MASK
  6473. #define LPDDR4__DENALI_CTL_438__AXI_PARITY_ERROR_STATUS_MASK 0x00000300U
  6474. #define LPDDR4__DENALI_CTL_438__AXI_PARITY_ERROR_STATUS_SHIFT 8U
  6475. #define LPDDR4__DENALI_CTL_438__AXI_PARITY_ERROR_STATUS_WIDTH 2U
  6476. #define LPDDR4__AXI_PARITY_ERROR_STATUS__REG DENALI_CTL_438
  6477. #define LPDDR4__AXI_PARITY_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_438__AXI_PARITY_ERROR_STATUS
  6478. #define LPDDR4__DENALI_CTL_438__NWR_F0_MASK 0x00FF0000U
  6479. #define LPDDR4__DENALI_CTL_438__NWR_F0_SHIFT 16U
  6480. #define LPDDR4__DENALI_CTL_438__NWR_F0_WIDTH 8U
  6481. #define LPDDR4__NWR_F0__REG DENALI_CTL_438
  6482. #define LPDDR4__NWR_F0__FLD LPDDR4__DENALI_CTL_438__NWR_F0
  6483. #define LPDDR4__DENALI_CTL_438__NWR_F1_MASK 0xFF000000U
  6484. #define LPDDR4__DENALI_CTL_438__NWR_F1_SHIFT 24U
  6485. #define LPDDR4__DENALI_CTL_438__NWR_F1_WIDTH 8U
  6486. #define LPDDR4__NWR_F1__REG DENALI_CTL_438
  6487. #define LPDDR4__NWR_F1__FLD LPDDR4__DENALI_CTL_438__NWR_F1
  6488. #define LPDDR4__DENALI_CTL_439_READ_MASK 0x001F01FFU
  6489. #define LPDDR4__DENALI_CTL_439_WRITE_MASK 0x001F01FFU
  6490. #define LPDDR4__DENALI_CTL_439__NWR_F2_MASK 0x000000FFU
  6491. #define LPDDR4__DENALI_CTL_439__NWR_F2_SHIFT 0U
  6492. #define LPDDR4__DENALI_CTL_439__NWR_F2_WIDTH 8U
  6493. #define LPDDR4__NWR_F2__REG DENALI_CTL_439
  6494. #define LPDDR4__NWR_F2__FLD LPDDR4__DENALI_CTL_439__NWR_F2
  6495. #define LPDDR4__DENALI_CTL_439__MC_RESERVED59_MASK 0x00000100U
  6496. #define LPDDR4__DENALI_CTL_439__MC_RESERVED59_SHIFT 8U
  6497. #define LPDDR4__DENALI_CTL_439__MC_RESERVED59_WIDTH 1U
  6498. #define LPDDR4__DENALI_CTL_439__MC_RESERVED59_WOCLR 0U
  6499. #define LPDDR4__DENALI_CTL_439__MC_RESERVED59_WOSET 0U
  6500. #define LPDDR4__MC_RESERVED59__REG DENALI_CTL_439
  6501. #define LPDDR4__MC_RESERVED59__FLD LPDDR4__DENALI_CTL_439__MC_RESERVED59
  6502. #define LPDDR4__DENALI_CTL_439__REGPORT_PARAM_PARITY_PROTECTION_STATUS_MASK 0x001F0000U
  6503. #define LPDDR4__DENALI_CTL_439__REGPORT_PARAM_PARITY_PROTECTION_STATUS_SHIFT 16U
  6504. #define LPDDR4__DENALI_CTL_439__REGPORT_PARAM_PARITY_PROTECTION_STATUS_WIDTH 5U
  6505. #define LPDDR4__REGPORT_PARAM_PARITY_PROTECTION_STATUS__REG DENALI_CTL_439
  6506. #define LPDDR4__REGPORT_PARAM_PARITY_PROTECTION_STATUS__FLD LPDDR4__DENALI_CTL_439__REGPORT_PARAM_PARITY_PROTECTION_STATUS
  6507. #define LPDDR4__DENALI_CTL_440_READ_MASK 0xFFFFFFFFU
  6508. #define LPDDR4__DENALI_CTL_440_WRITE_MASK 0xFFFFFFFFU
  6509. #define LPDDR4__DENALI_CTL_440__MC_PARITY_INJECTION_BYTE_ENABLE_0_MASK 0xFFFFFFFFU
  6510. #define LPDDR4__DENALI_CTL_440__MC_PARITY_INJECTION_BYTE_ENABLE_0_SHIFT 0U
  6511. #define LPDDR4__DENALI_CTL_440__MC_PARITY_INJECTION_BYTE_ENABLE_0_WIDTH 32U
  6512. #define LPDDR4__MC_PARITY_INJECTION_BYTE_ENABLE_0__REG DENALI_CTL_440
  6513. #define LPDDR4__MC_PARITY_INJECTION_BYTE_ENABLE_0__FLD LPDDR4__DENALI_CTL_440__MC_PARITY_INJECTION_BYTE_ENABLE_0
  6514. #define LPDDR4__DENALI_CTL_441_READ_MASK 0xFFFFFFFFU
  6515. #define LPDDR4__DENALI_CTL_441_WRITE_MASK 0xFFFFFFFFU
  6516. #define LPDDR4__DENALI_CTL_441__MC_PARITY_INJECTION_BYTE_ENABLE_1_MASK 0xFFFFFFFFU
  6517. #define LPDDR4__DENALI_CTL_441__MC_PARITY_INJECTION_BYTE_ENABLE_1_SHIFT 0U
  6518. #define LPDDR4__DENALI_CTL_441__MC_PARITY_INJECTION_BYTE_ENABLE_1_WIDTH 32U
  6519. #define LPDDR4__MC_PARITY_INJECTION_BYTE_ENABLE_1__REG DENALI_CTL_441
  6520. #define LPDDR4__MC_PARITY_INJECTION_BYTE_ENABLE_1__FLD LPDDR4__DENALI_CTL_441__MC_PARITY_INJECTION_BYTE_ENABLE_1
  6521. #define LPDDR4__DENALI_CTL_442_READ_MASK 0x01010101U
  6522. #define LPDDR4__DENALI_CTL_442_WRITE_MASK 0x01010101U
  6523. #define LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE_MASK 0x00000001U
  6524. #define LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE_SHIFT 0U
  6525. #define LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE_WIDTH 1U
  6526. #define LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE_WOCLR 0U
  6527. #define LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE_WOSET 0U
  6528. #define LPDDR4__MC_PARITY_ERROR_TYPE__REG DENALI_CTL_442
  6529. #define LPDDR4__MC_PARITY_ERROR_TYPE__FLD LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE
  6530. #define LPDDR4__DENALI_CTL_442__REGPORT_ADDR_PARITY_PROTECTION_EN_MASK 0x00000100U
  6531. #define LPDDR4__DENALI_CTL_442__REGPORT_ADDR_PARITY_PROTECTION_EN_SHIFT 8U
  6532. #define LPDDR4__DENALI_CTL_442__REGPORT_ADDR_PARITY_PROTECTION_EN_WIDTH 1U
  6533. #define LPDDR4__DENALI_CTL_442__REGPORT_ADDR_PARITY_PROTECTION_EN_WOCLR 0U
  6534. #define LPDDR4__DENALI_CTL_442__REGPORT_ADDR_PARITY_PROTECTION_EN_WOSET 0U
  6535. #define LPDDR4__REGPORT_ADDR_PARITY_PROTECTION_EN__REG DENALI_CTL_442
  6536. #define LPDDR4__REGPORT_ADDR_PARITY_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_442__REGPORT_ADDR_PARITY_PROTECTION_EN
  6537. #define LPDDR4__DENALI_CTL_442__REGPORT_WRITEMASK_PARITY_PROTECTION_EN_MASK 0x00010000U
  6538. #define LPDDR4__DENALI_CTL_442__REGPORT_WRITEMASK_PARITY_PROTECTION_EN_SHIFT 16U
  6539. #define LPDDR4__DENALI_CTL_442__REGPORT_WRITEMASK_PARITY_PROTECTION_EN_WIDTH 1U
  6540. #define LPDDR4__DENALI_CTL_442__REGPORT_WRITEMASK_PARITY_PROTECTION_EN_WOCLR 0U
  6541. #define LPDDR4__DENALI_CTL_442__REGPORT_WRITEMASK_PARITY_PROTECTION_EN_WOSET 0U
  6542. #define LPDDR4__REGPORT_WRITEMASK_PARITY_PROTECTION_EN__REG DENALI_CTL_442
  6543. #define LPDDR4__REGPORT_WRITEMASK_PARITY_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_442__REGPORT_WRITEMASK_PARITY_PROTECTION_EN
  6544. #define LPDDR4__DENALI_CTL_442__REGPORT_WRITE_PARITY_PROTECTION_EN_MASK 0x01000000U
  6545. #define LPDDR4__DENALI_CTL_442__REGPORT_WRITE_PARITY_PROTECTION_EN_SHIFT 24U
  6546. #define LPDDR4__DENALI_CTL_442__REGPORT_WRITE_PARITY_PROTECTION_EN_WIDTH 1U
  6547. #define LPDDR4__DENALI_CTL_442__REGPORT_WRITE_PARITY_PROTECTION_EN_WOCLR 0U
  6548. #define LPDDR4__DENALI_CTL_442__REGPORT_WRITE_PARITY_PROTECTION_EN_WOSET 0U
  6549. #define LPDDR4__REGPORT_WRITE_PARITY_PROTECTION_EN__REG DENALI_CTL_442
  6550. #define LPDDR4__REGPORT_WRITE_PARITY_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_442__REGPORT_WRITE_PARITY_PROTECTION_EN
  6551. #define LPDDR4__DENALI_CTL_443_READ_MASK 0x01010101U
  6552. #define LPDDR4__DENALI_CTL_443_WRITE_MASK 0x01010101U
  6553. #define LPDDR4__DENALI_CTL_443__REGPORT_READ_PARITY_PROTECTION_EN_MASK 0x00000001U
  6554. #define LPDDR4__DENALI_CTL_443__REGPORT_READ_PARITY_PROTECTION_EN_SHIFT 0U
  6555. #define LPDDR4__DENALI_CTL_443__REGPORT_READ_PARITY_PROTECTION_EN_WIDTH 1U
  6556. #define LPDDR4__DENALI_CTL_443__REGPORT_READ_PARITY_PROTECTION_EN_WOCLR 0U
  6557. #define LPDDR4__DENALI_CTL_443__REGPORT_READ_PARITY_PROTECTION_EN_WOSET 0U
  6558. #define LPDDR4__REGPORT_READ_PARITY_PROTECTION_EN__REG DENALI_CTL_443
  6559. #define LPDDR4__REGPORT_READ_PARITY_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_443__REGPORT_READ_PARITY_PROTECTION_EN
  6560. #define LPDDR4__DENALI_CTL_443__PARAMREG_PARITY_PROTECTION_EN_MASK 0x00000100U
  6561. #define LPDDR4__DENALI_CTL_443__PARAMREG_PARITY_PROTECTION_EN_SHIFT 8U
  6562. #define LPDDR4__DENALI_CTL_443__PARAMREG_PARITY_PROTECTION_EN_WIDTH 1U
  6563. #define LPDDR4__DENALI_CTL_443__PARAMREG_PARITY_PROTECTION_EN_WOCLR 0U
  6564. #define LPDDR4__DENALI_CTL_443__PARAMREG_PARITY_PROTECTION_EN_WOSET 0U
  6565. #define LPDDR4__PARAMREG_PARITY_PROTECTION_EN__REG DENALI_CTL_443
  6566. #define LPDDR4__PARAMREG_PARITY_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_443__PARAMREG_PARITY_PROTECTION_EN
  6567. #define LPDDR4__DENALI_CTL_443__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN_MASK 0x00010000U
  6568. #define LPDDR4__DENALI_CTL_443__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN_SHIFT 16U
  6569. #define LPDDR4__DENALI_CTL_443__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN_WIDTH 1U
  6570. #define LPDDR4__DENALI_CTL_443__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN_WOCLR 0U
  6571. #define LPDDR4__DENALI_CTL_443__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN_WOSET 0U
  6572. #define LPDDR4__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN__REG DENALI_CTL_443
  6573. #define LPDDR4__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN__FLD LPDDR4__DENALI_CTL_443__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN
  6574. #define LPDDR4__DENALI_CTL_443__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN_MASK 0x01000000U
  6575. #define LPDDR4__DENALI_CTL_443__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN_SHIFT 24U
  6576. #define LPDDR4__DENALI_CTL_443__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN_WIDTH 1U
  6577. #define LPDDR4__DENALI_CTL_443__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN_WOCLR 0U
  6578. #define LPDDR4__DENALI_CTL_443__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN_WOSET 0U
  6579. #define LPDDR4__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN__REG DENALI_CTL_443
  6580. #define LPDDR4__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN__FLD LPDDR4__DENALI_CTL_443__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN
  6581. #define LPDDR4__DENALI_CTL_444_READ_MASK 0x00010101U
  6582. #define LPDDR4__DENALI_CTL_444_WRITE_MASK 0x00010101U
  6583. #define LPDDR4__DENALI_CTL_444__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN_MASK 0x00000001U
  6584. #define LPDDR4__DENALI_CTL_444__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN_SHIFT 0U
  6585. #define LPDDR4__DENALI_CTL_444__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN_WIDTH 1U
  6586. #define LPDDR4__DENALI_CTL_444__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN_WOCLR 0U
  6587. #define LPDDR4__DENALI_CTL_444__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN_WOSET 0U
  6588. #define LPDDR4__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN__REG DENALI_CTL_444
  6589. #define LPDDR4__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN__FLD LPDDR4__DENALI_CTL_444__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN
  6590. #define LPDDR4__DENALI_CTL_444__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN_MASK 0x00000100U
  6591. #define LPDDR4__DENALI_CTL_444__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN_SHIFT 8U
  6592. #define LPDDR4__DENALI_CTL_444__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN_WIDTH 1U
  6593. #define LPDDR4__DENALI_CTL_444__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN_WOCLR 0U
  6594. #define LPDDR4__DENALI_CTL_444__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN_WOSET 0U
  6595. #define LPDDR4__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN__REG DENALI_CTL_444
  6596. #define LPDDR4__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN__FLD LPDDR4__DENALI_CTL_444__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN
  6597. #define LPDDR4__DENALI_CTL_444__PARAMREG_PARITY_PROTECTION_INJECTION_EN_MASK 0x00010000U
  6598. #define LPDDR4__DENALI_CTL_444__PARAMREG_PARITY_PROTECTION_INJECTION_EN_SHIFT 16U
  6599. #define LPDDR4__DENALI_CTL_444__PARAMREG_PARITY_PROTECTION_INJECTION_EN_WIDTH 1U
  6600. #define LPDDR4__DENALI_CTL_444__PARAMREG_PARITY_PROTECTION_INJECTION_EN_WOCLR 0U
  6601. #define LPDDR4__DENALI_CTL_444__PARAMREG_PARITY_PROTECTION_INJECTION_EN_WOSET 0U
  6602. #define LPDDR4__PARAMREG_PARITY_PROTECTION_INJECTION_EN__REG DENALI_CTL_444
  6603. #define LPDDR4__PARAMREG_PARITY_PROTECTION_INJECTION_EN__FLD LPDDR4__DENALI_CTL_444__PARAMREG_PARITY_PROTECTION_INJECTION_EN
  6604. #define LPDDR4__DENALI_CTL_445_READ_MASK 0xFFFFFFFFU
  6605. #define LPDDR4__DENALI_CTL_445_WRITE_MASK 0xFFFFFFFFU
  6606. #define LPDDR4__DENALI_CTL_445__MC_RESERVED60_0_MASK 0xFFFFFFFFU
  6607. #define LPDDR4__DENALI_CTL_445__MC_RESERVED60_0_SHIFT 0U
  6608. #define LPDDR4__DENALI_CTL_445__MC_RESERVED60_0_WIDTH 32U
  6609. #define LPDDR4__MC_RESERVED60_0__REG DENALI_CTL_445
  6610. #define LPDDR4__MC_RESERVED60_0__FLD LPDDR4__DENALI_CTL_445__MC_RESERVED60_0
  6611. #define LPDDR4__DENALI_CTL_446_READ_MASK 0xFFFFFFFFU
  6612. #define LPDDR4__DENALI_CTL_446_WRITE_MASK 0xFFFFFFFFU
  6613. #define LPDDR4__DENALI_CTL_446__MC_RESERVED60_1_MASK 0xFFFFFFFFU
  6614. #define LPDDR4__DENALI_CTL_446__MC_RESERVED60_1_SHIFT 0U
  6615. #define LPDDR4__DENALI_CTL_446__MC_RESERVED60_1_WIDTH 32U
  6616. #define LPDDR4__MC_RESERVED60_1__REG DENALI_CTL_446
  6617. #define LPDDR4__MC_RESERVED60_1__FLD LPDDR4__DENALI_CTL_446__MC_RESERVED60_1
  6618. #define LPDDR4__DENALI_CTL_447_READ_MASK 0x00000107U
  6619. #define LPDDR4__DENALI_CTL_447_WRITE_MASK 0x00000107U
  6620. #define LPDDR4__DENALI_CTL_447__MC_RESERVED60_2_MASK 0x00000007U
  6621. #define LPDDR4__DENALI_CTL_447__MC_RESERVED60_2_SHIFT 0U
  6622. #define LPDDR4__DENALI_CTL_447__MC_RESERVED60_2_WIDTH 3U
  6623. #define LPDDR4__MC_RESERVED60_2__REG DENALI_CTL_447
  6624. #define LPDDR4__MC_RESERVED60_2__FLD LPDDR4__DENALI_CTL_447__MC_RESERVED60_2
  6625. #define LPDDR4__DENALI_CTL_447__PORT_TO_CORE_PROTECTION_EN_MASK 0x00000100U
  6626. #define LPDDR4__DENALI_CTL_447__PORT_TO_CORE_PROTECTION_EN_SHIFT 8U
  6627. #define LPDDR4__DENALI_CTL_447__PORT_TO_CORE_PROTECTION_EN_WIDTH 1U
  6628. #define LPDDR4__DENALI_CTL_447__PORT_TO_CORE_PROTECTION_EN_WOCLR 0U
  6629. #define LPDDR4__DENALI_CTL_447__PORT_TO_CORE_PROTECTION_EN_WOSET 0U
  6630. #define LPDDR4__PORT_TO_CORE_PROTECTION_EN__REG DENALI_CTL_447
  6631. #define LPDDR4__PORT_TO_CORE_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_447__PORT_TO_CORE_PROTECTION_EN
  6632. #define LPDDR4__DENALI_CTL_448_READ_MASK 0xFFFFFFFFU
  6633. #define LPDDR4__DENALI_CTL_448_WRITE_MASK 0xFFFFFFFFU
  6634. #define LPDDR4__DENALI_CTL_448__PORT_TO_CORE_PROTECTION_INJECTION_EN_0_MASK 0xFFFFFFFFU
  6635. #define LPDDR4__DENALI_CTL_448__PORT_TO_CORE_PROTECTION_INJECTION_EN_0_SHIFT 0U
  6636. #define LPDDR4__DENALI_CTL_448__PORT_TO_CORE_PROTECTION_INJECTION_EN_0_WIDTH 32U
  6637. #define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_0__REG DENALI_CTL_448
  6638. #define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_0__FLD LPDDR4__DENALI_CTL_448__PORT_TO_CORE_PROTECTION_INJECTION_EN_0
  6639. #define LPDDR4__DENALI_CTL_449_READ_MASK 0xFFFFFFFFU
  6640. #define LPDDR4__DENALI_CTL_449_WRITE_MASK 0xFFFFFFFFU
  6641. #define LPDDR4__DENALI_CTL_449__PORT_TO_CORE_PROTECTION_INJECTION_EN_1_MASK 0xFFFFFFFFU
  6642. #define LPDDR4__DENALI_CTL_449__PORT_TO_CORE_PROTECTION_INJECTION_EN_1_SHIFT 0U
  6643. #define LPDDR4__DENALI_CTL_449__PORT_TO_CORE_PROTECTION_INJECTION_EN_1_WIDTH 32U
  6644. #define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_1__REG DENALI_CTL_449
  6645. #define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_1__FLD LPDDR4__DENALI_CTL_449__PORT_TO_CORE_PROTECTION_INJECTION_EN_1
  6646. #define LPDDR4__DENALI_CTL_450_READ_MASK 0x00000007U
  6647. #define LPDDR4__DENALI_CTL_450_WRITE_MASK 0x00000007U
  6648. #define LPDDR4__DENALI_CTL_450__PORT_TO_CORE_PROTECTION_INJECTION_EN_2_MASK 0x00000007U
  6649. #define LPDDR4__DENALI_CTL_450__PORT_TO_CORE_PROTECTION_INJECTION_EN_2_SHIFT 0U
  6650. #define LPDDR4__DENALI_CTL_450__PORT_TO_CORE_PROTECTION_INJECTION_EN_2_WIDTH 3U
  6651. #define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_2__REG DENALI_CTL_450
  6652. #define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_2__FLD LPDDR4__DENALI_CTL_450__PORT_TO_CORE_PROTECTION_INJECTION_EN_2
  6653. #define LPDDR4__DENALI_CTL_451_READ_MASK 0xFFFFFFFFU
  6654. #define LPDDR4__DENALI_CTL_451_WRITE_MASK 0xFFFFFFFFU
  6655. #define LPDDR4__DENALI_CTL_451__MC_RESERVED61_0_MASK 0xFFFFFFFFU
  6656. #define LPDDR4__DENALI_CTL_451__MC_RESERVED61_0_SHIFT 0U
  6657. #define LPDDR4__DENALI_CTL_451__MC_RESERVED61_0_WIDTH 32U
  6658. #define LPDDR4__MC_RESERVED61_0__REG DENALI_CTL_451
  6659. #define LPDDR4__MC_RESERVED61_0__FLD LPDDR4__DENALI_CTL_451__MC_RESERVED61_0
  6660. #define LPDDR4__DENALI_CTL_452_READ_MASK 0xFFFFFFFFU
  6661. #define LPDDR4__DENALI_CTL_452_WRITE_MASK 0xFFFFFFFFU
  6662. #define LPDDR4__DENALI_CTL_452__MC_RESERVED61_1_MASK 0xFFFFFFFFU
  6663. #define LPDDR4__DENALI_CTL_452__MC_RESERVED61_1_SHIFT 0U
  6664. #define LPDDR4__DENALI_CTL_452__MC_RESERVED61_1_WIDTH 32U
  6665. #define LPDDR4__MC_RESERVED61_1__REG DENALI_CTL_452
  6666. #define LPDDR4__MC_RESERVED61_1__FLD LPDDR4__DENALI_CTL_452__MC_RESERVED61_1
  6667. #define LPDDR4__DENALI_CTL_453_READ_MASK 0xFFFFFFFFU
  6668. #define LPDDR4__DENALI_CTL_453_WRITE_MASK 0xFFFFFFFFU
  6669. #define LPDDR4__DENALI_CTL_453__MC_RESERVED61_2_MASK 0xFFFFFFFFU
  6670. #define LPDDR4__DENALI_CTL_453__MC_RESERVED61_2_SHIFT 0U
  6671. #define LPDDR4__DENALI_CTL_453__MC_RESERVED61_2_WIDTH 32U
  6672. #define LPDDR4__MC_RESERVED61_2__REG DENALI_CTL_453
  6673. #define LPDDR4__MC_RESERVED61_2__FLD LPDDR4__DENALI_CTL_453__MC_RESERVED61_2
  6674. #define LPDDR4__DENALI_CTL_454_READ_MASK 0x0000000FU
  6675. #define LPDDR4__DENALI_CTL_454_WRITE_MASK 0x0000000FU
  6676. #define LPDDR4__DENALI_CTL_454__MC_RESERVED61_3_MASK 0x0000000FU
  6677. #define LPDDR4__DENALI_CTL_454__MC_RESERVED61_3_SHIFT 0U
  6678. #define LPDDR4__DENALI_CTL_454__MC_RESERVED61_3_WIDTH 4U
  6679. #define LPDDR4__MC_RESERVED61_3__REG DENALI_CTL_454
  6680. #define LPDDR4__MC_RESERVED61_3__FLD LPDDR4__DENALI_CTL_454__MC_RESERVED61_3
  6681. #define LPDDR4__DENALI_CTL_455_READ_MASK 0xFFFFFFFFU
  6682. #define LPDDR4__DENALI_CTL_455_WRITE_MASK 0xFFFFFFFFU
  6683. #define LPDDR4__DENALI_CTL_455__PORT_TO_CORE_LR_ERR_INJ_EN_0_MASK 0xFFFFFFFFU
  6684. #define LPDDR4__DENALI_CTL_455__PORT_TO_CORE_LR_ERR_INJ_EN_0_SHIFT 0U
  6685. #define LPDDR4__DENALI_CTL_455__PORT_TO_CORE_LR_ERR_INJ_EN_0_WIDTH 32U
  6686. #define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_0__REG DENALI_CTL_455
  6687. #define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_0__FLD LPDDR4__DENALI_CTL_455__PORT_TO_CORE_LR_ERR_INJ_EN_0
  6688. #define LPDDR4__DENALI_CTL_456_READ_MASK 0xFFFFFFFFU
  6689. #define LPDDR4__DENALI_CTL_456_WRITE_MASK 0xFFFFFFFFU
  6690. #define LPDDR4__DENALI_CTL_456__PORT_TO_CORE_LR_ERR_INJ_EN_1_MASK 0xFFFFFFFFU
  6691. #define LPDDR4__DENALI_CTL_456__PORT_TO_CORE_LR_ERR_INJ_EN_1_SHIFT 0U
  6692. #define LPDDR4__DENALI_CTL_456__PORT_TO_CORE_LR_ERR_INJ_EN_1_WIDTH 32U
  6693. #define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_1__REG DENALI_CTL_456
  6694. #define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_1__FLD LPDDR4__DENALI_CTL_456__PORT_TO_CORE_LR_ERR_INJ_EN_1
  6695. #define LPDDR4__DENALI_CTL_457_READ_MASK 0xFFFFFFFFU
  6696. #define LPDDR4__DENALI_CTL_457_WRITE_MASK 0xFFFFFFFFU
  6697. #define LPDDR4__DENALI_CTL_457__PORT_TO_CORE_LR_ERR_INJ_EN_2_MASK 0xFFFFFFFFU
  6698. #define LPDDR4__DENALI_CTL_457__PORT_TO_CORE_LR_ERR_INJ_EN_2_SHIFT 0U
  6699. #define LPDDR4__DENALI_CTL_457__PORT_TO_CORE_LR_ERR_INJ_EN_2_WIDTH 32U
  6700. #define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_2__REG DENALI_CTL_457
  6701. #define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_2__FLD LPDDR4__DENALI_CTL_457__PORT_TO_CORE_LR_ERR_INJ_EN_2
  6702. #define LPDDR4__DENALI_CTL_458_READ_MASK 0x0000000FU
  6703. #define LPDDR4__DENALI_CTL_458_WRITE_MASK 0x0000000FU
  6704. #define LPDDR4__DENALI_CTL_458__PORT_TO_CORE_LR_ERR_INJ_EN_3_MASK 0x0000000FU
  6705. #define LPDDR4__DENALI_CTL_458__PORT_TO_CORE_LR_ERR_INJ_EN_3_SHIFT 0U
  6706. #define LPDDR4__DENALI_CTL_458__PORT_TO_CORE_LR_ERR_INJ_EN_3_WIDTH 4U
  6707. #define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_3__REG DENALI_CTL_458
  6708. #define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_3__FLD LPDDR4__DENALI_CTL_458__PORT_TO_CORE_LR_ERR_INJ_EN_3
  6709. #endif /* REG_LPDDR4_DDR_CONTROLLER_MACROS_H_ */