lpddr4_data_slice_3_macros.h 152 KB

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  1. /* SPDX-License-Identifier: BSD-3-Clause */
  2. /**********************************************************************
  3. * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
  4. *
  5. * THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT
  6. *
  7. **********************************************************************
  8. */
  9. #ifndef REG_LPDDR4_DATA_SLICE_3_MACROS_H_
  10. #define REG_LPDDR4_DATA_SLICE_3_MACROS_H_
  11. #define LPDDR4__DENALI_PHY_768_READ_MASK 0x000F07FFU
  12. #define LPDDR4__DENALI_PHY_768_WRITE_MASK 0x000F07FFU
  13. #define LPDDR4__DENALI_PHY_768__PHY_CLK_WR_BYPASS_SLAVE_DELAY_3_MASK 0x000007FFU
  14. #define LPDDR4__DENALI_PHY_768__PHY_CLK_WR_BYPASS_SLAVE_DELAY_3_SHIFT 0U
  15. #define LPDDR4__DENALI_PHY_768__PHY_CLK_WR_BYPASS_SLAVE_DELAY_3_WIDTH 11U
  16. #define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_3__REG DENALI_PHY_768
  17. #define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_768__PHY_CLK_WR_BYPASS_SLAVE_DELAY_3
  18. #define LPDDR4__DENALI_PHY_768__PHY_IO_PAD_DELAY_TIMING_BYPASS_3_MASK 0x000F0000U
  19. #define LPDDR4__DENALI_PHY_768__PHY_IO_PAD_DELAY_TIMING_BYPASS_3_SHIFT 16U
  20. #define LPDDR4__DENALI_PHY_768__PHY_IO_PAD_DELAY_TIMING_BYPASS_3_WIDTH 4U
  21. #define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_3__REG DENALI_PHY_768
  22. #define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_3__FLD LPDDR4__DENALI_PHY_768__PHY_IO_PAD_DELAY_TIMING_BYPASS_3
  23. #define LPDDR4__DENALI_PHY_769_READ_MASK 0x000703FFU
  24. #define LPDDR4__DENALI_PHY_769_WRITE_MASK 0x000703FFU
  25. #define LPDDR4__DENALI_PHY_769__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3_MASK 0x000003FFU
  26. #define LPDDR4__DENALI_PHY_769__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3_SHIFT 0U
  27. #define LPDDR4__DENALI_PHY_769__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3_WIDTH 10U
  28. #define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3__REG DENALI_PHY_769
  29. #define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3__FLD LPDDR4__DENALI_PHY_769__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3
  30. #define LPDDR4__DENALI_PHY_769__PHY_WRITE_PATH_LAT_ADD_BYPASS_3_MASK 0x00070000U
  31. #define LPDDR4__DENALI_PHY_769__PHY_WRITE_PATH_LAT_ADD_BYPASS_3_SHIFT 16U
  32. #define LPDDR4__DENALI_PHY_769__PHY_WRITE_PATH_LAT_ADD_BYPASS_3_WIDTH 3U
  33. #define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_3__REG DENALI_PHY_769
  34. #define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_3__FLD LPDDR4__DENALI_PHY_769__PHY_WRITE_PATH_LAT_ADD_BYPASS_3
  35. #define LPDDR4__DENALI_PHY_770_READ_MASK 0x010303FFU
  36. #define LPDDR4__DENALI_PHY_770_WRITE_MASK 0x010303FFU
  37. #define LPDDR4__DENALI_PHY_770__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3_MASK 0x000003FFU
  38. #define LPDDR4__DENALI_PHY_770__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3_SHIFT 0U
  39. #define LPDDR4__DENALI_PHY_770__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3_WIDTH 10U
  40. #define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3__REG DENALI_PHY_770
  41. #define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_770__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3
  42. #define LPDDR4__DENALI_PHY_770__PHY_BYPASS_TWO_CYC_PREAMBLE_3_MASK 0x00030000U
  43. #define LPDDR4__DENALI_PHY_770__PHY_BYPASS_TWO_CYC_PREAMBLE_3_SHIFT 16U
  44. #define LPDDR4__DENALI_PHY_770__PHY_BYPASS_TWO_CYC_PREAMBLE_3_WIDTH 2U
  45. #define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_3__REG DENALI_PHY_770
  46. #define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_3__FLD LPDDR4__DENALI_PHY_770__PHY_BYPASS_TWO_CYC_PREAMBLE_3
  47. #define LPDDR4__DENALI_PHY_770__PHY_CLK_BYPASS_OVERRIDE_3_MASK 0x01000000U
  48. #define LPDDR4__DENALI_PHY_770__PHY_CLK_BYPASS_OVERRIDE_3_SHIFT 24U
  49. #define LPDDR4__DENALI_PHY_770__PHY_CLK_BYPASS_OVERRIDE_3_WIDTH 1U
  50. #define LPDDR4__DENALI_PHY_770__PHY_CLK_BYPASS_OVERRIDE_3_WOCLR 0U
  51. #define LPDDR4__DENALI_PHY_770__PHY_CLK_BYPASS_OVERRIDE_3_WOSET 0U
  52. #define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_3__REG DENALI_PHY_770
  53. #define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_3__FLD LPDDR4__DENALI_PHY_770__PHY_CLK_BYPASS_OVERRIDE_3
  54. #define LPDDR4__DENALI_PHY_771_READ_MASK 0x3F3F3F3FU
  55. #define LPDDR4__DENALI_PHY_771_WRITE_MASK 0x3F3F3F3FU
  56. #define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ0_SHIFT_3_MASK 0x0000003FU
  57. #define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ0_SHIFT_3_SHIFT 0U
  58. #define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ0_SHIFT_3_WIDTH 6U
  59. #define LPDDR4__PHY_SW_WRDQ0_SHIFT_3__REG DENALI_PHY_771
  60. #define LPDDR4__PHY_SW_WRDQ0_SHIFT_3__FLD LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ0_SHIFT_3
  61. #define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ1_SHIFT_3_MASK 0x00003F00U
  62. #define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ1_SHIFT_3_SHIFT 8U
  63. #define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ1_SHIFT_3_WIDTH 6U
  64. #define LPDDR4__PHY_SW_WRDQ1_SHIFT_3__REG DENALI_PHY_771
  65. #define LPDDR4__PHY_SW_WRDQ1_SHIFT_3__FLD LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ1_SHIFT_3
  66. #define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ2_SHIFT_3_MASK 0x003F0000U
  67. #define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ2_SHIFT_3_SHIFT 16U
  68. #define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ2_SHIFT_3_WIDTH 6U
  69. #define LPDDR4__PHY_SW_WRDQ2_SHIFT_3__REG DENALI_PHY_771
  70. #define LPDDR4__PHY_SW_WRDQ2_SHIFT_3__FLD LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ2_SHIFT_3
  71. #define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ3_SHIFT_3_MASK 0x3F000000U
  72. #define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ3_SHIFT_3_SHIFT 24U
  73. #define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ3_SHIFT_3_WIDTH 6U
  74. #define LPDDR4__PHY_SW_WRDQ3_SHIFT_3__REG DENALI_PHY_771
  75. #define LPDDR4__PHY_SW_WRDQ3_SHIFT_3__FLD LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ3_SHIFT_3
  76. #define LPDDR4__DENALI_PHY_772_READ_MASK 0x3F3F3F3FU
  77. #define LPDDR4__DENALI_PHY_772_WRITE_MASK 0x3F3F3F3FU
  78. #define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ4_SHIFT_3_MASK 0x0000003FU
  79. #define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ4_SHIFT_3_SHIFT 0U
  80. #define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ4_SHIFT_3_WIDTH 6U
  81. #define LPDDR4__PHY_SW_WRDQ4_SHIFT_3__REG DENALI_PHY_772
  82. #define LPDDR4__PHY_SW_WRDQ4_SHIFT_3__FLD LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ4_SHIFT_3
  83. #define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ5_SHIFT_3_MASK 0x00003F00U
  84. #define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ5_SHIFT_3_SHIFT 8U
  85. #define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ5_SHIFT_3_WIDTH 6U
  86. #define LPDDR4__PHY_SW_WRDQ5_SHIFT_3__REG DENALI_PHY_772
  87. #define LPDDR4__PHY_SW_WRDQ5_SHIFT_3__FLD LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ5_SHIFT_3
  88. #define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ6_SHIFT_3_MASK 0x003F0000U
  89. #define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ6_SHIFT_3_SHIFT 16U
  90. #define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ6_SHIFT_3_WIDTH 6U
  91. #define LPDDR4__PHY_SW_WRDQ6_SHIFT_3__REG DENALI_PHY_772
  92. #define LPDDR4__PHY_SW_WRDQ6_SHIFT_3__FLD LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ6_SHIFT_3
  93. #define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ7_SHIFT_3_MASK 0x3F000000U
  94. #define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ7_SHIFT_3_SHIFT 24U
  95. #define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ7_SHIFT_3_WIDTH 6U
  96. #define LPDDR4__PHY_SW_WRDQ7_SHIFT_3__REG DENALI_PHY_772
  97. #define LPDDR4__PHY_SW_WRDQ7_SHIFT_3__FLD LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ7_SHIFT_3
  98. #define LPDDR4__DENALI_PHY_773_READ_MASK 0x01030F3FU
  99. #define LPDDR4__DENALI_PHY_773_WRITE_MASK 0x01030F3FU
  100. #define LPDDR4__DENALI_PHY_773__PHY_SW_WRDM_SHIFT_3_MASK 0x0000003FU
  101. #define LPDDR4__DENALI_PHY_773__PHY_SW_WRDM_SHIFT_3_SHIFT 0U
  102. #define LPDDR4__DENALI_PHY_773__PHY_SW_WRDM_SHIFT_3_WIDTH 6U
  103. #define LPDDR4__PHY_SW_WRDM_SHIFT_3__REG DENALI_PHY_773
  104. #define LPDDR4__PHY_SW_WRDM_SHIFT_3__FLD LPDDR4__DENALI_PHY_773__PHY_SW_WRDM_SHIFT_3
  105. #define LPDDR4__DENALI_PHY_773__PHY_SW_WRDQS_SHIFT_3_MASK 0x00000F00U
  106. #define LPDDR4__DENALI_PHY_773__PHY_SW_WRDQS_SHIFT_3_SHIFT 8U
  107. #define LPDDR4__DENALI_PHY_773__PHY_SW_WRDQS_SHIFT_3_WIDTH 4U
  108. #define LPDDR4__PHY_SW_WRDQS_SHIFT_3__REG DENALI_PHY_773
  109. #define LPDDR4__PHY_SW_WRDQS_SHIFT_3__FLD LPDDR4__DENALI_PHY_773__PHY_SW_WRDQS_SHIFT_3
  110. #define LPDDR4__DENALI_PHY_773__PHY_PER_RANK_CS_MAP_3_MASK 0x00030000U
  111. #define LPDDR4__DENALI_PHY_773__PHY_PER_RANK_CS_MAP_3_SHIFT 16U
  112. #define LPDDR4__DENALI_PHY_773__PHY_PER_RANK_CS_MAP_3_WIDTH 2U
  113. #define LPDDR4__PHY_PER_RANK_CS_MAP_3__REG DENALI_PHY_773
  114. #define LPDDR4__PHY_PER_RANK_CS_MAP_3__FLD LPDDR4__DENALI_PHY_773__PHY_PER_RANK_CS_MAP_3
  115. #define LPDDR4__DENALI_PHY_773__PHY_PER_CS_TRAINING_MULTICAST_EN_3_MASK 0x01000000U
  116. #define LPDDR4__DENALI_PHY_773__PHY_PER_CS_TRAINING_MULTICAST_EN_3_SHIFT 24U
  117. #define LPDDR4__DENALI_PHY_773__PHY_PER_CS_TRAINING_MULTICAST_EN_3_WIDTH 1U
  118. #define LPDDR4__DENALI_PHY_773__PHY_PER_CS_TRAINING_MULTICAST_EN_3_WOCLR 0U
  119. #define LPDDR4__DENALI_PHY_773__PHY_PER_CS_TRAINING_MULTICAST_EN_3_WOSET 0U
  120. #define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_3__REG DENALI_PHY_773
  121. #define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_3__FLD LPDDR4__DENALI_PHY_773__PHY_PER_CS_TRAINING_MULTICAST_EN_3
  122. #define LPDDR4__DENALI_PHY_774_READ_MASK 0x1F1F0301U
  123. #define LPDDR4__DENALI_PHY_774_WRITE_MASK 0x1F1F0301U
  124. #define LPDDR4__DENALI_PHY_774__PHY_PER_CS_TRAINING_INDEX_3_MASK 0x00000001U
  125. #define LPDDR4__DENALI_PHY_774__PHY_PER_CS_TRAINING_INDEX_3_SHIFT 0U
  126. #define LPDDR4__DENALI_PHY_774__PHY_PER_CS_TRAINING_INDEX_3_WIDTH 1U
  127. #define LPDDR4__DENALI_PHY_774__PHY_PER_CS_TRAINING_INDEX_3_WOCLR 0U
  128. #define LPDDR4__DENALI_PHY_774__PHY_PER_CS_TRAINING_INDEX_3_WOSET 0U
  129. #define LPDDR4__PHY_PER_CS_TRAINING_INDEX_3__REG DENALI_PHY_774
  130. #define LPDDR4__PHY_PER_CS_TRAINING_INDEX_3__FLD LPDDR4__DENALI_PHY_774__PHY_PER_CS_TRAINING_INDEX_3
  131. #define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3_MASK 0x00000300U
  132. #define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3_SHIFT 8U
  133. #define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3_WIDTH 2U
  134. #define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3__REG DENALI_PHY_774
  135. #define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3__FLD LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3
  136. #define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_DLY_3_MASK 0x001F0000U
  137. #define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_DLY_3_SHIFT 16U
  138. #define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_DLY_3_WIDTH 5U
  139. #define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_3__REG DENALI_PHY_774
  140. #define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_3__FLD LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_DLY_3
  141. #define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3_MASK 0x1F000000U
  142. #define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3_SHIFT 24U
  143. #define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3_WIDTH 5U
  144. #define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3__REG DENALI_PHY_774
  145. #define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3__FLD LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3
  146. #define LPDDR4__DENALI_PHY_775_READ_MASK 0x1F030F0FU
  147. #define LPDDR4__DENALI_PHY_775_WRITE_MASK 0x1F030F0FU
  148. #define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RPTR_UPDATE_3_MASK 0x0000000FU
  149. #define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RPTR_UPDATE_3_SHIFT 0U
  150. #define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RPTR_UPDATE_3_WIDTH 4U
  151. #define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_3__REG DENALI_PHY_775
  152. #define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_3__FLD LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RPTR_UPDATE_3
  153. #define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3_MASK 0x00000F00U
  154. #define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3_SHIFT 8U
  155. #define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3_WIDTH 4U
  156. #define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3__REG DENALI_PHY_775
  157. #define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3__FLD LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3
  158. #define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_3_MASK 0x00030000U
  159. #define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_3_SHIFT 16U
  160. #define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_3_WIDTH 2U
  161. #define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_3__REG DENALI_PHY_775
  162. #define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_3__FLD LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_3
  163. #define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3_MASK 0x1F000000U
  164. #define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3_SHIFT 24U
  165. #define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3_WIDTH 5U
  166. #define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3__REG DENALI_PHY_775
  167. #define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3__FLD LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3
  168. #define LPDDR4__DENALI_PHY_776_READ_MASK 0x0101FF03U
  169. #define LPDDR4__DENALI_PHY_776_WRITE_MASK 0x0101FF03U
  170. #define LPDDR4__DENALI_PHY_776__PHY_CTRL_LPBK_EN_3_MASK 0x00000003U
  171. #define LPDDR4__DENALI_PHY_776__PHY_CTRL_LPBK_EN_3_SHIFT 0U
  172. #define LPDDR4__DENALI_PHY_776__PHY_CTRL_LPBK_EN_3_WIDTH 2U
  173. #define LPDDR4__PHY_CTRL_LPBK_EN_3__REG DENALI_PHY_776
  174. #define LPDDR4__PHY_CTRL_LPBK_EN_3__FLD LPDDR4__DENALI_PHY_776__PHY_CTRL_LPBK_EN_3
  175. #define LPDDR4__DENALI_PHY_776__PHY_LPBK_CONTROL_3_MASK 0x0001FF00U
  176. #define LPDDR4__DENALI_PHY_776__PHY_LPBK_CONTROL_3_SHIFT 8U
  177. #define LPDDR4__DENALI_PHY_776__PHY_LPBK_CONTROL_3_WIDTH 9U
  178. #define LPDDR4__PHY_LPBK_CONTROL_3__REG DENALI_PHY_776
  179. #define LPDDR4__PHY_LPBK_CONTROL_3__FLD LPDDR4__DENALI_PHY_776__PHY_LPBK_CONTROL_3
  180. #define LPDDR4__DENALI_PHY_776__PHY_LPBK_DFX_TIMEOUT_EN_3_MASK 0x01000000U
  181. #define LPDDR4__DENALI_PHY_776__PHY_LPBK_DFX_TIMEOUT_EN_3_SHIFT 24U
  182. #define LPDDR4__DENALI_PHY_776__PHY_LPBK_DFX_TIMEOUT_EN_3_WIDTH 1U
  183. #define LPDDR4__DENALI_PHY_776__PHY_LPBK_DFX_TIMEOUT_EN_3_WOCLR 0U
  184. #define LPDDR4__DENALI_PHY_776__PHY_LPBK_DFX_TIMEOUT_EN_3_WOSET 0U
  185. #define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_3__REG DENALI_PHY_776
  186. #define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_3__FLD LPDDR4__DENALI_PHY_776__PHY_LPBK_DFX_TIMEOUT_EN_3
  187. #define LPDDR4__DENALI_PHY_777_READ_MASK 0xFFFFFFFFU
  188. #define LPDDR4__DENALI_PHY_777_WRITE_MASK 0xFFFFFFFFU
  189. #define LPDDR4__DENALI_PHY_777__PHY_AUTO_TIMING_MARGIN_CONTROL_3_MASK 0xFFFFFFFFU
  190. #define LPDDR4__DENALI_PHY_777__PHY_AUTO_TIMING_MARGIN_CONTROL_3_SHIFT 0U
  191. #define LPDDR4__DENALI_PHY_777__PHY_AUTO_TIMING_MARGIN_CONTROL_3_WIDTH 32U
  192. #define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_3__REG DENALI_PHY_777
  193. #define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_3__FLD LPDDR4__DENALI_PHY_777__PHY_AUTO_TIMING_MARGIN_CONTROL_3
  194. #define LPDDR4__DENALI_PHY_778_READ_MASK 0x0FFFFFFFU
  195. #define LPDDR4__DENALI_PHY_778_WRITE_MASK 0x0FFFFFFFU
  196. #define LPDDR4__DENALI_PHY_778__PHY_AUTO_TIMING_MARGIN_OBS_3_MASK 0x0FFFFFFFU
  197. #define LPDDR4__DENALI_PHY_778__PHY_AUTO_TIMING_MARGIN_OBS_3_SHIFT 0U
  198. #define LPDDR4__DENALI_PHY_778__PHY_AUTO_TIMING_MARGIN_OBS_3_WIDTH 28U
  199. #define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_3__REG DENALI_PHY_778
  200. #define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_3__FLD LPDDR4__DENALI_PHY_778__PHY_AUTO_TIMING_MARGIN_OBS_3
  201. #define LPDDR4__DENALI_PHY_779_READ_MASK 0x0101FF7FU
  202. #define LPDDR4__DENALI_PHY_779_WRITE_MASK 0x0101FF7FU
  203. #define LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_START_3_MASK 0x0000007FU
  204. #define LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_START_3_SHIFT 0U
  205. #define LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_START_3_WIDTH 7U
  206. #define LPDDR4__PHY_PRBS_PATTERN_START_3__REG DENALI_PHY_779
  207. #define LPDDR4__PHY_PRBS_PATTERN_START_3__FLD LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_START_3
  208. #define LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_MASK_3_MASK 0x0001FF00U
  209. #define LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_MASK_3_SHIFT 8U
  210. #define LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_MASK_3_WIDTH 9U
  211. #define LPDDR4__PHY_PRBS_PATTERN_MASK_3__REG DENALI_PHY_779
  212. #define LPDDR4__PHY_PRBS_PATTERN_MASK_3__FLD LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_MASK_3
  213. #define LPDDR4__DENALI_PHY_779__PHY_RDLVL_MULTI_PATT_ENABLE_3_MASK 0x01000000U
  214. #define LPDDR4__DENALI_PHY_779__PHY_RDLVL_MULTI_PATT_ENABLE_3_SHIFT 24U
  215. #define LPDDR4__DENALI_PHY_779__PHY_RDLVL_MULTI_PATT_ENABLE_3_WIDTH 1U
  216. #define LPDDR4__DENALI_PHY_779__PHY_RDLVL_MULTI_PATT_ENABLE_3_WOCLR 0U
  217. #define LPDDR4__DENALI_PHY_779__PHY_RDLVL_MULTI_PATT_ENABLE_3_WOSET 0U
  218. #define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_3__REG DENALI_PHY_779
  219. #define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_3__FLD LPDDR4__DENALI_PHY_779__PHY_RDLVL_MULTI_PATT_ENABLE_3
  220. #define LPDDR4__DENALI_PHY_780_READ_MASK 0x007F3F01U
  221. #define LPDDR4__DENALI_PHY_780_WRITE_MASK 0x007F3F01U
  222. #define LPDDR4__DENALI_PHY_780__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3_MASK 0x00000001U
  223. #define LPDDR4__DENALI_PHY_780__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3_SHIFT 0U
  224. #define LPDDR4__DENALI_PHY_780__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3_WIDTH 1U
  225. #define LPDDR4__DENALI_PHY_780__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3_WOCLR 0U
  226. #define LPDDR4__DENALI_PHY_780__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3_WOSET 0U
  227. #define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3__REG DENALI_PHY_780
  228. #define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3__FLD LPDDR4__DENALI_PHY_780__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3
  229. #define LPDDR4__DENALI_PHY_780__PHY_VREF_INITIAL_STEPSIZE_3_MASK 0x00003F00U
  230. #define LPDDR4__DENALI_PHY_780__PHY_VREF_INITIAL_STEPSIZE_3_SHIFT 8U
  231. #define LPDDR4__DENALI_PHY_780__PHY_VREF_INITIAL_STEPSIZE_3_WIDTH 6U
  232. #define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_3__REG DENALI_PHY_780
  233. #define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_3__FLD LPDDR4__DENALI_PHY_780__PHY_VREF_INITIAL_STEPSIZE_3
  234. #define LPDDR4__DENALI_PHY_780__PHY_VREF_TRAIN_OBS_3_MASK 0x007F0000U
  235. #define LPDDR4__DENALI_PHY_780__PHY_VREF_TRAIN_OBS_3_SHIFT 16U
  236. #define LPDDR4__DENALI_PHY_780__PHY_VREF_TRAIN_OBS_3_WIDTH 7U
  237. #define LPDDR4__PHY_VREF_TRAIN_OBS_3__REG DENALI_PHY_780
  238. #define LPDDR4__PHY_VREF_TRAIN_OBS_3__FLD LPDDR4__DENALI_PHY_780__PHY_VREF_TRAIN_OBS_3
  239. #define LPDDR4__DENALI_PHY_781_READ_MASK 0x000F03FFU
  240. #define LPDDR4__DENALI_PHY_781_WRITE_MASK 0x000F03FFU
  241. #define LPDDR4__DENALI_PHY_781__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3_MASK 0x000003FFU
  242. #define LPDDR4__DENALI_PHY_781__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3_SHIFT 0U
  243. #define LPDDR4__DENALI_PHY_781__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3_WIDTH 10U
  244. #define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3__REG DENALI_PHY_781
  245. #define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_781__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3
  246. #define LPDDR4__DENALI_PHY_781__PHY_GATE_ERROR_DELAY_SELECT_3_MASK 0x000F0000U
  247. #define LPDDR4__DENALI_PHY_781__PHY_GATE_ERROR_DELAY_SELECT_3_SHIFT 16U
  248. #define LPDDR4__DENALI_PHY_781__PHY_GATE_ERROR_DELAY_SELECT_3_WIDTH 4U
  249. #define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_3__REG DENALI_PHY_781
  250. #define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_3__FLD LPDDR4__DENALI_PHY_781__PHY_GATE_ERROR_DELAY_SELECT_3
  251. #define LPDDR4__DENALI_PHY_781__SC_PHY_SNAP_OBS_REGS_3_MASK 0x01000000U
  252. #define LPDDR4__DENALI_PHY_781__SC_PHY_SNAP_OBS_REGS_3_SHIFT 24U
  253. #define LPDDR4__DENALI_PHY_781__SC_PHY_SNAP_OBS_REGS_3_WIDTH 1U
  254. #define LPDDR4__DENALI_PHY_781__SC_PHY_SNAP_OBS_REGS_3_WOCLR 0U
  255. #define LPDDR4__DENALI_PHY_781__SC_PHY_SNAP_OBS_REGS_3_WOSET 0U
  256. #define LPDDR4__SC_PHY_SNAP_OBS_REGS_3__REG DENALI_PHY_781
  257. #define LPDDR4__SC_PHY_SNAP_OBS_REGS_3__FLD LPDDR4__DENALI_PHY_781__SC_PHY_SNAP_OBS_REGS_3
  258. #define LPDDR4__DENALI_PHY_782_READ_MASK 0x070101FFU
  259. #define LPDDR4__DENALI_PHY_782_WRITE_MASK 0x070101FFU
  260. #define LPDDR4__DENALI_PHY_782__PHY_GATE_SMPL1_SLAVE_DELAY_3_MASK 0x000001FFU
  261. #define LPDDR4__DENALI_PHY_782__PHY_GATE_SMPL1_SLAVE_DELAY_3_SHIFT 0U
  262. #define LPDDR4__DENALI_PHY_782__PHY_GATE_SMPL1_SLAVE_DELAY_3_WIDTH 9U
  263. #define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_3__REG DENALI_PHY_782
  264. #define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_782__PHY_GATE_SMPL1_SLAVE_DELAY_3
  265. #define LPDDR4__DENALI_PHY_782__PHY_LPDDR_3_MASK 0x00010000U
  266. #define LPDDR4__DENALI_PHY_782__PHY_LPDDR_3_SHIFT 16U
  267. #define LPDDR4__DENALI_PHY_782__PHY_LPDDR_3_WIDTH 1U
  268. #define LPDDR4__DENALI_PHY_782__PHY_LPDDR_3_WOCLR 0U
  269. #define LPDDR4__DENALI_PHY_782__PHY_LPDDR_3_WOSET 0U
  270. #define LPDDR4__PHY_LPDDR_3__REG DENALI_PHY_782
  271. #define LPDDR4__PHY_LPDDR_3__FLD LPDDR4__DENALI_PHY_782__PHY_LPDDR_3
  272. #define LPDDR4__DENALI_PHY_782__PHY_MEM_CLASS_3_MASK 0x07000000U
  273. #define LPDDR4__DENALI_PHY_782__PHY_MEM_CLASS_3_SHIFT 24U
  274. #define LPDDR4__DENALI_PHY_782__PHY_MEM_CLASS_3_WIDTH 3U
  275. #define LPDDR4__PHY_MEM_CLASS_3__REG DENALI_PHY_782
  276. #define LPDDR4__PHY_MEM_CLASS_3__FLD LPDDR4__DENALI_PHY_782__PHY_MEM_CLASS_3
  277. #define LPDDR4__DENALI_PHY_783_READ_MASK 0x000301FFU
  278. #define LPDDR4__DENALI_PHY_783_WRITE_MASK 0x000301FFU
  279. #define LPDDR4__DENALI_PHY_783__PHY_GATE_SMPL2_SLAVE_DELAY_3_MASK 0x000001FFU
  280. #define LPDDR4__DENALI_PHY_783__PHY_GATE_SMPL2_SLAVE_DELAY_3_SHIFT 0U
  281. #define LPDDR4__DENALI_PHY_783__PHY_GATE_SMPL2_SLAVE_DELAY_3_WIDTH 9U
  282. #define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_3__REG DENALI_PHY_783
  283. #define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_783__PHY_GATE_SMPL2_SLAVE_DELAY_3
  284. #define LPDDR4__DENALI_PHY_783__ON_FLY_GATE_ADJUST_EN_3_MASK 0x00030000U
  285. #define LPDDR4__DENALI_PHY_783__ON_FLY_GATE_ADJUST_EN_3_SHIFT 16U
  286. #define LPDDR4__DENALI_PHY_783__ON_FLY_GATE_ADJUST_EN_3_WIDTH 2U
  287. #define LPDDR4__ON_FLY_GATE_ADJUST_EN_3__REG DENALI_PHY_783
  288. #define LPDDR4__ON_FLY_GATE_ADJUST_EN_3__FLD LPDDR4__DENALI_PHY_783__ON_FLY_GATE_ADJUST_EN_3
  289. #define LPDDR4__DENALI_PHY_784_READ_MASK 0xFFFFFFFFU
  290. #define LPDDR4__DENALI_PHY_784_WRITE_MASK 0xFFFFFFFFU
  291. #define LPDDR4__DENALI_PHY_784__PHY_GATE_TRACKING_OBS_3_MASK 0xFFFFFFFFU
  292. #define LPDDR4__DENALI_PHY_784__PHY_GATE_TRACKING_OBS_3_SHIFT 0U
  293. #define LPDDR4__DENALI_PHY_784__PHY_GATE_TRACKING_OBS_3_WIDTH 32U
  294. #define LPDDR4__PHY_GATE_TRACKING_OBS_3__REG DENALI_PHY_784
  295. #define LPDDR4__PHY_GATE_TRACKING_OBS_3__FLD LPDDR4__DENALI_PHY_784__PHY_GATE_TRACKING_OBS_3
  296. #define LPDDR4__DENALI_PHY_785_READ_MASK 0x00000301U
  297. #define LPDDR4__DENALI_PHY_785_WRITE_MASK 0x00000301U
  298. #define LPDDR4__DENALI_PHY_785__PHY_DFI40_POLARITY_3_MASK 0x00000001U
  299. #define LPDDR4__DENALI_PHY_785__PHY_DFI40_POLARITY_3_SHIFT 0U
  300. #define LPDDR4__DENALI_PHY_785__PHY_DFI40_POLARITY_3_WIDTH 1U
  301. #define LPDDR4__DENALI_PHY_785__PHY_DFI40_POLARITY_3_WOCLR 0U
  302. #define LPDDR4__DENALI_PHY_785__PHY_DFI40_POLARITY_3_WOSET 0U
  303. #define LPDDR4__PHY_DFI40_POLARITY_3__REG DENALI_PHY_785
  304. #define LPDDR4__PHY_DFI40_POLARITY_3__FLD LPDDR4__DENALI_PHY_785__PHY_DFI40_POLARITY_3
  305. #define LPDDR4__DENALI_PHY_785__PHY_LP4_PST_AMBLE_3_MASK 0x00000300U
  306. #define LPDDR4__DENALI_PHY_785__PHY_LP4_PST_AMBLE_3_SHIFT 8U
  307. #define LPDDR4__DENALI_PHY_785__PHY_LP4_PST_AMBLE_3_WIDTH 2U
  308. #define LPDDR4__PHY_LP4_PST_AMBLE_3__REG DENALI_PHY_785
  309. #define LPDDR4__PHY_LP4_PST_AMBLE_3__FLD LPDDR4__DENALI_PHY_785__PHY_LP4_PST_AMBLE_3
  310. #define LPDDR4__DENALI_PHY_786_READ_MASK 0xFFFFFFFFU
  311. #define LPDDR4__DENALI_PHY_786_WRITE_MASK 0xFFFFFFFFU
  312. #define LPDDR4__DENALI_PHY_786__PHY_RDLVL_PATT8_3_MASK 0xFFFFFFFFU
  313. #define LPDDR4__DENALI_PHY_786__PHY_RDLVL_PATT8_3_SHIFT 0U
  314. #define LPDDR4__DENALI_PHY_786__PHY_RDLVL_PATT8_3_WIDTH 32U
  315. #define LPDDR4__PHY_RDLVL_PATT8_3__REG DENALI_PHY_786
  316. #define LPDDR4__PHY_RDLVL_PATT8_3__FLD LPDDR4__DENALI_PHY_786__PHY_RDLVL_PATT8_3
  317. #define LPDDR4__DENALI_PHY_787_READ_MASK 0xFFFFFFFFU
  318. #define LPDDR4__DENALI_PHY_787_WRITE_MASK 0xFFFFFFFFU
  319. #define LPDDR4__DENALI_PHY_787__PHY_RDLVL_PATT9_3_MASK 0xFFFFFFFFU
  320. #define LPDDR4__DENALI_PHY_787__PHY_RDLVL_PATT9_3_SHIFT 0U
  321. #define LPDDR4__DENALI_PHY_787__PHY_RDLVL_PATT9_3_WIDTH 32U
  322. #define LPDDR4__PHY_RDLVL_PATT9_3__REG DENALI_PHY_787
  323. #define LPDDR4__PHY_RDLVL_PATT9_3__FLD LPDDR4__DENALI_PHY_787__PHY_RDLVL_PATT9_3
  324. #define LPDDR4__DENALI_PHY_788_READ_MASK 0xFFFFFFFFU
  325. #define LPDDR4__DENALI_PHY_788_WRITE_MASK 0xFFFFFFFFU
  326. #define LPDDR4__DENALI_PHY_788__PHY_RDLVL_PATT10_3_MASK 0xFFFFFFFFU
  327. #define LPDDR4__DENALI_PHY_788__PHY_RDLVL_PATT10_3_SHIFT 0U
  328. #define LPDDR4__DENALI_PHY_788__PHY_RDLVL_PATT10_3_WIDTH 32U
  329. #define LPDDR4__PHY_RDLVL_PATT10_3__REG DENALI_PHY_788
  330. #define LPDDR4__PHY_RDLVL_PATT10_3__FLD LPDDR4__DENALI_PHY_788__PHY_RDLVL_PATT10_3
  331. #define LPDDR4__DENALI_PHY_789_READ_MASK 0xFFFFFFFFU
  332. #define LPDDR4__DENALI_PHY_789_WRITE_MASK 0xFFFFFFFFU
  333. #define LPDDR4__DENALI_PHY_789__PHY_RDLVL_PATT11_3_MASK 0xFFFFFFFFU
  334. #define LPDDR4__DENALI_PHY_789__PHY_RDLVL_PATT11_3_SHIFT 0U
  335. #define LPDDR4__DENALI_PHY_789__PHY_RDLVL_PATT11_3_WIDTH 32U
  336. #define LPDDR4__PHY_RDLVL_PATT11_3__REG DENALI_PHY_789
  337. #define LPDDR4__PHY_RDLVL_PATT11_3__FLD LPDDR4__DENALI_PHY_789__PHY_RDLVL_PATT11_3
  338. #define LPDDR4__DENALI_PHY_790_READ_MASK 0xFFFFFFFFU
  339. #define LPDDR4__DENALI_PHY_790_WRITE_MASK 0xFFFFFFFFU
  340. #define LPDDR4__DENALI_PHY_790__PHY_RDLVL_PATT12_3_MASK 0xFFFFFFFFU
  341. #define LPDDR4__DENALI_PHY_790__PHY_RDLVL_PATT12_3_SHIFT 0U
  342. #define LPDDR4__DENALI_PHY_790__PHY_RDLVL_PATT12_3_WIDTH 32U
  343. #define LPDDR4__PHY_RDLVL_PATT12_3__REG DENALI_PHY_790
  344. #define LPDDR4__PHY_RDLVL_PATT12_3__FLD LPDDR4__DENALI_PHY_790__PHY_RDLVL_PATT12_3
  345. #define LPDDR4__DENALI_PHY_791_READ_MASK 0xFFFFFFFFU
  346. #define LPDDR4__DENALI_PHY_791_WRITE_MASK 0xFFFFFFFFU
  347. #define LPDDR4__DENALI_PHY_791__PHY_RDLVL_PATT13_3_MASK 0xFFFFFFFFU
  348. #define LPDDR4__DENALI_PHY_791__PHY_RDLVL_PATT13_3_SHIFT 0U
  349. #define LPDDR4__DENALI_PHY_791__PHY_RDLVL_PATT13_3_WIDTH 32U
  350. #define LPDDR4__PHY_RDLVL_PATT13_3__REG DENALI_PHY_791
  351. #define LPDDR4__PHY_RDLVL_PATT13_3__FLD LPDDR4__DENALI_PHY_791__PHY_RDLVL_PATT13_3
  352. #define LPDDR4__DENALI_PHY_792_READ_MASK 0xFFFFFFFFU
  353. #define LPDDR4__DENALI_PHY_792_WRITE_MASK 0xFFFFFFFFU
  354. #define LPDDR4__DENALI_PHY_792__PHY_RDLVL_PATT14_3_MASK 0xFFFFFFFFU
  355. #define LPDDR4__DENALI_PHY_792__PHY_RDLVL_PATT14_3_SHIFT 0U
  356. #define LPDDR4__DENALI_PHY_792__PHY_RDLVL_PATT14_3_WIDTH 32U
  357. #define LPDDR4__PHY_RDLVL_PATT14_3__REG DENALI_PHY_792
  358. #define LPDDR4__PHY_RDLVL_PATT14_3__FLD LPDDR4__DENALI_PHY_792__PHY_RDLVL_PATT14_3
  359. #define LPDDR4__DENALI_PHY_793_READ_MASK 0xFFFFFFFFU
  360. #define LPDDR4__DENALI_PHY_793_WRITE_MASK 0xFFFFFFFFU
  361. #define LPDDR4__DENALI_PHY_793__PHY_RDLVL_PATT15_3_MASK 0xFFFFFFFFU
  362. #define LPDDR4__DENALI_PHY_793__PHY_RDLVL_PATT15_3_SHIFT 0U
  363. #define LPDDR4__DENALI_PHY_793__PHY_RDLVL_PATT15_3_WIDTH 32U
  364. #define LPDDR4__PHY_RDLVL_PATT15_3__REG DENALI_PHY_793
  365. #define LPDDR4__PHY_RDLVL_PATT15_3__FLD LPDDR4__DENALI_PHY_793__PHY_RDLVL_PATT15_3
  366. #define LPDDR4__DENALI_PHY_794_READ_MASK 0x070F0107U
  367. #define LPDDR4__DENALI_PHY_794_WRITE_MASK 0x070F0107U
  368. #define LPDDR4__DENALI_PHY_794__PHY_SLAVE_LOOP_CNT_UPDATE_3_MASK 0x00000007U
  369. #define LPDDR4__DENALI_PHY_794__PHY_SLAVE_LOOP_CNT_UPDATE_3_SHIFT 0U
  370. #define LPDDR4__DENALI_PHY_794__PHY_SLAVE_LOOP_CNT_UPDATE_3_WIDTH 3U
  371. #define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_3__REG DENALI_PHY_794
  372. #define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_3__FLD LPDDR4__DENALI_PHY_794__PHY_SLAVE_LOOP_CNT_UPDATE_3
  373. #define LPDDR4__DENALI_PHY_794__PHY_SW_FIFO_PTR_RST_DISABLE_3_MASK 0x00000100U
  374. #define LPDDR4__DENALI_PHY_794__PHY_SW_FIFO_PTR_RST_DISABLE_3_SHIFT 8U
  375. #define LPDDR4__DENALI_PHY_794__PHY_SW_FIFO_PTR_RST_DISABLE_3_WIDTH 1U
  376. #define LPDDR4__DENALI_PHY_794__PHY_SW_FIFO_PTR_RST_DISABLE_3_WOCLR 0U
  377. #define LPDDR4__DENALI_PHY_794__PHY_SW_FIFO_PTR_RST_DISABLE_3_WOSET 0U
  378. #define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_3__REG DENALI_PHY_794
  379. #define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_3__FLD LPDDR4__DENALI_PHY_794__PHY_SW_FIFO_PTR_RST_DISABLE_3
  380. #define LPDDR4__DENALI_PHY_794__PHY_MASTER_DLY_LOCK_OBS_SELECT_3_MASK 0x000F0000U
  381. #define LPDDR4__DENALI_PHY_794__PHY_MASTER_DLY_LOCK_OBS_SELECT_3_SHIFT 16U
  382. #define LPDDR4__DENALI_PHY_794__PHY_MASTER_DLY_LOCK_OBS_SELECT_3_WIDTH 4U
  383. #define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_3__REG DENALI_PHY_794
  384. #define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_794__PHY_MASTER_DLY_LOCK_OBS_SELECT_3
  385. #define LPDDR4__DENALI_PHY_794__PHY_RDDQ_ENC_OBS_SELECT_3_MASK 0x07000000U
  386. #define LPDDR4__DENALI_PHY_794__PHY_RDDQ_ENC_OBS_SELECT_3_SHIFT 24U
  387. #define LPDDR4__DENALI_PHY_794__PHY_RDDQ_ENC_OBS_SELECT_3_WIDTH 3U
  388. #define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_3__REG DENALI_PHY_794
  389. #define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_794__PHY_RDDQ_ENC_OBS_SELECT_3
  390. #define LPDDR4__DENALI_PHY_795_READ_MASK 0x0F0F0F0FU
  391. #define LPDDR4__DENALI_PHY_795_WRITE_MASK 0x0F0F0F0FU
  392. #define LPDDR4__DENALI_PHY_795__PHY_RDDQS_DQ_ENC_OBS_SELECT_3_MASK 0x0000000FU
  393. #define LPDDR4__DENALI_PHY_795__PHY_RDDQS_DQ_ENC_OBS_SELECT_3_SHIFT 0U
  394. #define LPDDR4__DENALI_PHY_795__PHY_RDDQS_DQ_ENC_OBS_SELECT_3_WIDTH 4U
  395. #define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_3__REG DENALI_PHY_795
  396. #define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_795__PHY_RDDQS_DQ_ENC_OBS_SELECT_3
  397. #define LPDDR4__DENALI_PHY_795__PHY_WR_ENC_OBS_SELECT_3_MASK 0x00000F00U
  398. #define LPDDR4__DENALI_PHY_795__PHY_WR_ENC_OBS_SELECT_3_SHIFT 8U
  399. #define LPDDR4__DENALI_PHY_795__PHY_WR_ENC_OBS_SELECT_3_WIDTH 4U
  400. #define LPDDR4__PHY_WR_ENC_OBS_SELECT_3__REG DENALI_PHY_795
  401. #define LPDDR4__PHY_WR_ENC_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_795__PHY_WR_ENC_OBS_SELECT_3
  402. #define LPDDR4__DENALI_PHY_795__PHY_WR_SHIFT_OBS_SELECT_3_MASK 0x000F0000U
  403. #define LPDDR4__DENALI_PHY_795__PHY_WR_SHIFT_OBS_SELECT_3_SHIFT 16U
  404. #define LPDDR4__DENALI_PHY_795__PHY_WR_SHIFT_OBS_SELECT_3_WIDTH 4U
  405. #define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_3__REG DENALI_PHY_795
  406. #define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_795__PHY_WR_SHIFT_OBS_SELECT_3
  407. #define LPDDR4__DENALI_PHY_795__PHY_FIFO_PTR_OBS_SELECT_3_MASK 0x0F000000U
  408. #define LPDDR4__DENALI_PHY_795__PHY_FIFO_PTR_OBS_SELECT_3_SHIFT 24U
  409. #define LPDDR4__DENALI_PHY_795__PHY_FIFO_PTR_OBS_SELECT_3_WIDTH 4U
  410. #define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_3__REG DENALI_PHY_795
  411. #define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_795__PHY_FIFO_PTR_OBS_SELECT_3
  412. #define LPDDR4__DENALI_PHY_796_READ_MASK 0xFF030001U
  413. #define LPDDR4__DENALI_PHY_796_WRITE_MASK 0xFF030001U
  414. #define LPDDR4__DENALI_PHY_796__PHY_LVL_DEBUG_MODE_3_MASK 0x00000001U
  415. #define LPDDR4__DENALI_PHY_796__PHY_LVL_DEBUG_MODE_3_SHIFT 0U
  416. #define LPDDR4__DENALI_PHY_796__PHY_LVL_DEBUG_MODE_3_WIDTH 1U
  417. #define LPDDR4__DENALI_PHY_796__PHY_LVL_DEBUG_MODE_3_WOCLR 0U
  418. #define LPDDR4__DENALI_PHY_796__PHY_LVL_DEBUG_MODE_3_WOSET 0U
  419. #define LPDDR4__PHY_LVL_DEBUG_MODE_3__REG DENALI_PHY_796
  420. #define LPDDR4__PHY_LVL_DEBUG_MODE_3__FLD LPDDR4__DENALI_PHY_796__PHY_LVL_DEBUG_MODE_3
  421. #define LPDDR4__DENALI_PHY_796__SC_PHY_LVL_DEBUG_CONT_3_MASK 0x00000100U
  422. #define LPDDR4__DENALI_PHY_796__SC_PHY_LVL_DEBUG_CONT_3_SHIFT 8U
  423. #define LPDDR4__DENALI_PHY_796__SC_PHY_LVL_DEBUG_CONT_3_WIDTH 1U
  424. #define LPDDR4__DENALI_PHY_796__SC_PHY_LVL_DEBUG_CONT_3_WOCLR 0U
  425. #define LPDDR4__DENALI_PHY_796__SC_PHY_LVL_DEBUG_CONT_3_WOSET 0U
  426. #define LPDDR4__SC_PHY_LVL_DEBUG_CONT_3__REG DENALI_PHY_796
  427. #define LPDDR4__SC_PHY_LVL_DEBUG_CONT_3__FLD LPDDR4__DENALI_PHY_796__SC_PHY_LVL_DEBUG_CONT_3
  428. #define LPDDR4__DENALI_PHY_796__PHY_WRLVL_ALGO_3_MASK 0x00030000U
  429. #define LPDDR4__DENALI_PHY_796__PHY_WRLVL_ALGO_3_SHIFT 16U
  430. #define LPDDR4__DENALI_PHY_796__PHY_WRLVL_ALGO_3_WIDTH 2U
  431. #define LPDDR4__PHY_WRLVL_ALGO_3__REG DENALI_PHY_796
  432. #define LPDDR4__PHY_WRLVL_ALGO_3__FLD LPDDR4__DENALI_PHY_796__PHY_WRLVL_ALGO_3
  433. #define LPDDR4__DENALI_PHY_796__PHY_WRLVL_PER_START_3_MASK 0xFF000000U
  434. #define LPDDR4__DENALI_PHY_796__PHY_WRLVL_PER_START_3_SHIFT 24U
  435. #define LPDDR4__DENALI_PHY_796__PHY_WRLVL_PER_START_3_WIDTH 8U
  436. #define LPDDR4__PHY_WRLVL_PER_START_3__REG DENALI_PHY_796
  437. #define LPDDR4__PHY_WRLVL_PER_START_3__FLD LPDDR4__DENALI_PHY_796__PHY_WRLVL_PER_START_3
  438. #define LPDDR4__DENALI_PHY_797_READ_MASK 0x00FF0F3FU
  439. #define LPDDR4__DENALI_PHY_797_WRITE_MASK 0x00FF0F3FU
  440. #define LPDDR4__DENALI_PHY_797__PHY_WRLVL_CAPTURE_CNT_3_MASK 0x0000003FU
  441. #define LPDDR4__DENALI_PHY_797__PHY_WRLVL_CAPTURE_CNT_3_SHIFT 0U
  442. #define LPDDR4__DENALI_PHY_797__PHY_WRLVL_CAPTURE_CNT_3_WIDTH 6U
  443. #define LPDDR4__PHY_WRLVL_CAPTURE_CNT_3__REG DENALI_PHY_797
  444. #define LPDDR4__PHY_WRLVL_CAPTURE_CNT_3__FLD LPDDR4__DENALI_PHY_797__PHY_WRLVL_CAPTURE_CNT_3
  445. #define LPDDR4__DENALI_PHY_797__PHY_WRLVL_UPDT_WAIT_CNT_3_MASK 0x00000F00U
  446. #define LPDDR4__DENALI_PHY_797__PHY_WRLVL_UPDT_WAIT_CNT_3_SHIFT 8U
  447. #define LPDDR4__DENALI_PHY_797__PHY_WRLVL_UPDT_WAIT_CNT_3_WIDTH 4U
  448. #define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_3__REG DENALI_PHY_797
  449. #define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_797__PHY_WRLVL_UPDT_WAIT_CNT_3
  450. #define LPDDR4__DENALI_PHY_797__PHY_DQ_MASK_3_MASK 0x00FF0000U
  451. #define LPDDR4__DENALI_PHY_797__PHY_DQ_MASK_3_SHIFT 16U
  452. #define LPDDR4__DENALI_PHY_797__PHY_DQ_MASK_3_WIDTH 8U
  453. #define LPDDR4__PHY_DQ_MASK_3__REG DENALI_PHY_797
  454. #define LPDDR4__PHY_DQ_MASK_3__FLD LPDDR4__DENALI_PHY_797__PHY_DQ_MASK_3
  455. #define LPDDR4__DENALI_PHY_798_READ_MASK 0x0F3F03FFU
  456. #define LPDDR4__DENALI_PHY_798_WRITE_MASK 0x0F3F03FFU
  457. #define LPDDR4__DENALI_PHY_798__PHY_GTLVL_PER_START_3_MASK 0x000003FFU
  458. #define LPDDR4__DENALI_PHY_798__PHY_GTLVL_PER_START_3_SHIFT 0U
  459. #define LPDDR4__DENALI_PHY_798__PHY_GTLVL_PER_START_3_WIDTH 10U
  460. #define LPDDR4__PHY_GTLVL_PER_START_3__REG DENALI_PHY_798
  461. #define LPDDR4__PHY_GTLVL_PER_START_3__FLD LPDDR4__DENALI_PHY_798__PHY_GTLVL_PER_START_3
  462. #define LPDDR4__DENALI_PHY_798__PHY_GTLVL_CAPTURE_CNT_3_MASK 0x003F0000U
  463. #define LPDDR4__DENALI_PHY_798__PHY_GTLVL_CAPTURE_CNT_3_SHIFT 16U
  464. #define LPDDR4__DENALI_PHY_798__PHY_GTLVL_CAPTURE_CNT_3_WIDTH 6U
  465. #define LPDDR4__PHY_GTLVL_CAPTURE_CNT_3__REG DENALI_PHY_798
  466. #define LPDDR4__PHY_GTLVL_CAPTURE_CNT_3__FLD LPDDR4__DENALI_PHY_798__PHY_GTLVL_CAPTURE_CNT_3
  467. #define LPDDR4__DENALI_PHY_798__PHY_GTLVL_UPDT_WAIT_CNT_3_MASK 0x0F000000U
  468. #define LPDDR4__DENALI_PHY_798__PHY_GTLVL_UPDT_WAIT_CNT_3_SHIFT 24U
  469. #define LPDDR4__DENALI_PHY_798__PHY_GTLVL_UPDT_WAIT_CNT_3_WIDTH 4U
  470. #define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_3__REG DENALI_PHY_798
  471. #define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_798__PHY_GTLVL_UPDT_WAIT_CNT_3
  472. #define LPDDR4__DENALI_PHY_799_READ_MASK 0x1F030F3FU
  473. #define LPDDR4__DENALI_PHY_799_WRITE_MASK 0x1F030F3FU
  474. #define LPDDR4__DENALI_PHY_799__PHY_RDLVL_CAPTURE_CNT_3_MASK 0x0000003FU
  475. #define LPDDR4__DENALI_PHY_799__PHY_RDLVL_CAPTURE_CNT_3_SHIFT 0U
  476. #define LPDDR4__DENALI_PHY_799__PHY_RDLVL_CAPTURE_CNT_3_WIDTH 6U
  477. #define LPDDR4__PHY_RDLVL_CAPTURE_CNT_3__REG DENALI_PHY_799
  478. #define LPDDR4__PHY_RDLVL_CAPTURE_CNT_3__FLD LPDDR4__DENALI_PHY_799__PHY_RDLVL_CAPTURE_CNT_3
  479. #define LPDDR4__DENALI_PHY_799__PHY_RDLVL_UPDT_WAIT_CNT_3_MASK 0x00000F00U
  480. #define LPDDR4__DENALI_PHY_799__PHY_RDLVL_UPDT_WAIT_CNT_3_SHIFT 8U
  481. #define LPDDR4__DENALI_PHY_799__PHY_RDLVL_UPDT_WAIT_CNT_3_WIDTH 4U
  482. #define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_3__REG DENALI_PHY_799
  483. #define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_799__PHY_RDLVL_UPDT_WAIT_CNT_3
  484. #define LPDDR4__DENALI_PHY_799__PHY_RDLVL_OP_MODE_3_MASK 0x00030000U
  485. #define LPDDR4__DENALI_PHY_799__PHY_RDLVL_OP_MODE_3_SHIFT 16U
  486. #define LPDDR4__DENALI_PHY_799__PHY_RDLVL_OP_MODE_3_WIDTH 2U
  487. #define LPDDR4__PHY_RDLVL_OP_MODE_3__REG DENALI_PHY_799
  488. #define LPDDR4__PHY_RDLVL_OP_MODE_3__FLD LPDDR4__DENALI_PHY_799__PHY_RDLVL_OP_MODE_3
  489. #define LPDDR4__DENALI_PHY_799__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3_MASK 0x1F000000U
  490. #define LPDDR4__DENALI_PHY_799__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3_SHIFT 24U
  491. #define LPDDR4__DENALI_PHY_799__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3_WIDTH 5U
  492. #define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3__REG DENALI_PHY_799
  493. #define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_799__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3
  494. #define LPDDR4__DENALI_PHY_800_READ_MASK 0x3FFFFFFFU
  495. #define LPDDR4__DENALI_PHY_800_WRITE_MASK 0x3FFFFFFFU
  496. #define LPDDR4__DENALI_PHY_800__PHY_RDLVL_PERIODIC_OBS_SELECT_3_MASK 0x000000FFU
  497. #define LPDDR4__DENALI_PHY_800__PHY_RDLVL_PERIODIC_OBS_SELECT_3_SHIFT 0U
  498. #define LPDDR4__DENALI_PHY_800__PHY_RDLVL_PERIODIC_OBS_SELECT_3_WIDTH 8U
  499. #define LPDDR4__PHY_RDLVL_PERIODIC_OBS_SELECT_3__REG DENALI_PHY_800
  500. #define LPDDR4__PHY_RDLVL_PERIODIC_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_800__PHY_RDLVL_PERIODIC_OBS_SELECT_3
  501. #define LPDDR4__DENALI_PHY_800__PHY_RDLVL_DATA_MASK_3_MASK 0x0000FF00U
  502. #define LPDDR4__DENALI_PHY_800__PHY_RDLVL_DATA_MASK_3_SHIFT 8U
  503. #define LPDDR4__DENALI_PHY_800__PHY_RDLVL_DATA_MASK_3_WIDTH 8U
  504. #define LPDDR4__PHY_RDLVL_DATA_MASK_3__REG DENALI_PHY_800
  505. #define LPDDR4__PHY_RDLVL_DATA_MASK_3__FLD LPDDR4__DENALI_PHY_800__PHY_RDLVL_DATA_MASK_3
  506. #define LPDDR4__DENALI_PHY_800__PHY_WDQLVL_CLK_JITTER_TOLERANCE_3_MASK 0x00FF0000U
  507. #define LPDDR4__DENALI_PHY_800__PHY_WDQLVL_CLK_JITTER_TOLERANCE_3_SHIFT 16U
  508. #define LPDDR4__DENALI_PHY_800__PHY_WDQLVL_CLK_JITTER_TOLERANCE_3_WIDTH 8U
  509. #define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_3__REG DENALI_PHY_800
  510. #define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_3__FLD LPDDR4__DENALI_PHY_800__PHY_WDQLVL_CLK_JITTER_TOLERANCE_3
  511. #define LPDDR4__DENALI_PHY_800__PHY_WDQLVL_BURST_CNT_3_MASK 0x3F000000U
  512. #define LPDDR4__DENALI_PHY_800__PHY_WDQLVL_BURST_CNT_3_SHIFT 24U
  513. #define LPDDR4__DENALI_PHY_800__PHY_WDQLVL_BURST_CNT_3_WIDTH 6U
  514. #define LPDDR4__PHY_WDQLVL_BURST_CNT_3__REG DENALI_PHY_800
  515. #define LPDDR4__PHY_WDQLVL_BURST_CNT_3__FLD LPDDR4__DENALI_PHY_800__PHY_WDQLVL_BURST_CNT_3
  516. #define LPDDR4__DENALI_PHY_801_READ_MASK 0x0F07FF07U
  517. #define LPDDR4__DENALI_PHY_801_WRITE_MASK 0x0F07FF07U
  518. #define LPDDR4__DENALI_PHY_801__PHY_WDQLVL_PATT_3_MASK 0x00000007U
  519. #define LPDDR4__DENALI_PHY_801__PHY_WDQLVL_PATT_3_SHIFT 0U
  520. #define LPDDR4__DENALI_PHY_801__PHY_WDQLVL_PATT_3_WIDTH 3U
  521. #define LPDDR4__PHY_WDQLVL_PATT_3__REG DENALI_PHY_801
  522. #define LPDDR4__PHY_WDQLVL_PATT_3__FLD LPDDR4__DENALI_PHY_801__PHY_WDQLVL_PATT_3
  523. #define LPDDR4__DENALI_PHY_801__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3_MASK 0x0007FF00U
  524. #define LPDDR4__DENALI_PHY_801__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3_SHIFT 8U
  525. #define LPDDR4__DENALI_PHY_801__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3_WIDTH 11U
  526. #define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3__REG DENALI_PHY_801
  527. #define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3__FLD LPDDR4__DENALI_PHY_801__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3
  528. #define LPDDR4__DENALI_PHY_801__PHY_WDQLVL_UPDT_WAIT_CNT_3_MASK 0x0F000000U
  529. #define LPDDR4__DENALI_PHY_801__PHY_WDQLVL_UPDT_WAIT_CNT_3_SHIFT 24U
  530. #define LPDDR4__DENALI_PHY_801__PHY_WDQLVL_UPDT_WAIT_CNT_3_WIDTH 4U
  531. #define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_3__REG DENALI_PHY_801
  532. #define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_801__PHY_WDQLVL_UPDT_WAIT_CNT_3
  533. #define LPDDR4__DENALI_PHY_802_READ_MASK 0x0000FF0FU
  534. #define LPDDR4__DENALI_PHY_802_WRITE_MASK 0x0000FF0FU
  535. #define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_DQDM_OBS_SELECT_3_MASK 0x0000000FU
  536. #define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_DQDM_OBS_SELECT_3_SHIFT 0U
  537. #define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_DQDM_OBS_SELECT_3_WIDTH 4U
  538. #define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_3__REG DENALI_PHY_802
  539. #define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_802__PHY_WDQLVL_DQDM_OBS_SELECT_3
  540. #define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_PERIODIC_OBS_SELECT_3_MASK 0x0000FF00U
  541. #define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_PERIODIC_OBS_SELECT_3_SHIFT 8U
  542. #define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_PERIODIC_OBS_SELECT_3_WIDTH 8U
  543. #define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_3__REG DENALI_PHY_802
  544. #define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_802__PHY_WDQLVL_PERIODIC_OBS_SELECT_3
  545. #define LPDDR4__DENALI_PHY_802__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3_MASK 0x00010000U
  546. #define LPDDR4__DENALI_PHY_802__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3_SHIFT 16U
  547. #define LPDDR4__DENALI_PHY_802__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3_WIDTH 1U
  548. #define LPDDR4__DENALI_PHY_802__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3_WOCLR 0U
  549. #define LPDDR4__DENALI_PHY_802__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3_WOSET 0U
  550. #define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3__REG DENALI_PHY_802
  551. #define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3__FLD LPDDR4__DENALI_PHY_802__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3
  552. #define LPDDR4__DENALI_PHY_803_READ_MASK 0x000001FFU
  553. #define LPDDR4__DENALI_PHY_803_WRITE_MASK 0x000001FFU
  554. #define LPDDR4__DENALI_PHY_803__PHY_WDQLVL_DATADM_MASK_3_MASK 0x000001FFU
  555. #define LPDDR4__DENALI_PHY_803__PHY_WDQLVL_DATADM_MASK_3_SHIFT 0U
  556. #define LPDDR4__DENALI_PHY_803__PHY_WDQLVL_DATADM_MASK_3_WIDTH 9U
  557. #define LPDDR4__PHY_WDQLVL_DATADM_MASK_3__REG DENALI_PHY_803
  558. #define LPDDR4__PHY_WDQLVL_DATADM_MASK_3__FLD LPDDR4__DENALI_PHY_803__PHY_WDQLVL_DATADM_MASK_3
  559. #define LPDDR4__DENALI_PHY_804_READ_MASK 0xFFFFFFFFU
  560. #define LPDDR4__DENALI_PHY_804_WRITE_MASK 0xFFFFFFFFU
  561. #define LPDDR4__DENALI_PHY_804__PHY_USER_PATT0_3_MASK 0xFFFFFFFFU
  562. #define LPDDR4__DENALI_PHY_804__PHY_USER_PATT0_3_SHIFT 0U
  563. #define LPDDR4__DENALI_PHY_804__PHY_USER_PATT0_3_WIDTH 32U
  564. #define LPDDR4__PHY_USER_PATT0_3__REG DENALI_PHY_804
  565. #define LPDDR4__PHY_USER_PATT0_3__FLD LPDDR4__DENALI_PHY_804__PHY_USER_PATT0_3
  566. #define LPDDR4__DENALI_PHY_805_READ_MASK 0xFFFFFFFFU
  567. #define LPDDR4__DENALI_PHY_805_WRITE_MASK 0xFFFFFFFFU
  568. #define LPDDR4__DENALI_PHY_805__PHY_USER_PATT1_3_MASK 0xFFFFFFFFU
  569. #define LPDDR4__DENALI_PHY_805__PHY_USER_PATT1_3_SHIFT 0U
  570. #define LPDDR4__DENALI_PHY_805__PHY_USER_PATT1_3_WIDTH 32U
  571. #define LPDDR4__PHY_USER_PATT1_3__REG DENALI_PHY_805
  572. #define LPDDR4__PHY_USER_PATT1_3__FLD LPDDR4__DENALI_PHY_805__PHY_USER_PATT1_3
  573. #define LPDDR4__DENALI_PHY_806_READ_MASK 0xFFFFFFFFU
  574. #define LPDDR4__DENALI_PHY_806_WRITE_MASK 0xFFFFFFFFU
  575. #define LPDDR4__DENALI_PHY_806__PHY_USER_PATT2_3_MASK 0xFFFFFFFFU
  576. #define LPDDR4__DENALI_PHY_806__PHY_USER_PATT2_3_SHIFT 0U
  577. #define LPDDR4__DENALI_PHY_806__PHY_USER_PATT2_3_WIDTH 32U
  578. #define LPDDR4__PHY_USER_PATT2_3__REG DENALI_PHY_806
  579. #define LPDDR4__PHY_USER_PATT2_3__FLD LPDDR4__DENALI_PHY_806__PHY_USER_PATT2_3
  580. #define LPDDR4__DENALI_PHY_807_READ_MASK 0xFFFFFFFFU
  581. #define LPDDR4__DENALI_PHY_807_WRITE_MASK 0xFFFFFFFFU
  582. #define LPDDR4__DENALI_PHY_807__PHY_USER_PATT3_3_MASK 0xFFFFFFFFU
  583. #define LPDDR4__DENALI_PHY_807__PHY_USER_PATT3_3_SHIFT 0U
  584. #define LPDDR4__DENALI_PHY_807__PHY_USER_PATT3_3_WIDTH 32U
  585. #define LPDDR4__PHY_USER_PATT3_3__REG DENALI_PHY_807
  586. #define LPDDR4__PHY_USER_PATT3_3__FLD LPDDR4__DENALI_PHY_807__PHY_USER_PATT3_3
  587. #define LPDDR4__DENALI_PHY_808_READ_MASK 0x0001FFFFU
  588. #define LPDDR4__DENALI_PHY_808_WRITE_MASK 0x0001FFFFU
  589. #define LPDDR4__DENALI_PHY_808__PHY_USER_PATT4_3_MASK 0x0000FFFFU
  590. #define LPDDR4__DENALI_PHY_808__PHY_USER_PATT4_3_SHIFT 0U
  591. #define LPDDR4__DENALI_PHY_808__PHY_USER_PATT4_3_WIDTH 16U
  592. #define LPDDR4__PHY_USER_PATT4_3__REG DENALI_PHY_808
  593. #define LPDDR4__PHY_USER_PATT4_3__FLD LPDDR4__DENALI_PHY_808__PHY_USER_PATT4_3
  594. #define LPDDR4__DENALI_PHY_808__PHY_NTP_MULT_TRAIN_3_MASK 0x00010000U
  595. #define LPDDR4__DENALI_PHY_808__PHY_NTP_MULT_TRAIN_3_SHIFT 16U
  596. #define LPDDR4__DENALI_PHY_808__PHY_NTP_MULT_TRAIN_3_WIDTH 1U
  597. #define LPDDR4__DENALI_PHY_808__PHY_NTP_MULT_TRAIN_3_WOCLR 0U
  598. #define LPDDR4__DENALI_PHY_808__PHY_NTP_MULT_TRAIN_3_WOSET 0U
  599. #define LPDDR4__PHY_NTP_MULT_TRAIN_3__REG DENALI_PHY_808
  600. #define LPDDR4__PHY_NTP_MULT_TRAIN_3__FLD LPDDR4__DENALI_PHY_808__PHY_NTP_MULT_TRAIN_3
  601. #define LPDDR4__DENALI_PHY_809_READ_MASK 0x03FF03FFU
  602. #define LPDDR4__DENALI_PHY_809_WRITE_MASK 0x03FF03FFU
  603. #define LPDDR4__DENALI_PHY_809__PHY_NTP_EARLY_THRESHOLD_3_MASK 0x000003FFU
  604. #define LPDDR4__DENALI_PHY_809__PHY_NTP_EARLY_THRESHOLD_3_SHIFT 0U
  605. #define LPDDR4__DENALI_PHY_809__PHY_NTP_EARLY_THRESHOLD_3_WIDTH 10U
  606. #define LPDDR4__PHY_NTP_EARLY_THRESHOLD_3__REG DENALI_PHY_809
  607. #define LPDDR4__PHY_NTP_EARLY_THRESHOLD_3__FLD LPDDR4__DENALI_PHY_809__PHY_NTP_EARLY_THRESHOLD_3
  608. #define LPDDR4__DENALI_PHY_809__PHY_NTP_PERIOD_THRESHOLD_3_MASK 0x03FF0000U
  609. #define LPDDR4__DENALI_PHY_809__PHY_NTP_PERIOD_THRESHOLD_3_SHIFT 16U
  610. #define LPDDR4__DENALI_PHY_809__PHY_NTP_PERIOD_THRESHOLD_3_WIDTH 10U
  611. #define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_3__REG DENALI_PHY_809
  612. #define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_3__FLD LPDDR4__DENALI_PHY_809__PHY_NTP_PERIOD_THRESHOLD_3
  613. #define LPDDR4__DENALI_PHY_810_READ_MASK 0x03FF03FFU
  614. #define LPDDR4__DENALI_PHY_810_WRITE_MASK 0x03FF03FFU
  615. #define LPDDR4__DENALI_PHY_810__PHY_NTP_PERIOD_THRESHOLD_MIN_3_MASK 0x000003FFU
  616. #define LPDDR4__DENALI_PHY_810__PHY_NTP_PERIOD_THRESHOLD_MIN_3_SHIFT 0U
  617. #define LPDDR4__DENALI_PHY_810__PHY_NTP_PERIOD_THRESHOLD_MIN_3_WIDTH 10U
  618. #define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_3__REG DENALI_PHY_810
  619. #define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_3__FLD LPDDR4__DENALI_PHY_810__PHY_NTP_PERIOD_THRESHOLD_MIN_3
  620. #define LPDDR4__DENALI_PHY_810__PHY_NTP_PERIOD_THRESHOLD_MAX_3_MASK 0x03FF0000U
  621. #define LPDDR4__DENALI_PHY_810__PHY_NTP_PERIOD_THRESHOLD_MAX_3_SHIFT 16U
  622. #define LPDDR4__DENALI_PHY_810__PHY_NTP_PERIOD_THRESHOLD_MAX_3_WIDTH 10U
  623. #define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_3__REG DENALI_PHY_810
  624. #define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_3__FLD LPDDR4__DENALI_PHY_810__PHY_NTP_PERIOD_THRESHOLD_MAX_3
  625. #define LPDDR4__DENALI_PHY_811_READ_MASK 0x00FF0001U
  626. #define LPDDR4__DENALI_PHY_811_WRITE_MASK 0x00FF0001U
  627. #define LPDDR4__DENALI_PHY_811__PHY_CALVL_VREF_DRIVING_SLICE_3_MASK 0x00000001U
  628. #define LPDDR4__DENALI_PHY_811__PHY_CALVL_VREF_DRIVING_SLICE_3_SHIFT 0U
  629. #define LPDDR4__DENALI_PHY_811__PHY_CALVL_VREF_DRIVING_SLICE_3_WIDTH 1U
  630. #define LPDDR4__DENALI_PHY_811__PHY_CALVL_VREF_DRIVING_SLICE_3_WOCLR 0U
  631. #define LPDDR4__DENALI_PHY_811__PHY_CALVL_VREF_DRIVING_SLICE_3_WOSET 0U
  632. #define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_3__REG DENALI_PHY_811
  633. #define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_3__FLD LPDDR4__DENALI_PHY_811__PHY_CALVL_VREF_DRIVING_SLICE_3
  634. #define LPDDR4__DENALI_PHY_811__SC_PHY_MANUAL_CLEAR_3_MASK 0x00003F00U
  635. #define LPDDR4__DENALI_PHY_811__SC_PHY_MANUAL_CLEAR_3_SHIFT 8U
  636. #define LPDDR4__DENALI_PHY_811__SC_PHY_MANUAL_CLEAR_3_WIDTH 6U
  637. #define LPDDR4__SC_PHY_MANUAL_CLEAR_3__REG DENALI_PHY_811
  638. #define LPDDR4__SC_PHY_MANUAL_CLEAR_3__FLD LPDDR4__DENALI_PHY_811__SC_PHY_MANUAL_CLEAR_3
  639. #define LPDDR4__DENALI_PHY_811__PHY_FIFO_PTR_OBS_3_MASK 0x00FF0000U
  640. #define LPDDR4__DENALI_PHY_811__PHY_FIFO_PTR_OBS_3_SHIFT 16U
  641. #define LPDDR4__DENALI_PHY_811__PHY_FIFO_PTR_OBS_3_WIDTH 8U
  642. #define LPDDR4__PHY_FIFO_PTR_OBS_3__REG DENALI_PHY_811
  643. #define LPDDR4__PHY_FIFO_PTR_OBS_3__FLD LPDDR4__DENALI_PHY_811__PHY_FIFO_PTR_OBS_3
  644. #define LPDDR4__DENALI_PHY_812_READ_MASK 0xFFFFFFFFU
  645. #define LPDDR4__DENALI_PHY_812_WRITE_MASK 0xFFFFFFFFU
  646. #define LPDDR4__DENALI_PHY_812__PHY_LPBK_RESULT_OBS_3_MASK 0xFFFFFFFFU
  647. #define LPDDR4__DENALI_PHY_812__PHY_LPBK_RESULT_OBS_3_SHIFT 0U
  648. #define LPDDR4__DENALI_PHY_812__PHY_LPBK_RESULT_OBS_3_WIDTH 32U
  649. #define LPDDR4__PHY_LPBK_RESULT_OBS_3__REG DENALI_PHY_812
  650. #define LPDDR4__PHY_LPBK_RESULT_OBS_3__FLD LPDDR4__DENALI_PHY_812__PHY_LPBK_RESULT_OBS_3
  651. #define LPDDR4__DENALI_PHY_813_READ_MASK 0x07FFFFFFU
  652. #define LPDDR4__DENALI_PHY_813_WRITE_MASK 0x07FFFFFFU
  653. #define LPDDR4__DENALI_PHY_813__PHY_LPBK_ERROR_COUNT_OBS_3_MASK 0x0000FFFFU
  654. #define LPDDR4__DENALI_PHY_813__PHY_LPBK_ERROR_COUNT_OBS_3_SHIFT 0U
  655. #define LPDDR4__DENALI_PHY_813__PHY_LPBK_ERROR_COUNT_OBS_3_WIDTH 16U
  656. #define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_3__REG DENALI_PHY_813
  657. #define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_3__FLD LPDDR4__DENALI_PHY_813__PHY_LPBK_ERROR_COUNT_OBS_3
  658. #define LPDDR4__DENALI_PHY_813__PHY_MASTER_DLY_LOCK_OBS_3_MASK 0x07FF0000U
  659. #define LPDDR4__DENALI_PHY_813__PHY_MASTER_DLY_LOCK_OBS_3_SHIFT 16U
  660. #define LPDDR4__DENALI_PHY_813__PHY_MASTER_DLY_LOCK_OBS_3_WIDTH 11U
  661. #define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_3__REG DENALI_PHY_813
  662. #define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_3__FLD LPDDR4__DENALI_PHY_813__PHY_MASTER_DLY_LOCK_OBS_3
  663. #define LPDDR4__DENALI_PHY_814_READ_MASK 0xFFFF7F7FU
  664. #define LPDDR4__DENALI_PHY_814_WRITE_MASK 0xFFFF7F7FU
  665. #define LPDDR4__DENALI_PHY_814__PHY_RDDQ_SLV_DLY_ENC_OBS_3_MASK 0x0000007FU
  666. #define LPDDR4__DENALI_PHY_814__PHY_RDDQ_SLV_DLY_ENC_OBS_3_SHIFT 0U
  667. #define LPDDR4__DENALI_PHY_814__PHY_RDDQ_SLV_DLY_ENC_OBS_3_WIDTH 7U
  668. #define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_814
  669. #define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_814__PHY_RDDQ_SLV_DLY_ENC_OBS_3
  670. #define LPDDR4__DENALI_PHY_814__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3_MASK 0x00007F00U
  671. #define LPDDR4__DENALI_PHY_814__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3_SHIFT 8U
  672. #define LPDDR4__DENALI_PHY_814__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3_WIDTH 7U
  673. #define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_814
  674. #define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_814__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3
  675. #define LPDDR4__DENALI_PHY_814__PHY_MEAS_DLY_STEP_VALUE_3_MASK 0x00FF0000U
  676. #define LPDDR4__DENALI_PHY_814__PHY_MEAS_DLY_STEP_VALUE_3_SHIFT 16U
  677. #define LPDDR4__DENALI_PHY_814__PHY_MEAS_DLY_STEP_VALUE_3_WIDTH 8U
  678. #define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_3__REG DENALI_PHY_814
  679. #define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_3__FLD LPDDR4__DENALI_PHY_814__PHY_MEAS_DLY_STEP_VALUE_3
  680. #define LPDDR4__DENALI_PHY_814__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3_MASK 0xFF000000U
  681. #define LPDDR4__DENALI_PHY_814__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3_SHIFT 24U
  682. #define LPDDR4__DENALI_PHY_814__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3_WIDTH 8U
  683. #define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_814
  684. #define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_814__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3
  685. #define LPDDR4__DENALI_PHY_815_READ_MASK 0x7F07FFFFU
  686. #define LPDDR4__DENALI_PHY_815_WRITE_MASK 0x7F07FFFFU
  687. #define LPDDR4__DENALI_PHY_815__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3_MASK 0x000000FFU
  688. #define LPDDR4__DENALI_PHY_815__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3_SHIFT 0U
  689. #define LPDDR4__DENALI_PHY_815__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3_WIDTH 8U
  690. #define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_815
  691. #define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_815__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3
  692. #define LPDDR4__DENALI_PHY_815__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3_MASK 0x0007FF00U
  693. #define LPDDR4__DENALI_PHY_815__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3_SHIFT 8U
  694. #define LPDDR4__DENALI_PHY_815__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3_WIDTH 11U
  695. #define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_815
  696. #define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_815__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3
  697. #define LPDDR4__DENALI_PHY_815__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3_MASK 0x7F000000U
  698. #define LPDDR4__DENALI_PHY_815__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3_SHIFT 24U
  699. #define LPDDR4__DENALI_PHY_815__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3_WIDTH 7U
  700. #define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_815
  701. #define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_815__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3
  702. #define LPDDR4__DENALI_PHY_816_READ_MASK 0x0007FFFFU
  703. #define LPDDR4__DENALI_PHY_816_WRITE_MASK 0x0007FFFFU
  704. #define LPDDR4__DENALI_PHY_816__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3_MASK 0x000000FFU
  705. #define LPDDR4__DENALI_PHY_816__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3_SHIFT 0U
  706. #define LPDDR4__DENALI_PHY_816__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3_WIDTH 8U
  707. #define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_816
  708. #define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_816__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3
  709. #define LPDDR4__DENALI_PHY_816__PHY_WR_ADDER_SLV_DLY_ENC_OBS_3_MASK 0x0000FF00U
  710. #define LPDDR4__DENALI_PHY_816__PHY_WR_ADDER_SLV_DLY_ENC_OBS_3_SHIFT 8U
  711. #define LPDDR4__DENALI_PHY_816__PHY_WR_ADDER_SLV_DLY_ENC_OBS_3_WIDTH 8U
  712. #define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_816
  713. #define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_816__PHY_WR_ADDER_SLV_DLY_ENC_OBS_3
  714. #define LPDDR4__DENALI_PHY_816__PHY_WR_SHIFT_OBS_3_MASK 0x00070000U
  715. #define LPDDR4__DENALI_PHY_816__PHY_WR_SHIFT_OBS_3_SHIFT 16U
  716. #define LPDDR4__DENALI_PHY_816__PHY_WR_SHIFT_OBS_3_WIDTH 3U
  717. #define LPDDR4__PHY_WR_SHIFT_OBS_3__REG DENALI_PHY_816
  718. #define LPDDR4__PHY_WR_SHIFT_OBS_3__FLD LPDDR4__DENALI_PHY_816__PHY_WR_SHIFT_OBS_3
  719. #define LPDDR4__DENALI_PHY_817_READ_MASK 0x03FF03FFU
  720. #define LPDDR4__DENALI_PHY_817_WRITE_MASK 0x03FF03FFU
  721. #define LPDDR4__DENALI_PHY_817__PHY_WRLVL_HARD0_DELAY_OBS_3_MASK 0x000003FFU
  722. #define LPDDR4__DENALI_PHY_817__PHY_WRLVL_HARD0_DELAY_OBS_3_SHIFT 0U
  723. #define LPDDR4__DENALI_PHY_817__PHY_WRLVL_HARD0_DELAY_OBS_3_WIDTH 10U
  724. #define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_3__REG DENALI_PHY_817
  725. #define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_3__FLD LPDDR4__DENALI_PHY_817__PHY_WRLVL_HARD0_DELAY_OBS_3
  726. #define LPDDR4__DENALI_PHY_817__PHY_WRLVL_HARD1_DELAY_OBS_3_MASK 0x03FF0000U
  727. #define LPDDR4__DENALI_PHY_817__PHY_WRLVL_HARD1_DELAY_OBS_3_SHIFT 16U
  728. #define LPDDR4__DENALI_PHY_817__PHY_WRLVL_HARD1_DELAY_OBS_3_WIDTH 10U
  729. #define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_3__REG DENALI_PHY_817
  730. #define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_3__FLD LPDDR4__DENALI_PHY_817__PHY_WRLVL_HARD1_DELAY_OBS_3
  731. #define LPDDR4__DENALI_PHY_818_READ_MASK 0x0001FFFFU
  732. #define LPDDR4__DENALI_PHY_818_WRITE_MASK 0x0001FFFFU
  733. #define LPDDR4__DENALI_PHY_818__PHY_WRLVL_STATUS_OBS_3_MASK 0x0001FFFFU
  734. #define LPDDR4__DENALI_PHY_818__PHY_WRLVL_STATUS_OBS_3_SHIFT 0U
  735. #define LPDDR4__DENALI_PHY_818__PHY_WRLVL_STATUS_OBS_3_WIDTH 17U
  736. #define LPDDR4__PHY_WRLVL_STATUS_OBS_3__REG DENALI_PHY_818
  737. #define LPDDR4__PHY_WRLVL_STATUS_OBS_3__FLD LPDDR4__DENALI_PHY_818__PHY_WRLVL_STATUS_OBS_3
  738. #define LPDDR4__DENALI_PHY_819_READ_MASK 0x03FF03FFU
  739. #define LPDDR4__DENALI_PHY_819_WRITE_MASK 0x03FF03FFU
  740. #define LPDDR4__DENALI_PHY_819__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3_MASK 0x000003FFU
  741. #define LPDDR4__DENALI_PHY_819__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3_SHIFT 0U
  742. #define LPDDR4__DENALI_PHY_819__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3_WIDTH 10U
  743. #define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_819
  744. #define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_819__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3
  745. #define LPDDR4__DENALI_PHY_819__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3_MASK 0x03FF0000U
  746. #define LPDDR4__DENALI_PHY_819__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3_SHIFT 16U
  747. #define LPDDR4__DENALI_PHY_819__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3_WIDTH 10U
  748. #define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_819
  749. #define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_819__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3
  750. #define LPDDR4__DENALI_PHY_820_READ_MASK 0x3FFFFFFFU
  751. #define LPDDR4__DENALI_PHY_820_WRITE_MASK 0x3FFFFFFFU
  752. #define LPDDR4__DENALI_PHY_820__PHY_WRLVL_ERROR_OBS_3_MASK 0x0000FFFFU
  753. #define LPDDR4__DENALI_PHY_820__PHY_WRLVL_ERROR_OBS_3_SHIFT 0U
  754. #define LPDDR4__DENALI_PHY_820__PHY_WRLVL_ERROR_OBS_3_WIDTH 16U
  755. #define LPDDR4__PHY_WRLVL_ERROR_OBS_3__REG DENALI_PHY_820
  756. #define LPDDR4__PHY_WRLVL_ERROR_OBS_3__FLD LPDDR4__DENALI_PHY_820__PHY_WRLVL_ERROR_OBS_3
  757. #define LPDDR4__DENALI_PHY_820__PHY_GTLVL_HARD0_DELAY_OBS_3_MASK 0x3FFF0000U
  758. #define LPDDR4__DENALI_PHY_820__PHY_GTLVL_HARD0_DELAY_OBS_3_SHIFT 16U
  759. #define LPDDR4__DENALI_PHY_820__PHY_GTLVL_HARD0_DELAY_OBS_3_WIDTH 14U
  760. #define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_3__REG DENALI_PHY_820
  761. #define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_3__FLD LPDDR4__DENALI_PHY_820__PHY_GTLVL_HARD0_DELAY_OBS_3
  762. #define LPDDR4__DENALI_PHY_821_READ_MASK 0x00003FFFU
  763. #define LPDDR4__DENALI_PHY_821_WRITE_MASK 0x00003FFFU
  764. #define LPDDR4__DENALI_PHY_821__PHY_GTLVL_HARD1_DELAY_OBS_3_MASK 0x00003FFFU
  765. #define LPDDR4__DENALI_PHY_821__PHY_GTLVL_HARD1_DELAY_OBS_3_SHIFT 0U
  766. #define LPDDR4__DENALI_PHY_821__PHY_GTLVL_HARD1_DELAY_OBS_3_WIDTH 14U
  767. #define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_3__REG DENALI_PHY_821
  768. #define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_3__FLD LPDDR4__DENALI_PHY_821__PHY_GTLVL_HARD1_DELAY_OBS_3
  769. #define LPDDR4__DENALI_PHY_822_READ_MASK 0x0003FFFFU
  770. #define LPDDR4__DENALI_PHY_822_WRITE_MASK 0x0003FFFFU
  771. #define LPDDR4__DENALI_PHY_822__PHY_GTLVL_STATUS_OBS_3_MASK 0x0003FFFFU
  772. #define LPDDR4__DENALI_PHY_822__PHY_GTLVL_STATUS_OBS_3_SHIFT 0U
  773. #define LPDDR4__DENALI_PHY_822__PHY_GTLVL_STATUS_OBS_3_WIDTH 18U
  774. #define LPDDR4__PHY_GTLVL_STATUS_OBS_3__REG DENALI_PHY_822
  775. #define LPDDR4__PHY_GTLVL_STATUS_OBS_3__FLD LPDDR4__DENALI_PHY_822__PHY_GTLVL_STATUS_OBS_3
  776. #define LPDDR4__DENALI_PHY_823_READ_MASK 0x03FF03FFU
  777. #define LPDDR4__DENALI_PHY_823_WRITE_MASK 0x03FF03FFU
  778. #define LPDDR4__DENALI_PHY_823__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3_MASK 0x000003FFU
  779. #define LPDDR4__DENALI_PHY_823__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3_SHIFT 0U
  780. #define LPDDR4__DENALI_PHY_823__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3_WIDTH 10U
  781. #define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3__REG DENALI_PHY_823
  782. #define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3__FLD LPDDR4__DENALI_PHY_823__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3
  783. #define LPDDR4__DENALI_PHY_823__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3_MASK 0x03FF0000U
  784. #define LPDDR4__DENALI_PHY_823__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3_SHIFT 16U
  785. #define LPDDR4__DENALI_PHY_823__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3_WIDTH 10U
  786. #define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3__REG DENALI_PHY_823
  787. #define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3__FLD LPDDR4__DENALI_PHY_823__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3
  788. #define LPDDR4__DENALI_PHY_824_READ_MASK 0x00000003U
  789. #define LPDDR4__DENALI_PHY_824_WRITE_MASK 0x00000003U
  790. #define LPDDR4__DENALI_PHY_824__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3_MASK 0x00000003U
  791. #define LPDDR4__DENALI_PHY_824__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3_SHIFT 0U
  792. #define LPDDR4__DENALI_PHY_824__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3_WIDTH 2U
  793. #define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3__REG DENALI_PHY_824
  794. #define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3__FLD LPDDR4__DENALI_PHY_824__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3
  795. #define LPDDR4__DENALI_PHY_825_READ_MASK 0xFFFFFFFFU
  796. #define LPDDR4__DENALI_PHY_825_WRITE_MASK 0xFFFFFFFFU
  797. #define LPDDR4__DENALI_PHY_825__PHY_RDLVL_STATUS_OBS_3_MASK 0xFFFFFFFFU
  798. #define LPDDR4__DENALI_PHY_825__PHY_RDLVL_STATUS_OBS_3_SHIFT 0U
  799. #define LPDDR4__DENALI_PHY_825__PHY_RDLVL_STATUS_OBS_3_WIDTH 32U
  800. #define LPDDR4__PHY_RDLVL_STATUS_OBS_3__REG DENALI_PHY_825
  801. #define LPDDR4__PHY_RDLVL_STATUS_OBS_3__FLD LPDDR4__DENALI_PHY_825__PHY_RDLVL_STATUS_OBS_3
  802. #define LPDDR4__DENALI_PHY_826_READ_MASK 0xFFFFFFFFU
  803. #define LPDDR4__DENALI_PHY_826_WRITE_MASK 0xFFFFFFFFU
  804. #define LPDDR4__DENALI_PHY_826__PHY_RDLVL_PERIODIC_OBS_3_MASK 0xFFFFFFFFU
  805. #define LPDDR4__DENALI_PHY_826__PHY_RDLVL_PERIODIC_OBS_3_SHIFT 0U
  806. #define LPDDR4__DENALI_PHY_826__PHY_RDLVL_PERIODIC_OBS_3_WIDTH 32U
  807. #define LPDDR4__PHY_RDLVL_PERIODIC_OBS_3__REG DENALI_PHY_826
  808. #define LPDDR4__PHY_RDLVL_PERIODIC_OBS_3__FLD LPDDR4__DENALI_PHY_826__PHY_RDLVL_PERIODIC_OBS_3
  809. #define LPDDR4__DENALI_PHY_827_READ_MASK 0x07FF07FFU
  810. #define LPDDR4__DENALI_PHY_827_WRITE_MASK 0x07FF07FFU
  811. #define LPDDR4__DENALI_PHY_827__PHY_WDQLVL_DQDM_LE_DLY_OBS_3_MASK 0x000007FFU
  812. #define LPDDR4__DENALI_PHY_827__PHY_WDQLVL_DQDM_LE_DLY_OBS_3_SHIFT 0U
  813. #define LPDDR4__DENALI_PHY_827__PHY_WDQLVL_DQDM_LE_DLY_OBS_3_WIDTH 11U
  814. #define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_3__REG DENALI_PHY_827
  815. #define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_3__FLD LPDDR4__DENALI_PHY_827__PHY_WDQLVL_DQDM_LE_DLY_OBS_3
  816. #define LPDDR4__DENALI_PHY_827__PHY_WDQLVL_DQDM_TE_DLY_OBS_3_MASK 0x07FF0000U
  817. #define LPDDR4__DENALI_PHY_827__PHY_WDQLVL_DQDM_TE_DLY_OBS_3_SHIFT 16U
  818. #define LPDDR4__DENALI_PHY_827__PHY_WDQLVL_DQDM_TE_DLY_OBS_3_WIDTH 11U
  819. #define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_3__REG DENALI_PHY_827
  820. #define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_3__FLD LPDDR4__DENALI_PHY_827__PHY_WDQLVL_DQDM_TE_DLY_OBS_3
  821. #define LPDDR4__DENALI_PHY_828_READ_MASK 0xFFFFFFFFU
  822. #define LPDDR4__DENALI_PHY_828_WRITE_MASK 0xFFFFFFFFU
  823. #define LPDDR4__DENALI_PHY_828__PHY_WDQLVL_STATUS_OBS_3_MASK 0xFFFFFFFFU
  824. #define LPDDR4__DENALI_PHY_828__PHY_WDQLVL_STATUS_OBS_3_SHIFT 0U
  825. #define LPDDR4__DENALI_PHY_828__PHY_WDQLVL_STATUS_OBS_3_WIDTH 32U
  826. #define LPDDR4__PHY_WDQLVL_STATUS_OBS_3__REG DENALI_PHY_828
  827. #define LPDDR4__PHY_WDQLVL_STATUS_OBS_3__FLD LPDDR4__DENALI_PHY_828__PHY_WDQLVL_STATUS_OBS_3
  828. #define LPDDR4__DENALI_PHY_829_READ_MASK 0xFFFFFFFFU
  829. #define LPDDR4__DENALI_PHY_829_WRITE_MASK 0xFFFFFFFFU
  830. #define LPDDR4__DENALI_PHY_829__PHY_WDQLVL_PERIODIC_OBS_3_MASK 0xFFFFFFFFU
  831. #define LPDDR4__DENALI_PHY_829__PHY_WDQLVL_PERIODIC_OBS_3_SHIFT 0U
  832. #define LPDDR4__DENALI_PHY_829__PHY_WDQLVL_PERIODIC_OBS_3_WIDTH 32U
  833. #define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_3__REG DENALI_PHY_829
  834. #define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_3__FLD LPDDR4__DENALI_PHY_829__PHY_WDQLVL_PERIODIC_OBS_3
  835. #define LPDDR4__DENALI_PHY_830_READ_MASK 0x7FFFFFFFU
  836. #define LPDDR4__DENALI_PHY_830_WRITE_MASK 0x7FFFFFFFU
  837. #define LPDDR4__DENALI_PHY_830__PHY_DDL_MODE_3_MASK 0x7FFFFFFFU
  838. #define LPDDR4__DENALI_PHY_830__PHY_DDL_MODE_3_SHIFT 0U
  839. #define LPDDR4__DENALI_PHY_830__PHY_DDL_MODE_3_WIDTH 31U
  840. #define LPDDR4__PHY_DDL_MODE_3__REG DENALI_PHY_830
  841. #define LPDDR4__PHY_DDL_MODE_3__FLD LPDDR4__DENALI_PHY_830__PHY_DDL_MODE_3
  842. #define LPDDR4__DENALI_PHY_831_READ_MASK 0x0000003FU
  843. #define LPDDR4__DENALI_PHY_831_WRITE_MASK 0x0000003FU
  844. #define LPDDR4__DENALI_PHY_831__PHY_DDL_MASK_3_MASK 0x0000003FU
  845. #define LPDDR4__DENALI_PHY_831__PHY_DDL_MASK_3_SHIFT 0U
  846. #define LPDDR4__DENALI_PHY_831__PHY_DDL_MASK_3_WIDTH 6U
  847. #define LPDDR4__PHY_DDL_MASK_3__REG DENALI_PHY_831
  848. #define LPDDR4__PHY_DDL_MASK_3__FLD LPDDR4__DENALI_PHY_831__PHY_DDL_MASK_3
  849. #define LPDDR4__DENALI_PHY_832_READ_MASK 0xFFFFFFFFU
  850. #define LPDDR4__DENALI_PHY_832_WRITE_MASK 0xFFFFFFFFU
  851. #define LPDDR4__DENALI_PHY_832__PHY_DDL_TEST_OBS_3_MASK 0xFFFFFFFFU
  852. #define LPDDR4__DENALI_PHY_832__PHY_DDL_TEST_OBS_3_SHIFT 0U
  853. #define LPDDR4__DENALI_PHY_832__PHY_DDL_TEST_OBS_3_WIDTH 32U
  854. #define LPDDR4__PHY_DDL_TEST_OBS_3__REG DENALI_PHY_832
  855. #define LPDDR4__PHY_DDL_TEST_OBS_3__FLD LPDDR4__DENALI_PHY_832__PHY_DDL_TEST_OBS_3
  856. #define LPDDR4__DENALI_PHY_833_READ_MASK 0xFFFFFFFFU
  857. #define LPDDR4__DENALI_PHY_833_WRITE_MASK 0xFFFFFFFFU
  858. #define LPDDR4__DENALI_PHY_833__PHY_DDL_TEST_MSTR_DLY_OBS_3_MASK 0xFFFFFFFFU
  859. #define LPDDR4__DENALI_PHY_833__PHY_DDL_TEST_MSTR_DLY_OBS_3_SHIFT 0U
  860. #define LPDDR4__DENALI_PHY_833__PHY_DDL_TEST_MSTR_DLY_OBS_3_WIDTH 32U
  861. #define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_3__REG DENALI_PHY_833
  862. #define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_3__FLD LPDDR4__DENALI_PHY_833__PHY_DDL_TEST_MSTR_DLY_OBS_3
  863. #define LPDDR4__DENALI_PHY_834_READ_MASK 0x010001FFU
  864. #define LPDDR4__DENALI_PHY_834_WRITE_MASK 0x010001FFU
  865. #define LPDDR4__DENALI_PHY_834__PHY_DDL_TRACK_UPD_THRESHOLD_3_MASK 0x000000FFU
  866. #define LPDDR4__DENALI_PHY_834__PHY_DDL_TRACK_UPD_THRESHOLD_3_SHIFT 0U
  867. #define LPDDR4__DENALI_PHY_834__PHY_DDL_TRACK_UPD_THRESHOLD_3_WIDTH 8U
  868. #define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_3__REG DENALI_PHY_834
  869. #define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_3__FLD LPDDR4__DENALI_PHY_834__PHY_DDL_TRACK_UPD_THRESHOLD_3
  870. #define LPDDR4__DENALI_PHY_834__PHY_LP4_WDQS_OE_EXTEND_3_MASK 0x00000100U
  871. #define LPDDR4__DENALI_PHY_834__PHY_LP4_WDQS_OE_EXTEND_3_SHIFT 8U
  872. #define LPDDR4__DENALI_PHY_834__PHY_LP4_WDQS_OE_EXTEND_3_WIDTH 1U
  873. #define LPDDR4__DENALI_PHY_834__PHY_LP4_WDQS_OE_EXTEND_3_WOCLR 0U
  874. #define LPDDR4__DENALI_PHY_834__PHY_LP4_WDQS_OE_EXTEND_3_WOSET 0U
  875. #define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_3__REG DENALI_PHY_834
  876. #define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_3__FLD LPDDR4__DENALI_PHY_834__PHY_LP4_WDQS_OE_EXTEND_3
  877. #define LPDDR4__DENALI_PHY_834__SC_PHY_RX_CAL_START_3_MASK 0x00010000U
  878. #define LPDDR4__DENALI_PHY_834__SC_PHY_RX_CAL_START_3_SHIFT 16U
  879. #define LPDDR4__DENALI_PHY_834__SC_PHY_RX_CAL_START_3_WIDTH 1U
  880. #define LPDDR4__DENALI_PHY_834__SC_PHY_RX_CAL_START_3_WOCLR 0U
  881. #define LPDDR4__DENALI_PHY_834__SC_PHY_RX_CAL_START_3_WOSET 0U
  882. #define LPDDR4__SC_PHY_RX_CAL_START_3__REG DENALI_PHY_834
  883. #define LPDDR4__SC_PHY_RX_CAL_START_3__FLD LPDDR4__DENALI_PHY_834__SC_PHY_RX_CAL_START_3
  884. #define LPDDR4__DENALI_PHY_834__PHY_RX_CAL_OVERRIDE_3_MASK 0x01000000U
  885. #define LPDDR4__DENALI_PHY_834__PHY_RX_CAL_OVERRIDE_3_SHIFT 24U
  886. #define LPDDR4__DENALI_PHY_834__PHY_RX_CAL_OVERRIDE_3_WIDTH 1U
  887. #define LPDDR4__DENALI_PHY_834__PHY_RX_CAL_OVERRIDE_3_WOCLR 0U
  888. #define LPDDR4__DENALI_PHY_834__PHY_RX_CAL_OVERRIDE_3_WOSET 0U
  889. #define LPDDR4__PHY_RX_CAL_OVERRIDE_3__REG DENALI_PHY_834
  890. #define LPDDR4__PHY_RX_CAL_OVERRIDE_3__FLD LPDDR4__DENALI_PHY_834__PHY_RX_CAL_OVERRIDE_3
  891. #define LPDDR4__DENALI_PHY_835_READ_MASK 0x01FF01FFU
  892. #define LPDDR4__DENALI_PHY_835_WRITE_MASK 0x01FF01FFU
  893. #define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_SAMPLE_WAIT_3_MASK 0x000000FFU
  894. #define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_SAMPLE_WAIT_3_SHIFT 0U
  895. #define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_SAMPLE_WAIT_3_WIDTH 8U
  896. #define LPDDR4__PHY_RX_CAL_SAMPLE_WAIT_3__REG DENALI_PHY_835
  897. #define LPDDR4__PHY_RX_CAL_SAMPLE_WAIT_3__FLD LPDDR4__DENALI_PHY_835__PHY_RX_CAL_SAMPLE_WAIT_3
  898. #define LPDDR4__DENALI_PHY_835__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_3_MASK 0x00000100U
  899. #define LPDDR4__DENALI_PHY_835__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_3_SHIFT 8U
  900. #define LPDDR4__DENALI_PHY_835__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_3_WIDTH 1U
  901. #define LPDDR4__DENALI_PHY_835__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_3_WOCLR 0U
  902. #define LPDDR4__DENALI_PHY_835__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_3_WOSET 0U
  903. #define LPDDR4__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_3__REG DENALI_PHY_835
  904. #define LPDDR4__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_3__FLD LPDDR4__DENALI_PHY_835__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_3
  905. #define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_DQ0_3_MASK 0x01FF0000U
  906. #define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_DQ0_3_SHIFT 16U
  907. #define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_DQ0_3_WIDTH 9U
  908. #define LPDDR4__PHY_RX_CAL_DQ0_3__REG DENALI_PHY_835
  909. #define LPDDR4__PHY_RX_CAL_DQ0_3__FLD LPDDR4__DENALI_PHY_835__PHY_RX_CAL_DQ0_3
  910. #define LPDDR4__DENALI_PHY_836_READ_MASK 0x01FF01FFU
  911. #define LPDDR4__DENALI_PHY_836_WRITE_MASK 0x01FF01FFU
  912. #define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ1_3_MASK 0x000001FFU
  913. #define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ1_3_SHIFT 0U
  914. #define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ1_3_WIDTH 9U
  915. #define LPDDR4__PHY_RX_CAL_DQ1_3__REG DENALI_PHY_836
  916. #define LPDDR4__PHY_RX_CAL_DQ1_3__FLD LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ1_3
  917. #define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ2_3_MASK 0x01FF0000U
  918. #define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ2_3_SHIFT 16U
  919. #define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ2_3_WIDTH 9U
  920. #define LPDDR4__PHY_RX_CAL_DQ2_3__REG DENALI_PHY_836
  921. #define LPDDR4__PHY_RX_CAL_DQ2_3__FLD LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ2_3
  922. #define LPDDR4__DENALI_PHY_837_READ_MASK 0x01FF01FFU
  923. #define LPDDR4__DENALI_PHY_837_WRITE_MASK 0x01FF01FFU
  924. #define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ3_3_MASK 0x000001FFU
  925. #define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ3_3_SHIFT 0U
  926. #define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ3_3_WIDTH 9U
  927. #define LPDDR4__PHY_RX_CAL_DQ3_3__REG DENALI_PHY_837
  928. #define LPDDR4__PHY_RX_CAL_DQ3_3__FLD LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ3_3
  929. #define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ4_3_MASK 0x01FF0000U
  930. #define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ4_3_SHIFT 16U
  931. #define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ4_3_WIDTH 9U
  932. #define LPDDR4__PHY_RX_CAL_DQ4_3__REG DENALI_PHY_837
  933. #define LPDDR4__PHY_RX_CAL_DQ4_3__FLD LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ4_3
  934. #define LPDDR4__DENALI_PHY_838_READ_MASK 0x01FF01FFU
  935. #define LPDDR4__DENALI_PHY_838_WRITE_MASK 0x01FF01FFU
  936. #define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ5_3_MASK 0x000001FFU
  937. #define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ5_3_SHIFT 0U
  938. #define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ5_3_WIDTH 9U
  939. #define LPDDR4__PHY_RX_CAL_DQ5_3__REG DENALI_PHY_838
  940. #define LPDDR4__PHY_RX_CAL_DQ5_3__FLD LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ5_3
  941. #define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ6_3_MASK 0x01FF0000U
  942. #define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ6_3_SHIFT 16U
  943. #define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ6_3_WIDTH 9U
  944. #define LPDDR4__PHY_RX_CAL_DQ6_3__REG DENALI_PHY_838
  945. #define LPDDR4__PHY_RX_CAL_DQ6_3__FLD LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ6_3
  946. #define LPDDR4__DENALI_PHY_839_READ_MASK 0x000001FFU
  947. #define LPDDR4__DENALI_PHY_839_WRITE_MASK 0x000001FFU
  948. #define LPDDR4__DENALI_PHY_839__PHY_RX_CAL_DQ7_3_MASK 0x000001FFU
  949. #define LPDDR4__DENALI_PHY_839__PHY_RX_CAL_DQ7_3_SHIFT 0U
  950. #define LPDDR4__DENALI_PHY_839__PHY_RX_CAL_DQ7_3_WIDTH 9U
  951. #define LPDDR4__PHY_RX_CAL_DQ7_3__REG DENALI_PHY_839
  952. #define LPDDR4__PHY_RX_CAL_DQ7_3__FLD LPDDR4__DENALI_PHY_839__PHY_RX_CAL_DQ7_3
  953. #define LPDDR4__DENALI_PHY_840_READ_MASK 0x0003FFFFU
  954. #define LPDDR4__DENALI_PHY_840_WRITE_MASK 0x0003FFFFU
  955. #define LPDDR4__DENALI_PHY_840__PHY_RX_CAL_DM_3_MASK 0x0003FFFFU
  956. #define LPDDR4__DENALI_PHY_840__PHY_RX_CAL_DM_3_SHIFT 0U
  957. #define LPDDR4__DENALI_PHY_840__PHY_RX_CAL_DM_3_WIDTH 18U
  958. #define LPDDR4__PHY_RX_CAL_DM_3__REG DENALI_PHY_840
  959. #define LPDDR4__PHY_RX_CAL_DM_3__FLD LPDDR4__DENALI_PHY_840__PHY_RX_CAL_DM_3
  960. #define LPDDR4__DENALI_PHY_841_READ_MASK 0x01FF01FFU
  961. #define LPDDR4__DENALI_PHY_841_WRITE_MASK 0x01FF01FFU
  962. #define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_DQS_3_MASK 0x000001FFU
  963. #define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_DQS_3_SHIFT 0U
  964. #define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_DQS_3_WIDTH 9U
  965. #define LPDDR4__PHY_RX_CAL_DQS_3__REG DENALI_PHY_841
  966. #define LPDDR4__PHY_RX_CAL_DQS_3__FLD LPDDR4__DENALI_PHY_841__PHY_RX_CAL_DQS_3
  967. #define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_FDBK_3_MASK 0x01FF0000U
  968. #define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_FDBK_3_SHIFT 16U
  969. #define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_FDBK_3_WIDTH 9U
  970. #define LPDDR4__PHY_RX_CAL_FDBK_3__REG DENALI_PHY_841
  971. #define LPDDR4__PHY_RX_CAL_FDBK_3__FLD LPDDR4__DENALI_PHY_841__PHY_RX_CAL_FDBK_3
  972. #define LPDDR4__DENALI_PHY_842_READ_MASK 0x01FF07FFU
  973. #define LPDDR4__DENALI_PHY_842_WRITE_MASK 0x01FF07FFU
  974. #define LPDDR4__DENALI_PHY_842__PHY_RX_CAL_OBS_3_MASK 0x000007FFU
  975. #define LPDDR4__DENALI_PHY_842__PHY_RX_CAL_OBS_3_SHIFT 0U
  976. #define LPDDR4__DENALI_PHY_842__PHY_RX_CAL_OBS_3_WIDTH 11U
  977. #define LPDDR4__PHY_RX_CAL_OBS_3__REG DENALI_PHY_842
  978. #define LPDDR4__PHY_RX_CAL_OBS_3__FLD LPDDR4__DENALI_PHY_842__PHY_RX_CAL_OBS_3
  979. #define LPDDR4__DENALI_PHY_842__PHY_RX_CAL_LOCK_OBS_3_MASK 0x01FF0000U
  980. #define LPDDR4__DENALI_PHY_842__PHY_RX_CAL_LOCK_OBS_3_SHIFT 16U
  981. #define LPDDR4__DENALI_PHY_842__PHY_RX_CAL_LOCK_OBS_3_WIDTH 9U
  982. #define LPDDR4__PHY_RX_CAL_LOCK_OBS_3__REG DENALI_PHY_842
  983. #define LPDDR4__PHY_RX_CAL_LOCK_OBS_3__FLD LPDDR4__DENALI_PHY_842__PHY_RX_CAL_LOCK_OBS_3
  984. #define LPDDR4__DENALI_PHY_843_READ_MASK 0x017F7F01U
  985. #define LPDDR4__DENALI_PHY_843_WRITE_MASK 0x017F7F01U
  986. #define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DISABLE_3_MASK 0x00000001U
  987. #define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DISABLE_3_SHIFT 0U
  988. #define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DISABLE_3_WIDTH 1U
  989. #define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DISABLE_3_WOCLR 0U
  990. #define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DISABLE_3_WOSET 0U
  991. #define LPDDR4__PHY_RX_CAL_DISABLE_3__REG DENALI_PHY_843
  992. #define LPDDR4__PHY_RX_CAL_DISABLE_3__FLD LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DISABLE_3
  993. #define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_SE_ADJUST_3_MASK 0x00007F00U
  994. #define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_SE_ADJUST_3_SHIFT 8U
  995. #define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_SE_ADJUST_3_WIDTH 7U
  996. #define LPDDR4__PHY_RX_CAL_SE_ADJUST_3__REG DENALI_PHY_843
  997. #define LPDDR4__PHY_RX_CAL_SE_ADJUST_3__FLD LPDDR4__DENALI_PHY_843__PHY_RX_CAL_SE_ADJUST_3
  998. #define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DIFF_ADJUST_3_MASK 0x007F0000U
  999. #define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DIFF_ADJUST_3_SHIFT 16U
  1000. #define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DIFF_ADJUST_3_WIDTH 7U
  1001. #define LPDDR4__PHY_RX_CAL_DIFF_ADJUST_3__REG DENALI_PHY_843
  1002. #define LPDDR4__PHY_RX_CAL_DIFF_ADJUST_3__FLD LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DIFF_ADJUST_3
  1003. #define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_COMP_VAL_3_MASK 0x01000000U
  1004. #define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_COMP_VAL_3_SHIFT 24U
  1005. #define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_COMP_VAL_3_WIDTH 1U
  1006. #define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_COMP_VAL_3_WOCLR 0U
  1007. #define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_COMP_VAL_3_WOSET 0U
  1008. #define LPDDR4__PHY_RX_CAL_COMP_VAL_3__REG DENALI_PHY_843
  1009. #define LPDDR4__PHY_RX_CAL_COMP_VAL_3__FLD LPDDR4__DENALI_PHY_843__PHY_RX_CAL_COMP_VAL_3
  1010. #define LPDDR4__DENALI_PHY_844_READ_MASK 0x07FF0FFFU
  1011. #define LPDDR4__DENALI_PHY_844_WRITE_MASK 0x07FF0FFFU
  1012. #define LPDDR4__DENALI_PHY_844__PHY_RX_CAL_INDEX_MASK_3_MASK 0x00000FFFU
  1013. #define LPDDR4__DENALI_PHY_844__PHY_RX_CAL_INDEX_MASK_3_SHIFT 0U
  1014. #define LPDDR4__DENALI_PHY_844__PHY_RX_CAL_INDEX_MASK_3_WIDTH 12U
  1015. #define LPDDR4__PHY_RX_CAL_INDEX_MASK_3__REG DENALI_PHY_844
  1016. #define LPDDR4__PHY_RX_CAL_INDEX_MASK_3__FLD LPDDR4__DENALI_PHY_844__PHY_RX_CAL_INDEX_MASK_3
  1017. #define LPDDR4__DENALI_PHY_844__PHY_PAD_RX_BIAS_EN_3_MASK 0x07FF0000U
  1018. #define LPDDR4__DENALI_PHY_844__PHY_PAD_RX_BIAS_EN_3_SHIFT 16U
  1019. #define LPDDR4__DENALI_PHY_844__PHY_PAD_RX_BIAS_EN_3_WIDTH 11U
  1020. #define LPDDR4__PHY_PAD_RX_BIAS_EN_3__REG DENALI_PHY_844
  1021. #define LPDDR4__PHY_PAD_RX_BIAS_EN_3__FLD LPDDR4__DENALI_PHY_844__PHY_PAD_RX_BIAS_EN_3
  1022. #define LPDDR4__DENALI_PHY_845_READ_MASK 0x03FFFF1FU
  1023. #define LPDDR4__DENALI_PHY_845_WRITE_MASK 0x03FFFF1FU
  1024. #define LPDDR4__DENALI_PHY_845__PHY_STATIC_TOG_DISABLE_3_MASK 0x0000001FU
  1025. #define LPDDR4__DENALI_PHY_845__PHY_STATIC_TOG_DISABLE_3_SHIFT 0U
  1026. #define LPDDR4__DENALI_PHY_845__PHY_STATIC_TOG_DISABLE_3_WIDTH 5U
  1027. #define LPDDR4__PHY_STATIC_TOG_DISABLE_3__REG DENALI_PHY_845
  1028. #define LPDDR4__PHY_STATIC_TOG_DISABLE_3__FLD LPDDR4__DENALI_PHY_845__PHY_STATIC_TOG_DISABLE_3
  1029. #define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_CAL_SAMPLE_WAIT_3_MASK 0x0000FF00U
  1030. #define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_CAL_SAMPLE_WAIT_3_SHIFT 8U
  1031. #define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_CAL_SAMPLE_WAIT_3_WIDTH 8U
  1032. #define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_3__REG DENALI_PHY_845
  1033. #define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_3__FLD LPDDR4__DENALI_PHY_845__PHY_DATA_DC_CAL_SAMPLE_WAIT_3
  1034. #define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_CAL_TIMEOUT_3_MASK 0x00FF0000U
  1035. #define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_CAL_TIMEOUT_3_SHIFT 16U
  1036. #define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_CAL_TIMEOUT_3_WIDTH 8U
  1037. #define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_3__REG DENALI_PHY_845
  1038. #define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_3__FLD LPDDR4__DENALI_PHY_845__PHY_DATA_DC_CAL_TIMEOUT_3
  1039. #define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_WEIGHT_3_MASK 0x03000000U
  1040. #define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_WEIGHT_3_SHIFT 24U
  1041. #define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_WEIGHT_3_WIDTH 2U
  1042. #define LPDDR4__PHY_DATA_DC_WEIGHT_3__REG DENALI_PHY_845
  1043. #define LPDDR4__PHY_DATA_DC_WEIGHT_3__FLD LPDDR4__DENALI_PHY_845__PHY_DATA_DC_WEIGHT_3
  1044. #define LPDDR4__DENALI_PHY_846_READ_MASK 0x01FFFF3FU
  1045. #define LPDDR4__DENALI_PHY_846_WRITE_MASK 0x01FFFF3FU
  1046. #define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_START_3_MASK 0x0000003FU
  1047. #define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_START_3_SHIFT 0U
  1048. #define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_START_3_WIDTH 6U
  1049. #define LPDDR4__PHY_DATA_DC_ADJUST_START_3__REG DENALI_PHY_846
  1050. #define LPDDR4__PHY_DATA_DC_ADJUST_START_3__FLD LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_START_3
  1051. #define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_SAMPLE_CNT_3_MASK 0x0000FF00U
  1052. #define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_SAMPLE_CNT_3_SHIFT 8U
  1053. #define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_SAMPLE_CNT_3_WIDTH 8U
  1054. #define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_3__REG DENALI_PHY_846
  1055. #define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_3__FLD LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_SAMPLE_CNT_3
  1056. #define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_THRSHLD_3_MASK 0x00FF0000U
  1057. #define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_THRSHLD_3_SHIFT 16U
  1058. #define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_THRSHLD_3_WIDTH 8U
  1059. #define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_3__REG DENALI_PHY_846
  1060. #define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_3__FLD LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_THRSHLD_3
  1061. #define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_DIRECT_3_MASK 0x01000000U
  1062. #define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_DIRECT_3_SHIFT 24U
  1063. #define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_DIRECT_3_WIDTH 1U
  1064. #define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_DIRECT_3_WOCLR 0U
  1065. #define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_DIRECT_3_WOSET 0U
  1066. #define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_3__REG DENALI_PHY_846
  1067. #define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_3__FLD LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_DIRECT_3
  1068. #define LPDDR4__DENALI_PHY_847_READ_MASK 0x07030101U
  1069. #define LPDDR4__DENALI_PHY_847_WRITE_MASK 0x07030101U
  1070. #define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_POLARITY_3_MASK 0x00000001U
  1071. #define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_POLARITY_3_SHIFT 0U
  1072. #define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_POLARITY_3_WIDTH 1U
  1073. #define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_POLARITY_3_WOCLR 0U
  1074. #define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_POLARITY_3_WOSET 0U
  1075. #define LPDDR4__PHY_DATA_DC_CAL_POLARITY_3__REG DENALI_PHY_847
  1076. #define LPDDR4__PHY_DATA_DC_CAL_POLARITY_3__FLD LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_POLARITY_3
  1077. #define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_START_3_MASK 0x00000100U
  1078. #define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_START_3_SHIFT 8U
  1079. #define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_START_3_WIDTH 1U
  1080. #define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_START_3_WOCLR 0U
  1081. #define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_START_3_WOSET 0U
  1082. #define LPDDR4__PHY_DATA_DC_CAL_START_3__REG DENALI_PHY_847
  1083. #define LPDDR4__PHY_DATA_DC_CAL_START_3__FLD LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_START_3
  1084. #define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_SW_RANK_3_MASK 0x00030000U
  1085. #define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_SW_RANK_3_SHIFT 16U
  1086. #define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_SW_RANK_3_WIDTH 2U
  1087. #define LPDDR4__PHY_DATA_DC_SW_RANK_3__REG DENALI_PHY_847
  1088. #define LPDDR4__PHY_DATA_DC_SW_RANK_3__FLD LPDDR4__DENALI_PHY_847__PHY_DATA_DC_SW_RANK_3
  1089. #define LPDDR4__DENALI_PHY_847__PHY_FDBK_PWR_CTRL_3_MASK 0x07000000U
  1090. #define LPDDR4__DENALI_PHY_847__PHY_FDBK_PWR_CTRL_3_SHIFT 24U
  1091. #define LPDDR4__DENALI_PHY_847__PHY_FDBK_PWR_CTRL_3_WIDTH 3U
  1092. #define LPDDR4__PHY_FDBK_PWR_CTRL_3__REG DENALI_PHY_847
  1093. #define LPDDR4__PHY_FDBK_PWR_CTRL_3__FLD LPDDR4__DENALI_PHY_847__PHY_FDBK_PWR_CTRL_3
  1094. #define LPDDR4__DENALI_PHY_848_READ_MASK 0x01010101U
  1095. #define LPDDR4__DENALI_PHY_848_WRITE_MASK 0x01010101U
  1096. #define LPDDR4__DENALI_PHY_848__PHY_SLV_DLY_CTRL_GATE_DISABLE_3_MASK 0x00000001U
  1097. #define LPDDR4__DENALI_PHY_848__PHY_SLV_DLY_CTRL_GATE_DISABLE_3_SHIFT 0U
  1098. #define LPDDR4__DENALI_PHY_848__PHY_SLV_DLY_CTRL_GATE_DISABLE_3_WIDTH 1U
  1099. #define LPDDR4__DENALI_PHY_848__PHY_SLV_DLY_CTRL_GATE_DISABLE_3_WOCLR 0U
  1100. #define LPDDR4__DENALI_PHY_848__PHY_SLV_DLY_CTRL_GATE_DISABLE_3_WOSET 0U
  1101. #define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_3__REG DENALI_PHY_848
  1102. #define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_3__FLD LPDDR4__DENALI_PHY_848__PHY_SLV_DLY_CTRL_GATE_DISABLE_3
  1103. #define LPDDR4__DENALI_PHY_848__PHY_RDPATH_GATE_DISABLE_3_MASK 0x00000100U
  1104. #define LPDDR4__DENALI_PHY_848__PHY_RDPATH_GATE_DISABLE_3_SHIFT 8U
  1105. #define LPDDR4__DENALI_PHY_848__PHY_RDPATH_GATE_DISABLE_3_WIDTH 1U
  1106. #define LPDDR4__DENALI_PHY_848__PHY_RDPATH_GATE_DISABLE_3_WOCLR 0U
  1107. #define LPDDR4__DENALI_PHY_848__PHY_RDPATH_GATE_DISABLE_3_WOSET 0U
  1108. #define LPDDR4__PHY_RDPATH_GATE_DISABLE_3__REG DENALI_PHY_848
  1109. #define LPDDR4__PHY_RDPATH_GATE_DISABLE_3__FLD LPDDR4__DENALI_PHY_848__PHY_RDPATH_GATE_DISABLE_3
  1110. #define LPDDR4__DENALI_PHY_848__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3_MASK 0x00010000U
  1111. #define LPDDR4__DENALI_PHY_848__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3_SHIFT 16U
  1112. #define LPDDR4__DENALI_PHY_848__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3_WIDTH 1U
  1113. #define LPDDR4__DENALI_PHY_848__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3_WOCLR 0U
  1114. #define LPDDR4__DENALI_PHY_848__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3_WOSET 0U
  1115. #define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3__REG DENALI_PHY_848
  1116. #define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3__FLD LPDDR4__DENALI_PHY_848__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3
  1117. #define LPDDR4__DENALI_PHY_848__PHY_SLICE_PWR_RDC_DISABLE_3_MASK 0x01000000U
  1118. #define LPDDR4__DENALI_PHY_848__PHY_SLICE_PWR_RDC_DISABLE_3_SHIFT 24U
  1119. #define LPDDR4__DENALI_PHY_848__PHY_SLICE_PWR_RDC_DISABLE_3_WIDTH 1U
  1120. #define LPDDR4__DENALI_PHY_848__PHY_SLICE_PWR_RDC_DISABLE_3_WOCLR 0U
  1121. #define LPDDR4__DENALI_PHY_848__PHY_SLICE_PWR_RDC_DISABLE_3_WOSET 0U
  1122. #define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_3__REG DENALI_PHY_848
  1123. #define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_3__FLD LPDDR4__DENALI_PHY_848__PHY_SLICE_PWR_RDC_DISABLE_3
  1124. #define LPDDR4__DENALI_PHY_849_READ_MASK 0x3FFF07FFU
  1125. #define LPDDR4__DENALI_PHY_849_WRITE_MASK 0x3FFF07FFU
  1126. #define LPDDR4__DENALI_PHY_849__PHY_PARITY_ERROR_REGIF_3_MASK 0x000007FFU
  1127. #define LPDDR4__DENALI_PHY_849__PHY_PARITY_ERROR_REGIF_3_SHIFT 0U
  1128. #define LPDDR4__DENALI_PHY_849__PHY_PARITY_ERROR_REGIF_3_WIDTH 11U
  1129. #define LPDDR4__PHY_PARITY_ERROR_REGIF_3__REG DENALI_PHY_849
  1130. #define LPDDR4__PHY_PARITY_ERROR_REGIF_3__FLD LPDDR4__DENALI_PHY_849__PHY_PARITY_ERROR_REGIF_3
  1131. #define LPDDR4__DENALI_PHY_849__PHY_DS_FSM_ERROR_INFO_3_MASK 0x3FFF0000U
  1132. #define LPDDR4__DENALI_PHY_849__PHY_DS_FSM_ERROR_INFO_3_SHIFT 16U
  1133. #define LPDDR4__DENALI_PHY_849__PHY_DS_FSM_ERROR_INFO_3_WIDTH 14U
  1134. #define LPDDR4__PHY_DS_FSM_ERROR_INFO_3__REG DENALI_PHY_849
  1135. #define LPDDR4__PHY_DS_FSM_ERROR_INFO_3__FLD LPDDR4__DENALI_PHY_849__PHY_DS_FSM_ERROR_INFO_3
  1136. #define LPDDR4__DENALI_PHY_850_READ_MASK 0x00003FFFU
  1137. #define LPDDR4__DENALI_PHY_850_WRITE_MASK 0x00003FFFU
  1138. #define LPDDR4__DENALI_PHY_850__PHY_DS_FSM_ERROR_INFO_MASK_3_MASK 0x00003FFFU
  1139. #define LPDDR4__DENALI_PHY_850__PHY_DS_FSM_ERROR_INFO_MASK_3_SHIFT 0U
  1140. #define LPDDR4__DENALI_PHY_850__PHY_DS_FSM_ERROR_INFO_MASK_3_WIDTH 14U
  1141. #define LPDDR4__PHY_DS_FSM_ERROR_INFO_MASK_3__REG DENALI_PHY_850
  1142. #define LPDDR4__PHY_DS_FSM_ERROR_INFO_MASK_3__FLD LPDDR4__DENALI_PHY_850__PHY_DS_FSM_ERROR_INFO_MASK_3
  1143. #define LPDDR4__DENALI_PHY_850__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_3_MASK 0x3FFF0000U
  1144. #define LPDDR4__DENALI_PHY_850__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_3_SHIFT 16U
  1145. #define LPDDR4__DENALI_PHY_850__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_3_WIDTH 14U
  1146. #define LPDDR4__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_3__REG DENALI_PHY_850
  1147. #define LPDDR4__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_3__FLD LPDDR4__DENALI_PHY_850__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_3
  1148. #define LPDDR4__DENALI_PHY_851_READ_MASK 0x00001F1FU
  1149. #define LPDDR4__DENALI_PHY_851_WRITE_MASK 0x00001F1FU
  1150. #define LPDDR4__DENALI_PHY_851__PHY_DS_TRAIN_CALIB_ERROR_INFO_3_MASK 0x0000001FU
  1151. #define LPDDR4__DENALI_PHY_851__PHY_DS_TRAIN_CALIB_ERROR_INFO_3_SHIFT 0U
  1152. #define LPDDR4__DENALI_PHY_851__PHY_DS_TRAIN_CALIB_ERROR_INFO_3_WIDTH 5U
  1153. #define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_3__REG DENALI_PHY_851
  1154. #define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_3__FLD LPDDR4__DENALI_PHY_851__PHY_DS_TRAIN_CALIB_ERROR_INFO_3
  1155. #define LPDDR4__DENALI_PHY_851__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_3_MASK 0x00001F00U
  1156. #define LPDDR4__DENALI_PHY_851__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_3_SHIFT 8U
  1157. #define LPDDR4__DENALI_PHY_851__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_3_WIDTH 5U
  1158. #define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_3__REG DENALI_PHY_851
  1159. #define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_3__FLD LPDDR4__DENALI_PHY_851__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_3
  1160. #define LPDDR4__DENALI_PHY_851__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_3_MASK 0x001F0000U
  1161. #define LPDDR4__DENALI_PHY_851__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_3_SHIFT 16U
  1162. #define LPDDR4__DENALI_PHY_851__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_3_WIDTH 5U
  1163. #define LPDDR4__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_3__REG DENALI_PHY_851
  1164. #define LPDDR4__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_3__FLD LPDDR4__DENALI_PHY_851__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_3
  1165. #define LPDDR4__DENALI_PHY_852_READ_MASK 0x07FFFF07U
  1166. #define LPDDR4__DENALI_PHY_852_WRITE_MASK 0x07FFFF07U
  1167. #define LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_ENABLE_3_MASK 0x00000007U
  1168. #define LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_ENABLE_3_SHIFT 0U
  1169. #define LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_ENABLE_3_WIDTH 3U
  1170. #define LPDDR4__PHY_DQ_TSEL_ENABLE_3__REG DENALI_PHY_852
  1171. #define LPDDR4__PHY_DQ_TSEL_ENABLE_3__FLD LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_ENABLE_3
  1172. #define LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_SELECT_3_MASK 0x00FFFF00U
  1173. #define LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_SELECT_3_SHIFT 8U
  1174. #define LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_SELECT_3_WIDTH 16U
  1175. #define LPDDR4__PHY_DQ_TSEL_SELECT_3__REG DENALI_PHY_852
  1176. #define LPDDR4__PHY_DQ_TSEL_SELECT_3__FLD LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_SELECT_3
  1177. #define LPDDR4__DENALI_PHY_852__PHY_DQS_TSEL_ENABLE_3_MASK 0x07000000U
  1178. #define LPDDR4__DENALI_PHY_852__PHY_DQS_TSEL_ENABLE_3_SHIFT 24U
  1179. #define LPDDR4__DENALI_PHY_852__PHY_DQS_TSEL_ENABLE_3_WIDTH 3U
  1180. #define LPDDR4__PHY_DQS_TSEL_ENABLE_3__REG DENALI_PHY_852
  1181. #define LPDDR4__PHY_DQS_TSEL_ENABLE_3__FLD LPDDR4__DENALI_PHY_852__PHY_DQS_TSEL_ENABLE_3
  1182. #define LPDDR4__DENALI_PHY_853_READ_MASK 0x7F03FFFFU
  1183. #define LPDDR4__DENALI_PHY_853_WRITE_MASK 0x7F03FFFFU
  1184. #define LPDDR4__DENALI_PHY_853__PHY_DQS_TSEL_SELECT_3_MASK 0x0000FFFFU
  1185. #define LPDDR4__DENALI_PHY_853__PHY_DQS_TSEL_SELECT_3_SHIFT 0U
  1186. #define LPDDR4__DENALI_PHY_853__PHY_DQS_TSEL_SELECT_3_WIDTH 16U
  1187. #define LPDDR4__PHY_DQS_TSEL_SELECT_3__REG DENALI_PHY_853
  1188. #define LPDDR4__PHY_DQS_TSEL_SELECT_3__FLD LPDDR4__DENALI_PHY_853__PHY_DQS_TSEL_SELECT_3
  1189. #define LPDDR4__DENALI_PHY_853__PHY_TWO_CYC_PREAMBLE_3_MASK 0x00030000U
  1190. #define LPDDR4__DENALI_PHY_853__PHY_TWO_CYC_PREAMBLE_3_SHIFT 16U
  1191. #define LPDDR4__DENALI_PHY_853__PHY_TWO_CYC_PREAMBLE_3_WIDTH 2U
  1192. #define LPDDR4__PHY_TWO_CYC_PREAMBLE_3__REG DENALI_PHY_853
  1193. #define LPDDR4__PHY_TWO_CYC_PREAMBLE_3__FLD LPDDR4__DENALI_PHY_853__PHY_TWO_CYC_PREAMBLE_3
  1194. #define LPDDR4__DENALI_PHY_853__PHY_VREF_INITIAL_START_POINT_3_MASK 0x7F000000U
  1195. #define LPDDR4__DENALI_PHY_853__PHY_VREF_INITIAL_START_POINT_3_SHIFT 24U
  1196. #define LPDDR4__DENALI_PHY_853__PHY_VREF_INITIAL_START_POINT_3_WIDTH 7U
  1197. #define LPDDR4__PHY_VREF_INITIAL_START_POINT_3__REG DENALI_PHY_853
  1198. #define LPDDR4__PHY_VREF_INITIAL_START_POINT_3__FLD LPDDR4__DENALI_PHY_853__PHY_VREF_INITIAL_START_POINT_3
  1199. #define LPDDR4__DENALI_PHY_854_READ_MASK 0xFF01037FU
  1200. #define LPDDR4__DENALI_PHY_854_WRITE_MASK 0xFF01037FU
  1201. #define LPDDR4__DENALI_PHY_854__PHY_VREF_INITIAL_STOP_POINT_3_MASK 0x0000007FU
  1202. #define LPDDR4__DENALI_PHY_854__PHY_VREF_INITIAL_STOP_POINT_3_SHIFT 0U
  1203. #define LPDDR4__DENALI_PHY_854__PHY_VREF_INITIAL_STOP_POINT_3_WIDTH 7U
  1204. #define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_3__REG DENALI_PHY_854
  1205. #define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_3__FLD LPDDR4__DENALI_PHY_854__PHY_VREF_INITIAL_STOP_POINT_3
  1206. #define LPDDR4__DENALI_PHY_854__PHY_VREF_TRAINING_CTRL_3_MASK 0x00000300U
  1207. #define LPDDR4__DENALI_PHY_854__PHY_VREF_TRAINING_CTRL_3_SHIFT 8U
  1208. #define LPDDR4__DENALI_PHY_854__PHY_VREF_TRAINING_CTRL_3_WIDTH 2U
  1209. #define LPDDR4__PHY_VREF_TRAINING_CTRL_3__REG DENALI_PHY_854
  1210. #define LPDDR4__PHY_VREF_TRAINING_CTRL_3__FLD LPDDR4__DENALI_PHY_854__PHY_VREF_TRAINING_CTRL_3
  1211. #define LPDDR4__DENALI_PHY_854__PHY_NTP_TRAIN_EN_3_MASK 0x00010000U
  1212. #define LPDDR4__DENALI_PHY_854__PHY_NTP_TRAIN_EN_3_SHIFT 16U
  1213. #define LPDDR4__DENALI_PHY_854__PHY_NTP_TRAIN_EN_3_WIDTH 1U
  1214. #define LPDDR4__DENALI_PHY_854__PHY_NTP_TRAIN_EN_3_WOCLR 0U
  1215. #define LPDDR4__DENALI_PHY_854__PHY_NTP_TRAIN_EN_3_WOSET 0U
  1216. #define LPDDR4__PHY_NTP_TRAIN_EN_3__REG DENALI_PHY_854
  1217. #define LPDDR4__PHY_NTP_TRAIN_EN_3__FLD LPDDR4__DENALI_PHY_854__PHY_NTP_TRAIN_EN_3
  1218. #define LPDDR4__DENALI_PHY_854__PHY_NTP_WDQ_STEP_SIZE_3_MASK 0xFF000000U
  1219. #define LPDDR4__DENALI_PHY_854__PHY_NTP_WDQ_STEP_SIZE_3_SHIFT 24U
  1220. #define LPDDR4__DENALI_PHY_854__PHY_NTP_WDQ_STEP_SIZE_3_WIDTH 8U
  1221. #define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_3__REG DENALI_PHY_854
  1222. #define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_3__FLD LPDDR4__DENALI_PHY_854__PHY_NTP_WDQ_STEP_SIZE_3
  1223. #define LPDDR4__DENALI_PHY_855_READ_MASK 0x07FF07FFU
  1224. #define LPDDR4__DENALI_PHY_855_WRITE_MASK 0x07FF07FFU
  1225. #define LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_START_3_MASK 0x000007FFU
  1226. #define LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_START_3_SHIFT 0U
  1227. #define LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_START_3_WIDTH 11U
  1228. #define LPDDR4__PHY_NTP_WDQ_START_3__REG DENALI_PHY_855
  1229. #define LPDDR4__PHY_NTP_WDQ_START_3__FLD LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_START_3
  1230. #define LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_STOP_3_MASK 0x07FF0000U
  1231. #define LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_STOP_3_SHIFT 16U
  1232. #define LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_STOP_3_WIDTH 11U
  1233. #define LPDDR4__PHY_NTP_WDQ_STOP_3__REG DENALI_PHY_855
  1234. #define LPDDR4__PHY_NTP_WDQ_STOP_3__FLD LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_STOP_3
  1235. #define LPDDR4__DENALI_PHY_856_READ_MASK 0x0103FFFFU
  1236. #define LPDDR4__DENALI_PHY_856_WRITE_MASK 0x0103FFFFU
  1237. #define LPDDR4__DENALI_PHY_856__PHY_NTP_WDQ_BIT_EN_3_MASK 0x000000FFU
  1238. #define LPDDR4__DENALI_PHY_856__PHY_NTP_WDQ_BIT_EN_3_SHIFT 0U
  1239. #define LPDDR4__DENALI_PHY_856__PHY_NTP_WDQ_BIT_EN_3_WIDTH 8U
  1240. #define LPDDR4__PHY_NTP_WDQ_BIT_EN_3__REG DENALI_PHY_856
  1241. #define LPDDR4__PHY_NTP_WDQ_BIT_EN_3__FLD LPDDR4__DENALI_PHY_856__PHY_NTP_WDQ_BIT_EN_3
  1242. #define LPDDR4__DENALI_PHY_856__PHY_WDQLVL_DVW_MIN_3_MASK 0x0003FF00U
  1243. #define LPDDR4__DENALI_PHY_856__PHY_WDQLVL_DVW_MIN_3_SHIFT 8U
  1244. #define LPDDR4__DENALI_PHY_856__PHY_WDQLVL_DVW_MIN_3_WIDTH 10U
  1245. #define LPDDR4__PHY_WDQLVL_DVW_MIN_3__REG DENALI_PHY_856
  1246. #define LPDDR4__PHY_WDQLVL_DVW_MIN_3__FLD LPDDR4__DENALI_PHY_856__PHY_WDQLVL_DVW_MIN_3
  1247. #define LPDDR4__DENALI_PHY_856__PHY_SW_WDQLVL_DVW_MIN_EN_3_MASK 0x01000000U
  1248. #define LPDDR4__DENALI_PHY_856__PHY_SW_WDQLVL_DVW_MIN_EN_3_SHIFT 24U
  1249. #define LPDDR4__DENALI_PHY_856__PHY_SW_WDQLVL_DVW_MIN_EN_3_WIDTH 1U
  1250. #define LPDDR4__DENALI_PHY_856__PHY_SW_WDQLVL_DVW_MIN_EN_3_WOCLR 0U
  1251. #define LPDDR4__DENALI_PHY_856__PHY_SW_WDQLVL_DVW_MIN_EN_3_WOSET 0U
  1252. #define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_3__REG DENALI_PHY_856
  1253. #define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_3__FLD LPDDR4__DENALI_PHY_856__PHY_SW_WDQLVL_DVW_MIN_EN_3
  1254. #define LPDDR4__DENALI_PHY_857_READ_MASK 0x1F1F0F3FU
  1255. #define LPDDR4__DENALI_PHY_857_WRITE_MASK 0x1F1F0F3FU
  1256. #define LPDDR4__DENALI_PHY_857__PHY_WDQLVL_PER_START_OFFSET_3_MASK 0x0000003FU
  1257. #define LPDDR4__DENALI_PHY_857__PHY_WDQLVL_PER_START_OFFSET_3_SHIFT 0U
  1258. #define LPDDR4__DENALI_PHY_857__PHY_WDQLVL_PER_START_OFFSET_3_WIDTH 6U
  1259. #define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_3__REG DENALI_PHY_857
  1260. #define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_3__FLD LPDDR4__DENALI_PHY_857__PHY_WDQLVL_PER_START_OFFSET_3
  1261. #define LPDDR4__DENALI_PHY_857__PHY_FAST_LVL_EN_3_MASK 0x00000F00U
  1262. #define LPDDR4__DENALI_PHY_857__PHY_FAST_LVL_EN_3_SHIFT 8U
  1263. #define LPDDR4__DENALI_PHY_857__PHY_FAST_LVL_EN_3_WIDTH 4U
  1264. #define LPDDR4__PHY_FAST_LVL_EN_3__REG DENALI_PHY_857
  1265. #define LPDDR4__PHY_FAST_LVL_EN_3__FLD LPDDR4__DENALI_PHY_857__PHY_FAST_LVL_EN_3
  1266. #define LPDDR4__DENALI_PHY_857__PHY_PAD_TX_DCD_3_MASK 0x001F0000U
  1267. #define LPDDR4__DENALI_PHY_857__PHY_PAD_TX_DCD_3_SHIFT 16U
  1268. #define LPDDR4__DENALI_PHY_857__PHY_PAD_TX_DCD_3_WIDTH 5U
  1269. #define LPDDR4__PHY_PAD_TX_DCD_3__REG DENALI_PHY_857
  1270. #define LPDDR4__PHY_PAD_TX_DCD_3__FLD LPDDR4__DENALI_PHY_857__PHY_PAD_TX_DCD_3
  1271. #define LPDDR4__DENALI_PHY_857__PHY_PAD_RX_DCD_0_3_MASK 0x1F000000U
  1272. #define LPDDR4__DENALI_PHY_857__PHY_PAD_RX_DCD_0_3_SHIFT 24U
  1273. #define LPDDR4__DENALI_PHY_857__PHY_PAD_RX_DCD_0_3_WIDTH 5U
  1274. #define LPDDR4__PHY_PAD_RX_DCD_0_3__REG DENALI_PHY_857
  1275. #define LPDDR4__PHY_PAD_RX_DCD_0_3__FLD LPDDR4__DENALI_PHY_857__PHY_PAD_RX_DCD_0_3
  1276. #define LPDDR4__DENALI_PHY_858_READ_MASK 0x1F1F1F1FU
  1277. #define LPDDR4__DENALI_PHY_858_WRITE_MASK 0x1F1F1F1FU
  1278. #define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_1_3_MASK 0x0000001FU
  1279. #define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_1_3_SHIFT 0U
  1280. #define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_1_3_WIDTH 5U
  1281. #define LPDDR4__PHY_PAD_RX_DCD_1_3__REG DENALI_PHY_858
  1282. #define LPDDR4__PHY_PAD_RX_DCD_1_3__FLD LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_1_3
  1283. #define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_2_3_MASK 0x00001F00U
  1284. #define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_2_3_SHIFT 8U
  1285. #define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_2_3_WIDTH 5U
  1286. #define LPDDR4__PHY_PAD_RX_DCD_2_3__REG DENALI_PHY_858
  1287. #define LPDDR4__PHY_PAD_RX_DCD_2_3__FLD LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_2_3
  1288. #define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_3_3_MASK 0x001F0000U
  1289. #define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_3_3_SHIFT 16U
  1290. #define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_3_3_WIDTH 5U
  1291. #define LPDDR4__PHY_PAD_RX_DCD_3_3__REG DENALI_PHY_858
  1292. #define LPDDR4__PHY_PAD_RX_DCD_3_3__FLD LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_3_3
  1293. #define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_4_3_MASK 0x1F000000U
  1294. #define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_4_3_SHIFT 24U
  1295. #define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_4_3_WIDTH 5U
  1296. #define LPDDR4__PHY_PAD_RX_DCD_4_3__REG DENALI_PHY_858
  1297. #define LPDDR4__PHY_PAD_RX_DCD_4_3__FLD LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_4_3
  1298. #define LPDDR4__DENALI_PHY_859_READ_MASK 0x1F1F1F1FU
  1299. #define LPDDR4__DENALI_PHY_859_WRITE_MASK 0x1F1F1F1FU
  1300. #define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_5_3_MASK 0x0000001FU
  1301. #define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_5_3_SHIFT 0U
  1302. #define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_5_3_WIDTH 5U
  1303. #define LPDDR4__PHY_PAD_RX_DCD_5_3__REG DENALI_PHY_859
  1304. #define LPDDR4__PHY_PAD_RX_DCD_5_3__FLD LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_5_3
  1305. #define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_6_3_MASK 0x00001F00U
  1306. #define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_6_3_SHIFT 8U
  1307. #define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_6_3_WIDTH 5U
  1308. #define LPDDR4__PHY_PAD_RX_DCD_6_3__REG DENALI_PHY_859
  1309. #define LPDDR4__PHY_PAD_RX_DCD_6_3__FLD LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_6_3
  1310. #define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_7_3_MASK 0x001F0000U
  1311. #define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_7_3_SHIFT 16U
  1312. #define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_7_3_WIDTH 5U
  1313. #define LPDDR4__PHY_PAD_RX_DCD_7_3__REG DENALI_PHY_859
  1314. #define LPDDR4__PHY_PAD_RX_DCD_7_3__FLD LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_7_3
  1315. #define LPDDR4__DENALI_PHY_859__PHY_PAD_DM_RX_DCD_3_MASK 0x1F000000U
  1316. #define LPDDR4__DENALI_PHY_859__PHY_PAD_DM_RX_DCD_3_SHIFT 24U
  1317. #define LPDDR4__DENALI_PHY_859__PHY_PAD_DM_RX_DCD_3_WIDTH 5U
  1318. #define LPDDR4__PHY_PAD_DM_RX_DCD_3__REG DENALI_PHY_859
  1319. #define LPDDR4__PHY_PAD_DM_RX_DCD_3__FLD LPDDR4__DENALI_PHY_859__PHY_PAD_DM_RX_DCD_3
  1320. #define LPDDR4__DENALI_PHY_860_READ_MASK 0x003F1F1FU
  1321. #define LPDDR4__DENALI_PHY_860_WRITE_MASK 0x003F1F1FU
  1322. #define LPDDR4__DENALI_PHY_860__PHY_PAD_DQS_RX_DCD_3_MASK 0x0000001FU
  1323. #define LPDDR4__DENALI_PHY_860__PHY_PAD_DQS_RX_DCD_3_SHIFT 0U
  1324. #define LPDDR4__DENALI_PHY_860__PHY_PAD_DQS_RX_DCD_3_WIDTH 5U
  1325. #define LPDDR4__PHY_PAD_DQS_RX_DCD_3__REG DENALI_PHY_860
  1326. #define LPDDR4__PHY_PAD_DQS_RX_DCD_3__FLD LPDDR4__DENALI_PHY_860__PHY_PAD_DQS_RX_DCD_3
  1327. #define LPDDR4__DENALI_PHY_860__PHY_PAD_FDBK_RX_DCD_3_MASK 0x00001F00U
  1328. #define LPDDR4__DENALI_PHY_860__PHY_PAD_FDBK_RX_DCD_3_SHIFT 8U
  1329. #define LPDDR4__DENALI_PHY_860__PHY_PAD_FDBK_RX_DCD_3_WIDTH 5U
  1330. #define LPDDR4__PHY_PAD_FDBK_RX_DCD_3__REG DENALI_PHY_860
  1331. #define LPDDR4__PHY_PAD_FDBK_RX_DCD_3__FLD LPDDR4__DENALI_PHY_860__PHY_PAD_FDBK_RX_DCD_3
  1332. #define LPDDR4__DENALI_PHY_860__PHY_PAD_DSLICE_IO_CFG_3_MASK 0x003F0000U
  1333. #define LPDDR4__DENALI_PHY_860__PHY_PAD_DSLICE_IO_CFG_3_SHIFT 16U
  1334. #define LPDDR4__DENALI_PHY_860__PHY_PAD_DSLICE_IO_CFG_3_WIDTH 6U
  1335. #define LPDDR4__PHY_PAD_DSLICE_IO_CFG_3__REG DENALI_PHY_860
  1336. #define LPDDR4__PHY_PAD_DSLICE_IO_CFG_3__FLD LPDDR4__DENALI_PHY_860__PHY_PAD_DSLICE_IO_CFG_3
  1337. #define LPDDR4__DENALI_PHY_861_READ_MASK 0x03FF03FFU
  1338. #define LPDDR4__DENALI_PHY_861_WRITE_MASK 0x03FF03FFU
  1339. #define LPDDR4__DENALI_PHY_861__PHY_RDDQ0_SLAVE_DELAY_3_MASK 0x000003FFU
  1340. #define LPDDR4__DENALI_PHY_861__PHY_RDDQ0_SLAVE_DELAY_3_SHIFT 0U
  1341. #define LPDDR4__DENALI_PHY_861__PHY_RDDQ0_SLAVE_DELAY_3_WIDTH 10U
  1342. #define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_3__REG DENALI_PHY_861
  1343. #define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_861__PHY_RDDQ0_SLAVE_DELAY_3
  1344. #define LPDDR4__DENALI_PHY_861__PHY_RDDQ1_SLAVE_DELAY_3_MASK 0x03FF0000U
  1345. #define LPDDR4__DENALI_PHY_861__PHY_RDDQ1_SLAVE_DELAY_3_SHIFT 16U
  1346. #define LPDDR4__DENALI_PHY_861__PHY_RDDQ1_SLAVE_DELAY_3_WIDTH 10U
  1347. #define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_3__REG DENALI_PHY_861
  1348. #define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_861__PHY_RDDQ1_SLAVE_DELAY_3
  1349. #define LPDDR4__DENALI_PHY_862_READ_MASK 0x03FF03FFU
  1350. #define LPDDR4__DENALI_PHY_862_WRITE_MASK 0x03FF03FFU
  1351. #define LPDDR4__DENALI_PHY_862__PHY_RDDQ2_SLAVE_DELAY_3_MASK 0x000003FFU
  1352. #define LPDDR4__DENALI_PHY_862__PHY_RDDQ2_SLAVE_DELAY_3_SHIFT 0U
  1353. #define LPDDR4__DENALI_PHY_862__PHY_RDDQ2_SLAVE_DELAY_3_WIDTH 10U
  1354. #define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_3__REG DENALI_PHY_862
  1355. #define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_862__PHY_RDDQ2_SLAVE_DELAY_3
  1356. #define LPDDR4__DENALI_PHY_862__PHY_RDDQ3_SLAVE_DELAY_3_MASK 0x03FF0000U
  1357. #define LPDDR4__DENALI_PHY_862__PHY_RDDQ3_SLAVE_DELAY_3_SHIFT 16U
  1358. #define LPDDR4__DENALI_PHY_862__PHY_RDDQ3_SLAVE_DELAY_3_WIDTH 10U
  1359. #define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_3__REG DENALI_PHY_862
  1360. #define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_862__PHY_RDDQ3_SLAVE_DELAY_3
  1361. #define LPDDR4__DENALI_PHY_863_READ_MASK 0x03FF03FFU
  1362. #define LPDDR4__DENALI_PHY_863_WRITE_MASK 0x03FF03FFU
  1363. #define LPDDR4__DENALI_PHY_863__PHY_RDDQ4_SLAVE_DELAY_3_MASK 0x000003FFU
  1364. #define LPDDR4__DENALI_PHY_863__PHY_RDDQ4_SLAVE_DELAY_3_SHIFT 0U
  1365. #define LPDDR4__DENALI_PHY_863__PHY_RDDQ4_SLAVE_DELAY_3_WIDTH 10U
  1366. #define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_3__REG DENALI_PHY_863
  1367. #define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_863__PHY_RDDQ4_SLAVE_DELAY_3
  1368. #define LPDDR4__DENALI_PHY_863__PHY_RDDQ5_SLAVE_DELAY_3_MASK 0x03FF0000U
  1369. #define LPDDR4__DENALI_PHY_863__PHY_RDDQ5_SLAVE_DELAY_3_SHIFT 16U
  1370. #define LPDDR4__DENALI_PHY_863__PHY_RDDQ5_SLAVE_DELAY_3_WIDTH 10U
  1371. #define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_3__REG DENALI_PHY_863
  1372. #define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_863__PHY_RDDQ5_SLAVE_DELAY_3
  1373. #define LPDDR4__DENALI_PHY_864_READ_MASK 0x03FF03FFU
  1374. #define LPDDR4__DENALI_PHY_864_WRITE_MASK 0x03FF03FFU
  1375. #define LPDDR4__DENALI_PHY_864__PHY_RDDQ6_SLAVE_DELAY_3_MASK 0x000003FFU
  1376. #define LPDDR4__DENALI_PHY_864__PHY_RDDQ6_SLAVE_DELAY_3_SHIFT 0U
  1377. #define LPDDR4__DENALI_PHY_864__PHY_RDDQ6_SLAVE_DELAY_3_WIDTH 10U
  1378. #define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_3__REG DENALI_PHY_864
  1379. #define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_864__PHY_RDDQ6_SLAVE_DELAY_3
  1380. #define LPDDR4__DENALI_PHY_864__PHY_RDDQ7_SLAVE_DELAY_3_MASK 0x03FF0000U
  1381. #define LPDDR4__DENALI_PHY_864__PHY_RDDQ7_SLAVE_DELAY_3_SHIFT 16U
  1382. #define LPDDR4__DENALI_PHY_864__PHY_RDDQ7_SLAVE_DELAY_3_WIDTH 10U
  1383. #define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_3__REG DENALI_PHY_864
  1384. #define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_864__PHY_RDDQ7_SLAVE_DELAY_3
  1385. #define LPDDR4__DENALI_PHY_865_READ_MASK 0x000703FFU
  1386. #define LPDDR4__DENALI_PHY_865_WRITE_MASK 0x000703FFU
  1387. #define LPDDR4__DENALI_PHY_865__PHY_RDDM_SLAVE_DELAY_3_MASK 0x000003FFU
  1388. #define LPDDR4__DENALI_PHY_865__PHY_RDDM_SLAVE_DELAY_3_SHIFT 0U
  1389. #define LPDDR4__DENALI_PHY_865__PHY_RDDM_SLAVE_DELAY_3_WIDTH 10U
  1390. #define LPDDR4__PHY_RDDM_SLAVE_DELAY_3__REG DENALI_PHY_865
  1391. #define LPDDR4__PHY_RDDM_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_865__PHY_RDDM_SLAVE_DELAY_3
  1392. #define LPDDR4__DENALI_PHY_865__PHY_DATA_DC_CAL_CLK_SEL_3_MASK 0x00070000U
  1393. #define LPDDR4__DENALI_PHY_865__PHY_DATA_DC_CAL_CLK_SEL_3_SHIFT 16U
  1394. #define LPDDR4__DENALI_PHY_865__PHY_DATA_DC_CAL_CLK_SEL_3_WIDTH 3U
  1395. #define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_3__REG DENALI_PHY_865
  1396. #define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_3__FLD LPDDR4__DENALI_PHY_865__PHY_DATA_DC_CAL_CLK_SEL_3
  1397. #define LPDDR4__DENALI_PHY_866_READ_MASK 0xFFFFFFFFU
  1398. #define LPDDR4__DENALI_PHY_866_WRITE_MASK 0xFFFFFFFFU
  1399. #define LPDDR4__DENALI_PHY_866__PHY_DQ_OE_TIMING_3_MASK 0x000000FFU
  1400. #define LPDDR4__DENALI_PHY_866__PHY_DQ_OE_TIMING_3_SHIFT 0U
  1401. #define LPDDR4__DENALI_PHY_866__PHY_DQ_OE_TIMING_3_WIDTH 8U
  1402. #define LPDDR4__PHY_DQ_OE_TIMING_3__REG DENALI_PHY_866
  1403. #define LPDDR4__PHY_DQ_OE_TIMING_3__FLD LPDDR4__DENALI_PHY_866__PHY_DQ_OE_TIMING_3
  1404. #define LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_RD_TIMING_3_MASK 0x0000FF00U
  1405. #define LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_RD_TIMING_3_SHIFT 8U
  1406. #define LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_RD_TIMING_3_WIDTH 8U
  1407. #define LPDDR4__PHY_DQ_TSEL_RD_TIMING_3__REG DENALI_PHY_866
  1408. #define LPDDR4__PHY_DQ_TSEL_RD_TIMING_3__FLD LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_RD_TIMING_3
  1409. #define LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_WR_TIMING_3_MASK 0x00FF0000U
  1410. #define LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_WR_TIMING_3_SHIFT 16U
  1411. #define LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_WR_TIMING_3_WIDTH 8U
  1412. #define LPDDR4__PHY_DQ_TSEL_WR_TIMING_3__REG DENALI_PHY_866
  1413. #define LPDDR4__PHY_DQ_TSEL_WR_TIMING_3__FLD LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_WR_TIMING_3
  1414. #define LPDDR4__DENALI_PHY_866__PHY_DQS_OE_TIMING_3_MASK 0xFF000000U
  1415. #define LPDDR4__DENALI_PHY_866__PHY_DQS_OE_TIMING_3_SHIFT 24U
  1416. #define LPDDR4__DENALI_PHY_866__PHY_DQS_OE_TIMING_3_WIDTH 8U
  1417. #define LPDDR4__PHY_DQS_OE_TIMING_3__REG DENALI_PHY_866
  1418. #define LPDDR4__PHY_DQS_OE_TIMING_3__FLD LPDDR4__DENALI_PHY_866__PHY_DQS_OE_TIMING_3
  1419. #define LPDDR4__DENALI_PHY_867_READ_MASK 0xFFFFFF0FU
  1420. #define LPDDR4__DENALI_PHY_867_WRITE_MASK 0xFFFFFF0FU
  1421. #define LPDDR4__DENALI_PHY_867__PHY_IO_PAD_DELAY_TIMING_3_MASK 0x0000000FU
  1422. #define LPDDR4__DENALI_PHY_867__PHY_IO_PAD_DELAY_TIMING_3_SHIFT 0U
  1423. #define LPDDR4__DENALI_PHY_867__PHY_IO_PAD_DELAY_TIMING_3_WIDTH 4U
  1424. #define LPDDR4__PHY_IO_PAD_DELAY_TIMING_3__REG DENALI_PHY_867
  1425. #define LPDDR4__PHY_IO_PAD_DELAY_TIMING_3__FLD LPDDR4__DENALI_PHY_867__PHY_IO_PAD_DELAY_TIMING_3
  1426. #define LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_RD_TIMING_3_MASK 0x0000FF00U
  1427. #define LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_RD_TIMING_3_SHIFT 8U
  1428. #define LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_RD_TIMING_3_WIDTH 8U
  1429. #define LPDDR4__PHY_DQS_TSEL_RD_TIMING_3__REG DENALI_PHY_867
  1430. #define LPDDR4__PHY_DQS_TSEL_RD_TIMING_3__FLD LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_RD_TIMING_3
  1431. #define LPDDR4__DENALI_PHY_867__PHY_DQS_OE_RD_TIMING_3_MASK 0x00FF0000U
  1432. #define LPDDR4__DENALI_PHY_867__PHY_DQS_OE_RD_TIMING_3_SHIFT 16U
  1433. #define LPDDR4__DENALI_PHY_867__PHY_DQS_OE_RD_TIMING_3_WIDTH 8U
  1434. #define LPDDR4__PHY_DQS_OE_RD_TIMING_3__REG DENALI_PHY_867
  1435. #define LPDDR4__PHY_DQS_OE_RD_TIMING_3__FLD LPDDR4__DENALI_PHY_867__PHY_DQS_OE_RD_TIMING_3
  1436. #define LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_WR_TIMING_3_MASK 0xFF000000U
  1437. #define LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_WR_TIMING_3_SHIFT 24U
  1438. #define LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_WR_TIMING_3_WIDTH 8U
  1439. #define LPDDR4__PHY_DQS_TSEL_WR_TIMING_3__REG DENALI_PHY_867
  1440. #define LPDDR4__PHY_DQS_TSEL_WR_TIMING_3__FLD LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_WR_TIMING_3
  1441. #define LPDDR4__DENALI_PHY_868_READ_MASK 0x0FFFFFFFU
  1442. #define LPDDR4__DENALI_PHY_868_WRITE_MASK 0x0FFFFFFFU
  1443. #define LPDDR4__DENALI_PHY_868__PHY_VREF_SETTING_TIME_3_MASK 0x0000FFFFU
  1444. #define LPDDR4__DENALI_PHY_868__PHY_VREF_SETTING_TIME_3_SHIFT 0U
  1445. #define LPDDR4__DENALI_PHY_868__PHY_VREF_SETTING_TIME_3_WIDTH 16U
  1446. #define LPDDR4__PHY_VREF_SETTING_TIME_3__REG DENALI_PHY_868
  1447. #define LPDDR4__PHY_VREF_SETTING_TIME_3__FLD LPDDR4__DENALI_PHY_868__PHY_VREF_SETTING_TIME_3
  1448. #define LPDDR4__DENALI_PHY_868__PHY_PAD_VREF_CTRL_DQ_3_MASK 0x0FFF0000U
  1449. #define LPDDR4__DENALI_PHY_868__PHY_PAD_VREF_CTRL_DQ_3_SHIFT 16U
  1450. #define LPDDR4__DENALI_PHY_868__PHY_PAD_VREF_CTRL_DQ_3_WIDTH 12U
  1451. #define LPDDR4__PHY_PAD_VREF_CTRL_DQ_3__REG DENALI_PHY_868
  1452. #define LPDDR4__PHY_PAD_VREF_CTRL_DQ_3__FLD LPDDR4__DENALI_PHY_868__PHY_PAD_VREF_CTRL_DQ_3
  1453. #define LPDDR4__DENALI_PHY_869_READ_MASK 0x03FFFF01U
  1454. #define LPDDR4__DENALI_PHY_869_WRITE_MASK 0x03FFFF01U
  1455. #define LPDDR4__DENALI_PHY_869__PHY_PER_CS_TRAINING_EN_3_MASK 0x00000001U
  1456. #define LPDDR4__DENALI_PHY_869__PHY_PER_CS_TRAINING_EN_3_SHIFT 0U
  1457. #define LPDDR4__DENALI_PHY_869__PHY_PER_CS_TRAINING_EN_3_WIDTH 1U
  1458. #define LPDDR4__DENALI_PHY_869__PHY_PER_CS_TRAINING_EN_3_WOCLR 0U
  1459. #define LPDDR4__DENALI_PHY_869__PHY_PER_CS_TRAINING_EN_3_WOSET 0U
  1460. #define LPDDR4__PHY_PER_CS_TRAINING_EN_3__REG DENALI_PHY_869
  1461. #define LPDDR4__PHY_PER_CS_TRAINING_EN_3__FLD LPDDR4__DENALI_PHY_869__PHY_PER_CS_TRAINING_EN_3
  1462. #define LPDDR4__DENALI_PHY_869__PHY_DQ_IE_TIMING_3_MASK 0x0000FF00U
  1463. #define LPDDR4__DENALI_PHY_869__PHY_DQ_IE_TIMING_3_SHIFT 8U
  1464. #define LPDDR4__DENALI_PHY_869__PHY_DQ_IE_TIMING_3_WIDTH 8U
  1465. #define LPDDR4__PHY_DQ_IE_TIMING_3__REG DENALI_PHY_869
  1466. #define LPDDR4__PHY_DQ_IE_TIMING_3__FLD LPDDR4__DENALI_PHY_869__PHY_DQ_IE_TIMING_3
  1467. #define LPDDR4__DENALI_PHY_869__PHY_DQS_IE_TIMING_3_MASK 0x00FF0000U
  1468. #define LPDDR4__DENALI_PHY_869__PHY_DQS_IE_TIMING_3_SHIFT 16U
  1469. #define LPDDR4__DENALI_PHY_869__PHY_DQS_IE_TIMING_3_WIDTH 8U
  1470. #define LPDDR4__PHY_DQS_IE_TIMING_3__REG DENALI_PHY_869
  1471. #define LPDDR4__PHY_DQS_IE_TIMING_3__FLD LPDDR4__DENALI_PHY_869__PHY_DQS_IE_TIMING_3
  1472. #define LPDDR4__DENALI_PHY_869__PHY_RDDATA_EN_IE_DLY_3_MASK 0x03000000U
  1473. #define LPDDR4__DENALI_PHY_869__PHY_RDDATA_EN_IE_DLY_3_SHIFT 24U
  1474. #define LPDDR4__DENALI_PHY_869__PHY_RDDATA_EN_IE_DLY_3_WIDTH 2U
  1475. #define LPDDR4__PHY_RDDATA_EN_IE_DLY_3__REG DENALI_PHY_869
  1476. #define LPDDR4__PHY_RDDATA_EN_IE_DLY_3__FLD LPDDR4__DENALI_PHY_869__PHY_RDDATA_EN_IE_DLY_3
  1477. #define LPDDR4__DENALI_PHY_870_READ_MASK 0x1F1F0103U
  1478. #define LPDDR4__DENALI_PHY_870_WRITE_MASK 0x1F1F0103U
  1479. #define LPDDR4__DENALI_PHY_870__PHY_IE_MODE_3_MASK 0x00000003U
  1480. #define LPDDR4__DENALI_PHY_870__PHY_IE_MODE_3_SHIFT 0U
  1481. #define LPDDR4__DENALI_PHY_870__PHY_IE_MODE_3_WIDTH 2U
  1482. #define LPDDR4__PHY_IE_MODE_3__REG DENALI_PHY_870
  1483. #define LPDDR4__PHY_IE_MODE_3__FLD LPDDR4__DENALI_PHY_870__PHY_IE_MODE_3
  1484. #define LPDDR4__DENALI_PHY_870__PHY_DBI_MODE_3_MASK 0x00000100U
  1485. #define LPDDR4__DENALI_PHY_870__PHY_DBI_MODE_3_SHIFT 8U
  1486. #define LPDDR4__DENALI_PHY_870__PHY_DBI_MODE_3_WIDTH 1U
  1487. #define LPDDR4__DENALI_PHY_870__PHY_DBI_MODE_3_WOCLR 0U
  1488. #define LPDDR4__DENALI_PHY_870__PHY_DBI_MODE_3_WOSET 0U
  1489. #define LPDDR4__PHY_DBI_MODE_3__REG DENALI_PHY_870
  1490. #define LPDDR4__PHY_DBI_MODE_3__FLD LPDDR4__DENALI_PHY_870__PHY_DBI_MODE_3
  1491. #define LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_TSEL_DLY_3_MASK 0x001F0000U
  1492. #define LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_TSEL_DLY_3_SHIFT 16U
  1493. #define LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_TSEL_DLY_3_WIDTH 5U
  1494. #define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_3__REG DENALI_PHY_870
  1495. #define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_3__FLD LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_TSEL_DLY_3
  1496. #define LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_OE_DLY_3_MASK 0x1F000000U
  1497. #define LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_OE_DLY_3_SHIFT 24U
  1498. #define LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_OE_DLY_3_WIDTH 5U
  1499. #define LPDDR4__PHY_RDDATA_EN_OE_DLY_3__REG DENALI_PHY_870
  1500. #define LPDDR4__PHY_RDDATA_EN_OE_DLY_3__FLD LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_OE_DLY_3
  1501. #define LPDDR4__DENALI_PHY_871_READ_MASK 0x3F07FF0FU
  1502. #define LPDDR4__DENALI_PHY_871_WRITE_MASK 0x3F07FF0FU
  1503. #define LPDDR4__DENALI_PHY_871__PHY_SW_MASTER_MODE_3_MASK 0x0000000FU
  1504. #define LPDDR4__DENALI_PHY_871__PHY_SW_MASTER_MODE_3_SHIFT 0U
  1505. #define LPDDR4__DENALI_PHY_871__PHY_SW_MASTER_MODE_3_WIDTH 4U
  1506. #define LPDDR4__PHY_SW_MASTER_MODE_3__REG DENALI_PHY_871
  1507. #define LPDDR4__PHY_SW_MASTER_MODE_3__FLD LPDDR4__DENALI_PHY_871__PHY_SW_MASTER_MODE_3
  1508. #define LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_START_3_MASK 0x0007FF00U
  1509. #define LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_START_3_SHIFT 8U
  1510. #define LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_START_3_WIDTH 11U
  1511. #define LPDDR4__PHY_MASTER_DELAY_START_3__REG DENALI_PHY_871
  1512. #define LPDDR4__PHY_MASTER_DELAY_START_3__FLD LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_START_3
  1513. #define LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_STEP_3_MASK 0x3F000000U
  1514. #define LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_STEP_3_SHIFT 24U
  1515. #define LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_STEP_3_WIDTH 6U
  1516. #define LPDDR4__PHY_MASTER_DELAY_STEP_3__REG DENALI_PHY_871
  1517. #define LPDDR4__PHY_MASTER_DELAY_STEP_3__FLD LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_STEP_3
  1518. #define LPDDR4__DENALI_PHY_872_READ_MASK 0xFF0FFFFFU
  1519. #define LPDDR4__DENALI_PHY_872_WRITE_MASK 0xFF0FFFFFU
  1520. #define LPDDR4__DENALI_PHY_872__PHY_MASTER_DELAY_WAIT_3_MASK 0x000000FFU
  1521. #define LPDDR4__DENALI_PHY_872__PHY_MASTER_DELAY_WAIT_3_SHIFT 0U
  1522. #define LPDDR4__DENALI_PHY_872__PHY_MASTER_DELAY_WAIT_3_WIDTH 8U
  1523. #define LPDDR4__PHY_MASTER_DELAY_WAIT_3__REG DENALI_PHY_872
  1524. #define LPDDR4__PHY_MASTER_DELAY_WAIT_3__FLD LPDDR4__DENALI_PHY_872__PHY_MASTER_DELAY_WAIT_3
  1525. #define LPDDR4__DENALI_PHY_872__PHY_MASTER_DELAY_HALF_MEASURE_3_MASK 0x0000FF00U
  1526. #define LPDDR4__DENALI_PHY_872__PHY_MASTER_DELAY_HALF_MEASURE_3_SHIFT 8U
  1527. #define LPDDR4__DENALI_PHY_872__PHY_MASTER_DELAY_HALF_MEASURE_3_WIDTH 8U
  1528. #define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_3__REG DENALI_PHY_872
  1529. #define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_3__FLD LPDDR4__DENALI_PHY_872__PHY_MASTER_DELAY_HALF_MEASURE_3
  1530. #define LPDDR4__DENALI_PHY_872__PHY_RPTR_UPDATE_3_MASK 0x000F0000U
  1531. #define LPDDR4__DENALI_PHY_872__PHY_RPTR_UPDATE_3_SHIFT 16U
  1532. #define LPDDR4__DENALI_PHY_872__PHY_RPTR_UPDATE_3_WIDTH 4U
  1533. #define LPDDR4__PHY_RPTR_UPDATE_3__REG DENALI_PHY_872
  1534. #define LPDDR4__PHY_RPTR_UPDATE_3__FLD LPDDR4__DENALI_PHY_872__PHY_RPTR_UPDATE_3
  1535. #define LPDDR4__DENALI_PHY_872__PHY_WRLVL_DLY_STEP_3_MASK 0xFF000000U
  1536. #define LPDDR4__DENALI_PHY_872__PHY_WRLVL_DLY_STEP_3_SHIFT 24U
  1537. #define LPDDR4__DENALI_PHY_872__PHY_WRLVL_DLY_STEP_3_WIDTH 8U
  1538. #define LPDDR4__PHY_WRLVL_DLY_STEP_3__REG DENALI_PHY_872
  1539. #define LPDDR4__PHY_WRLVL_DLY_STEP_3__FLD LPDDR4__DENALI_PHY_872__PHY_WRLVL_DLY_STEP_3
  1540. #define LPDDR4__DENALI_PHY_873_READ_MASK 0x1F0F3F0FU
  1541. #define LPDDR4__DENALI_PHY_873_WRITE_MASK 0x1F0F3F0FU
  1542. #define LPDDR4__DENALI_PHY_873__PHY_WRLVL_DLY_FINE_STEP_3_MASK 0x0000000FU
  1543. #define LPDDR4__DENALI_PHY_873__PHY_WRLVL_DLY_FINE_STEP_3_SHIFT 0U
  1544. #define LPDDR4__DENALI_PHY_873__PHY_WRLVL_DLY_FINE_STEP_3_WIDTH 4U
  1545. #define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_3__REG DENALI_PHY_873
  1546. #define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_3__FLD LPDDR4__DENALI_PHY_873__PHY_WRLVL_DLY_FINE_STEP_3
  1547. #define LPDDR4__DENALI_PHY_873__PHY_WRLVL_RESP_WAIT_CNT_3_MASK 0x00003F00U
  1548. #define LPDDR4__DENALI_PHY_873__PHY_WRLVL_RESP_WAIT_CNT_3_SHIFT 8U
  1549. #define LPDDR4__DENALI_PHY_873__PHY_WRLVL_RESP_WAIT_CNT_3_WIDTH 6U
  1550. #define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_3__REG DENALI_PHY_873
  1551. #define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_873__PHY_WRLVL_RESP_WAIT_CNT_3
  1552. #define LPDDR4__DENALI_PHY_873__PHY_GTLVL_DLY_STEP_3_MASK 0x000F0000U
  1553. #define LPDDR4__DENALI_PHY_873__PHY_GTLVL_DLY_STEP_3_SHIFT 16U
  1554. #define LPDDR4__DENALI_PHY_873__PHY_GTLVL_DLY_STEP_3_WIDTH 4U
  1555. #define LPDDR4__PHY_GTLVL_DLY_STEP_3__REG DENALI_PHY_873
  1556. #define LPDDR4__PHY_GTLVL_DLY_STEP_3__FLD LPDDR4__DENALI_PHY_873__PHY_GTLVL_DLY_STEP_3
  1557. #define LPDDR4__DENALI_PHY_873__PHY_GTLVL_RESP_WAIT_CNT_3_MASK 0x1F000000U
  1558. #define LPDDR4__DENALI_PHY_873__PHY_GTLVL_RESP_WAIT_CNT_3_SHIFT 24U
  1559. #define LPDDR4__DENALI_PHY_873__PHY_GTLVL_RESP_WAIT_CNT_3_WIDTH 5U
  1560. #define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_3__REG DENALI_PHY_873
  1561. #define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_873__PHY_GTLVL_RESP_WAIT_CNT_3
  1562. #define LPDDR4__DENALI_PHY_874_READ_MASK 0x03FF03FFU
  1563. #define LPDDR4__DENALI_PHY_874_WRITE_MASK 0x03FF03FFU
  1564. #define LPDDR4__DENALI_PHY_874__PHY_GTLVL_BACK_STEP_3_MASK 0x000003FFU
  1565. #define LPDDR4__DENALI_PHY_874__PHY_GTLVL_BACK_STEP_3_SHIFT 0U
  1566. #define LPDDR4__DENALI_PHY_874__PHY_GTLVL_BACK_STEP_3_WIDTH 10U
  1567. #define LPDDR4__PHY_GTLVL_BACK_STEP_3__REG DENALI_PHY_874
  1568. #define LPDDR4__PHY_GTLVL_BACK_STEP_3__FLD LPDDR4__DENALI_PHY_874__PHY_GTLVL_BACK_STEP_3
  1569. #define LPDDR4__DENALI_PHY_874__PHY_GTLVL_FINAL_STEP_3_MASK 0x03FF0000U
  1570. #define LPDDR4__DENALI_PHY_874__PHY_GTLVL_FINAL_STEP_3_SHIFT 16U
  1571. #define LPDDR4__DENALI_PHY_874__PHY_GTLVL_FINAL_STEP_3_WIDTH 10U
  1572. #define LPDDR4__PHY_GTLVL_FINAL_STEP_3__REG DENALI_PHY_874
  1573. #define LPDDR4__PHY_GTLVL_FINAL_STEP_3__FLD LPDDR4__DENALI_PHY_874__PHY_GTLVL_FINAL_STEP_3
  1574. #define LPDDR4__DENALI_PHY_875_READ_MASK 0x0F010FFFU
  1575. #define LPDDR4__DENALI_PHY_875_WRITE_MASK 0x0F010FFFU
  1576. #define LPDDR4__DENALI_PHY_875__PHY_WDQLVL_DLY_STEP_3_MASK 0x000000FFU
  1577. #define LPDDR4__DENALI_PHY_875__PHY_WDQLVL_DLY_STEP_3_SHIFT 0U
  1578. #define LPDDR4__DENALI_PHY_875__PHY_WDQLVL_DLY_STEP_3_WIDTH 8U
  1579. #define LPDDR4__PHY_WDQLVL_DLY_STEP_3__REG DENALI_PHY_875
  1580. #define LPDDR4__PHY_WDQLVL_DLY_STEP_3__FLD LPDDR4__DENALI_PHY_875__PHY_WDQLVL_DLY_STEP_3
  1581. #define LPDDR4__DENALI_PHY_875__PHY_WDQLVL_QTR_DLY_STEP_3_MASK 0x00000F00U
  1582. #define LPDDR4__DENALI_PHY_875__PHY_WDQLVL_QTR_DLY_STEP_3_SHIFT 8U
  1583. #define LPDDR4__DENALI_PHY_875__PHY_WDQLVL_QTR_DLY_STEP_3_WIDTH 4U
  1584. #define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_3__REG DENALI_PHY_875
  1585. #define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_3__FLD LPDDR4__DENALI_PHY_875__PHY_WDQLVL_QTR_DLY_STEP_3
  1586. #define LPDDR4__DENALI_PHY_875__PHY_TOGGLE_PRE_SUPPORT_3_MASK 0x00010000U
  1587. #define LPDDR4__DENALI_PHY_875__PHY_TOGGLE_PRE_SUPPORT_3_SHIFT 16U
  1588. #define LPDDR4__DENALI_PHY_875__PHY_TOGGLE_PRE_SUPPORT_3_WIDTH 1U
  1589. #define LPDDR4__DENALI_PHY_875__PHY_TOGGLE_PRE_SUPPORT_3_WOCLR 0U
  1590. #define LPDDR4__DENALI_PHY_875__PHY_TOGGLE_PRE_SUPPORT_3_WOSET 0U
  1591. #define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_3__REG DENALI_PHY_875
  1592. #define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_3__FLD LPDDR4__DENALI_PHY_875__PHY_TOGGLE_PRE_SUPPORT_3
  1593. #define LPDDR4__DENALI_PHY_875__PHY_RDLVL_DLY_STEP_3_MASK 0x0F000000U
  1594. #define LPDDR4__DENALI_PHY_875__PHY_RDLVL_DLY_STEP_3_SHIFT 24U
  1595. #define LPDDR4__DENALI_PHY_875__PHY_RDLVL_DLY_STEP_3_WIDTH 4U
  1596. #define LPDDR4__PHY_RDLVL_DLY_STEP_3__REG DENALI_PHY_875
  1597. #define LPDDR4__PHY_RDLVL_DLY_STEP_3__FLD LPDDR4__DENALI_PHY_875__PHY_RDLVL_DLY_STEP_3
  1598. #define LPDDR4__DENALI_PHY_876_READ_MASK 0x000003FFU
  1599. #define LPDDR4__DENALI_PHY_876_WRITE_MASK 0x000003FFU
  1600. #define LPDDR4__DENALI_PHY_876__PHY_RDLVL_MAX_EDGE_3_MASK 0x000003FFU
  1601. #define LPDDR4__DENALI_PHY_876__PHY_RDLVL_MAX_EDGE_3_SHIFT 0U
  1602. #define LPDDR4__DENALI_PHY_876__PHY_RDLVL_MAX_EDGE_3_WIDTH 10U
  1603. #define LPDDR4__PHY_RDLVL_MAX_EDGE_3__REG DENALI_PHY_876
  1604. #define LPDDR4__PHY_RDLVL_MAX_EDGE_3__FLD LPDDR4__DENALI_PHY_876__PHY_RDLVL_MAX_EDGE_3
  1605. #define LPDDR4__DENALI_PHY_877_READ_MASK 0x3F0103FFU
  1606. #define LPDDR4__DENALI_PHY_877_WRITE_MASK 0x3F0103FFU
  1607. #define LPDDR4__DENALI_PHY_877__PHY_RDLVL_DVW_MIN_3_MASK 0x000003FFU
  1608. #define LPDDR4__DENALI_PHY_877__PHY_RDLVL_DVW_MIN_3_SHIFT 0U
  1609. #define LPDDR4__DENALI_PHY_877__PHY_RDLVL_DVW_MIN_3_WIDTH 10U
  1610. #define LPDDR4__PHY_RDLVL_DVW_MIN_3__REG DENALI_PHY_877
  1611. #define LPDDR4__PHY_RDLVL_DVW_MIN_3__FLD LPDDR4__DENALI_PHY_877__PHY_RDLVL_DVW_MIN_3
  1612. #define LPDDR4__DENALI_PHY_877__PHY_SW_RDLVL_DVW_MIN_EN_3_MASK 0x00010000U
  1613. #define LPDDR4__DENALI_PHY_877__PHY_SW_RDLVL_DVW_MIN_EN_3_SHIFT 16U
  1614. #define LPDDR4__DENALI_PHY_877__PHY_SW_RDLVL_DVW_MIN_EN_3_WIDTH 1U
  1615. #define LPDDR4__DENALI_PHY_877__PHY_SW_RDLVL_DVW_MIN_EN_3_WOCLR 0U
  1616. #define LPDDR4__DENALI_PHY_877__PHY_SW_RDLVL_DVW_MIN_EN_3_WOSET 0U
  1617. #define LPDDR4__PHY_SW_RDLVL_DVW_MIN_EN_3__REG DENALI_PHY_877
  1618. #define LPDDR4__PHY_SW_RDLVL_DVW_MIN_EN_3__FLD LPDDR4__DENALI_PHY_877__PHY_SW_RDLVL_DVW_MIN_EN_3
  1619. #define LPDDR4__DENALI_PHY_877__PHY_RDLVL_PER_START_OFFSET_3_MASK 0x3F000000U
  1620. #define LPDDR4__DENALI_PHY_877__PHY_RDLVL_PER_START_OFFSET_3_SHIFT 24U
  1621. #define LPDDR4__DENALI_PHY_877__PHY_RDLVL_PER_START_OFFSET_3_WIDTH 6U
  1622. #define LPDDR4__PHY_RDLVL_PER_START_OFFSET_3__REG DENALI_PHY_877
  1623. #define LPDDR4__PHY_RDLVL_PER_START_OFFSET_3__FLD LPDDR4__DENALI_PHY_877__PHY_RDLVL_PER_START_OFFSET_3
  1624. #define LPDDR4__DENALI_PHY_878_READ_MASK 0x00030703U
  1625. #define LPDDR4__DENALI_PHY_878_WRITE_MASK 0x00030703U
  1626. #define LPDDR4__DENALI_PHY_878__PHY_WRPATH_GATE_DISABLE_3_MASK 0x00000003U
  1627. #define LPDDR4__DENALI_PHY_878__PHY_WRPATH_GATE_DISABLE_3_SHIFT 0U
  1628. #define LPDDR4__DENALI_PHY_878__PHY_WRPATH_GATE_DISABLE_3_WIDTH 2U
  1629. #define LPDDR4__PHY_WRPATH_GATE_DISABLE_3__REG DENALI_PHY_878
  1630. #define LPDDR4__PHY_WRPATH_GATE_DISABLE_3__FLD LPDDR4__DENALI_PHY_878__PHY_WRPATH_GATE_DISABLE_3
  1631. #define LPDDR4__DENALI_PHY_878__PHY_WRPATH_GATE_TIMING_3_MASK 0x00000700U
  1632. #define LPDDR4__DENALI_PHY_878__PHY_WRPATH_GATE_TIMING_3_SHIFT 8U
  1633. #define LPDDR4__DENALI_PHY_878__PHY_WRPATH_GATE_TIMING_3_WIDTH 3U
  1634. #define LPDDR4__PHY_WRPATH_GATE_TIMING_3__REG DENALI_PHY_878
  1635. #define LPDDR4__PHY_WRPATH_GATE_TIMING_3__FLD LPDDR4__DENALI_PHY_878__PHY_WRPATH_GATE_TIMING_3
  1636. #define LPDDR4__DENALI_PHY_878__PHY_DATA_DC_INIT_DISABLE_3_MASK 0x00030000U
  1637. #define LPDDR4__DENALI_PHY_878__PHY_DATA_DC_INIT_DISABLE_3_SHIFT 16U
  1638. #define LPDDR4__DENALI_PHY_878__PHY_DATA_DC_INIT_DISABLE_3_WIDTH 2U
  1639. #define LPDDR4__PHY_DATA_DC_INIT_DISABLE_3__REG DENALI_PHY_878
  1640. #define LPDDR4__PHY_DATA_DC_INIT_DISABLE_3__FLD LPDDR4__DENALI_PHY_878__PHY_DATA_DC_INIT_DISABLE_3
  1641. #define LPDDR4__DENALI_PHY_879_READ_MASK 0x07FF03FFU
  1642. #define LPDDR4__DENALI_PHY_879_WRITE_MASK 0x07FF03FFU
  1643. #define LPDDR4__DENALI_PHY_879__PHY_DATA_DC_DQS_INIT_SLV_DELAY_3_MASK 0x000003FFU
  1644. #define LPDDR4__DENALI_PHY_879__PHY_DATA_DC_DQS_INIT_SLV_DELAY_3_SHIFT 0U
  1645. #define LPDDR4__DENALI_PHY_879__PHY_DATA_DC_DQS_INIT_SLV_DELAY_3_WIDTH 10U
  1646. #define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_3__REG DENALI_PHY_879
  1647. #define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_3__FLD LPDDR4__DENALI_PHY_879__PHY_DATA_DC_DQS_INIT_SLV_DELAY_3
  1648. #define LPDDR4__DENALI_PHY_879__PHY_DATA_DC_DQ_INIT_SLV_DELAY_3_MASK 0x07FF0000U
  1649. #define LPDDR4__DENALI_PHY_879__PHY_DATA_DC_DQ_INIT_SLV_DELAY_3_SHIFT 16U
  1650. #define LPDDR4__DENALI_PHY_879__PHY_DATA_DC_DQ_INIT_SLV_DELAY_3_WIDTH 11U
  1651. #define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_3__REG DENALI_PHY_879
  1652. #define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_3__FLD LPDDR4__DENALI_PHY_879__PHY_DATA_DC_DQ_INIT_SLV_DELAY_3
  1653. #define LPDDR4__DENALI_PHY_880_READ_MASK 0xFFFF0101U
  1654. #define LPDDR4__DENALI_PHY_880_WRITE_MASK 0xFFFF0101U
  1655. #define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WRLVL_ENABLE_3_MASK 0x00000001U
  1656. #define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WRLVL_ENABLE_3_SHIFT 0U
  1657. #define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WRLVL_ENABLE_3_WIDTH 1U
  1658. #define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WRLVL_ENABLE_3_WOCLR 0U
  1659. #define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WRLVL_ENABLE_3_WOSET 0U
  1660. #define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_3__REG DENALI_PHY_880
  1661. #define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_3__FLD LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WRLVL_ENABLE_3
  1662. #define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WDQLVL_ENABLE_3_MASK 0x00000100U
  1663. #define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WDQLVL_ENABLE_3_SHIFT 8U
  1664. #define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WDQLVL_ENABLE_3_WIDTH 1U
  1665. #define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WDQLVL_ENABLE_3_WOCLR 0U
  1666. #define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WDQLVL_ENABLE_3_WOSET 0U
  1667. #define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_3__REG DENALI_PHY_880
  1668. #define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_3__FLD LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WDQLVL_ENABLE_3
  1669. #define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_DM_CLK_SE_THRSHLD_3_MASK 0x00FF0000U
  1670. #define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_DM_CLK_SE_THRSHLD_3_SHIFT 16U
  1671. #define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_DM_CLK_SE_THRSHLD_3_WIDTH 8U
  1672. #define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_3__REG DENALI_PHY_880
  1673. #define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_3__FLD LPDDR4__DENALI_PHY_880__PHY_DATA_DC_DM_CLK_SE_THRSHLD_3
  1674. #define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3_MASK 0xFF000000U
  1675. #define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3_SHIFT 24U
  1676. #define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3_WIDTH 8U
  1677. #define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3__REG DENALI_PHY_880
  1678. #define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3__FLD LPDDR4__DENALI_PHY_880__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3
  1679. #define LPDDR4__DENALI_PHY_881_READ_MASK 0x001F3F7FU
  1680. #define LPDDR4__DENALI_PHY_881_WRITE_MASK 0x001F3F7FU
  1681. #define LPDDR4__DENALI_PHY_881__PHY_WDQ_OSC_DELTA_3_MASK 0x0000007FU
  1682. #define LPDDR4__DENALI_PHY_881__PHY_WDQ_OSC_DELTA_3_SHIFT 0U
  1683. #define LPDDR4__DENALI_PHY_881__PHY_WDQ_OSC_DELTA_3_WIDTH 7U
  1684. #define LPDDR4__PHY_WDQ_OSC_DELTA_3__REG DENALI_PHY_881
  1685. #define LPDDR4__PHY_WDQ_OSC_DELTA_3__FLD LPDDR4__DENALI_PHY_881__PHY_WDQ_OSC_DELTA_3
  1686. #define LPDDR4__DENALI_PHY_881__PHY_MEAS_DLY_STEP_ENABLE_3_MASK 0x00003F00U
  1687. #define LPDDR4__DENALI_PHY_881__PHY_MEAS_DLY_STEP_ENABLE_3_SHIFT 8U
  1688. #define LPDDR4__DENALI_PHY_881__PHY_MEAS_DLY_STEP_ENABLE_3_WIDTH 6U
  1689. #define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_3__REG DENALI_PHY_881
  1690. #define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_3__FLD LPDDR4__DENALI_PHY_881__PHY_MEAS_DLY_STEP_ENABLE_3
  1691. #define LPDDR4__DENALI_PHY_881__PHY_RDDATA_EN_DLY_3_MASK 0x001F0000U
  1692. #define LPDDR4__DENALI_PHY_881__PHY_RDDATA_EN_DLY_3_SHIFT 16U
  1693. #define LPDDR4__DENALI_PHY_881__PHY_RDDATA_EN_DLY_3_WIDTH 5U
  1694. #define LPDDR4__PHY_RDDATA_EN_DLY_3__REG DENALI_PHY_881
  1695. #define LPDDR4__PHY_RDDATA_EN_DLY_3__FLD LPDDR4__DENALI_PHY_881__PHY_RDDATA_EN_DLY_3
  1696. #define LPDDR4__DENALI_PHY_882_READ_MASK 0xFFFFFFFFU
  1697. #define LPDDR4__DENALI_PHY_882_WRITE_MASK 0xFFFFFFFFU
  1698. #define LPDDR4__DENALI_PHY_882__PHY_DQ_DM_SWIZZLE0_3_MASK 0xFFFFFFFFU
  1699. #define LPDDR4__DENALI_PHY_882__PHY_DQ_DM_SWIZZLE0_3_SHIFT 0U
  1700. #define LPDDR4__DENALI_PHY_882__PHY_DQ_DM_SWIZZLE0_3_WIDTH 32U
  1701. #define LPDDR4__PHY_DQ_DM_SWIZZLE0_3__REG DENALI_PHY_882
  1702. #define LPDDR4__PHY_DQ_DM_SWIZZLE0_3__FLD LPDDR4__DENALI_PHY_882__PHY_DQ_DM_SWIZZLE0_3
  1703. #define LPDDR4__DENALI_PHY_883_READ_MASK 0x0000000FU
  1704. #define LPDDR4__DENALI_PHY_883_WRITE_MASK 0x0000000FU
  1705. #define LPDDR4__DENALI_PHY_883__PHY_DQ_DM_SWIZZLE1_3_MASK 0x0000000FU
  1706. #define LPDDR4__DENALI_PHY_883__PHY_DQ_DM_SWIZZLE1_3_SHIFT 0U
  1707. #define LPDDR4__DENALI_PHY_883__PHY_DQ_DM_SWIZZLE1_3_WIDTH 4U
  1708. #define LPDDR4__PHY_DQ_DM_SWIZZLE1_3__REG DENALI_PHY_883
  1709. #define LPDDR4__PHY_DQ_DM_SWIZZLE1_3__FLD LPDDR4__DENALI_PHY_883__PHY_DQ_DM_SWIZZLE1_3
  1710. #define LPDDR4__DENALI_PHY_884_READ_MASK 0x07FF07FFU
  1711. #define LPDDR4__DENALI_PHY_884_WRITE_MASK 0x07FF07FFU
  1712. #define LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ0_SLAVE_DELAY_3_MASK 0x000007FFU
  1713. #define LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ0_SLAVE_DELAY_3_SHIFT 0U
  1714. #define LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ0_SLAVE_DELAY_3_WIDTH 11U
  1715. #define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_3__REG DENALI_PHY_884
  1716. #define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ0_SLAVE_DELAY_3
  1717. #define LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ1_SLAVE_DELAY_3_MASK 0x07FF0000U
  1718. #define LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ1_SLAVE_DELAY_3_SHIFT 16U
  1719. #define LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ1_SLAVE_DELAY_3_WIDTH 11U
  1720. #define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_3__REG DENALI_PHY_884
  1721. #define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ1_SLAVE_DELAY_3
  1722. #define LPDDR4__DENALI_PHY_885_READ_MASK 0x07FF07FFU
  1723. #define LPDDR4__DENALI_PHY_885_WRITE_MASK 0x07FF07FFU
  1724. #define LPDDR4__DENALI_PHY_885__PHY_CLK_WRDQ2_SLAVE_DELAY_3_MASK 0x000007FFU
  1725. #define LPDDR4__DENALI_PHY_885__PHY_CLK_WRDQ2_SLAVE_DELAY_3_SHIFT 0U
  1726. #define LPDDR4__DENALI_PHY_885__PHY_CLK_WRDQ2_SLAVE_DELAY_3_WIDTH 11U
  1727. #define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_3__REG DENALI_PHY_885
  1728. #define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_885__PHY_CLK_WRDQ2_SLAVE_DELAY_3
  1729. #define LPDDR4__DENALI_PHY_885__PHY_CLK_WRDQ3_SLAVE_DELAY_3_MASK 0x07FF0000U
  1730. #define LPDDR4__DENALI_PHY_885__PHY_CLK_WRDQ3_SLAVE_DELAY_3_SHIFT 16U
  1731. #define LPDDR4__DENALI_PHY_885__PHY_CLK_WRDQ3_SLAVE_DELAY_3_WIDTH 11U
  1732. #define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_3__REG DENALI_PHY_885
  1733. #define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_885__PHY_CLK_WRDQ3_SLAVE_DELAY_3
  1734. #define LPDDR4__DENALI_PHY_886_READ_MASK 0x07FF07FFU
  1735. #define LPDDR4__DENALI_PHY_886_WRITE_MASK 0x07FF07FFU
  1736. #define LPDDR4__DENALI_PHY_886__PHY_CLK_WRDQ4_SLAVE_DELAY_3_MASK 0x000007FFU
  1737. #define LPDDR4__DENALI_PHY_886__PHY_CLK_WRDQ4_SLAVE_DELAY_3_SHIFT 0U
  1738. #define LPDDR4__DENALI_PHY_886__PHY_CLK_WRDQ4_SLAVE_DELAY_3_WIDTH 11U
  1739. #define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_3__REG DENALI_PHY_886
  1740. #define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_886__PHY_CLK_WRDQ4_SLAVE_DELAY_3
  1741. #define LPDDR4__DENALI_PHY_886__PHY_CLK_WRDQ5_SLAVE_DELAY_3_MASK 0x07FF0000U
  1742. #define LPDDR4__DENALI_PHY_886__PHY_CLK_WRDQ5_SLAVE_DELAY_3_SHIFT 16U
  1743. #define LPDDR4__DENALI_PHY_886__PHY_CLK_WRDQ5_SLAVE_DELAY_3_WIDTH 11U
  1744. #define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_3__REG DENALI_PHY_886
  1745. #define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_886__PHY_CLK_WRDQ5_SLAVE_DELAY_3
  1746. #define LPDDR4__DENALI_PHY_887_READ_MASK 0x07FF07FFU
  1747. #define LPDDR4__DENALI_PHY_887_WRITE_MASK 0x07FF07FFU
  1748. #define LPDDR4__DENALI_PHY_887__PHY_CLK_WRDQ6_SLAVE_DELAY_3_MASK 0x000007FFU
  1749. #define LPDDR4__DENALI_PHY_887__PHY_CLK_WRDQ6_SLAVE_DELAY_3_SHIFT 0U
  1750. #define LPDDR4__DENALI_PHY_887__PHY_CLK_WRDQ6_SLAVE_DELAY_3_WIDTH 11U
  1751. #define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_3__REG DENALI_PHY_887
  1752. #define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_887__PHY_CLK_WRDQ6_SLAVE_DELAY_3
  1753. #define LPDDR4__DENALI_PHY_887__PHY_CLK_WRDQ7_SLAVE_DELAY_3_MASK 0x07FF0000U
  1754. #define LPDDR4__DENALI_PHY_887__PHY_CLK_WRDQ7_SLAVE_DELAY_3_SHIFT 16U
  1755. #define LPDDR4__DENALI_PHY_887__PHY_CLK_WRDQ7_SLAVE_DELAY_3_WIDTH 11U
  1756. #define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_3__REG DENALI_PHY_887
  1757. #define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_887__PHY_CLK_WRDQ7_SLAVE_DELAY_3
  1758. #define LPDDR4__DENALI_PHY_888_READ_MASK 0x03FF07FFU
  1759. #define LPDDR4__DENALI_PHY_888_WRITE_MASK 0x03FF07FFU
  1760. #define LPDDR4__DENALI_PHY_888__PHY_CLK_WRDM_SLAVE_DELAY_3_MASK 0x000007FFU
  1761. #define LPDDR4__DENALI_PHY_888__PHY_CLK_WRDM_SLAVE_DELAY_3_SHIFT 0U
  1762. #define LPDDR4__DENALI_PHY_888__PHY_CLK_WRDM_SLAVE_DELAY_3_WIDTH 11U
  1763. #define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_3__REG DENALI_PHY_888
  1764. #define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_888__PHY_CLK_WRDM_SLAVE_DELAY_3
  1765. #define LPDDR4__DENALI_PHY_888__PHY_CLK_WRDQS_SLAVE_DELAY_3_MASK 0x03FF0000U
  1766. #define LPDDR4__DENALI_PHY_888__PHY_CLK_WRDQS_SLAVE_DELAY_3_SHIFT 16U
  1767. #define LPDDR4__DENALI_PHY_888__PHY_CLK_WRDQS_SLAVE_DELAY_3_WIDTH 10U
  1768. #define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_3__REG DENALI_PHY_888
  1769. #define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_888__PHY_CLK_WRDQS_SLAVE_DELAY_3
  1770. #define LPDDR4__DENALI_PHY_889_READ_MASK 0x0003FF03U
  1771. #define LPDDR4__DENALI_PHY_889_WRITE_MASK 0x0003FF03U
  1772. #define LPDDR4__DENALI_PHY_889__PHY_WRLVL_THRESHOLD_ADJUST_3_MASK 0x00000003U
  1773. #define LPDDR4__DENALI_PHY_889__PHY_WRLVL_THRESHOLD_ADJUST_3_SHIFT 0U
  1774. #define LPDDR4__DENALI_PHY_889__PHY_WRLVL_THRESHOLD_ADJUST_3_WIDTH 2U
  1775. #define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_3__REG DENALI_PHY_889
  1776. #define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_3__FLD LPDDR4__DENALI_PHY_889__PHY_WRLVL_THRESHOLD_ADJUST_3
  1777. #define LPDDR4__DENALI_PHY_889__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3_MASK 0x0003FF00U
  1778. #define LPDDR4__DENALI_PHY_889__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3_SHIFT 8U
  1779. #define LPDDR4__DENALI_PHY_889__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3_WIDTH 10U
  1780. #define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3__REG DENALI_PHY_889
  1781. #define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_889__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3
  1782. #define LPDDR4__DENALI_PHY_890_READ_MASK 0x03FF03FFU
  1783. #define LPDDR4__DENALI_PHY_890_WRITE_MASK 0x03FF03FFU
  1784. #define LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
  1785. #define LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3_SHIFT 0U
  1786. #define LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3_WIDTH 10U
  1787. #define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3__REG DENALI_PHY_890
  1788. #define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3
  1789. #define LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U
  1790. #define LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3_SHIFT 16U
  1791. #define LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3_WIDTH 10U
  1792. #define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3__REG DENALI_PHY_890
  1793. #define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3
  1794. #define LPDDR4__DENALI_PHY_891_READ_MASK 0x03FF03FFU
  1795. #define LPDDR4__DENALI_PHY_891_WRITE_MASK 0x03FF03FFU
  1796. #define LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
  1797. #define LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3_SHIFT 0U
  1798. #define LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3_WIDTH 10U
  1799. #define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3__REG DENALI_PHY_891
  1800. #define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3
  1801. #define LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U
  1802. #define LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3_SHIFT 16U
  1803. #define LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3_WIDTH 10U
  1804. #define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3__REG DENALI_PHY_891
  1805. #define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3
  1806. #define LPDDR4__DENALI_PHY_892_READ_MASK 0x03FF03FFU
  1807. #define LPDDR4__DENALI_PHY_892_WRITE_MASK 0x03FF03FFU
  1808. #define LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
  1809. #define LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3_SHIFT 0U
  1810. #define LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3_WIDTH 10U
  1811. #define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3__REG DENALI_PHY_892
  1812. #define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3
  1813. #define LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U
  1814. #define LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3_SHIFT 16U
  1815. #define LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3_WIDTH 10U
  1816. #define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3__REG DENALI_PHY_892
  1817. #define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3
  1818. #define LPDDR4__DENALI_PHY_893_READ_MASK 0x03FF03FFU
  1819. #define LPDDR4__DENALI_PHY_893_WRITE_MASK 0x03FF03FFU
  1820. #define LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
  1821. #define LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3_SHIFT 0U
  1822. #define LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3_WIDTH 10U
  1823. #define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3__REG DENALI_PHY_893
  1824. #define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3
  1825. #define LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U
  1826. #define LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3_SHIFT 16U
  1827. #define LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3_WIDTH 10U
  1828. #define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3__REG DENALI_PHY_893
  1829. #define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3
  1830. #define LPDDR4__DENALI_PHY_894_READ_MASK 0x03FF03FFU
  1831. #define LPDDR4__DENALI_PHY_894_WRITE_MASK 0x03FF03FFU
  1832. #define LPDDR4__DENALI_PHY_894__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
  1833. #define LPDDR4__DENALI_PHY_894__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3_SHIFT 0U
  1834. #define LPDDR4__DENALI_PHY_894__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3_WIDTH 10U
  1835. #define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3__REG DENALI_PHY_894
  1836. #define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_894__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3
  1837. #define LPDDR4__DENALI_PHY_894__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U
  1838. #define LPDDR4__DENALI_PHY_894__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3_SHIFT 16U
  1839. #define LPDDR4__DENALI_PHY_894__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3_WIDTH 10U
  1840. #define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3__REG DENALI_PHY_894
  1841. #define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_894__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3
  1842. #define LPDDR4__DENALI_PHY_895_READ_MASK 0x03FF03FFU
  1843. #define LPDDR4__DENALI_PHY_895_WRITE_MASK 0x03FF03FFU
  1844. #define LPDDR4__DENALI_PHY_895__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
  1845. #define LPDDR4__DENALI_PHY_895__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3_SHIFT 0U
  1846. #define LPDDR4__DENALI_PHY_895__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3_WIDTH 10U
  1847. #define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3__REG DENALI_PHY_895
  1848. #define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_895__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3
  1849. #define LPDDR4__DENALI_PHY_895__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U
  1850. #define LPDDR4__DENALI_PHY_895__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3_SHIFT 16U
  1851. #define LPDDR4__DENALI_PHY_895__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3_WIDTH 10U
  1852. #define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3__REG DENALI_PHY_895
  1853. #define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_895__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3
  1854. #define LPDDR4__DENALI_PHY_896_READ_MASK 0x03FF03FFU
  1855. #define LPDDR4__DENALI_PHY_896_WRITE_MASK 0x03FF03FFU
  1856. #define LPDDR4__DENALI_PHY_896__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
  1857. #define LPDDR4__DENALI_PHY_896__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3_SHIFT 0U
  1858. #define LPDDR4__DENALI_PHY_896__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3_WIDTH 10U
  1859. #define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3__REG DENALI_PHY_896
  1860. #define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_896__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3
  1861. #define LPDDR4__DENALI_PHY_896__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U
  1862. #define LPDDR4__DENALI_PHY_896__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3_SHIFT 16U
  1863. #define LPDDR4__DENALI_PHY_896__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3_WIDTH 10U
  1864. #define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3__REG DENALI_PHY_896
  1865. #define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_896__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3
  1866. #define LPDDR4__DENALI_PHY_897_READ_MASK 0x03FF03FFU
  1867. #define LPDDR4__DENALI_PHY_897_WRITE_MASK 0x03FF03FFU
  1868. #define LPDDR4__DENALI_PHY_897__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
  1869. #define LPDDR4__DENALI_PHY_897__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3_SHIFT 0U
  1870. #define LPDDR4__DENALI_PHY_897__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3_WIDTH 10U
  1871. #define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3__REG DENALI_PHY_897
  1872. #define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_897__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3
  1873. #define LPDDR4__DENALI_PHY_897__PHY_RDDQS_DM_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U
  1874. #define LPDDR4__DENALI_PHY_897__PHY_RDDQS_DM_RISE_SLAVE_DELAY_3_SHIFT 16U
  1875. #define LPDDR4__DENALI_PHY_897__PHY_RDDQS_DM_RISE_SLAVE_DELAY_3_WIDTH 10U
  1876. #define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_3__REG DENALI_PHY_897
  1877. #define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_897__PHY_RDDQS_DM_RISE_SLAVE_DELAY_3
  1878. #define LPDDR4__DENALI_PHY_898_READ_MASK 0x03FF03FFU
  1879. #define LPDDR4__DENALI_PHY_898_WRITE_MASK 0x03FF03FFU
  1880. #define LPDDR4__DENALI_PHY_898__PHY_RDDQS_DM_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
  1881. #define LPDDR4__DENALI_PHY_898__PHY_RDDQS_DM_FALL_SLAVE_DELAY_3_SHIFT 0U
  1882. #define LPDDR4__DENALI_PHY_898__PHY_RDDQS_DM_FALL_SLAVE_DELAY_3_WIDTH 10U
  1883. #define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_3__REG DENALI_PHY_898
  1884. #define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_898__PHY_RDDQS_DM_FALL_SLAVE_DELAY_3
  1885. #define LPDDR4__DENALI_PHY_898__PHY_RDDQS_GATE_SLAVE_DELAY_3_MASK 0x03FF0000U
  1886. #define LPDDR4__DENALI_PHY_898__PHY_RDDQS_GATE_SLAVE_DELAY_3_SHIFT 16U
  1887. #define LPDDR4__DENALI_PHY_898__PHY_RDDQS_GATE_SLAVE_DELAY_3_WIDTH 10U
  1888. #define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_3__REG DENALI_PHY_898
  1889. #define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_898__PHY_RDDQS_GATE_SLAVE_DELAY_3
  1890. #define LPDDR4__DENALI_PHY_899_READ_MASK 0x03FF070FU
  1891. #define LPDDR4__DENALI_PHY_899_WRITE_MASK 0x03FF070FU
  1892. #define LPDDR4__DENALI_PHY_899__PHY_RDDQS_LATENCY_ADJUST_3_MASK 0x0000000FU
  1893. #define LPDDR4__DENALI_PHY_899__PHY_RDDQS_LATENCY_ADJUST_3_SHIFT 0U
  1894. #define LPDDR4__DENALI_PHY_899__PHY_RDDQS_LATENCY_ADJUST_3_WIDTH 4U
  1895. #define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_3__REG DENALI_PHY_899
  1896. #define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_3__FLD LPDDR4__DENALI_PHY_899__PHY_RDDQS_LATENCY_ADJUST_3
  1897. #define LPDDR4__DENALI_PHY_899__PHY_WRITE_PATH_LAT_ADD_3_MASK 0x00000700U
  1898. #define LPDDR4__DENALI_PHY_899__PHY_WRITE_PATH_LAT_ADD_3_SHIFT 8U
  1899. #define LPDDR4__DENALI_PHY_899__PHY_WRITE_PATH_LAT_ADD_3_WIDTH 3U
  1900. #define LPDDR4__PHY_WRITE_PATH_LAT_ADD_3__REG DENALI_PHY_899
  1901. #define LPDDR4__PHY_WRITE_PATH_LAT_ADD_3__FLD LPDDR4__DENALI_PHY_899__PHY_WRITE_PATH_LAT_ADD_3
  1902. #define LPDDR4__DENALI_PHY_899__PHY_WRLVL_DELAY_EARLY_THRESHOLD_3_MASK 0x03FF0000U
  1903. #define LPDDR4__DENALI_PHY_899__PHY_WRLVL_DELAY_EARLY_THRESHOLD_3_SHIFT 16U
  1904. #define LPDDR4__DENALI_PHY_899__PHY_WRLVL_DELAY_EARLY_THRESHOLD_3_WIDTH 10U
  1905. #define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_3__REG DENALI_PHY_899
  1906. #define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_3__FLD LPDDR4__DENALI_PHY_899__PHY_WRLVL_DELAY_EARLY_THRESHOLD_3
  1907. #define LPDDR4__DENALI_PHY_900_READ_MASK 0x000103FFU
  1908. #define LPDDR4__DENALI_PHY_900_WRITE_MASK 0x000103FFU
  1909. #define LPDDR4__DENALI_PHY_900__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3_MASK 0x000003FFU
  1910. #define LPDDR4__DENALI_PHY_900__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3_SHIFT 0U
  1911. #define LPDDR4__DENALI_PHY_900__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3_WIDTH 10U
  1912. #define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3__REG DENALI_PHY_900
  1913. #define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3__FLD LPDDR4__DENALI_PHY_900__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3
  1914. #define LPDDR4__DENALI_PHY_900__PHY_WRLVL_EARLY_FORCE_ZERO_3_MASK 0x00010000U
  1915. #define LPDDR4__DENALI_PHY_900__PHY_WRLVL_EARLY_FORCE_ZERO_3_SHIFT 16U
  1916. #define LPDDR4__DENALI_PHY_900__PHY_WRLVL_EARLY_FORCE_ZERO_3_WIDTH 1U
  1917. #define LPDDR4__DENALI_PHY_900__PHY_WRLVL_EARLY_FORCE_ZERO_3_WOCLR 0U
  1918. #define LPDDR4__DENALI_PHY_900__PHY_WRLVL_EARLY_FORCE_ZERO_3_WOSET 0U
  1919. #define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_3__REG DENALI_PHY_900
  1920. #define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_3__FLD LPDDR4__DENALI_PHY_900__PHY_WRLVL_EARLY_FORCE_ZERO_3
  1921. #define LPDDR4__DENALI_PHY_901_READ_MASK 0x000F03FFU
  1922. #define LPDDR4__DENALI_PHY_901_WRITE_MASK 0x000F03FFU
  1923. #define LPDDR4__DENALI_PHY_901__PHY_GTLVL_RDDQS_SLV_DLY_START_3_MASK 0x000003FFU
  1924. #define LPDDR4__DENALI_PHY_901__PHY_GTLVL_RDDQS_SLV_DLY_START_3_SHIFT 0U
  1925. #define LPDDR4__DENALI_PHY_901__PHY_GTLVL_RDDQS_SLV_DLY_START_3_WIDTH 10U
  1926. #define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_3__REG DENALI_PHY_901
  1927. #define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_3__FLD LPDDR4__DENALI_PHY_901__PHY_GTLVL_RDDQS_SLV_DLY_START_3
  1928. #define LPDDR4__DENALI_PHY_901__PHY_GTLVL_LAT_ADJ_START_3_MASK 0x000F0000U
  1929. #define LPDDR4__DENALI_PHY_901__PHY_GTLVL_LAT_ADJ_START_3_SHIFT 16U
  1930. #define LPDDR4__DENALI_PHY_901__PHY_GTLVL_LAT_ADJ_START_3_WIDTH 4U
  1931. #define LPDDR4__PHY_GTLVL_LAT_ADJ_START_3__REG DENALI_PHY_901
  1932. #define LPDDR4__PHY_GTLVL_LAT_ADJ_START_3__FLD LPDDR4__DENALI_PHY_901__PHY_GTLVL_LAT_ADJ_START_3
  1933. #define LPDDR4__DENALI_PHY_902_READ_MASK 0x010F07FFU
  1934. #define LPDDR4__DENALI_PHY_902_WRITE_MASK 0x010F07FFU
  1935. #define LPDDR4__DENALI_PHY_902__PHY_WDQLVL_DQDM_SLV_DLY_START_3_MASK 0x000007FFU
  1936. #define LPDDR4__DENALI_PHY_902__PHY_WDQLVL_DQDM_SLV_DLY_START_3_SHIFT 0U
  1937. #define LPDDR4__DENALI_PHY_902__PHY_WDQLVL_DQDM_SLV_DLY_START_3_WIDTH 11U
  1938. #define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_3__REG DENALI_PHY_902
  1939. #define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_3__FLD LPDDR4__DENALI_PHY_902__PHY_WDQLVL_DQDM_SLV_DLY_START_3
  1940. #define LPDDR4__DENALI_PHY_902__PHY_NTP_WRLAT_START_3_MASK 0x000F0000U
  1941. #define LPDDR4__DENALI_PHY_902__PHY_NTP_WRLAT_START_3_SHIFT 16U
  1942. #define LPDDR4__DENALI_PHY_902__PHY_NTP_WRLAT_START_3_WIDTH 4U
  1943. #define LPDDR4__PHY_NTP_WRLAT_START_3__REG DENALI_PHY_902
  1944. #define LPDDR4__PHY_NTP_WRLAT_START_3__FLD LPDDR4__DENALI_PHY_902__PHY_NTP_WRLAT_START_3
  1945. #define LPDDR4__DENALI_PHY_902__PHY_NTP_PASS_3_MASK 0x01000000U
  1946. #define LPDDR4__DENALI_PHY_902__PHY_NTP_PASS_3_SHIFT 24U
  1947. #define LPDDR4__DENALI_PHY_902__PHY_NTP_PASS_3_WIDTH 1U
  1948. #define LPDDR4__DENALI_PHY_902__PHY_NTP_PASS_3_WOCLR 0U
  1949. #define LPDDR4__DENALI_PHY_902__PHY_NTP_PASS_3_WOSET 0U
  1950. #define LPDDR4__PHY_NTP_PASS_3__REG DENALI_PHY_902
  1951. #define LPDDR4__PHY_NTP_PASS_3__FLD LPDDR4__DENALI_PHY_902__PHY_NTP_PASS_3
  1952. #define LPDDR4__DENALI_PHY_903_READ_MASK 0x000003FFU
  1953. #define LPDDR4__DENALI_PHY_903_WRITE_MASK 0x000003FFU
  1954. #define LPDDR4__DENALI_PHY_903__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3_MASK 0x000003FFU
  1955. #define LPDDR4__DENALI_PHY_903__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3_SHIFT 0U
  1956. #define LPDDR4__DENALI_PHY_903__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3_WIDTH 10U
  1957. #define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3__REG DENALI_PHY_903
  1958. #define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3__FLD LPDDR4__DENALI_PHY_903__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3
  1959. #define LPDDR4__DENALI_PHY_904_READ_MASK 0xFFFFFFFFU
  1960. #define LPDDR4__DENALI_PHY_904_WRITE_MASK 0xFFFFFFFFU
  1961. #define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQS_CLK_ADJUST_3_MASK 0x000000FFU
  1962. #define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQS_CLK_ADJUST_3_SHIFT 0U
  1963. #define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQS_CLK_ADJUST_3_WIDTH 8U
  1964. #define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_3__REG DENALI_PHY_904
  1965. #define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQS_CLK_ADJUST_3
  1966. #define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQ0_CLK_ADJUST_3_MASK 0x0000FF00U
  1967. #define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQ0_CLK_ADJUST_3_SHIFT 8U
  1968. #define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQ0_CLK_ADJUST_3_WIDTH 8U
  1969. #define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_3__REG DENALI_PHY_904
  1970. #define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQ0_CLK_ADJUST_3
  1971. #define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQ1_CLK_ADJUST_3_MASK 0x00FF0000U
  1972. #define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQ1_CLK_ADJUST_3_SHIFT 16U
  1973. #define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQ1_CLK_ADJUST_3_WIDTH 8U
  1974. #define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_3__REG DENALI_PHY_904
  1975. #define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQ1_CLK_ADJUST_3
  1976. #define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQ2_CLK_ADJUST_3_MASK 0xFF000000U
  1977. #define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQ2_CLK_ADJUST_3_SHIFT 24U
  1978. #define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQ2_CLK_ADJUST_3_WIDTH 8U
  1979. #define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_3__REG DENALI_PHY_904
  1980. #define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQ2_CLK_ADJUST_3
  1981. #define LPDDR4__DENALI_PHY_905_READ_MASK 0xFFFFFFFFU
  1982. #define LPDDR4__DENALI_PHY_905_WRITE_MASK 0xFFFFFFFFU
  1983. #define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ3_CLK_ADJUST_3_MASK 0x000000FFU
  1984. #define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ3_CLK_ADJUST_3_SHIFT 0U
  1985. #define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ3_CLK_ADJUST_3_WIDTH 8U
  1986. #define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_3__REG DENALI_PHY_905
  1987. #define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ3_CLK_ADJUST_3
  1988. #define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ4_CLK_ADJUST_3_MASK 0x0000FF00U
  1989. #define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ4_CLK_ADJUST_3_SHIFT 8U
  1990. #define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ4_CLK_ADJUST_3_WIDTH 8U
  1991. #define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_3__REG DENALI_PHY_905
  1992. #define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ4_CLK_ADJUST_3
  1993. #define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ5_CLK_ADJUST_3_MASK 0x00FF0000U
  1994. #define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ5_CLK_ADJUST_3_SHIFT 16U
  1995. #define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ5_CLK_ADJUST_3_WIDTH 8U
  1996. #define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_3__REG DENALI_PHY_905
  1997. #define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ5_CLK_ADJUST_3
  1998. #define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ6_CLK_ADJUST_3_MASK 0xFF000000U
  1999. #define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ6_CLK_ADJUST_3_SHIFT 24U
  2000. #define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ6_CLK_ADJUST_3_WIDTH 8U
  2001. #define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_3__REG DENALI_PHY_905
  2002. #define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ6_CLK_ADJUST_3
  2003. #define LPDDR4__DENALI_PHY_906_READ_MASK 0xFFFFFFFFU
  2004. #define LPDDR4__DENALI_PHY_906_WRITE_MASK 0xFFFFFFFFU
  2005. #define LPDDR4__DENALI_PHY_906__PHY_DATA_DC_DQ7_CLK_ADJUST_3_MASK 0x000000FFU
  2006. #define LPDDR4__DENALI_PHY_906__PHY_DATA_DC_DQ7_CLK_ADJUST_3_SHIFT 0U
  2007. #define LPDDR4__DENALI_PHY_906__PHY_DATA_DC_DQ7_CLK_ADJUST_3_WIDTH 8U
  2008. #define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_3__REG DENALI_PHY_906
  2009. #define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_906__PHY_DATA_DC_DQ7_CLK_ADJUST_3
  2010. #define LPDDR4__DENALI_PHY_906__PHY_DATA_DC_DM_CLK_ADJUST_3_MASK 0x0000FF00U
  2011. #define LPDDR4__DENALI_PHY_906__PHY_DATA_DC_DM_CLK_ADJUST_3_SHIFT 8U
  2012. #define LPDDR4__DENALI_PHY_906__PHY_DATA_DC_DM_CLK_ADJUST_3_WIDTH 8U
  2013. #define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_3__REG DENALI_PHY_906
  2014. #define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_906__PHY_DATA_DC_DM_CLK_ADJUST_3
  2015. #define LPDDR4__DENALI_PHY_906__PHY_DSLICE_PAD_BOOSTPN_SETTING_3_MASK 0xFFFF0000U
  2016. #define LPDDR4__DENALI_PHY_906__PHY_DSLICE_PAD_BOOSTPN_SETTING_3_SHIFT 16U
  2017. #define LPDDR4__DENALI_PHY_906__PHY_DSLICE_PAD_BOOSTPN_SETTING_3_WIDTH 16U
  2018. #define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_3__REG DENALI_PHY_906
  2019. #define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_3__FLD LPDDR4__DENALI_PHY_906__PHY_DSLICE_PAD_BOOSTPN_SETTING_3
  2020. #define LPDDR4__DENALI_PHY_907_READ_MASK 0x0003033FU
  2021. #define LPDDR4__DENALI_PHY_907_WRITE_MASK 0x0003033FU
  2022. #define LPDDR4__DENALI_PHY_907__PHY_DSLICE_PAD_RX_CTLE_SETTING_3_MASK 0x0000003FU
  2023. #define LPDDR4__DENALI_PHY_907__PHY_DSLICE_PAD_RX_CTLE_SETTING_3_SHIFT 0U
  2024. #define LPDDR4__DENALI_PHY_907__PHY_DSLICE_PAD_RX_CTLE_SETTING_3_WIDTH 6U
  2025. #define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_3__REG DENALI_PHY_907
  2026. #define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_3__FLD LPDDR4__DENALI_PHY_907__PHY_DSLICE_PAD_RX_CTLE_SETTING_3
  2027. #define LPDDR4__DENALI_PHY_907__PHY_DQ_FFE_3_MASK 0x00000300U
  2028. #define LPDDR4__DENALI_PHY_907__PHY_DQ_FFE_3_SHIFT 8U
  2029. #define LPDDR4__DENALI_PHY_907__PHY_DQ_FFE_3_WIDTH 2U
  2030. #define LPDDR4__PHY_DQ_FFE_3__REG DENALI_PHY_907
  2031. #define LPDDR4__PHY_DQ_FFE_3__FLD LPDDR4__DENALI_PHY_907__PHY_DQ_FFE_3
  2032. #define LPDDR4__DENALI_PHY_907__PHY_DQS_FFE_3_MASK 0x00030000U
  2033. #define LPDDR4__DENALI_PHY_907__PHY_DQS_FFE_3_SHIFT 16U
  2034. #define LPDDR4__DENALI_PHY_907__PHY_DQS_FFE_3_WIDTH 2U
  2035. #define LPDDR4__PHY_DQS_FFE_3__REG DENALI_PHY_907
  2036. #define LPDDR4__PHY_DQS_FFE_3__FLD LPDDR4__DENALI_PHY_907__PHY_DQS_FFE_3
  2037. #endif /* REG_LPDDR4_DATA_SLICE_3_MACROS_H_ */