lpddr4_data_slice_1_macros.h 152 KB

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  1. /* SPDX-License-Identifier: BSD-3-Clause */
  2. /**********************************************************************
  3. * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
  4. *
  5. * THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT
  6. *
  7. **********************************************************************
  8. */
  9. #ifndef REG_LPDDR4_DATA_SLICE_1_MACROS_H_
  10. #define REG_LPDDR4_DATA_SLICE_1_MACROS_H_
  11. #define LPDDR4__DENALI_PHY_256_READ_MASK 0x000F07FFU
  12. #define LPDDR4__DENALI_PHY_256_WRITE_MASK 0x000F07FFU
  13. #define LPDDR4__DENALI_PHY_256__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1_MASK 0x000007FFU
  14. #define LPDDR4__DENALI_PHY_256__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1_SHIFT 0U
  15. #define LPDDR4__DENALI_PHY_256__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1_WIDTH 11U
  16. #define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1__REG DENALI_PHY_256
  17. #define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_256__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1
  18. #define LPDDR4__DENALI_PHY_256__PHY_IO_PAD_DELAY_TIMING_BYPASS_1_MASK 0x000F0000U
  19. #define LPDDR4__DENALI_PHY_256__PHY_IO_PAD_DELAY_TIMING_BYPASS_1_SHIFT 16U
  20. #define LPDDR4__DENALI_PHY_256__PHY_IO_PAD_DELAY_TIMING_BYPASS_1_WIDTH 4U
  21. #define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_1__REG DENALI_PHY_256
  22. #define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_1__FLD LPDDR4__DENALI_PHY_256__PHY_IO_PAD_DELAY_TIMING_BYPASS_1
  23. #define LPDDR4__DENALI_PHY_257_READ_MASK 0x000703FFU
  24. #define LPDDR4__DENALI_PHY_257_WRITE_MASK 0x000703FFU
  25. #define LPDDR4__DENALI_PHY_257__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1_MASK 0x000003FFU
  26. #define LPDDR4__DENALI_PHY_257__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1_SHIFT 0U
  27. #define LPDDR4__DENALI_PHY_257__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1_WIDTH 10U
  28. #define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1__REG DENALI_PHY_257
  29. #define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1__FLD LPDDR4__DENALI_PHY_257__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1
  30. #define LPDDR4__DENALI_PHY_257__PHY_WRITE_PATH_LAT_ADD_BYPASS_1_MASK 0x00070000U
  31. #define LPDDR4__DENALI_PHY_257__PHY_WRITE_PATH_LAT_ADD_BYPASS_1_SHIFT 16U
  32. #define LPDDR4__DENALI_PHY_257__PHY_WRITE_PATH_LAT_ADD_BYPASS_1_WIDTH 3U
  33. #define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_1__REG DENALI_PHY_257
  34. #define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_1__FLD LPDDR4__DENALI_PHY_257__PHY_WRITE_PATH_LAT_ADD_BYPASS_1
  35. #define LPDDR4__DENALI_PHY_258_READ_MASK 0x010303FFU
  36. #define LPDDR4__DENALI_PHY_258_WRITE_MASK 0x010303FFU
  37. #define LPDDR4__DENALI_PHY_258__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1_MASK 0x000003FFU
  38. #define LPDDR4__DENALI_PHY_258__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1_SHIFT 0U
  39. #define LPDDR4__DENALI_PHY_258__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1_WIDTH 10U
  40. #define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1__REG DENALI_PHY_258
  41. #define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_258__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1
  42. #define LPDDR4__DENALI_PHY_258__PHY_BYPASS_TWO_CYC_PREAMBLE_1_MASK 0x00030000U
  43. #define LPDDR4__DENALI_PHY_258__PHY_BYPASS_TWO_CYC_PREAMBLE_1_SHIFT 16U
  44. #define LPDDR4__DENALI_PHY_258__PHY_BYPASS_TWO_CYC_PREAMBLE_1_WIDTH 2U
  45. #define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_1__REG DENALI_PHY_258
  46. #define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_1__FLD LPDDR4__DENALI_PHY_258__PHY_BYPASS_TWO_CYC_PREAMBLE_1
  47. #define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_MASK 0x01000000U
  48. #define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_SHIFT 24U
  49. #define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_WIDTH 1U
  50. #define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_WOCLR 0U
  51. #define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_WOSET 0U
  52. #define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_1__REG DENALI_PHY_258
  53. #define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_1__FLD LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1
  54. #define LPDDR4__DENALI_PHY_259_READ_MASK 0x3F3F3F3FU
  55. #define LPDDR4__DENALI_PHY_259_WRITE_MASK 0x3F3F3F3FU
  56. #define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1_MASK 0x0000003FU
  57. #define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1_SHIFT 0U
  58. #define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1_WIDTH 6U
  59. #define LPDDR4__PHY_SW_WRDQ0_SHIFT_1__REG DENALI_PHY_259
  60. #define LPDDR4__PHY_SW_WRDQ0_SHIFT_1__FLD LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1
  61. #define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1_MASK 0x00003F00U
  62. #define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1_SHIFT 8U
  63. #define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1_WIDTH 6U
  64. #define LPDDR4__PHY_SW_WRDQ1_SHIFT_1__REG DENALI_PHY_259
  65. #define LPDDR4__PHY_SW_WRDQ1_SHIFT_1__FLD LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1
  66. #define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1_MASK 0x003F0000U
  67. #define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1_SHIFT 16U
  68. #define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1_WIDTH 6U
  69. #define LPDDR4__PHY_SW_WRDQ2_SHIFT_1__REG DENALI_PHY_259
  70. #define LPDDR4__PHY_SW_WRDQ2_SHIFT_1__FLD LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1
  71. #define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1_MASK 0x3F000000U
  72. #define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1_SHIFT 24U
  73. #define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1_WIDTH 6U
  74. #define LPDDR4__PHY_SW_WRDQ3_SHIFT_1__REG DENALI_PHY_259
  75. #define LPDDR4__PHY_SW_WRDQ3_SHIFT_1__FLD LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1
  76. #define LPDDR4__DENALI_PHY_260_READ_MASK 0x3F3F3F3FU
  77. #define LPDDR4__DENALI_PHY_260_WRITE_MASK 0x3F3F3F3FU
  78. #define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1_MASK 0x0000003FU
  79. #define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1_SHIFT 0U
  80. #define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1_WIDTH 6U
  81. #define LPDDR4__PHY_SW_WRDQ4_SHIFT_1__REG DENALI_PHY_260
  82. #define LPDDR4__PHY_SW_WRDQ4_SHIFT_1__FLD LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1
  83. #define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1_MASK 0x00003F00U
  84. #define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1_SHIFT 8U
  85. #define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1_WIDTH 6U
  86. #define LPDDR4__PHY_SW_WRDQ5_SHIFT_1__REG DENALI_PHY_260
  87. #define LPDDR4__PHY_SW_WRDQ5_SHIFT_1__FLD LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1
  88. #define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1_MASK 0x003F0000U
  89. #define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1_SHIFT 16U
  90. #define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1_WIDTH 6U
  91. #define LPDDR4__PHY_SW_WRDQ6_SHIFT_1__REG DENALI_PHY_260
  92. #define LPDDR4__PHY_SW_WRDQ6_SHIFT_1__FLD LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1
  93. #define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1_MASK 0x3F000000U
  94. #define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1_SHIFT 24U
  95. #define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1_WIDTH 6U
  96. #define LPDDR4__PHY_SW_WRDQ7_SHIFT_1__REG DENALI_PHY_260
  97. #define LPDDR4__PHY_SW_WRDQ7_SHIFT_1__FLD LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1
  98. #define LPDDR4__DENALI_PHY_261_READ_MASK 0x01030F3FU
  99. #define LPDDR4__DENALI_PHY_261_WRITE_MASK 0x01030F3FU
  100. #define LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1_MASK 0x0000003FU
  101. #define LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1_SHIFT 0U
  102. #define LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1_WIDTH 6U
  103. #define LPDDR4__PHY_SW_WRDM_SHIFT_1__REG DENALI_PHY_261
  104. #define LPDDR4__PHY_SW_WRDM_SHIFT_1__FLD LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1
  105. #define LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1_MASK 0x00000F00U
  106. #define LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1_SHIFT 8U
  107. #define LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1_WIDTH 4U
  108. #define LPDDR4__PHY_SW_WRDQS_SHIFT_1__REG DENALI_PHY_261
  109. #define LPDDR4__PHY_SW_WRDQS_SHIFT_1__FLD LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1
  110. #define LPDDR4__DENALI_PHY_261__PHY_PER_RANK_CS_MAP_1_MASK 0x00030000U
  111. #define LPDDR4__DENALI_PHY_261__PHY_PER_RANK_CS_MAP_1_SHIFT 16U
  112. #define LPDDR4__DENALI_PHY_261__PHY_PER_RANK_CS_MAP_1_WIDTH 2U
  113. #define LPDDR4__PHY_PER_RANK_CS_MAP_1__REG DENALI_PHY_261
  114. #define LPDDR4__PHY_PER_RANK_CS_MAP_1__FLD LPDDR4__DENALI_PHY_261__PHY_PER_RANK_CS_MAP_1
  115. #define LPDDR4__DENALI_PHY_261__PHY_PER_CS_TRAINING_MULTICAST_EN_1_MASK 0x01000000U
  116. #define LPDDR4__DENALI_PHY_261__PHY_PER_CS_TRAINING_MULTICAST_EN_1_SHIFT 24U
  117. #define LPDDR4__DENALI_PHY_261__PHY_PER_CS_TRAINING_MULTICAST_EN_1_WIDTH 1U
  118. #define LPDDR4__DENALI_PHY_261__PHY_PER_CS_TRAINING_MULTICAST_EN_1_WOCLR 0U
  119. #define LPDDR4__DENALI_PHY_261__PHY_PER_CS_TRAINING_MULTICAST_EN_1_WOSET 0U
  120. #define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_1__REG DENALI_PHY_261
  121. #define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_1__FLD LPDDR4__DENALI_PHY_261__PHY_PER_CS_TRAINING_MULTICAST_EN_1
  122. #define LPDDR4__DENALI_PHY_262_READ_MASK 0x1F1F0301U
  123. #define LPDDR4__DENALI_PHY_262_WRITE_MASK 0x1F1F0301U
  124. #define LPDDR4__DENALI_PHY_262__PHY_PER_CS_TRAINING_INDEX_1_MASK 0x00000001U
  125. #define LPDDR4__DENALI_PHY_262__PHY_PER_CS_TRAINING_INDEX_1_SHIFT 0U
  126. #define LPDDR4__DENALI_PHY_262__PHY_PER_CS_TRAINING_INDEX_1_WIDTH 1U
  127. #define LPDDR4__DENALI_PHY_262__PHY_PER_CS_TRAINING_INDEX_1_WOCLR 0U
  128. #define LPDDR4__DENALI_PHY_262__PHY_PER_CS_TRAINING_INDEX_1_WOSET 0U
  129. #define LPDDR4__PHY_PER_CS_TRAINING_INDEX_1__REG DENALI_PHY_262
  130. #define LPDDR4__PHY_PER_CS_TRAINING_INDEX_1__FLD LPDDR4__DENALI_PHY_262__PHY_PER_CS_TRAINING_INDEX_1
  131. #define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1_MASK 0x00000300U
  132. #define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1_SHIFT 8U
  133. #define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1_WIDTH 2U
  134. #define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1__REG DENALI_PHY_262
  135. #define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1__FLD LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1
  136. #define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_DLY_1_MASK 0x001F0000U
  137. #define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_DLY_1_SHIFT 16U
  138. #define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_DLY_1_WIDTH 5U
  139. #define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_1__REG DENALI_PHY_262
  140. #define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_1__FLD LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_DLY_1
  141. #define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1_MASK 0x1F000000U
  142. #define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1_SHIFT 24U
  143. #define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1_WIDTH 5U
  144. #define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1__REG DENALI_PHY_262
  145. #define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1__FLD LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1
  146. #define LPDDR4__DENALI_PHY_263_READ_MASK 0x1F030F0FU
  147. #define LPDDR4__DENALI_PHY_263_WRITE_MASK 0x1F030F0FU
  148. #define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RPTR_UPDATE_1_MASK 0x0000000FU
  149. #define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RPTR_UPDATE_1_SHIFT 0U
  150. #define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RPTR_UPDATE_1_WIDTH 4U
  151. #define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_1__REG DENALI_PHY_263
  152. #define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_1__FLD LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RPTR_UPDATE_1
  153. #define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1_MASK 0x00000F00U
  154. #define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1_SHIFT 8U
  155. #define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1_WIDTH 4U
  156. #define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1__REG DENALI_PHY_263
  157. #define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1__FLD LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1
  158. #define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1_MASK 0x00030000U
  159. #define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1_SHIFT 16U
  160. #define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1_WIDTH 2U
  161. #define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1__REG DENALI_PHY_263
  162. #define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1
  163. #define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1_MASK 0x1F000000U
  164. #define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1_SHIFT 24U
  165. #define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1_WIDTH 5U
  166. #define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1__REG DENALI_PHY_263
  167. #define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1__FLD LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1
  168. #define LPDDR4__DENALI_PHY_264_READ_MASK 0x0101FF03U
  169. #define LPDDR4__DENALI_PHY_264_WRITE_MASK 0x0101FF03U
  170. #define LPDDR4__DENALI_PHY_264__PHY_CTRL_LPBK_EN_1_MASK 0x00000003U
  171. #define LPDDR4__DENALI_PHY_264__PHY_CTRL_LPBK_EN_1_SHIFT 0U
  172. #define LPDDR4__DENALI_PHY_264__PHY_CTRL_LPBK_EN_1_WIDTH 2U
  173. #define LPDDR4__PHY_CTRL_LPBK_EN_1__REG DENALI_PHY_264
  174. #define LPDDR4__PHY_CTRL_LPBK_EN_1__FLD LPDDR4__DENALI_PHY_264__PHY_CTRL_LPBK_EN_1
  175. #define LPDDR4__DENALI_PHY_264__PHY_LPBK_CONTROL_1_MASK 0x0001FF00U
  176. #define LPDDR4__DENALI_PHY_264__PHY_LPBK_CONTROL_1_SHIFT 8U
  177. #define LPDDR4__DENALI_PHY_264__PHY_LPBK_CONTROL_1_WIDTH 9U
  178. #define LPDDR4__PHY_LPBK_CONTROL_1__REG DENALI_PHY_264
  179. #define LPDDR4__PHY_LPBK_CONTROL_1__FLD LPDDR4__DENALI_PHY_264__PHY_LPBK_CONTROL_1
  180. #define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_MASK 0x01000000U
  181. #define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_SHIFT 24U
  182. #define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_WIDTH 1U
  183. #define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_WOCLR 0U
  184. #define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_WOSET 0U
  185. #define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_1__REG DENALI_PHY_264
  186. #define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_1__FLD LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1
  187. #define LPDDR4__DENALI_PHY_265_READ_MASK 0xFFFFFFFFU
  188. #define LPDDR4__DENALI_PHY_265_WRITE_MASK 0xFFFFFFFFU
  189. #define LPDDR4__DENALI_PHY_265__PHY_AUTO_TIMING_MARGIN_CONTROL_1_MASK 0xFFFFFFFFU
  190. #define LPDDR4__DENALI_PHY_265__PHY_AUTO_TIMING_MARGIN_CONTROL_1_SHIFT 0U
  191. #define LPDDR4__DENALI_PHY_265__PHY_AUTO_TIMING_MARGIN_CONTROL_1_WIDTH 32U
  192. #define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_1__REG DENALI_PHY_265
  193. #define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_1__FLD LPDDR4__DENALI_PHY_265__PHY_AUTO_TIMING_MARGIN_CONTROL_1
  194. #define LPDDR4__DENALI_PHY_266_READ_MASK 0x0FFFFFFFU
  195. #define LPDDR4__DENALI_PHY_266_WRITE_MASK 0x0FFFFFFFU
  196. #define LPDDR4__DENALI_PHY_266__PHY_AUTO_TIMING_MARGIN_OBS_1_MASK 0x0FFFFFFFU
  197. #define LPDDR4__DENALI_PHY_266__PHY_AUTO_TIMING_MARGIN_OBS_1_SHIFT 0U
  198. #define LPDDR4__DENALI_PHY_266__PHY_AUTO_TIMING_MARGIN_OBS_1_WIDTH 28U
  199. #define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_1__REG DENALI_PHY_266
  200. #define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_1__FLD LPDDR4__DENALI_PHY_266__PHY_AUTO_TIMING_MARGIN_OBS_1
  201. #define LPDDR4__DENALI_PHY_267_READ_MASK 0x0101FF7FU
  202. #define LPDDR4__DENALI_PHY_267_WRITE_MASK 0x0101FF7FU
  203. #define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_START_1_MASK 0x0000007FU
  204. #define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_START_1_SHIFT 0U
  205. #define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_START_1_WIDTH 7U
  206. #define LPDDR4__PHY_PRBS_PATTERN_START_1__REG DENALI_PHY_267
  207. #define LPDDR4__PHY_PRBS_PATTERN_START_1__FLD LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_START_1
  208. #define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_MASK_1_MASK 0x0001FF00U
  209. #define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_MASK_1_SHIFT 8U
  210. #define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_MASK_1_WIDTH 9U
  211. #define LPDDR4__PHY_PRBS_PATTERN_MASK_1__REG DENALI_PHY_267
  212. #define LPDDR4__PHY_PRBS_PATTERN_MASK_1__FLD LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_MASK_1
  213. #define LPDDR4__DENALI_PHY_267__PHY_RDLVL_MULTI_PATT_ENABLE_1_MASK 0x01000000U
  214. #define LPDDR4__DENALI_PHY_267__PHY_RDLVL_MULTI_PATT_ENABLE_1_SHIFT 24U
  215. #define LPDDR4__DENALI_PHY_267__PHY_RDLVL_MULTI_PATT_ENABLE_1_WIDTH 1U
  216. #define LPDDR4__DENALI_PHY_267__PHY_RDLVL_MULTI_PATT_ENABLE_1_WOCLR 0U
  217. #define LPDDR4__DENALI_PHY_267__PHY_RDLVL_MULTI_PATT_ENABLE_1_WOSET 0U
  218. #define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_1__REG DENALI_PHY_267
  219. #define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_1__FLD LPDDR4__DENALI_PHY_267__PHY_RDLVL_MULTI_PATT_ENABLE_1
  220. #define LPDDR4__DENALI_PHY_268_READ_MASK 0x007F3F01U
  221. #define LPDDR4__DENALI_PHY_268_WRITE_MASK 0x007F3F01U
  222. #define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_MASK 0x00000001U
  223. #define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_SHIFT 0U
  224. #define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_WIDTH 1U
  225. #define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_WOCLR 0U
  226. #define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_WOSET 0U
  227. #define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1__REG DENALI_PHY_268
  228. #define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1__FLD LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1
  229. #define LPDDR4__DENALI_PHY_268__PHY_VREF_INITIAL_STEPSIZE_1_MASK 0x00003F00U
  230. #define LPDDR4__DENALI_PHY_268__PHY_VREF_INITIAL_STEPSIZE_1_SHIFT 8U
  231. #define LPDDR4__DENALI_PHY_268__PHY_VREF_INITIAL_STEPSIZE_1_WIDTH 6U
  232. #define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_1__REG DENALI_PHY_268
  233. #define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_1__FLD LPDDR4__DENALI_PHY_268__PHY_VREF_INITIAL_STEPSIZE_1
  234. #define LPDDR4__DENALI_PHY_268__PHY_VREF_TRAIN_OBS_1_MASK 0x007F0000U
  235. #define LPDDR4__DENALI_PHY_268__PHY_VREF_TRAIN_OBS_1_SHIFT 16U
  236. #define LPDDR4__DENALI_PHY_268__PHY_VREF_TRAIN_OBS_1_WIDTH 7U
  237. #define LPDDR4__PHY_VREF_TRAIN_OBS_1__REG DENALI_PHY_268
  238. #define LPDDR4__PHY_VREF_TRAIN_OBS_1__FLD LPDDR4__DENALI_PHY_268__PHY_VREF_TRAIN_OBS_1
  239. #define LPDDR4__DENALI_PHY_269_READ_MASK 0x000F03FFU
  240. #define LPDDR4__DENALI_PHY_269_WRITE_MASK 0x000F03FFU
  241. #define LPDDR4__DENALI_PHY_269__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1_MASK 0x000003FFU
  242. #define LPDDR4__DENALI_PHY_269__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1_SHIFT 0U
  243. #define LPDDR4__DENALI_PHY_269__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1_WIDTH 10U
  244. #define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1__REG DENALI_PHY_269
  245. #define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_269__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1
  246. #define LPDDR4__DENALI_PHY_269__PHY_GATE_ERROR_DELAY_SELECT_1_MASK 0x000F0000U
  247. #define LPDDR4__DENALI_PHY_269__PHY_GATE_ERROR_DELAY_SELECT_1_SHIFT 16U
  248. #define LPDDR4__DENALI_PHY_269__PHY_GATE_ERROR_DELAY_SELECT_1_WIDTH 4U
  249. #define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_1__REG DENALI_PHY_269
  250. #define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_1__FLD LPDDR4__DENALI_PHY_269__PHY_GATE_ERROR_DELAY_SELECT_1
  251. #define LPDDR4__DENALI_PHY_269__SC_PHY_SNAP_OBS_REGS_1_MASK 0x01000000U
  252. #define LPDDR4__DENALI_PHY_269__SC_PHY_SNAP_OBS_REGS_1_SHIFT 24U
  253. #define LPDDR4__DENALI_PHY_269__SC_PHY_SNAP_OBS_REGS_1_WIDTH 1U
  254. #define LPDDR4__DENALI_PHY_269__SC_PHY_SNAP_OBS_REGS_1_WOCLR 0U
  255. #define LPDDR4__DENALI_PHY_269__SC_PHY_SNAP_OBS_REGS_1_WOSET 0U
  256. #define LPDDR4__SC_PHY_SNAP_OBS_REGS_1__REG DENALI_PHY_269
  257. #define LPDDR4__SC_PHY_SNAP_OBS_REGS_1__FLD LPDDR4__DENALI_PHY_269__SC_PHY_SNAP_OBS_REGS_1
  258. #define LPDDR4__DENALI_PHY_270_READ_MASK 0x070101FFU
  259. #define LPDDR4__DENALI_PHY_270_WRITE_MASK 0x070101FFU
  260. #define LPDDR4__DENALI_PHY_270__PHY_GATE_SMPL1_SLAVE_DELAY_1_MASK 0x000001FFU
  261. #define LPDDR4__DENALI_PHY_270__PHY_GATE_SMPL1_SLAVE_DELAY_1_SHIFT 0U
  262. #define LPDDR4__DENALI_PHY_270__PHY_GATE_SMPL1_SLAVE_DELAY_1_WIDTH 9U
  263. #define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_1__REG DENALI_PHY_270
  264. #define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_270__PHY_GATE_SMPL1_SLAVE_DELAY_1
  265. #define LPDDR4__DENALI_PHY_270__PHY_LPDDR_1_MASK 0x00010000U
  266. #define LPDDR4__DENALI_PHY_270__PHY_LPDDR_1_SHIFT 16U
  267. #define LPDDR4__DENALI_PHY_270__PHY_LPDDR_1_WIDTH 1U
  268. #define LPDDR4__DENALI_PHY_270__PHY_LPDDR_1_WOCLR 0U
  269. #define LPDDR4__DENALI_PHY_270__PHY_LPDDR_1_WOSET 0U
  270. #define LPDDR4__PHY_LPDDR_1__REG DENALI_PHY_270
  271. #define LPDDR4__PHY_LPDDR_1__FLD LPDDR4__DENALI_PHY_270__PHY_LPDDR_1
  272. #define LPDDR4__DENALI_PHY_270__PHY_MEM_CLASS_1_MASK 0x07000000U
  273. #define LPDDR4__DENALI_PHY_270__PHY_MEM_CLASS_1_SHIFT 24U
  274. #define LPDDR4__DENALI_PHY_270__PHY_MEM_CLASS_1_WIDTH 3U
  275. #define LPDDR4__PHY_MEM_CLASS_1__REG DENALI_PHY_270
  276. #define LPDDR4__PHY_MEM_CLASS_1__FLD LPDDR4__DENALI_PHY_270__PHY_MEM_CLASS_1
  277. #define LPDDR4__DENALI_PHY_271_READ_MASK 0x000301FFU
  278. #define LPDDR4__DENALI_PHY_271_WRITE_MASK 0x000301FFU
  279. #define LPDDR4__DENALI_PHY_271__PHY_GATE_SMPL2_SLAVE_DELAY_1_MASK 0x000001FFU
  280. #define LPDDR4__DENALI_PHY_271__PHY_GATE_SMPL2_SLAVE_DELAY_1_SHIFT 0U
  281. #define LPDDR4__DENALI_PHY_271__PHY_GATE_SMPL2_SLAVE_DELAY_1_WIDTH 9U
  282. #define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_1__REG DENALI_PHY_271
  283. #define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_271__PHY_GATE_SMPL2_SLAVE_DELAY_1
  284. #define LPDDR4__DENALI_PHY_271__ON_FLY_GATE_ADJUST_EN_1_MASK 0x00030000U
  285. #define LPDDR4__DENALI_PHY_271__ON_FLY_GATE_ADJUST_EN_1_SHIFT 16U
  286. #define LPDDR4__DENALI_PHY_271__ON_FLY_GATE_ADJUST_EN_1_WIDTH 2U
  287. #define LPDDR4__ON_FLY_GATE_ADJUST_EN_1__REG DENALI_PHY_271
  288. #define LPDDR4__ON_FLY_GATE_ADJUST_EN_1__FLD LPDDR4__DENALI_PHY_271__ON_FLY_GATE_ADJUST_EN_1
  289. #define LPDDR4__DENALI_PHY_272_READ_MASK 0xFFFFFFFFU
  290. #define LPDDR4__DENALI_PHY_272_WRITE_MASK 0xFFFFFFFFU
  291. #define LPDDR4__DENALI_PHY_272__PHY_GATE_TRACKING_OBS_1_MASK 0xFFFFFFFFU
  292. #define LPDDR4__DENALI_PHY_272__PHY_GATE_TRACKING_OBS_1_SHIFT 0U
  293. #define LPDDR4__DENALI_PHY_272__PHY_GATE_TRACKING_OBS_1_WIDTH 32U
  294. #define LPDDR4__PHY_GATE_TRACKING_OBS_1__REG DENALI_PHY_272
  295. #define LPDDR4__PHY_GATE_TRACKING_OBS_1__FLD LPDDR4__DENALI_PHY_272__PHY_GATE_TRACKING_OBS_1
  296. #define LPDDR4__DENALI_PHY_273_READ_MASK 0x00000301U
  297. #define LPDDR4__DENALI_PHY_273_WRITE_MASK 0x00000301U
  298. #define LPDDR4__DENALI_PHY_273__PHY_DFI40_POLARITY_1_MASK 0x00000001U
  299. #define LPDDR4__DENALI_PHY_273__PHY_DFI40_POLARITY_1_SHIFT 0U
  300. #define LPDDR4__DENALI_PHY_273__PHY_DFI40_POLARITY_1_WIDTH 1U
  301. #define LPDDR4__DENALI_PHY_273__PHY_DFI40_POLARITY_1_WOCLR 0U
  302. #define LPDDR4__DENALI_PHY_273__PHY_DFI40_POLARITY_1_WOSET 0U
  303. #define LPDDR4__PHY_DFI40_POLARITY_1__REG DENALI_PHY_273
  304. #define LPDDR4__PHY_DFI40_POLARITY_1__FLD LPDDR4__DENALI_PHY_273__PHY_DFI40_POLARITY_1
  305. #define LPDDR4__DENALI_PHY_273__PHY_LP4_PST_AMBLE_1_MASK 0x00000300U
  306. #define LPDDR4__DENALI_PHY_273__PHY_LP4_PST_AMBLE_1_SHIFT 8U
  307. #define LPDDR4__DENALI_PHY_273__PHY_LP4_PST_AMBLE_1_WIDTH 2U
  308. #define LPDDR4__PHY_LP4_PST_AMBLE_1__REG DENALI_PHY_273
  309. #define LPDDR4__PHY_LP4_PST_AMBLE_1__FLD LPDDR4__DENALI_PHY_273__PHY_LP4_PST_AMBLE_1
  310. #define LPDDR4__DENALI_PHY_274_READ_MASK 0xFFFFFFFFU
  311. #define LPDDR4__DENALI_PHY_274_WRITE_MASK 0xFFFFFFFFU
  312. #define LPDDR4__DENALI_PHY_274__PHY_RDLVL_PATT8_1_MASK 0xFFFFFFFFU
  313. #define LPDDR4__DENALI_PHY_274__PHY_RDLVL_PATT8_1_SHIFT 0U
  314. #define LPDDR4__DENALI_PHY_274__PHY_RDLVL_PATT8_1_WIDTH 32U
  315. #define LPDDR4__PHY_RDLVL_PATT8_1__REG DENALI_PHY_274
  316. #define LPDDR4__PHY_RDLVL_PATT8_1__FLD LPDDR4__DENALI_PHY_274__PHY_RDLVL_PATT8_1
  317. #define LPDDR4__DENALI_PHY_275_READ_MASK 0xFFFFFFFFU
  318. #define LPDDR4__DENALI_PHY_275_WRITE_MASK 0xFFFFFFFFU
  319. #define LPDDR4__DENALI_PHY_275__PHY_RDLVL_PATT9_1_MASK 0xFFFFFFFFU
  320. #define LPDDR4__DENALI_PHY_275__PHY_RDLVL_PATT9_1_SHIFT 0U
  321. #define LPDDR4__DENALI_PHY_275__PHY_RDLVL_PATT9_1_WIDTH 32U
  322. #define LPDDR4__PHY_RDLVL_PATT9_1__REG DENALI_PHY_275
  323. #define LPDDR4__PHY_RDLVL_PATT9_1__FLD LPDDR4__DENALI_PHY_275__PHY_RDLVL_PATT9_1
  324. #define LPDDR4__DENALI_PHY_276_READ_MASK 0xFFFFFFFFU
  325. #define LPDDR4__DENALI_PHY_276_WRITE_MASK 0xFFFFFFFFU
  326. #define LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT10_1_MASK 0xFFFFFFFFU
  327. #define LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT10_1_SHIFT 0U
  328. #define LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT10_1_WIDTH 32U
  329. #define LPDDR4__PHY_RDLVL_PATT10_1__REG DENALI_PHY_276
  330. #define LPDDR4__PHY_RDLVL_PATT10_1__FLD LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT10_1
  331. #define LPDDR4__DENALI_PHY_277_READ_MASK 0xFFFFFFFFU
  332. #define LPDDR4__DENALI_PHY_277_WRITE_MASK 0xFFFFFFFFU
  333. #define LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT11_1_MASK 0xFFFFFFFFU
  334. #define LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT11_1_SHIFT 0U
  335. #define LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT11_1_WIDTH 32U
  336. #define LPDDR4__PHY_RDLVL_PATT11_1__REG DENALI_PHY_277
  337. #define LPDDR4__PHY_RDLVL_PATT11_1__FLD LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT11_1
  338. #define LPDDR4__DENALI_PHY_278_READ_MASK 0xFFFFFFFFU
  339. #define LPDDR4__DENALI_PHY_278_WRITE_MASK 0xFFFFFFFFU
  340. #define LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT12_1_MASK 0xFFFFFFFFU
  341. #define LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT12_1_SHIFT 0U
  342. #define LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT12_1_WIDTH 32U
  343. #define LPDDR4__PHY_RDLVL_PATT12_1__REG DENALI_PHY_278
  344. #define LPDDR4__PHY_RDLVL_PATT12_1__FLD LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT12_1
  345. #define LPDDR4__DENALI_PHY_279_READ_MASK 0xFFFFFFFFU
  346. #define LPDDR4__DENALI_PHY_279_WRITE_MASK 0xFFFFFFFFU
  347. #define LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT13_1_MASK 0xFFFFFFFFU
  348. #define LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT13_1_SHIFT 0U
  349. #define LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT13_1_WIDTH 32U
  350. #define LPDDR4__PHY_RDLVL_PATT13_1__REG DENALI_PHY_279
  351. #define LPDDR4__PHY_RDLVL_PATT13_1__FLD LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT13_1
  352. #define LPDDR4__DENALI_PHY_280_READ_MASK 0xFFFFFFFFU
  353. #define LPDDR4__DENALI_PHY_280_WRITE_MASK 0xFFFFFFFFU
  354. #define LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT14_1_MASK 0xFFFFFFFFU
  355. #define LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT14_1_SHIFT 0U
  356. #define LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT14_1_WIDTH 32U
  357. #define LPDDR4__PHY_RDLVL_PATT14_1__REG DENALI_PHY_280
  358. #define LPDDR4__PHY_RDLVL_PATT14_1__FLD LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT14_1
  359. #define LPDDR4__DENALI_PHY_281_READ_MASK 0xFFFFFFFFU
  360. #define LPDDR4__DENALI_PHY_281_WRITE_MASK 0xFFFFFFFFU
  361. #define LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT15_1_MASK 0xFFFFFFFFU
  362. #define LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT15_1_SHIFT 0U
  363. #define LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT15_1_WIDTH 32U
  364. #define LPDDR4__PHY_RDLVL_PATT15_1__REG DENALI_PHY_281
  365. #define LPDDR4__PHY_RDLVL_PATT15_1__FLD LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT15_1
  366. #define LPDDR4__DENALI_PHY_282_READ_MASK 0x070F0107U
  367. #define LPDDR4__DENALI_PHY_282_WRITE_MASK 0x070F0107U
  368. #define LPDDR4__DENALI_PHY_282__PHY_SLAVE_LOOP_CNT_UPDATE_1_MASK 0x00000007U
  369. #define LPDDR4__DENALI_PHY_282__PHY_SLAVE_LOOP_CNT_UPDATE_1_SHIFT 0U
  370. #define LPDDR4__DENALI_PHY_282__PHY_SLAVE_LOOP_CNT_UPDATE_1_WIDTH 3U
  371. #define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_1__REG DENALI_PHY_282
  372. #define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_1__FLD LPDDR4__DENALI_PHY_282__PHY_SLAVE_LOOP_CNT_UPDATE_1
  373. #define LPDDR4__DENALI_PHY_282__PHY_SW_FIFO_PTR_RST_DISABLE_1_MASK 0x00000100U
  374. #define LPDDR4__DENALI_PHY_282__PHY_SW_FIFO_PTR_RST_DISABLE_1_SHIFT 8U
  375. #define LPDDR4__DENALI_PHY_282__PHY_SW_FIFO_PTR_RST_DISABLE_1_WIDTH 1U
  376. #define LPDDR4__DENALI_PHY_282__PHY_SW_FIFO_PTR_RST_DISABLE_1_WOCLR 0U
  377. #define LPDDR4__DENALI_PHY_282__PHY_SW_FIFO_PTR_RST_DISABLE_1_WOSET 0U
  378. #define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_1__REG DENALI_PHY_282
  379. #define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_1__FLD LPDDR4__DENALI_PHY_282__PHY_SW_FIFO_PTR_RST_DISABLE_1
  380. #define LPDDR4__DENALI_PHY_282__PHY_MASTER_DLY_LOCK_OBS_SELECT_1_MASK 0x000F0000U
  381. #define LPDDR4__DENALI_PHY_282__PHY_MASTER_DLY_LOCK_OBS_SELECT_1_SHIFT 16U
  382. #define LPDDR4__DENALI_PHY_282__PHY_MASTER_DLY_LOCK_OBS_SELECT_1_WIDTH 4U
  383. #define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_1__REG DENALI_PHY_282
  384. #define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_282__PHY_MASTER_DLY_LOCK_OBS_SELECT_1
  385. #define LPDDR4__DENALI_PHY_282__PHY_RDDQ_ENC_OBS_SELECT_1_MASK 0x07000000U
  386. #define LPDDR4__DENALI_PHY_282__PHY_RDDQ_ENC_OBS_SELECT_1_SHIFT 24U
  387. #define LPDDR4__DENALI_PHY_282__PHY_RDDQ_ENC_OBS_SELECT_1_WIDTH 3U
  388. #define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_1__REG DENALI_PHY_282
  389. #define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_282__PHY_RDDQ_ENC_OBS_SELECT_1
  390. #define LPDDR4__DENALI_PHY_283_READ_MASK 0x0F0F0F0FU
  391. #define LPDDR4__DENALI_PHY_283_WRITE_MASK 0x0F0F0F0FU
  392. #define LPDDR4__DENALI_PHY_283__PHY_RDDQS_DQ_ENC_OBS_SELECT_1_MASK 0x0000000FU
  393. #define LPDDR4__DENALI_PHY_283__PHY_RDDQS_DQ_ENC_OBS_SELECT_1_SHIFT 0U
  394. #define LPDDR4__DENALI_PHY_283__PHY_RDDQS_DQ_ENC_OBS_SELECT_1_WIDTH 4U
  395. #define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_1__REG DENALI_PHY_283
  396. #define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_283__PHY_RDDQS_DQ_ENC_OBS_SELECT_1
  397. #define LPDDR4__DENALI_PHY_283__PHY_WR_ENC_OBS_SELECT_1_MASK 0x00000F00U
  398. #define LPDDR4__DENALI_PHY_283__PHY_WR_ENC_OBS_SELECT_1_SHIFT 8U
  399. #define LPDDR4__DENALI_PHY_283__PHY_WR_ENC_OBS_SELECT_1_WIDTH 4U
  400. #define LPDDR4__PHY_WR_ENC_OBS_SELECT_1__REG DENALI_PHY_283
  401. #define LPDDR4__PHY_WR_ENC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_283__PHY_WR_ENC_OBS_SELECT_1
  402. #define LPDDR4__DENALI_PHY_283__PHY_WR_SHIFT_OBS_SELECT_1_MASK 0x000F0000U
  403. #define LPDDR4__DENALI_PHY_283__PHY_WR_SHIFT_OBS_SELECT_1_SHIFT 16U
  404. #define LPDDR4__DENALI_PHY_283__PHY_WR_SHIFT_OBS_SELECT_1_WIDTH 4U
  405. #define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_1__REG DENALI_PHY_283
  406. #define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_283__PHY_WR_SHIFT_OBS_SELECT_1
  407. #define LPDDR4__DENALI_PHY_283__PHY_FIFO_PTR_OBS_SELECT_1_MASK 0x0F000000U
  408. #define LPDDR4__DENALI_PHY_283__PHY_FIFO_PTR_OBS_SELECT_1_SHIFT 24U
  409. #define LPDDR4__DENALI_PHY_283__PHY_FIFO_PTR_OBS_SELECT_1_WIDTH 4U
  410. #define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_1__REG DENALI_PHY_283
  411. #define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_283__PHY_FIFO_PTR_OBS_SELECT_1
  412. #define LPDDR4__DENALI_PHY_284_READ_MASK 0xFF030001U
  413. #define LPDDR4__DENALI_PHY_284_WRITE_MASK 0xFF030001U
  414. #define LPDDR4__DENALI_PHY_284__PHY_LVL_DEBUG_MODE_1_MASK 0x00000001U
  415. #define LPDDR4__DENALI_PHY_284__PHY_LVL_DEBUG_MODE_1_SHIFT 0U
  416. #define LPDDR4__DENALI_PHY_284__PHY_LVL_DEBUG_MODE_1_WIDTH 1U
  417. #define LPDDR4__DENALI_PHY_284__PHY_LVL_DEBUG_MODE_1_WOCLR 0U
  418. #define LPDDR4__DENALI_PHY_284__PHY_LVL_DEBUG_MODE_1_WOSET 0U
  419. #define LPDDR4__PHY_LVL_DEBUG_MODE_1__REG DENALI_PHY_284
  420. #define LPDDR4__PHY_LVL_DEBUG_MODE_1__FLD LPDDR4__DENALI_PHY_284__PHY_LVL_DEBUG_MODE_1
  421. #define LPDDR4__DENALI_PHY_284__SC_PHY_LVL_DEBUG_CONT_1_MASK 0x00000100U
  422. #define LPDDR4__DENALI_PHY_284__SC_PHY_LVL_DEBUG_CONT_1_SHIFT 8U
  423. #define LPDDR4__DENALI_PHY_284__SC_PHY_LVL_DEBUG_CONT_1_WIDTH 1U
  424. #define LPDDR4__DENALI_PHY_284__SC_PHY_LVL_DEBUG_CONT_1_WOCLR 0U
  425. #define LPDDR4__DENALI_PHY_284__SC_PHY_LVL_DEBUG_CONT_1_WOSET 0U
  426. #define LPDDR4__SC_PHY_LVL_DEBUG_CONT_1__REG DENALI_PHY_284
  427. #define LPDDR4__SC_PHY_LVL_DEBUG_CONT_1__FLD LPDDR4__DENALI_PHY_284__SC_PHY_LVL_DEBUG_CONT_1
  428. #define LPDDR4__DENALI_PHY_284__PHY_WRLVL_ALGO_1_MASK 0x00030000U
  429. #define LPDDR4__DENALI_PHY_284__PHY_WRLVL_ALGO_1_SHIFT 16U
  430. #define LPDDR4__DENALI_PHY_284__PHY_WRLVL_ALGO_1_WIDTH 2U
  431. #define LPDDR4__PHY_WRLVL_ALGO_1__REG DENALI_PHY_284
  432. #define LPDDR4__PHY_WRLVL_ALGO_1__FLD LPDDR4__DENALI_PHY_284__PHY_WRLVL_ALGO_1
  433. #define LPDDR4__DENALI_PHY_284__PHY_WRLVL_PER_START_1_MASK 0xFF000000U
  434. #define LPDDR4__DENALI_PHY_284__PHY_WRLVL_PER_START_1_SHIFT 24U
  435. #define LPDDR4__DENALI_PHY_284__PHY_WRLVL_PER_START_1_WIDTH 8U
  436. #define LPDDR4__PHY_WRLVL_PER_START_1__REG DENALI_PHY_284
  437. #define LPDDR4__PHY_WRLVL_PER_START_1__FLD LPDDR4__DENALI_PHY_284__PHY_WRLVL_PER_START_1
  438. #define LPDDR4__DENALI_PHY_285_READ_MASK 0x00FF0F3FU
  439. #define LPDDR4__DENALI_PHY_285_WRITE_MASK 0x00FF0F3FU
  440. #define LPDDR4__DENALI_PHY_285__PHY_WRLVL_CAPTURE_CNT_1_MASK 0x0000003FU
  441. #define LPDDR4__DENALI_PHY_285__PHY_WRLVL_CAPTURE_CNT_1_SHIFT 0U
  442. #define LPDDR4__DENALI_PHY_285__PHY_WRLVL_CAPTURE_CNT_1_WIDTH 6U
  443. #define LPDDR4__PHY_WRLVL_CAPTURE_CNT_1__REG DENALI_PHY_285
  444. #define LPDDR4__PHY_WRLVL_CAPTURE_CNT_1__FLD LPDDR4__DENALI_PHY_285__PHY_WRLVL_CAPTURE_CNT_1
  445. #define LPDDR4__DENALI_PHY_285__PHY_WRLVL_UPDT_WAIT_CNT_1_MASK 0x00000F00U
  446. #define LPDDR4__DENALI_PHY_285__PHY_WRLVL_UPDT_WAIT_CNT_1_SHIFT 8U
  447. #define LPDDR4__DENALI_PHY_285__PHY_WRLVL_UPDT_WAIT_CNT_1_WIDTH 4U
  448. #define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_1__REG DENALI_PHY_285
  449. #define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_285__PHY_WRLVL_UPDT_WAIT_CNT_1
  450. #define LPDDR4__DENALI_PHY_285__PHY_DQ_MASK_1_MASK 0x00FF0000U
  451. #define LPDDR4__DENALI_PHY_285__PHY_DQ_MASK_1_SHIFT 16U
  452. #define LPDDR4__DENALI_PHY_285__PHY_DQ_MASK_1_WIDTH 8U
  453. #define LPDDR4__PHY_DQ_MASK_1__REG DENALI_PHY_285
  454. #define LPDDR4__PHY_DQ_MASK_1__FLD LPDDR4__DENALI_PHY_285__PHY_DQ_MASK_1
  455. #define LPDDR4__DENALI_PHY_286_READ_MASK 0x0F3F03FFU
  456. #define LPDDR4__DENALI_PHY_286_WRITE_MASK 0x0F3F03FFU
  457. #define LPDDR4__DENALI_PHY_286__PHY_GTLVL_PER_START_1_MASK 0x000003FFU
  458. #define LPDDR4__DENALI_PHY_286__PHY_GTLVL_PER_START_1_SHIFT 0U
  459. #define LPDDR4__DENALI_PHY_286__PHY_GTLVL_PER_START_1_WIDTH 10U
  460. #define LPDDR4__PHY_GTLVL_PER_START_1__REG DENALI_PHY_286
  461. #define LPDDR4__PHY_GTLVL_PER_START_1__FLD LPDDR4__DENALI_PHY_286__PHY_GTLVL_PER_START_1
  462. #define LPDDR4__DENALI_PHY_286__PHY_GTLVL_CAPTURE_CNT_1_MASK 0x003F0000U
  463. #define LPDDR4__DENALI_PHY_286__PHY_GTLVL_CAPTURE_CNT_1_SHIFT 16U
  464. #define LPDDR4__DENALI_PHY_286__PHY_GTLVL_CAPTURE_CNT_1_WIDTH 6U
  465. #define LPDDR4__PHY_GTLVL_CAPTURE_CNT_1__REG DENALI_PHY_286
  466. #define LPDDR4__PHY_GTLVL_CAPTURE_CNT_1__FLD LPDDR4__DENALI_PHY_286__PHY_GTLVL_CAPTURE_CNT_1
  467. #define LPDDR4__DENALI_PHY_286__PHY_GTLVL_UPDT_WAIT_CNT_1_MASK 0x0F000000U
  468. #define LPDDR4__DENALI_PHY_286__PHY_GTLVL_UPDT_WAIT_CNT_1_SHIFT 24U
  469. #define LPDDR4__DENALI_PHY_286__PHY_GTLVL_UPDT_WAIT_CNT_1_WIDTH 4U
  470. #define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_1__REG DENALI_PHY_286
  471. #define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_286__PHY_GTLVL_UPDT_WAIT_CNT_1
  472. #define LPDDR4__DENALI_PHY_287_READ_MASK 0x1F030F3FU
  473. #define LPDDR4__DENALI_PHY_287_WRITE_MASK 0x1F030F3FU
  474. #define LPDDR4__DENALI_PHY_287__PHY_RDLVL_CAPTURE_CNT_1_MASK 0x0000003FU
  475. #define LPDDR4__DENALI_PHY_287__PHY_RDLVL_CAPTURE_CNT_1_SHIFT 0U
  476. #define LPDDR4__DENALI_PHY_287__PHY_RDLVL_CAPTURE_CNT_1_WIDTH 6U
  477. #define LPDDR4__PHY_RDLVL_CAPTURE_CNT_1__REG DENALI_PHY_287
  478. #define LPDDR4__PHY_RDLVL_CAPTURE_CNT_1__FLD LPDDR4__DENALI_PHY_287__PHY_RDLVL_CAPTURE_CNT_1
  479. #define LPDDR4__DENALI_PHY_287__PHY_RDLVL_UPDT_WAIT_CNT_1_MASK 0x00000F00U
  480. #define LPDDR4__DENALI_PHY_287__PHY_RDLVL_UPDT_WAIT_CNT_1_SHIFT 8U
  481. #define LPDDR4__DENALI_PHY_287__PHY_RDLVL_UPDT_WAIT_CNT_1_WIDTH 4U
  482. #define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_1__REG DENALI_PHY_287
  483. #define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_287__PHY_RDLVL_UPDT_WAIT_CNT_1
  484. #define LPDDR4__DENALI_PHY_287__PHY_RDLVL_OP_MODE_1_MASK 0x00030000U
  485. #define LPDDR4__DENALI_PHY_287__PHY_RDLVL_OP_MODE_1_SHIFT 16U
  486. #define LPDDR4__DENALI_PHY_287__PHY_RDLVL_OP_MODE_1_WIDTH 2U
  487. #define LPDDR4__PHY_RDLVL_OP_MODE_1__REG DENALI_PHY_287
  488. #define LPDDR4__PHY_RDLVL_OP_MODE_1__FLD LPDDR4__DENALI_PHY_287__PHY_RDLVL_OP_MODE_1
  489. #define LPDDR4__DENALI_PHY_287__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1_MASK 0x1F000000U
  490. #define LPDDR4__DENALI_PHY_287__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1_SHIFT 24U
  491. #define LPDDR4__DENALI_PHY_287__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1_WIDTH 5U
  492. #define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1__REG DENALI_PHY_287
  493. #define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_287__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1
  494. #define LPDDR4__DENALI_PHY_288_READ_MASK 0x3FFFFFFFU
  495. #define LPDDR4__DENALI_PHY_288_WRITE_MASK 0x3FFFFFFFU
  496. #define LPDDR4__DENALI_PHY_288__PHY_RDLVL_PERIODIC_OBS_SELECT_1_MASK 0x000000FFU
  497. #define LPDDR4__DENALI_PHY_288__PHY_RDLVL_PERIODIC_OBS_SELECT_1_SHIFT 0U
  498. #define LPDDR4__DENALI_PHY_288__PHY_RDLVL_PERIODIC_OBS_SELECT_1_WIDTH 8U
  499. #define LPDDR4__PHY_RDLVL_PERIODIC_OBS_SELECT_1__REG DENALI_PHY_288
  500. #define LPDDR4__PHY_RDLVL_PERIODIC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_288__PHY_RDLVL_PERIODIC_OBS_SELECT_1
  501. #define LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_MASK_1_MASK 0x0000FF00U
  502. #define LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_MASK_1_SHIFT 8U
  503. #define LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_MASK_1_WIDTH 8U
  504. #define LPDDR4__PHY_RDLVL_DATA_MASK_1__REG DENALI_PHY_288
  505. #define LPDDR4__PHY_RDLVL_DATA_MASK_1__FLD LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_MASK_1
  506. #define LPDDR4__DENALI_PHY_288__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1_MASK 0x00FF0000U
  507. #define LPDDR4__DENALI_PHY_288__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1_SHIFT 16U
  508. #define LPDDR4__DENALI_PHY_288__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1_WIDTH 8U
  509. #define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1__REG DENALI_PHY_288
  510. #define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1__FLD LPDDR4__DENALI_PHY_288__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1
  511. #define LPDDR4__DENALI_PHY_288__PHY_WDQLVL_BURST_CNT_1_MASK 0x3F000000U
  512. #define LPDDR4__DENALI_PHY_288__PHY_WDQLVL_BURST_CNT_1_SHIFT 24U
  513. #define LPDDR4__DENALI_PHY_288__PHY_WDQLVL_BURST_CNT_1_WIDTH 6U
  514. #define LPDDR4__PHY_WDQLVL_BURST_CNT_1__REG DENALI_PHY_288
  515. #define LPDDR4__PHY_WDQLVL_BURST_CNT_1__FLD LPDDR4__DENALI_PHY_288__PHY_WDQLVL_BURST_CNT_1
  516. #define LPDDR4__DENALI_PHY_289_READ_MASK 0x0F07FF07U
  517. #define LPDDR4__DENALI_PHY_289_WRITE_MASK 0x0F07FF07U
  518. #define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_PATT_1_MASK 0x00000007U
  519. #define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_PATT_1_SHIFT 0U
  520. #define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_PATT_1_WIDTH 3U
  521. #define LPDDR4__PHY_WDQLVL_PATT_1__REG DENALI_PHY_289
  522. #define LPDDR4__PHY_WDQLVL_PATT_1__FLD LPDDR4__DENALI_PHY_289__PHY_WDQLVL_PATT_1
  523. #define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1_MASK 0x0007FF00U
  524. #define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1_SHIFT 8U
  525. #define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1_WIDTH 11U
  526. #define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1__REG DENALI_PHY_289
  527. #define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1__FLD LPDDR4__DENALI_PHY_289__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1
  528. #define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_UPDT_WAIT_CNT_1_MASK 0x0F000000U
  529. #define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_UPDT_WAIT_CNT_1_SHIFT 24U
  530. #define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_UPDT_WAIT_CNT_1_WIDTH 4U
  531. #define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_1__REG DENALI_PHY_289
  532. #define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_289__PHY_WDQLVL_UPDT_WAIT_CNT_1
  533. #define LPDDR4__DENALI_PHY_290_READ_MASK 0x0000FF0FU
  534. #define LPDDR4__DENALI_PHY_290_WRITE_MASK 0x0000FF0FU
  535. #define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_OBS_SELECT_1_MASK 0x0000000FU
  536. #define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_OBS_SELECT_1_SHIFT 0U
  537. #define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_OBS_SELECT_1_WIDTH 4U
  538. #define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_1__REG DENALI_PHY_290
  539. #define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_OBS_SELECT_1
  540. #define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_PERIODIC_OBS_SELECT_1_MASK 0x0000FF00U
  541. #define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_PERIODIC_OBS_SELECT_1_SHIFT 8U
  542. #define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_PERIODIC_OBS_SELECT_1_WIDTH 8U
  543. #define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_1__REG DENALI_PHY_290
  544. #define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_290__PHY_WDQLVL_PERIODIC_OBS_SELECT_1
  545. #define LPDDR4__DENALI_PHY_290__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_MASK 0x00010000U
  546. #define LPDDR4__DENALI_PHY_290__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_SHIFT 16U
  547. #define LPDDR4__DENALI_PHY_290__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_WIDTH 1U
  548. #define LPDDR4__DENALI_PHY_290__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_WOCLR 0U
  549. #define LPDDR4__DENALI_PHY_290__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_WOSET 0U
  550. #define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1__REG DENALI_PHY_290
  551. #define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1__FLD LPDDR4__DENALI_PHY_290__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1
  552. #define LPDDR4__DENALI_PHY_291_READ_MASK 0x000001FFU
  553. #define LPDDR4__DENALI_PHY_291_WRITE_MASK 0x000001FFU
  554. #define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DATADM_MASK_1_MASK 0x000001FFU
  555. #define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DATADM_MASK_1_SHIFT 0U
  556. #define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DATADM_MASK_1_WIDTH 9U
  557. #define LPDDR4__PHY_WDQLVL_DATADM_MASK_1__REG DENALI_PHY_291
  558. #define LPDDR4__PHY_WDQLVL_DATADM_MASK_1__FLD LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DATADM_MASK_1
  559. #define LPDDR4__DENALI_PHY_292_READ_MASK 0xFFFFFFFFU
  560. #define LPDDR4__DENALI_PHY_292_WRITE_MASK 0xFFFFFFFFU
  561. #define LPDDR4__DENALI_PHY_292__PHY_USER_PATT0_1_MASK 0xFFFFFFFFU
  562. #define LPDDR4__DENALI_PHY_292__PHY_USER_PATT0_1_SHIFT 0U
  563. #define LPDDR4__DENALI_PHY_292__PHY_USER_PATT0_1_WIDTH 32U
  564. #define LPDDR4__PHY_USER_PATT0_1__REG DENALI_PHY_292
  565. #define LPDDR4__PHY_USER_PATT0_1__FLD LPDDR4__DENALI_PHY_292__PHY_USER_PATT0_1
  566. #define LPDDR4__DENALI_PHY_293_READ_MASK 0xFFFFFFFFU
  567. #define LPDDR4__DENALI_PHY_293_WRITE_MASK 0xFFFFFFFFU
  568. #define LPDDR4__DENALI_PHY_293__PHY_USER_PATT1_1_MASK 0xFFFFFFFFU
  569. #define LPDDR4__DENALI_PHY_293__PHY_USER_PATT1_1_SHIFT 0U
  570. #define LPDDR4__DENALI_PHY_293__PHY_USER_PATT1_1_WIDTH 32U
  571. #define LPDDR4__PHY_USER_PATT1_1__REG DENALI_PHY_293
  572. #define LPDDR4__PHY_USER_PATT1_1__FLD LPDDR4__DENALI_PHY_293__PHY_USER_PATT1_1
  573. #define LPDDR4__DENALI_PHY_294_READ_MASK 0xFFFFFFFFU
  574. #define LPDDR4__DENALI_PHY_294_WRITE_MASK 0xFFFFFFFFU
  575. #define LPDDR4__DENALI_PHY_294__PHY_USER_PATT2_1_MASK 0xFFFFFFFFU
  576. #define LPDDR4__DENALI_PHY_294__PHY_USER_PATT2_1_SHIFT 0U
  577. #define LPDDR4__DENALI_PHY_294__PHY_USER_PATT2_1_WIDTH 32U
  578. #define LPDDR4__PHY_USER_PATT2_1__REG DENALI_PHY_294
  579. #define LPDDR4__PHY_USER_PATT2_1__FLD LPDDR4__DENALI_PHY_294__PHY_USER_PATT2_1
  580. #define LPDDR4__DENALI_PHY_295_READ_MASK 0xFFFFFFFFU
  581. #define LPDDR4__DENALI_PHY_295_WRITE_MASK 0xFFFFFFFFU
  582. #define LPDDR4__DENALI_PHY_295__PHY_USER_PATT3_1_MASK 0xFFFFFFFFU
  583. #define LPDDR4__DENALI_PHY_295__PHY_USER_PATT3_1_SHIFT 0U
  584. #define LPDDR4__DENALI_PHY_295__PHY_USER_PATT3_1_WIDTH 32U
  585. #define LPDDR4__PHY_USER_PATT3_1__REG DENALI_PHY_295
  586. #define LPDDR4__PHY_USER_PATT3_1__FLD LPDDR4__DENALI_PHY_295__PHY_USER_PATT3_1
  587. #define LPDDR4__DENALI_PHY_296_READ_MASK 0x0001FFFFU
  588. #define LPDDR4__DENALI_PHY_296_WRITE_MASK 0x0001FFFFU
  589. #define LPDDR4__DENALI_PHY_296__PHY_USER_PATT4_1_MASK 0x0000FFFFU
  590. #define LPDDR4__DENALI_PHY_296__PHY_USER_PATT4_1_SHIFT 0U
  591. #define LPDDR4__DENALI_PHY_296__PHY_USER_PATT4_1_WIDTH 16U
  592. #define LPDDR4__PHY_USER_PATT4_1__REG DENALI_PHY_296
  593. #define LPDDR4__PHY_USER_PATT4_1__FLD LPDDR4__DENALI_PHY_296__PHY_USER_PATT4_1
  594. #define LPDDR4__DENALI_PHY_296__PHY_NTP_MULT_TRAIN_1_MASK 0x00010000U
  595. #define LPDDR4__DENALI_PHY_296__PHY_NTP_MULT_TRAIN_1_SHIFT 16U
  596. #define LPDDR4__DENALI_PHY_296__PHY_NTP_MULT_TRAIN_1_WIDTH 1U
  597. #define LPDDR4__DENALI_PHY_296__PHY_NTP_MULT_TRAIN_1_WOCLR 0U
  598. #define LPDDR4__DENALI_PHY_296__PHY_NTP_MULT_TRAIN_1_WOSET 0U
  599. #define LPDDR4__PHY_NTP_MULT_TRAIN_1__REG DENALI_PHY_296
  600. #define LPDDR4__PHY_NTP_MULT_TRAIN_1__FLD LPDDR4__DENALI_PHY_296__PHY_NTP_MULT_TRAIN_1
  601. #define LPDDR4__DENALI_PHY_297_READ_MASK 0x03FF03FFU
  602. #define LPDDR4__DENALI_PHY_297_WRITE_MASK 0x03FF03FFU
  603. #define LPDDR4__DENALI_PHY_297__PHY_NTP_EARLY_THRESHOLD_1_MASK 0x000003FFU
  604. #define LPDDR4__DENALI_PHY_297__PHY_NTP_EARLY_THRESHOLD_1_SHIFT 0U
  605. #define LPDDR4__DENALI_PHY_297__PHY_NTP_EARLY_THRESHOLD_1_WIDTH 10U
  606. #define LPDDR4__PHY_NTP_EARLY_THRESHOLD_1__REG DENALI_PHY_297
  607. #define LPDDR4__PHY_NTP_EARLY_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_297__PHY_NTP_EARLY_THRESHOLD_1
  608. #define LPDDR4__DENALI_PHY_297__PHY_NTP_PERIOD_THRESHOLD_1_MASK 0x03FF0000U
  609. #define LPDDR4__DENALI_PHY_297__PHY_NTP_PERIOD_THRESHOLD_1_SHIFT 16U
  610. #define LPDDR4__DENALI_PHY_297__PHY_NTP_PERIOD_THRESHOLD_1_WIDTH 10U
  611. #define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_1__REG DENALI_PHY_297
  612. #define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_297__PHY_NTP_PERIOD_THRESHOLD_1
  613. #define LPDDR4__DENALI_PHY_298_READ_MASK 0x03FF03FFU
  614. #define LPDDR4__DENALI_PHY_298_WRITE_MASK 0x03FF03FFU
  615. #define LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_MIN_1_MASK 0x000003FFU
  616. #define LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_MIN_1_SHIFT 0U
  617. #define LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_MIN_1_WIDTH 10U
  618. #define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_1__REG DENALI_PHY_298
  619. #define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_1__FLD LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_MIN_1
  620. #define LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_MAX_1_MASK 0x03FF0000U
  621. #define LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_MAX_1_SHIFT 16U
  622. #define LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_MAX_1_WIDTH 10U
  623. #define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_1__REG DENALI_PHY_298
  624. #define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_1__FLD LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_MAX_1
  625. #define LPDDR4__DENALI_PHY_299_READ_MASK 0x00FF0001U
  626. #define LPDDR4__DENALI_PHY_299_WRITE_MASK 0x00FF0001U
  627. #define LPDDR4__DENALI_PHY_299__PHY_CALVL_VREF_DRIVING_SLICE_1_MASK 0x00000001U
  628. #define LPDDR4__DENALI_PHY_299__PHY_CALVL_VREF_DRIVING_SLICE_1_SHIFT 0U
  629. #define LPDDR4__DENALI_PHY_299__PHY_CALVL_VREF_DRIVING_SLICE_1_WIDTH 1U
  630. #define LPDDR4__DENALI_PHY_299__PHY_CALVL_VREF_DRIVING_SLICE_1_WOCLR 0U
  631. #define LPDDR4__DENALI_PHY_299__PHY_CALVL_VREF_DRIVING_SLICE_1_WOSET 0U
  632. #define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_1__REG DENALI_PHY_299
  633. #define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_1__FLD LPDDR4__DENALI_PHY_299__PHY_CALVL_VREF_DRIVING_SLICE_1
  634. #define LPDDR4__DENALI_PHY_299__SC_PHY_MANUAL_CLEAR_1_MASK 0x00003F00U
  635. #define LPDDR4__DENALI_PHY_299__SC_PHY_MANUAL_CLEAR_1_SHIFT 8U
  636. #define LPDDR4__DENALI_PHY_299__SC_PHY_MANUAL_CLEAR_1_WIDTH 6U
  637. #define LPDDR4__SC_PHY_MANUAL_CLEAR_1__REG DENALI_PHY_299
  638. #define LPDDR4__SC_PHY_MANUAL_CLEAR_1__FLD LPDDR4__DENALI_PHY_299__SC_PHY_MANUAL_CLEAR_1
  639. #define LPDDR4__DENALI_PHY_299__PHY_FIFO_PTR_OBS_1_MASK 0x00FF0000U
  640. #define LPDDR4__DENALI_PHY_299__PHY_FIFO_PTR_OBS_1_SHIFT 16U
  641. #define LPDDR4__DENALI_PHY_299__PHY_FIFO_PTR_OBS_1_WIDTH 8U
  642. #define LPDDR4__PHY_FIFO_PTR_OBS_1__REG DENALI_PHY_299
  643. #define LPDDR4__PHY_FIFO_PTR_OBS_1__FLD LPDDR4__DENALI_PHY_299__PHY_FIFO_PTR_OBS_1
  644. #define LPDDR4__DENALI_PHY_300_READ_MASK 0xFFFFFFFFU
  645. #define LPDDR4__DENALI_PHY_300_WRITE_MASK 0xFFFFFFFFU
  646. #define LPDDR4__DENALI_PHY_300__PHY_LPBK_RESULT_OBS_1_MASK 0xFFFFFFFFU
  647. #define LPDDR4__DENALI_PHY_300__PHY_LPBK_RESULT_OBS_1_SHIFT 0U
  648. #define LPDDR4__DENALI_PHY_300__PHY_LPBK_RESULT_OBS_1_WIDTH 32U
  649. #define LPDDR4__PHY_LPBK_RESULT_OBS_1__REG DENALI_PHY_300
  650. #define LPDDR4__PHY_LPBK_RESULT_OBS_1__FLD LPDDR4__DENALI_PHY_300__PHY_LPBK_RESULT_OBS_1
  651. #define LPDDR4__DENALI_PHY_301_READ_MASK 0x07FFFFFFU
  652. #define LPDDR4__DENALI_PHY_301_WRITE_MASK 0x07FFFFFFU
  653. #define LPDDR4__DENALI_PHY_301__PHY_LPBK_ERROR_COUNT_OBS_1_MASK 0x0000FFFFU
  654. #define LPDDR4__DENALI_PHY_301__PHY_LPBK_ERROR_COUNT_OBS_1_SHIFT 0U
  655. #define LPDDR4__DENALI_PHY_301__PHY_LPBK_ERROR_COUNT_OBS_1_WIDTH 16U
  656. #define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_1__REG DENALI_PHY_301
  657. #define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_1__FLD LPDDR4__DENALI_PHY_301__PHY_LPBK_ERROR_COUNT_OBS_1
  658. #define LPDDR4__DENALI_PHY_301__PHY_MASTER_DLY_LOCK_OBS_1_MASK 0x07FF0000U
  659. #define LPDDR4__DENALI_PHY_301__PHY_MASTER_DLY_LOCK_OBS_1_SHIFT 16U
  660. #define LPDDR4__DENALI_PHY_301__PHY_MASTER_DLY_LOCK_OBS_1_WIDTH 11U
  661. #define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_1__REG DENALI_PHY_301
  662. #define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_1__FLD LPDDR4__DENALI_PHY_301__PHY_MASTER_DLY_LOCK_OBS_1
  663. #define LPDDR4__DENALI_PHY_302_READ_MASK 0xFFFF7F7FU
  664. #define LPDDR4__DENALI_PHY_302_WRITE_MASK 0xFFFF7F7FU
  665. #define LPDDR4__DENALI_PHY_302__PHY_RDDQ_SLV_DLY_ENC_OBS_1_MASK 0x0000007FU
  666. #define LPDDR4__DENALI_PHY_302__PHY_RDDQ_SLV_DLY_ENC_OBS_1_SHIFT 0U
  667. #define LPDDR4__DENALI_PHY_302__PHY_RDDQ_SLV_DLY_ENC_OBS_1_WIDTH 7U
  668. #define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_302
  669. #define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_302__PHY_RDDQ_SLV_DLY_ENC_OBS_1
  670. #define LPDDR4__DENALI_PHY_302__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1_MASK 0x00007F00U
  671. #define LPDDR4__DENALI_PHY_302__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1_SHIFT 8U
  672. #define LPDDR4__DENALI_PHY_302__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1_WIDTH 7U
  673. #define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_302
  674. #define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_302__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1
  675. #define LPDDR4__DENALI_PHY_302__PHY_MEAS_DLY_STEP_VALUE_1_MASK 0x00FF0000U
  676. #define LPDDR4__DENALI_PHY_302__PHY_MEAS_DLY_STEP_VALUE_1_SHIFT 16U
  677. #define LPDDR4__DENALI_PHY_302__PHY_MEAS_DLY_STEP_VALUE_1_WIDTH 8U
  678. #define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_1__REG DENALI_PHY_302
  679. #define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_1__FLD LPDDR4__DENALI_PHY_302__PHY_MEAS_DLY_STEP_VALUE_1
  680. #define LPDDR4__DENALI_PHY_302__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1_MASK 0xFF000000U
  681. #define LPDDR4__DENALI_PHY_302__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1_SHIFT 24U
  682. #define LPDDR4__DENALI_PHY_302__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1_WIDTH 8U
  683. #define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_302
  684. #define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_302__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1
  685. #define LPDDR4__DENALI_PHY_303_READ_MASK 0x7F07FFFFU
  686. #define LPDDR4__DENALI_PHY_303_WRITE_MASK 0x7F07FFFFU
  687. #define LPDDR4__DENALI_PHY_303__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1_MASK 0x000000FFU
  688. #define LPDDR4__DENALI_PHY_303__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1_SHIFT 0U
  689. #define LPDDR4__DENALI_PHY_303__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1_WIDTH 8U
  690. #define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_303
  691. #define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_303__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1
  692. #define LPDDR4__DENALI_PHY_303__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1_MASK 0x0007FF00U
  693. #define LPDDR4__DENALI_PHY_303__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1_SHIFT 8U
  694. #define LPDDR4__DENALI_PHY_303__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1_WIDTH 11U
  695. #define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_303
  696. #define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_303__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1
  697. #define LPDDR4__DENALI_PHY_303__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1_MASK 0x7F000000U
  698. #define LPDDR4__DENALI_PHY_303__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1_SHIFT 24U
  699. #define LPDDR4__DENALI_PHY_303__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1_WIDTH 7U
  700. #define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_303
  701. #define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_303__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1
  702. #define LPDDR4__DENALI_PHY_304_READ_MASK 0x0007FFFFU
  703. #define LPDDR4__DENALI_PHY_304_WRITE_MASK 0x0007FFFFU
  704. #define LPDDR4__DENALI_PHY_304__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1_MASK 0x000000FFU
  705. #define LPDDR4__DENALI_PHY_304__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1_SHIFT 0U
  706. #define LPDDR4__DENALI_PHY_304__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1_WIDTH 8U
  707. #define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_304
  708. #define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_304__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1
  709. #define LPDDR4__DENALI_PHY_304__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1_MASK 0x0000FF00U
  710. #define LPDDR4__DENALI_PHY_304__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1_SHIFT 8U
  711. #define LPDDR4__DENALI_PHY_304__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1_WIDTH 8U
  712. #define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_304
  713. #define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_304__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1
  714. #define LPDDR4__DENALI_PHY_304__PHY_WR_SHIFT_OBS_1_MASK 0x00070000U
  715. #define LPDDR4__DENALI_PHY_304__PHY_WR_SHIFT_OBS_1_SHIFT 16U
  716. #define LPDDR4__DENALI_PHY_304__PHY_WR_SHIFT_OBS_1_WIDTH 3U
  717. #define LPDDR4__PHY_WR_SHIFT_OBS_1__REG DENALI_PHY_304
  718. #define LPDDR4__PHY_WR_SHIFT_OBS_1__FLD LPDDR4__DENALI_PHY_304__PHY_WR_SHIFT_OBS_1
  719. #define LPDDR4__DENALI_PHY_305_READ_MASK 0x03FF03FFU
  720. #define LPDDR4__DENALI_PHY_305_WRITE_MASK 0x03FF03FFU
  721. #define LPDDR4__DENALI_PHY_305__PHY_WRLVL_HARD0_DELAY_OBS_1_MASK 0x000003FFU
  722. #define LPDDR4__DENALI_PHY_305__PHY_WRLVL_HARD0_DELAY_OBS_1_SHIFT 0U
  723. #define LPDDR4__DENALI_PHY_305__PHY_WRLVL_HARD0_DELAY_OBS_1_WIDTH 10U
  724. #define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_1__REG DENALI_PHY_305
  725. #define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_1__FLD LPDDR4__DENALI_PHY_305__PHY_WRLVL_HARD0_DELAY_OBS_1
  726. #define LPDDR4__DENALI_PHY_305__PHY_WRLVL_HARD1_DELAY_OBS_1_MASK 0x03FF0000U
  727. #define LPDDR4__DENALI_PHY_305__PHY_WRLVL_HARD1_DELAY_OBS_1_SHIFT 16U
  728. #define LPDDR4__DENALI_PHY_305__PHY_WRLVL_HARD1_DELAY_OBS_1_WIDTH 10U
  729. #define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_1__REG DENALI_PHY_305
  730. #define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_1__FLD LPDDR4__DENALI_PHY_305__PHY_WRLVL_HARD1_DELAY_OBS_1
  731. #define LPDDR4__DENALI_PHY_306_READ_MASK 0x0001FFFFU
  732. #define LPDDR4__DENALI_PHY_306_WRITE_MASK 0x0001FFFFU
  733. #define LPDDR4__DENALI_PHY_306__PHY_WRLVL_STATUS_OBS_1_MASK 0x0001FFFFU
  734. #define LPDDR4__DENALI_PHY_306__PHY_WRLVL_STATUS_OBS_1_SHIFT 0U
  735. #define LPDDR4__DENALI_PHY_306__PHY_WRLVL_STATUS_OBS_1_WIDTH 17U
  736. #define LPDDR4__PHY_WRLVL_STATUS_OBS_1__REG DENALI_PHY_306
  737. #define LPDDR4__PHY_WRLVL_STATUS_OBS_1__FLD LPDDR4__DENALI_PHY_306__PHY_WRLVL_STATUS_OBS_1
  738. #define LPDDR4__DENALI_PHY_307_READ_MASK 0x03FF03FFU
  739. #define LPDDR4__DENALI_PHY_307_WRITE_MASK 0x03FF03FFU
  740. #define LPDDR4__DENALI_PHY_307__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1_MASK 0x000003FFU
  741. #define LPDDR4__DENALI_PHY_307__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1_SHIFT 0U
  742. #define LPDDR4__DENALI_PHY_307__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1_WIDTH 10U
  743. #define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_307
  744. #define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_307__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1
  745. #define LPDDR4__DENALI_PHY_307__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1_MASK 0x03FF0000U
  746. #define LPDDR4__DENALI_PHY_307__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1_SHIFT 16U
  747. #define LPDDR4__DENALI_PHY_307__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1_WIDTH 10U
  748. #define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_307
  749. #define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_307__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1
  750. #define LPDDR4__DENALI_PHY_308_READ_MASK 0x3FFFFFFFU
  751. #define LPDDR4__DENALI_PHY_308_WRITE_MASK 0x3FFFFFFFU
  752. #define LPDDR4__DENALI_PHY_308__PHY_WRLVL_ERROR_OBS_1_MASK 0x0000FFFFU
  753. #define LPDDR4__DENALI_PHY_308__PHY_WRLVL_ERROR_OBS_1_SHIFT 0U
  754. #define LPDDR4__DENALI_PHY_308__PHY_WRLVL_ERROR_OBS_1_WIDTH 16U
  755. #define LPDDR4__PHY_WRLVL_ERROR_OBS_1__REG DENALI_PHY_308
  756. #define LPDDR4__PHY_WRLVL_ERROR_OBS_1__FLD LPDDR4__DENALI_PHY_308__PHY_WRLVL_ERROR_OBS_1
  757. #define LPDDR4__DENALI_PHY_308__PHY_GTLVL_HARD0_DELAY_OBS_1_MASK 0x3FFF0000U
  758. #define LPDDR4__DENALI_PHY_308__PHY_GTLVL_HARD0_DELAY_OBS_1_SHIFT 16U
  759. #define LPDDR4__DENALI_PHY_308__PHY_GTLVL_HARD0_DELAY_OBS_1_WIDTH 14U
  760. #define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_1__REG DENALI_PHY_308
  761. #define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_1__FLD LPDDR4__DENALI_PHY_308__PHY_GTLVL_HARD0_DELAY_OBS_1
  762. #define LPDDR4__DENALI_PHY_309_READ_MASK 0x00003FFFU
  763. #define LPDDR4__DENALI_PHY_309_WRITE_MASK 0x00003FFFU
  764. #define LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD1_DELAY_OBS_1_MASK 0x00003FFFU
  765. #define LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD1_DELAY_OBS_1_SHIFT 0U
  766. #define LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD1_DELAY_OBS_1_WIDTH 14U
  767. #define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_1__REG DENALI_PHY_309
  768. #define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_1__FLD LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD1_DELAY_OBS_1
  769. #define LPDDR4__DENALI_PHY_310_READ_MASK 0x0003FFFFU
  770. #define LPDDR4__DENALI_PHY_310_WRITE_MASK 0x0003FFFFU
  771. #define LPDDR4__DENALI_PHY_310__PHY_GTLVL_STATUS_OBS_1_MASK 0x0003FFFFU
  772. #define LPDDR4__DENALI_PHY_310__PHY_GTLVL_STATUS_OBS_1_SHIFT 0U
  773. #define LPDDR4__DENALI_PHY_310__PHY_GTLVL_STATUS_OBS_1_WIDTH 18U
  774. #define LPDDR4__PHY_GTLVL_STATUS_OBS_1__REG DENALI_PHY_310
  775. #define LPDDR4__PHY_GTLVL_STATUS_OBS_1__FLD LPDDR4__DENALI_PHY_310__PHY_GTLVL_STATUS_OBS_1
  776. #define LPDDR4__DENALI_PHY_311_READ_MASK 0x03FF03FFU
  777. #define LPDDR4__DENALI_PHY_311_WRITE_MASK 0x03FF03FFU
  778. #define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1_MASK 0x000003FFU
  779. #define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1_SHIFT 0U
  780. #define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1_WIDTH 10U
  781. #define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1__REG DENALI_PHY_311
  782. #define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1
  783. #define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1_MASK 0x03FF0000U
  784. #define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1_SHIFT 16U
  785. #define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1_WIDTH 10U
  786. #define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1__REG DENALI_PHY_311
  787. #define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1
  788. #define LPDDR4__DENALI_PHY_312_READ_MASK 0x00000003U
  789. #define LPDDR4__DENALI_PHY_312_WRITE_MASK 0x00000003U
  790. #define LPDDR4__DENALI_PHY_312__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1_MASK 0x00000003U
  791. #define LPDDR4__DENALI_PHY_312__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1_SHIFT 0U
  792. #define LPDDR4__DENALI_PHY_312__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1_WIDTH 2U
  793. #define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1__REG DENALI_PHY_312
  794. #define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1__FLD LPDDR4__DENALI_PHY_312__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1
  795. #define LPDDR4__DENALI_PHY_313_READ_MASK 0xFFFFFFFFU
  796. #define LPDDR4__DENALI_PHY_313_WRITE_MASK 0xFFFFFFFFU
  797. #define LPDDR4__DENALI_PHY_313__PHY_RDLVL_STATUS_OBS_1_MASK 0xFFFFFFFFU
  798. #define LPDDR4__DENALI_PHY_313__PHY_RDLVL_STATUS_OBS_1_SHIFT 0U
  799. #define LPDDR4__DENALI_PHY_313__PHY_RDLVL_STATUS_OBS_1_WIDTH 32U
  800. #define LPDDR4__PHY_RDLVL_STATUS_OBS_1__REG DENALI_PHY_313
  801. #define LPDDR4__PHY_RDLVL_STATUS_OBS_1__FLD LPDDR4__DENALI_PHY_313__PHY_RDLVL_STATUS_OBS_1
  802. #define LPDDR4__DENALI_PHY_314_READ_MASK 0xFFFFFFFFU
  803. #define LPDDR4__DENALI_PHY_314_WRITE_MASK 0xFFFFFFFFU
  804. #define LPDDR4__DENALI_PHY_314__PHY_RDLVL_PERIODIC_OBS_1_MASK 0xFFFFFFFFU
  805. #define LPDDR4__DENALI_PHY_314__PHY_RDLVL_PERIODIC_OBS_1_SHIFT 0U
  806. #define LPDDR4__DENALI_PHY_314__PHY_RDLVL_PERIODIC_OBS_1_WIDTH 32U
  807. #define LPDDR4__PHY_RDLVL_PERIODIC_OBS_1__REG DENALI_PHY_314
  808. #define LPDDR4__PHY_RDLVL_PERIODIC_OBS_1__FLD LPDDR4__DENALI_PHY_314__PHY_RDLVL_PERIODIC_OBS_1
  809. #define LPDDR4__DENALI_PHY_315_READ_MASK 0x07FF07FFU
  810. #define LPDDR4__DENALI_PHY_315_WRITE_MASK 0x07FF07FFU
  811. #define LPDDR4__DENALI_PHY_315__PHY_WDQLVL_DQDM_LE_DLY_OBS_1_MASK 0x000007FFU
  812. #define LPDDR4__DENALI_PHY_315__PHY_WDQLVL_DQDM_LE_DLY_OBS_1_SHIFT 0U
  813. #define LPDDR4__DENALI_PHY_315__PHY_WDQLVL_DQDM_LE_DLY_OBS_1_WIDTH 11U
  814. #define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_1__REG DENALI_PHY_315
  815. #define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_315__PHY_WDQLVL_DQDM_LE_DLY_OBS_1
  816. #define LPDDR4__DENALI_PHY_315__PHY_WDQLVL_DQDM_TE_DLY_OBS_1_MASK 0x07FF0000U
  817. #define LPDDR4__DENALI_PHY_315__PHY_WDQLVL_DQDM_TE_DLY_OBS_1_SHIFT 16U
  818. #define LPDDR4__DENALI_PHY_315__PHY_WDQLVL_DQDM_TE_DLY_OBS_1_WIDTH 11U
  819. #define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_1__REG DENALI_PHY_315
  820. #define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_315__PHY_WDQLVL_DQDM_TE_DLY_OBS_1
  821. #define LPDDR4__DENALI_PHY_316_READ_MASK 0xFFFFFFFFU
  822. #define LPDDR4__DENALI_PHY_316_WRITE_MASK 0xFFFFFFFFU
  823. #define LPDDR4__DENALI_PHY_316__PHY_WDQLVL_STATUS_OBS_1_MASK 0xFFFFFFFFU
  824. #define LPDDR4__DENALI_PHY_316__PHY_WDQLVL_STATUS_OBS_1_SHIFT 0U
  825. #define LPDDR4__DENALI_PHY_316__PHY_WDQLVL_STATUS_OBS_1_WIDTH 32U
  826. #define LPDDR4__PHY_WDQLVL_STATUS_OBS_1__REG DENALI_PHY_316
  827. #define LPDDR4__PHY_WDQLVL_STATUS_OBS_1__FLD LPDDR4__DENALI_PHY_316__PHY_WDQLVL_STATUS_OBS_1
  828. #define LPDDR4__DENALI_PHY_317_READ_MASK 0xFFFFFFFFU
  829. #define LPDDR4__DENALI_PHY_317_WRITE_MASK 0xFFFFFFFFU
  830. #define LPDDR4__DENALI_PHY_317__PHY_WDQLVL_PERIODIC_OBS_1_MASK 0xFFFFFFFFU
  831. #define LPDDR4__DENALI_PHY_317__PHY_WDQLVL_PERIODIC_OBS_1_SHIFT 0U
  832. #define LPDDR4__DENALI_PHY_317__PHY_WDQLVL_PERIODIC_OBS_1_WIDTH 32U
  833. #define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_1__REG DENALI_PHY_317
  834. #define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_1__FLD LPDDR4__DENALI_PHY_317__PHY_WDQLVL_PERIODIC_OBS_1
  835. #define LPDDR4__DENALI_PHY_318_READ_MASK 0x7FFFFFFFU
  836. #define LPDDR4__DENALI_PHY_318_WRITE_MASK 0x7FFFFFFFU
  837. #define LPDDR4__DENALI_PHY_318__PHY_DDL_MODE_1_MASK 0x7FFFFFFFU
  838. #define LPDDR4__DENALI_PHY_318__PHY_DDL_MODE_1_SHIFT 0U
  839. #define LPDDR4__DENALI_PHY_318__PHY_DDL_MODE_1_WIDTH 31U
  840. #define LPDDR4__PHY_DDL_MODE_1__REG DENALI_PHY_318
  841. #define LPDDR4__PHY_DDL_MODE_1__FLD LPDDR4__DENALI_PHY_318__PHY_DDL_MODE_1
  842. #define LPDDR4__DENALI_PHY_319_READ_MASK 0x0000003FU
  843. #define LPDDR4__DENALI_PHY_319_WRITE_MASK 0x0000003FU
  844. #define LPDDR4__DENALI_PHY_319__PHY_DDL_MASK_1_MASK 0x0000003FU
  845. #define LPDDR4__DENALI_PHY_319__PHY_DDL_MASK_1_SHIFT 0U
  846. #define LPDDR4__DENALI_PHY_319__PHY_DDL_MASK_1_WIDTH 6U
  847. #define LPDDR4__PHY_DDL_MASK_1__REG DENALI_PHY_319
  848. #define LPDDR4__PHY_DDL_MASK_1__FLD LPDDR4__DENALI_PHY_319__PHY_DDL_MASK_1
  849. #define LPDDR4__DENALI_PHY_320_READ_MASK 0xFFFFFFFFU
  850. #define LPDDR4__DENALI_PHY_320_WRITE_MASK 0xFFFFFFFFU
  851. #define LPDDR4__DENALI_PHY_320__PHY_DDL_TEST_OBS_1_MASK 0xFFFFFFFFU
  852. #define LPDDR4__DENALI_PHY_320__PHY_DDL_TEST_OBS_1_SHIFT 0U
  853. #define LPDDR4__DENALI_PHY_320__PHY_DDL_TEST_OBS_1_WIDTH 32U
  854. #define LPDDR4__PHY_DDL_TEST_OBS_1__REG DENALI_PHY_320
  855. #define LPDDR4__PHY_DDL_TEST_OBS_1__FLD LPDDR4__DENALI_PHY_320__PHY_DDL_TEST_OBS_1
  856. #define LPDDR4__DENALI_PHY_321_READ_MASK 0xFFFFFFFFU
  857. #define LPDDR4__DENALI_PHY_321_WRITE_MASK 0xFFFFFFFFU
  858. #define LPDDR4__DENALI_PHY_321__PHY_DDL_TEST_MSTR_DLY_OBS_1_MASK 0xFFFFFFFFU
  859. #define LPDDR4__DENALI_PHY_321__PHY_DDL_TEST_MSTR_DLY_OBS_1_SHIFT 0U
  860. #define LPDDR4__DENALI_PHY_321__PHY_DDL_TEST_MSTR_DLY_OBS_1_WIDTH 32U
  861. #define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_1__REG DENALI_PHY_321
  862. #define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_321__PHY_DDL_TEST_MSTR_DLY_OBS_1
  863. #define LPDDR4__DENALI_PHY_322_READ_MASK 0x010001FFU
  864. #define LPDDR4__DENALI_PHY_322_WRITE_MASK 0x010001FFU
  865. #define LPDDR4__DENALI_PHY_322__PHY_DDL_TRACK_UPD_THRESHOLD_1_MASK 0x000000FFU
  866. #define LPDDR4__DENALI_PHY_322__PHY_DDL_TRACK_UPD_THRESHOLD_1_SHIFT 0U
  867. #define LPDDR4__DENALI_PHY_322__PHY_DDL_TRACK_UPD_THRESHOLD_1_WIDTH 8U
  868. #define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_1__REG DENALI_PHY_322
  869. #define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_322__PHY_DDL_TRACK_UPD_THRESHOLD_1
  870. #define LPDDR4__DENALI_PHY_322__PHY_LP4_WDQS_OE_EXTEND_1_MASK 0x00000100U
  871. #define LPDDR4__DENALI_PHY_322__PHY_LP4_WDQS_OE_EXTEND_1_SHIFT 8U
  872. #define LPDDR4__DENALI_PHY_322__PHY_LP4_WDQS_OE_EXTEND_1_WIDTH 1U
  873. #define LPDDR4__DENALI_PHY_322__PHY_LP4_WDQS_OE_EXTEND_1_WOCLR 0U
  874. #define LPDDR4__DENALI_PHY_322__PHY_LP4_WDQS_OE_EXTEND_1_WOSET 0U
  875. #define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_1__REG DENALI_PHY_322
  876. #define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_1__FLD LPDDR4__DENALI_PHY_322__PHY_LP4_WDQS_OE_EXTEND_1
  877. #define LPDDR4__DENALI_PHY_322__SC_PHY_RX_CAL_START_1_MASK 0x00010000U
  878. #define LPDDR4__DENALI_PHY_322__SC_PHY_RX_CAL_START_1_SHIFT 16U
  879. #define LPDDR4__DENALI_PHY_322__SC_PHY_RX_CAL_START_1_WIDTH 1U
  880. #define LPDDR4__DENALI_PHY_322__SC_PHY_RX_CAL_START_1_WOCLR 0U
  881. #define LPDDR4__DENALI_PHY_322__SC_PHY_RX_CAL_START_1_WOSET 0U
  882. #define LPDDR4__SC_PHY_RX_CAL_START_1__REG DENALI_PHY_322
  883. #define LPDDR4__SC_PHY_RX_CAL_START_1__FLD LPDDR4__DENALI_PHY_322__SC_PHY_RX_CAL_START_1
  884. #define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_OVERRIDE_1_MASK 0x01000000U
  885. #define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_OVERRIDE_1_SHIFT 24U
  886. #define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_OVERRIDE_1_WIDTH 1U
  887. #define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_OVERRIDE_1_WOCLR 0U
  888. #define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_OVERRIDE_1_WOSET 0U
  889. #define LPDDR4__PHY_RX_CAL_OVERRIDE_1__REG DENALI_PHY_322
  890. #define LPDDR4__PHY_RX_CAL_OVERRIDE_1__FLD LPDDR4__DENALI_PHY_322__PHY_RX_CAL_OVERRIDE_1
  891. #define LPDDR4__DENALI_PHY_323_READ_MASK 0x01FF01FFU
  892. #define LPDDR4__DENALI_PHY_323_WRITE_MASK 0x01FF01FFU
  893. #define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_SAMPLE_WAIT_1_MASK 0x000000FFU
  894. #define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_SAMPLE_WAIT_1_SHIFT 0U
  895. #define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_SAMPLE_WAIT_1_WIDTH 8U
  896. #define LPDDR4__PHY_RX_CAL_SAMPLE_WAIT_1__REG DENALI_PHY_323
  897. #define LPDDR4__PHY_RX_CAL_SAMPLE_WAIT_1__FLD LPDDR4__DENALI_PHY_323__PHY_RX_CAL_SAMPLE_WAIT_1
  898. #define LPDDR4__DENALI_PHY_323__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_1_MASK 0x00000100U
  899. #define LPDDR4__DENALI_PHY_323__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_1_SHIFT 8U
  900. #define LPDDR4__DENALI_PHY_323__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_1_WIDTH 1U
  901. #define LPDDR4__DENALI_PHY_323__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_1_WOCLR 0U
  902. #define LPDDR4__DENALI_PHY_323__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_1_WOSET 0U
  903. #define LPDDR4__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_1__REG DENALI_PHY_323
  904. #define LPDDR4__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_1__FLD LPDDR4__DENALI_PHY_323__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_1
  905. #define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ0_1_MASK 0x01FF0000U
  906. #define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ0_1_SHIFT 16U
  907. #define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ0_1_WIDTH 9U
  908. #define LPDDR4__PHY_RX_CAL_DQ0_1__REG DENALI_PHY_323
  909. #define LPDDR4__PHY_RX_CAL_DQ0_1__FLD LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ0_1
  910. #define LPDDR4__DENALI_PHY_324_READ_MASK 0x01FF01FFU
  911. #define LPDDR4__DENALI_PHY_324_WRITE_MASK 0x01FF01FFU
  912. #define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ1_1_MASK 0x000001FFU
  913. #define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ1_1_SHIFT 0U
  914. #define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ1_1_WIDTH 9U
  915. #define LPDDR4__PHY_RX_CAL_DQ1_1__REG DENALI_PHY_324
  916. #define LPDDR4__PHY_RX_CAL_DQ1_1__FLD LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ1_1
  917. #define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ2_1_MASK 0x01FF0000U
  918. #define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ2_1_SHIFT 16U
  919. #define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ2_1_WIDTH 9U
  920. #define LPDDR4__PHY_RX_CAL_DQ2_1__REG DENALI_PHY_324
  921. #define LPDDR4__PHY_RX_CAL_DQ2_1__FLD LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ2_1
  922. #define LPDDR4__DENALI_PHY_325_READ_MASK 0x01FF01FFU
  923. #define LPDDR4__DENALI_PHY_325_WRITE_MASK 0x01FF01FFU
  924. #define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ3_1_MASK 0x000001FFU
  925. #define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ3_1_SHIFT 0U
  926. #define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ3_1_WIDTH 9U
  927. #define LPDDR4__PHY_RX_CAL_DQ3_1__REG DENALI_PHY_325
  928. #define LPDDR4__PHY_RX_CAL_DQ3_1__FLD LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ3_1
  929. #define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ4_1_MASK 0x01FF0000U
  930. #define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ4_1_SHIFT 16U
  931. #define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ4_1_WIDTH 9U
  932. #define LPDDR4__PHY_RX_CAL_DQ4_1__REG DENALI_PHY_325
  933. #define LPDDR4__PHY_RX_CAL_DQ4_1__FLD LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ4_1
  934. #define LPDDR4__DENALI_PHY_326_READ_MASK 0x01FF01FFU
  935. #define LPDDR4__DENALI_PHY_326_WRITE_MASK 0x01FF01FFU
  936. #define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ5_1_MASK 0x000001FFU
  937. #define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ5_1_SHIFT 0U
  938. #define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ5_1_WIDTH 9U
  939. #define LPDDR4__PHY_RX_CAL_DQ5_1__REG DENALI_PHY_326
  940. #define LPDDR4__PHY_RX_CAL_DQ5_1__FLD LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ5_1
  941. #define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ6_1_MASK 0x01FF0000U
  942. #define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ6_1_SHIFT 16U
  943. #define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ6_1_WIDTH 9U
  944. #define LPDDR4__PHY_RX_CAL_DQ6_1__REG DENALI_PHY_326
  945. #define LPDDR4__PHY_RX_CAL_DQ6_1__FLD LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ6_1
  946. #define LPDDR4__DENALI_PHY_327_READ_MASK 0x000001FFU
  947. #define LPDDR4__DENALI_PHY_327_WRITE_MASK 0x000001FFU
  948. #define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQ7_1_MASK 0x000001FFU
  949. #define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQ7_1_SHIFT 0U
  950. #define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQ7_1_WIDTH 9U
  951. #define LPDDR4__PHY_RX_CAL_DQ7_1__REG DENALI_PHY_327
  952. #define LPDDR4__PHY_RX_CAL_DQ7_1__FLD LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQ7_1
  953. #define LPDDR4__DENALI_PHY_328_READ_MASK 0x0003FFFFU
  954. #define LPDDR4__DENALI_PHY_328_WRITE_MASK 0x0003FFFFU
  955. #define LPDDR4__DENALI_PHY_328__PHY_RX_CAL_DM_1_MASK 0x0003FFFFU
  956. #define LPDDR4__DENALI_PHY_328__PHY_RX_CAL_DM_1_SHIFT 0U
  957. #define LPDDR4__DENALI_PHY_328__PHY_RX_CAL_DM_1_WIDTH 18U
  958. #define LPDDR4__PHY_RX_CAL_DM_1__REG DENALI_PHY_328
  959. #define LPDDR4__PHY_RX_CAL_DM_1__FLD LPDDR4__DENALI_PHY_328__PHY_RX_CAL_DM_1
  960. #define LPDDR4__DENALI_PHY_329_READ_MASK 0x01FF01FFU
  961. #define LPDDR4__DENALI_PHY_329_WRITE_MASK 0x01FF01FFU
  962. #define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_DQS_1_MASK 0x000001FFU
  963. #define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_DQS_1_SHIFT 0U
  964. #define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_DQS_1_WIDTH 9U
  965. #define LPDDR4__PHY_RX_CAL_DQS_1__REG DENALI_PHY_329
  966. #define LPDDR4__PHY_RX_CAL_DQS_1__FLD LPDDR4__DENALI_PHY_329__PHY_RX_CAL_DQS_1
  967. #define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_FDBK_1_MASK 0x01FF0000U
  968. #define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_FDBK_1_SHIFT 16U
  969. #define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_FDBK_1_WIDTH 9U
  970. #define LPDDR4__PHY_RX_CAL_FDBK_1__REG DENALI_PHY_329
  971. #define LPDDR4__PHY_RX_CAL_FDBK_1__FLD LPDDR4__DENALI_PHY_329__PHY_RX_CAL_FDBK_1
  972. #define LPDDR4__DENALI_PHY_330_READ_MASK 0x01FF07FFU
  973. #define LPDDR4__DENALI_PHY_330_WRITE_MASK 0x01FF07FFU
  974. #define LPDDR4__DENALI_PHY_330__PHY_RX_CAL_OBS_1_MASK 0x000007FFU
  975. #define LPDDR4__DENALI_PHY_330__PHY_RX_CAL_OBS_1_SHIFT 0U
  976. #define LPDDR4__DENALI_PHY_330__PHY_RX_CAL_OBS_1_WIDTH 11U
  977. #define LPDDR4__PHY_RX_CAL_OBS_1__REG DENALI_PHY_330
  978. #define LPDDR4__PHY_RX_CAL_OBS_1__FLD LPDDR4__DENALI_PHY_330__PHY_RX_CAL_OBS_1
  979. #define LPDDR4__DENALI_PHY_330__PHY_RX_CAL_LOCK_OBS_1_MASK 0x01FF0000U
  980. #define LPDDR4__DENALI_PHY_330__PHY_RX_CAL_LOCK_OBS_1_SHIFT 16U
  981. #define LPDDR4__DENALI_PHY_330__PHY_RX_CAL_LOCK_OBS_1_WIDTH 9U
  982. #define LPDDR4__PHY_RX_CAL_LOCK_OBS_1__REG DENALI_PHY_330
  983. #define LPDDR4__PHY_RX_CAL_LOCK_OBS_1__FLD LPDDR4__DENALI_PHY_330__PHY_RX_CAL_LOCK_OBS_1
  984. #define LPDDR4__DENALI_PHY_331_READ_MASK 0x017F7F01U
  985. #define LPDDR4__DENALI_PHY_331_WRITE_MASK 0x017F7F01U
  986. #define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DISABLE_1_MASK 0x00000001U
  987. #define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DISABLE_1_SHIFT 0U
  988. #define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DISABLE_1_WIDTH 1U
  989. #define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DISABLE_1_WOCLR 0U
  990. #define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DISABLE_1_WOSET 0U
  991. #define LPDDR4__PHY_RX_CAL_DISABLE_1__REG DENALI_PHY_331
  992. #define LPDDR4__PHY_RX_CAL_DISABLE_1__FLD LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DISABLE_1
  993. #define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_SE_ADJUST_1_MASK 0x00007F00U
  994. #define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_SE_ADJUST_1_SHIFT 8U
  995. #define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_SE_ADJUST_1_WIDTH 7U
  996. #define LPDDR4__PHY_RX_CAL_SE_ADJUST_1__REG DENALI_PHY_331
  997. #define LPDDR4__PHY_RX_CAL_SE_ADJUST_1__FLD LPDDR4__DENALI_PHY_331__PHY_RX_CAL_SE_ADJUST_1
  998. #define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DIFF_ADJUST_1_MASK 0x007F0000U
  999. #define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DIFF_ADJUST_1_SHIFT 16U
  1000. #define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DIFF_ADJUST_1_WIDTH 7U
  1001. #define LPDDR4__PHY_RX_CAL_DIFF_ADJUST_1__REG DENALI_PHY_331
  1002. #define LPDDR4__PHY_RX_CAL_DIFF_ADJUST_1__FLD LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DIFF_ADJUST_1
  1003. #define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_COMP_VAL_1_MASK 0x01000000U
  1004. #define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_COMP_VAL_1_SHIFT 24U
  1005. #define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_COMP_VAL_1_WIDTH 1U
  1006. #define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_COMP_VAL_1_WOCLR 0U
  1007. #define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_COMP_VAL_1_WOSET 0U
  1008. #define LPDDR4__PHY_RX_CAL_COMP_VAL_1__REG DENALI_PHY_331
  1009. #define LPDDR4__PHY_RX_CAL_COMP_VAL_1__FLD LPDDR4__DENALI_PHY_331__PHY_RX_CAL_COMP_VAL_1
  1010. #define LPDDR4__DENALI_PHY_332_READ_MASK 0x07FF0FFFU
  1011. #define LPDDR4__DENALI_PHY_332_WRITE_MASK 0x07FF0FFFU
  1012. #define LPDDR4__DENALI_PHY_332__PHY_RX_CAL_INDEX_MASK_1_MASK 0x00000FFFU
  1013. #define LPDDR4__DENALI_PHY_332__PHY_RX_CAL_INDEX_MASK_1_SHIFT 0U
  1014. #define LPDDR4__DENALI_PHY_332__PHY_RX_CAL_INDEX_MASK_1_WIDTH 12U
  1015. #define LPDDR4__PHY_RX_CAL_INDEX_MASK_1__REG DENALI_PHY_332
  1016. #define LPDDR4__PHY_RX_CAL_INDEX_MASK_1__FLD LPDDR4__DENALI_PHY_332__PHY_RX_CAL_INDEX_MASK_1
  1017. #define LPDDR4__DENALI_PHY_332__PHY_PAD_RX_BIAS_EN_1_MASK 0x07FF0000U
  1018. #define LPDDR4__DENALI_PHY_332__PHY_PAD_RX_BIAS_EN_1_SHIFT 16U
  1019. #define LPDDR4__DENALI_PHY_332__PHY_PAD_RX_BIAS_EN_1_WIDTH 11U
  1020. #define LPDDR4__PHY_PAD_RX_BIAS_EN_1__REG DENALI_PHY_332
  1021. #define LPDDR4__PHY_PAD_RX_BIAS_EN_1__FLD LPDDR4__DENALI_PHY_332__PHY_PAD_RX_BIAS_EN_1
  1022. #define LPDDR4__DENALI_PHY_333_READ_MASK 0x03FFFF1FU
  1023. #define LPDDR4__DENALI_PHY_333_WRITE_MASK 0x03FFFF1FU
  1024. #define LPDDR4__DENALI_PHY_333__PHY_STATIC_TOG_DISABLE_1_MASK 0x0000001FU
  1025. #define LPDDR4__DENALI_PHY_333__PHY_STATIC_TOG_DISABLE_1_SHIFT 0U
  1026. #define LPDDR4__DENALI_PHY_333__PHY_STATIC_TOG_DISABLE_1_WIDTH 5U
  1027. #define LPDDR4__PHY_STATIC_TOG_DISABLE_1__REG DENALI_PHY_333
  1028. #define LPDDR4__PHY_STATIC_TOG_DISABLE_1__FLD LPDDR4__DENALI_PHY_333__PHY_STATIC_TOG_DISABLE_1
  1029. #define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_CAL_SAMPLE_WAIT_1_MASK 0x0000FF00U
  1030. #define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_CAL_SAMPLE_WAIT_1_SHIFT 8U
  1031. #define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_CAL_SAMPLE_WAIT_1_WIDTH 8U
  1032. #define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_1__REG DENALI_PHY_333
  1033. #define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_1__FLD LPDDR4__DENALI_PHY_333__PHY_DATA_DC_CAL_SAMPLE_WAIT_1
  1034. #define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_CAL_TIMEOUT_1_MASK 0x00FF0000U
  1035. #define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_CAL_TIMEOUT_1_SHIFT 16U
  1036. #define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_CAL_TIMEOUT_1_WIDTH 8U
  1037. #define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_1__REG DENALI_PHY_333
  1038. #define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_1__FLD LPDDR4__DENALI_PHY_333__PHY_DATA_DC_CAL_TIMEOUT_1
  1039. #define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_WEIGHT_1_MASK 0x03000000U
  1040. #define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_WEIGHT_1_SHIFT 24U
  1041. #define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_WEIGHT_1_WIDTH 2U
  1042. #define LPDDR4__PHY_DATA_DC_WEIGHT_1__REG DENALI_PHY_333
  1043. #define LPDDR4__PHY_DATA_DC_WEIGHT_1__FLD LPDDR4__DENALI_PHY_333__PHY_DATA_DC_WEIGHT_1
  1044. #define LPDDR4__DENALI_PHY_334_READ_MASK 0x01FFFF3FU
  1045. #define LPDDR4__DENALI_PHY_334_WRITE_MASK 0x01FFFF3FU
  1046. #define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_START_1_MASK 0x0000003FU
  1047. #define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_START_1_SHIFT 0U
  1048. #define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_START_1_WIDTH 6U
  1049. #define LPDDR4__PHY_DATA_DC_ADJUST_START_1__REG DENALI_PHY_334
  1050. #define LPDDR4__PHY_DATA_DC_ADJUST_START_1__FLD LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_START_1
  1051. #define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_SAMPLE_CNT_1_MASK 0x0000FF00U
  1052. #define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_SAMPLE_CNT_1_SHIFT 8U
  1053. #define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_SAMPLE_CNT_1_WIDTH 8U
  1054. #define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_1__REG DENALI_PHY_334
  1055. #define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_1__FLD LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_SAMPLE_CNT_1
  1056. #define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_THRSHLD_1_MASK 0x00FF0000U
  1057. #define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_THRSHLD_1_SHIFT 16U
  1058. #define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_THRSHLD_1_WIDTH 8U
  1059. #define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_1__REG DENALI_PHY_334
  1060. #define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_1__FLD LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_THRSHLD_1
  1061. #define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_DIRECT_1_MASK 0x01000000U
  1062. #define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_DIRECT_1_SHIFT 24U
  1063. #define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_DIRECT_1_WIDTH 1U
  1064. #define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_DIRECT_1_WOCLR 0U
  1065. #define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_DIRECT_1_WOSET 0U
  1066. #define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_1__REG DENALI_PHY_334
  1067. #define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_1__FLD LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_DIRECT_1
  1068. #define LPDDR4__DENALI_PHY_335_READ_MASK 0x07030101U
  1069. #define LPDDR4__DENALI_PHY_335_WRITE_MASK 0x07030101U
  1070. #define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_POLARITY_1_MASK 0x00000001U
  1071. #define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_POLARITY_1_SHIFT 0U
  1072. #define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_POLARITY_1_WIDTH 1U
  1073. #define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_POLARITY_1_WOCLR 0U
  1074. #define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_POLARITY_1_WOSET 0U
  1075. #define LPDDR4__PHY_DATA_DC_CAL_POLARITY_1__REG DENALI_PHY_335
  1076. #define LPDDR4__PHY_DATA_DC_CAL_POLARITY_1__FLD LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_POLARITY_1
  1077. #define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_START_1_MASK 0x00000100U
  1078. #define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_START_1_SHIFT 8U
  1079. #define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_START_1_WIDTH 1U
  1080. #define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_START_1_WOCLR 0U
  1081. #define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_START_1_WOSET 0U
  1082. #define LPDDR4__PHY_DATA_DC_CAL_START_1__REG DENALI_PHY_335
  1083. #define LPDDR4__PHY_DATA_DC_CAL_START_1__FLD LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_START_1
  1084. #define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_SW_RANK_1_MASK 0x00030000U
  1085. #define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_SW_RANK_1_SHIFT 16U
  1086. #define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_SW_RANK_1_WIDTH 2U
  1087. #define LPDDR4__PHY_DATA_DC_SW_RANK_1__REG DENALI_PHY_335
  1088. #define LPDDR4__PHY_DATA_DC_SW_RANK_1__FLD LPDDR4__DENALI_PHY_335__PHY_DATA_DC_SW_RANK_1
  1089. #define LPDDR4__DENALI_PHY_335__PHY_FDBK_PWR_CTRL_1_MASK 0x07000000U
  1090. #define LPDDR4__DENALI_PHY_335__PHY_FDBK_PWR_CTRL_1_SHIFT 24U
  1091. #define LPDDR4__DENALI_PHY_335__PHY_FDBK_PWR_CTRL_1_WIDTH 3U
  1092. #define LPDDR4__PHY_FDBK_PWR_CTRL_1__REG DENALI_PHY_335
  1093. #define LPDDR4__PHY_FDBK_PWR_CTRL_1__FLD LPDDR4__DENALI_PHY_335__PHY_FDBK_PWR_CTRL_1
  1094. #define LPDDR4__DENALI_PHY_336_READ_MASK 0x01010101U
  1095. #define LPDDR4__DENALI_PHY_336_WRITE_MASK 0x01010101U
  1096. #define LPDDR4__DENALI_PHY_336__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_MASK 0x00000001U
  1097. #define LPDDR4__DENALI_PHY_336__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_SHIFT 0U
  1098. #define LPDDR4__DENALI_PHY_336__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_WIDTH 1U
  1099. #define LPDDR4__DENALI_PHY_336__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_WOCLR 0U
  1100. #define LPDDR4__DENALI_PHY_336__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_WOSET 0U
  1101. #define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_1__REG DENALI_PHY_336
  1102. #define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_336__PHY_SLV_DLY_CTRL_GATE_DISABLE_1
  1103. #define LPDDR4__DENALI_PHY_336__PHY_RDPATH_GATE_DISABLE_1_MASK 0x00000100U
  1104. #define LPDDR4__DENALI_PHY_336__PHY_RDPATH_GATE_DISABLE_1_SHIFT 8U
  1105. #define LPDDR4__DENALI_PHY_336__PHY_RDPATH_GATE_DISABLE_1_WIDTH 1U
  1106. #define LPDDR4__DENALI_PHY_336__PHY_RDPATH_GATE_DISABLE_1_WOCLR 0U
  1107. #define LPDDR4__DENALI_PHY_336__PHY_RDPATH_GATE_DISABLE_1_WOSET 0U
  1108. #define LPDDR4__PHY_RDPATH_GATE_DISABLE_1__REG DENALI_PHY_336
  1109. #define LPDDR4__PHY_RDPATH_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_336__PHY_RDPATH_GATE_DISABLE_1
  1110. #define LPDDR4__DENALI_PHY_336__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_MASK 0x00010000U
  1111. #define LPDDR4__DENALI_PHY_336__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_SHIFT 16U
  1112. #define LPDDR4__DENALI_PHY_336__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_WIDTH 1U
  1113. #define LPDDR4__DENALI_PHY_336__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_WOCLR 0U
  1114. #define LPDDR4__DENALI_PHY_336__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_WOSET 0U
  1115. #define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1__REG DENALI_PHY_336
  1116. #define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_336__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1
  1117. #define LPDDR4__DENALI_PHY_336__PHY_SLICE_PWR_RDC_DISABLE_1_MASK 0x01000000U
  1118. #define LPDDR4__DENALI_PHY_336__PHY_SLICE_PWR_RDC_DISABLE_1_SHIFT 24U
  1119. #define LPDDR4__DENALI_PHY_336__PHY_SLICE_PWR_RDC_DISABLE_1_WIDTH 1U
  1120. #define LPDDR4__DENALI_PHY_336__PHY_SLICE_PWR_RDC_DISABLE_1_WOCLR 0U
  1121. #define LPDDR4__DENALI_PHY_336__PHY_SLICE_PWR_RDC_DISABLE_1_WOSET 0U
  1122. #define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_1__REG DENALI_PHY_336
  1123. #define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_1__FLD LPDDR4__DENALI_PHY_336__PHY_SLICE_PWR_RDC_DISABLE_1
  1124. #define LPDDR4__DENALI_PHY_337_READ_MASK 0x3FFF07FFU
  1125. #define LPDDR4__DENALI_PHY_337_WRITE_MASK 0x3FFF07FFU
  1126. #define LPDDR4__DENALI_PHY_337__PHY_PARITY_ERROR_REGIF_1_MASK 0x000007FFU
  1127. #define LPDDR4__DENALI_PHY_337__PHY_PARITY_ERROR_REGIF_1_SHIFT 0U
  1128. #define LPDDR4__DENALI_PHY_337__PHY_PARITY_ERROR_REGIF_1_WIDTH 11U
  1129. #define LPDDR4__PHY_PARITY_ERROR_REGIF_1__REG DENALI_PHY_337
  1130. #define LPDDR4__PHY_PARITY_ERROR_REGIF_1__FLD LPDDR4__DENALI_PHY_337__PHY_PARITY_ERROR_REGIF_1
  1131. #define LPDDR4__DENALI_PHY_337__PHY_DS_FSM_ERROR_INFO_1_MASK 0x3FFF0000U
  1132. #define LPDDR4__DENALI_PHY_337__PHY_DS_FSM_ERROR_INFO_1_SHIFT 16U
  1133. #define LPDDR4__DENALI_PHY_337__PHY_DS_FSM_ERROR_INFO_1_WIDTH 14U
  1134. #define LPDDR4__PHY_DS_FSM_ERROR_INFO_1__REG DENALI_PHY_337
  1135. #define LPDDR4__PHY_DS_FSM_ERROR_INFO_1__FLD LPDDR4__DENALI_PHY_337__PHY_DS_FSM_ERROR_INFO_1
  1136. #define LPDDR4__DENALI_PHY_338_READ_MASK 0x00003FFFU
  1137. #define LPDDR4__DENALI_PHY_338_WRITE_MASK 0x00003FFFU
  1138. #define LPDDR4__DENALI_PHY_338__PHY_DS_FSM_ERROR_INFO_MASK_1_MASK 0x00003FFFU
  1139. #define LPDDR4__DENALI_PHY_338__PHY_DS_FSM_ERROR_INFO_MASK_1_SHIFT 0U
  1140. #define LPDDR4__DENALI_PHY_338__PHY_DS_FSM_ERROR_INFO_MASK_1_WIDTH 14U
  1141. #define LPDDR4__PHY_DS_FSM_ERROR_INFO_MASK_1__REG DENALI_PHY_338
  1142. #define LPDDR4__PHY_DS_FSM_ERROR_INFO_MASK_1__FLD LPDDR4__DENALI_PHY_338__PHY_DS_FSM_ERROR_INFO_MASK_1
  1143. #define LPDDR4__DENALI_PHY_338__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_1_MASK 0x3FFF0000U
  1144. #define LPDDR4__DENALI_PHY_338__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_1_SHIFT 16U
  1145. #define LPDDR4__DENALI_PHY_338__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_1_WIDTH 14U
  1146. #define LPDDR4__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_1__REG DENALI_PHY_338
  1147. #define LPDDR4__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_1__FLD LPDDR4__DENALI_PHY_338__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_1
  1148. #define LPDDR4__DENALI_PHY_339_READ_MASK 0x00001F1FU
  1149. #define LPDDR4__DENALI_PHY_339_WRITE_MASK 0x00001F1FU
  1150. #define LPDDR4__DENALI_PHY_339__PHY_DS_TRAIN_CALIB_ERROR_INFO_1_MASK 0x0000001FU
  1151. #define LPDDR4__DENALI_PHY_339__PHY_DS_TRAIN_CALIB_ERROR_INFO_1_SHIFT 0U
  1152. #define LPDDR4__DENALI_PHY_339__PHY_DS_TRAIN_CALIB_ERROR_INFO_1_WIDTH 5U
  1153. #define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_1__REG DENALI_PHY_339
  1154. #define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_1__FLD LPDDR4__DENALI_PHY_339__PHY_DS_TRAIN_CALIB_ERROR_INFO_1
  1155. #define LPDDR4__DENALI_PHY_339__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_1_MASK 0x00001F00U
  1156. #define LPDDR4__DENALI_PHY_339__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_1_SHIFT 8U
  1157. #define LPDDR4__DENALI_PHY_339__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_1_WIDTH 5U
  1158. #define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_1__REG DENALI_PHY_339
  1159. #define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_1__FLD LPDDR4__DENALI_PHY_339__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_1
  1160. #define LPDDR4__DENALI_PHY_339__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_1_MASK 0x001F0000U
  1161. #define LPDDR4__DENALI_PHY_339__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_1_SHIFT 16U
  1162. #define LPDDR4__DENALI_PHY_339__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_1_WIDTH 5U
  1163. #define LPDDR4__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_1__REG DENALI_PHY_339
  1164. #define LPDDR4__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_1__FLD LPDDR4__DENALI_PHY_339__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_1
  1165. #define LPDDR4__DENALI_PHY_340_READ_MASK 0x07FFFF07U
  1166. #define LPDDR4__DENALI_PHY_340_WRITE_MASK 0x07FFFF07U
  1167. #define LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_ENABLE_1_MASK 0x00000007U
  1168. #define LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_ENABLE_1_SHIFT 0U
  1169. #define LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_ENABLE_1_WIDTH 3U
  1170. #define LPDDR4__PHY_DQ_TSEL_ENABLE_1__REG DENALI_PHY_340
  1171. #define LPDDR4__PHY_DQ_TSEL_ENABLE_1__FLD LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_ENABLE_1
  1172. #define LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_SELECT_1_MASK 0x00FFFF00U
  1173. #define LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_SELECT_1_SHIFT 8U
  1174. #define LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_SELECT_1_WIDTH 16U
  1175. #define LPDDR4__PHY_DQ_TSEL_SELECT_1__REG DENALI_PHY_340
  1176. #define LPDDR4__PHY_DQ_TSEL_SELECT_1__FLD LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_SELECT_1
  1177. #define LPDDR4__DENALI_PHY_340__PHY_DQS_TSEL_ENABLE_1_MASK 0x07000000U
  1178. #define LPDDR4__DENALI_PHY_340__PHY_DQS_TSEL_ENABLE_1_SHIFT 24U
  1179. #define LPDDR4__DENALI_PHY_340__PHY_DQS_TSEL_ENABLE_1_WIDTH 3U
  1180. #define LPDDR4__PHY_DQS_TSEL_ENABLE_1__REG DENALI_PHY_340
  1181. #define LPDDR4__PHY_DQS_TSEL_ENABLE_1__FLD LPDDR4__DENALI_PHY_340__PHY_DQS_TSEL_ENABLE_1
  1182. #define LPDDR4__DENALI_PHY_341_READ_MASK 0x7F03FFFFU
  1183. #define LPDDR4__DENALI_PHY_341_WRITE_MASK 0x7F03FFFFU
  1184. #define LPDDR4__DENALI_PHY_341__PHY_DQS_TSEL_SELECT_1_MASK 0x0000FFFFU
  1185. #define LPDDR4__DENALI_PHY_341__PHY_DQS_TSEL_SELECT_1_SHIFT 0U
  1186. #define LPDDR4__DENALI_PHY_341__PHY_DQS_TSEL_SELECT_1_WIDTH 16U
  1187. #define LPDDR4__PHY_DQS_TSEL_SELECT_1__REG DENALI_PHY_341
  1188. #define LPDDR4__PHY_DQS_TSEL_SELECT_1__FLD LPDDR4__DENALI_PHY_341__PHY_DQS_TSEL_SELECT_1
  1189. #define LPDDR4__DENALI_PHY_341__PHY_TWO_CYC_PREAMBLE_1_MASK 0x00030000U
  1190. #define LPDDR4__DENALI_PHY_341__PHY_TWO_CYC_PREAMBLE_1_SHIFT 16U
  1191. #define LPDDR4__DENALI_PHY_341__PHY_TWO_CYC_PREAMBLE_1_WIDTH 2U
  1192. #define LPDDR4__PHY_TWO_CYC_PREAMBLE_1__REG DENALI_PHY_341
  1193. #define LPDDR4__PHY_TWO_CYC_PREAMBLE_1__FLD LPDDR4__DENALI_PHY_341__PHY_TWO_CYC_PREAMBLE_1
  1194. #define LPDDR4__DENALI_PHY_341__PHY_VREF_INITIAL_START_POINT_1_MASK 0x7F000000U
  1195. #define LPDDR4__DENALI_PHY_341__PHY_VREF_INITIAL_START_POINT_1_SHIFT 24U
  1196. #define LPDDR4__DENALI_PHY_341__PHY_VREF_INITIAL_START_POINT_1_WIDTH 7U
  1197. #define LPDDR4__PHY_VREF_INITIAL_START_POINT_1__REG DENALI_PHY_341
  1198. #define LPDDR4__PHY_VREF_INITIAL_START_POINT_1__FLD LPDDR4__DENALI_PHY_341__PHY_VREF_INITIAL_START_POINT_1
  1199. #define LPDDR4__DENALI_PHY_342_READ_MASK 0xFF01037FU
  1200. #define LPDDR4__DENALI_PHY_342_WRITE_MASK 0xFF01037FU
  1201. #define LPDDR4__DENALI_PHY_342__PHY_VREF_INITIAL_STOP_POINT_1_MASK 0x0000007FU
  1202. #define LPDDR4__DENALI_PHY_342__PHY_VREF_INITIAL_STOP_POINT_1_SHIFT 0U
  1203. #define LPDDR4__DENALI_PHY_342__PHY_VREF_INITIAL_STOP_POINT_1_WIDTH 7U
  1204. #define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_1__REG DENALI_PHY_342
  1205. #define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_1__FLD LPDDR4__DENALI_PHY_342__PHY_VREF_INITIAL_STOP_POINT_1
  1206. #define LPDDR4__DENALI_PHY_342__PHY_VREF_TRAINING_CTRL_1_MASK 0x00000300U
  1207. #define LPDDR4__DENALI_PHY_342__PHY_VREF_TRAINING_CTRL_1_SHIFT 8U
  1208. #define LPDDR4__DENALI_PHY_342__PHY_VREF_TRAINING_CTRL_1_WIDTH 2U
  1209. #define LPDDR4__PHY_VREF_TRAINING_CTRL_1__REG DENALI_PHY_342
  1210. #define LPDDR4__PHY_VREF_TRAINING_CTRL_1__FLD LPDDR4__DENALI_PHY_342__PHY_VREF_TRAINING_CTRL_1
  1211. #define LPDDR4__DENALI_PHY_342__PHY_NTP_TRAIN_EN_1_MASK 0x00010000U
  1212. #define LPDDR4__DENALI_PHY_342__PHY_NTP_TRAIN_EN_1_SHIFT 16U
  1213. #define LPDDR4__DENALI_PHY_342__PHY_NTP_TRAIN_EN_1_WIDTH 1U
  1214. #define LPDDR4__DENALI_PHY_342__PHY_NTP_TRAIN_EN_1_WOCLR 0U
  1215. #define LPDDR4__DENALI_PHY_342__PHY_NTP_TRAIN_EN_1_WOSET 0U
  1216. #define LPDDR4__PHY_NTP_TRAIN_EN_1__REG DENALI_PHY_342
  1217. #define LPDDR4__PHY_NTP_TRAIN_EN_1__FLD LPDDR4__DENALI_PHY_342__PHY_NTP_TRAIN_EN_1
  1218. #define LPDDR4__DENALI_PHY_342__PHY_NTP_WDQ_STEP_SIZE_1_MASK 0xFF000000U
  1219. #define LPDDR4__DENALI_PHY_342__PHY_NTP_WDQ_STEP_SIZE_1_SHIFT 24U
  1220. #define LPDDR4__DENALI_PHY_342__PHY_NTP_WDQ_STEP_SIZE_1_WIDTH 8U
  1221. #define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_1__REG DENALI_PHY_342
  1222. #define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_1__FLD LPDDR4__DENALI_PHY_342__PHY_NTP_WDQ_STEP_SIZE_1
  1223. #define LPDDR4__DENALI_PHY_343_READ_MASK 0x07FF07FFU
  1224. #define LPDDR4__DENALI_PHY_343_WRITE_MASK 0x07FF07FFU
  1225. #define LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_START_1_MASK 0x000007FFU
  1226. #define LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_START_1_SHIFT 0U
  1227. #define LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_START_1_WIDTH 11U
  1228. #define LPDDR4__PHY_NTP_WDQ_START_1__REG DENALI_PHY_343
  1229. #define LPDDR4__PHY_NTP_WDQ_START_1__FLD LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_START_1
  1230. #define LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_STOP_1_MASK 0x07FF0000U
  1231. #define LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_STOP_1_SHIFT 16U
  1232. #define LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_STOP_1_WIDTH 11U
  1233. #define LPDDR4__PHY_NTP_WDQ_STOP_1__REG DENALI_PHY_343
  1234. #define LPDDR4__PHY_NTP_WDQ_STOP_1__FLD LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_STOP_1
  1235. #define LPDDR4__DENALI_PHY_344_READ_MASK 0x0103FFFFU
  1236. #define LPDDR4__DENALI_PHY_344_WRITE_MASK 0x0103FFFFU
  1237. #define LPDDR4__DENALI_PHY_344__PHY_NTP_WDQ_BIT_EN_1_MASK 0x000000FFU
  1238. #define LPDDR4__DENALI_PHY_344__PHY_NTP_WDQ_BIT_EN_1_SHIFT 0U
  1239. #define LPDDR4__DENALI_PHY_344__PHY_NTP_WDQ_BIT_EN_1_WIDTH 8U
  1240. #define LPDDR4__PHY_NTP_WDQ_BIT_EN_1__REG DENALI_PHY_344
  1241. #define LPDDR4__PHY_NTP_WDQ_BIT_EN_1__FLD LPDDR4__DENALI_PHY_344__PHY_NTP_WDQ_BIT_EN_1
  1242. #define LPDDR4__DENALI_PHY_344__PHY_WDQLVL_DVW_MIN_1_MASK 0x0003FF00U
  1243. #define LPDDR4__DENALI_PHY_344__PHY_WDQLVL_DVW_MIN_1_SHIFT 8U
  1244. #define LPDDR4__DENALI_PHY_344__PHY_WDQLVL_DVW_MIN_1_WIDTH 10U
  1245. #define LPDDR4__PHY_WDQLVL_DVW_MIN_1__REG DENALI_PHY_344
  1246. #define LPDDR4__PHY_WDQLVL_DVW_MIN_1__FLD LPDDR4__DENALI_PHY_344__PHY_WDQLVL_DVW_MIN_1
  1247. #define LPDDR4__DENALI_PHY_344__PHY_SW_WDQLVL_DVW_MIN_EN_1_MASK 0x01000000U
  1248. #define LPDDR4__DENALI_PHY_344__PHY_SW_WDQLVL_DVW_MIN_EN_1_SHIFT 24U
  1249. #define LPDDR4__DENALI_PHY_344__PHY_SW_WDQLVL_DVW_MIN_EN_1_WIDTH 1U
  1250. #define LPDDR4__DENALI_PHY_344__PHY_SW_WDQLVL_DVW_MIN_EN_1_WOCLR 0U
  1251. #define LPDDR4__DENALI_PHY_344__PHY_SW_WDQLVL_DVW_MIN_EN_1_WOSET 0U
  1252. #define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_1__REG DENALI_PHY_344
  1253. #define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_1__FLD LPDDR4__DENALI_PHY_344__PHY_SW_WDQLVL_DVW_MIN_EN_1
  1254. #define LPDDR4__DENALI_PHY_345_READ_MASK 0x1F1F0F3FU
  1255. #define LPDDR4__DENALI_PHY_345_WRITE_MASK 0x1F1F0F3FU
  1256. #define LPDDR4__DENALI_PHY_345__PHY_WDQLVL_PER_START_OFFSET_1_MASK 0x0000003FU
  1257. #define LPDDR4__DENALI_PHY_345__PHY_WDQLVL_PER_START_OFFSET_1_SHIFT 0U
  1258. #define LPDDR4__DENALI_PHY_345__PHY_WDQLVL_PER_START_OFFSET_1_WIDTH 6U
  1259. #define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_1__REG DENALI_PHY_345
  1260. #define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_1__FLD LPDDR4__DENALI_PHY_345__PHY_WDQLVL_PER_START_OFFSET_1
  1261. #define LPDDR4__DENALI_PHY_345__PHY_FAST_LVL_EN_1_MASK 0x00000F00U
  1262. #define LPDDR4__DENALI_PHY_345__PHY_FAST_LVL_EN_1_SHIFT 8U
  1263. #define LPDDR4__DENALI_PHY_345__PHY_FAST_LVL_EN_1_WIDTH 4U
  1264. #define LPDDR4__PHY_FAST_LVL_EN_1__REG DENALI_PHY_345
  1265. #define LPDDR4__PHY_FAST_LVL_EN_1__FLD LPDDR4__DENALI_PHY_345__PHY_FAST_LVL_EN_1
  1266. #define LPDDR4__DENALI_PHY_345__PHY_PAD_TX_DCD_1_MASK 0x001F0000U
  1267. #define LPDDR4__DENALI_PHY_345__PHY_PAD_TX_DCD_1_SHIFT 16U
  1268. #define LPDDR4__DENALI_PHY_345__PHY_PAD_TX_DCD_1_WIDTH 5U
  1269. #define LPDDR4__PHY_PAD_TX_DCD_1__REG DENALI_PHY_345
  1270. #define LPDDR4__PHY_PAD_TX_DCD_1__FLD LPDDR4__DENALI_PHY_345__PHY_PAD_TX_DCD_1
  1271. #define LPDDR4__DENALI_PHY_345__PHY_PAD_RX_DCD_0_1_MASK 0x1F000000U
  1272. #define LPDDR4__DENALI_PHY_345__PHY_PAD_RX_DCD_0_1_SHIFT 24U
  1273. #define LPDDR4__DENALI_PHY_345__PHY_PAD_RX_DCD_0_1_WIDTH 5U
  1274. #define LPDDR4__PHY_PAD_RX_DCD_0_1__REG DENALI_PHY_345
  1275. #define LPDDR4__PHY_PAD_RX_DCD_0_1__FLD LPDDR4__DENALI_PHY_345__PHY_PAD_RX_DCD_0_1
  1276. #define LPDDR4__DENALI_PHY_346_READ_MASK 0x1F1F1F1FU
  1277. #define LPDDR4__DENALI_PHY_346_WRITE_MASK 0x1F1F1F1FU
  1278. #define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_1_1_MASK 0x0000001FU
  1279. #define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_1_1_SHIFT 0U
  1280. #define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_1_1_WIDTH 5U
  1281. #define LPDDR4__PHY_PAD_RX_DCD_1_1__REG DENALI_PHY_346
  1282. #define LPDDR4__PHY_PAD_RX_DCD_1_1__FLD LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_1_1
  1283. #define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_2_1_MASK 0x00001F00U
  1284. #define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_2_1_SHIFT 8U
  1285. #define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_2_1_WIDTH 5U
  1286. #define LPDDR4__PHY_PAD_RX_DCD_2_1__REG DENALI_PHY_346
  1287. #define LPDDR4__PHY_PAD_RX_DCD_2_1__FLD LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_2_1
  1288. #define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_3_1_MASK 0x001F0000U
  1289. #define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_3_1_SHIFT 16U
  1290. #define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_3_1_WIDTH 5U
  1291. #define LPDDR4__PHY_PAD_RX_DCD_3_1__REG DENALI_PHY_346
  1292. #define LPDDR4__PHY_PAD_RX_DCD_3_1__FLD LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_3_1
  1293. #define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_4_1_MASK 0x1F000000U
  1294. #define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_4_1_SHIFT 24U
  1295. #define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_4_1_WIDTH 5U
  1296. #define LPDDR4__PHY_PAD_RX_DCD_4_1__REG DENALI_PHY_346
  1297. #define LPDDR4__PHY_PAD_RX_DCD_4_1__FLD LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_4_1
  1298. #define LPDDR4__DENALI_PHY_347_READ_MASK 0x1F1F1F1FU
  1299. #define LPDDR4__DENALI_PHY_347_WRITE_MASK 0x1F1F1F1FU
  1300. #define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_5_1_MASK 0x0000001FU
  1301. #define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_5_1_SHIFT 0U
  1302. #define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_5_1_WIDTH 5U
  1303. #define LPDDR4__PHY_PAD_RX_DCD_5_1__REG DENALI_PHY_347
  1304. #define LPDDR4__PHY_PAD_RX_DCD_5_1__FLD LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_5_1
  1305. #define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_6_1_MASK 0x00001F00U
  1306. #define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_6_1_SHIFT 8U
  1307. #define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_6_1_WIDTH 5U
  1308. #define LPDDR4__PHY_PAD_RX_DCD_6_1__REG DENALI_PHY_347
  1309. #define LPDDR4__PHY_PAD_RX_DCD_6_1__FLD LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_6_1
  1310. #define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_7_1_MASK 0x001F0000U
  1311. #define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_7_1_SHIFT 16U
  1312. #define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_7_1_WIDTH 5U
  1313. #define LPDDR4__PHY_PAD_RX_DCD_7_1__REG DENALI_PHY_347
  1314. #define LPDDR4__PHY_PAD_RX_DCD_7_1__FLD LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_7_1
  1315. #define LPDDR4__DENALI_PHY_347__PHY_PAD_DM_RX_DCD_1_MASK 0x1F000000U
  1316. #define LPDDR4__DENALI_PHY_347__PHY_PAD_DM_RX_DCD_1_SHIFT 24U
  1317. #define LPDDR4__DENALI_PHY_347__PHY_PAD_DM_RX_DCD_1_WIDTH 5U
  1318. #define LPDDR4__PHY_PAD_DM_RX_DCD_1__REG DENALI_PHY_347
  1319. #define LPDDR4__PHY_PAD_DM_RX_DCD_1__FLD LPDDR4__DENALI_PHY_347__PHY_PAD_DM_RX_DCD_1
  1320. #define LPDDR4__DENALI_PHY_348_READ_MASK 0x003F1F1FU
  1321. #define LPDDR4__DENALI_PHY_348_WRITE_MASK 0x003F1F1FU
  1322. #define LPDDR4__DENALI_PHY_348__PHY_PAD_DQS_RX_DCD_1_MASK 0x0000001FU
  1323. #define LPDDR4__DENALI_PHY_348__PHY_PAD_DQS_RX_DCD_1_SHIFT 0U
  1324. #define LPDDR4__DENALI_PHY_348__PHY_PAD_DQS_RX_DCD_1_WIDTH 5U
  1325. #define LPDDR4__PHY_PAD_DQS_RX_DCD_1__REG DENALI_PHY_348
  1326. #define LPDDR4__PHY_PAD_DQS_RX_DCD_1__FLD LPDDR4__DENALI_PHY_348__PHY_PAD_DQS_RX_DCD_1
  1327. #define LPDDR4__DENALI_PHY_348__PHY_PAD_FDBK_RX_DCD_1_MASK 0x00001F00U
  1328. #define LPDDR4__DENALI_PHY_348__PHY_PAD_FDBK_RX_DCD_1_SHIFT 8U
  1329. #define LPDDR4__DENALI_PHY_348__PHY_PAD_FDBK_RX_DCD_1_WIDTH 5U
  1330. #define LPDDR4__PHY_PAD_FDBK_RX_DCD_1__REG DENALI_PHY_348
  1331. #define LPDDR4__PHY_PAD_FDBK_RX_DCD_1__FLD LPDDR4__DENALI_PHY_348__PHY_PAD_FDBK_RX_DCD_1
  1332. #define LPDDR4__DENALI_PHY_348__PHY_PAD_DSLICE_IO_CFG_1_MASK 0x003F0000U
  1333. #define LPDDR4__DENALI_PHY_348__PHY_PAD_DSLICE_IO_CFG_1_SHIFT 16U
  1334. #define LPDDR4__DENALI_PHY_348__PHY_PAD_DSLICE_IO_CFG_1_WIDTH 6U
  1335. #define LPDDR4__PHY_PAD_DSLICE_IO_CFG_1__REG DENALI_PHY_348
  1336. #define LPDDR4__PHY_PAD_DSLICE_IO_CFG_1__FLD LPDDR4__DENALI_PHY_348__PHY_PAD_DSLICE_IO_CFG_1
  1337. #define LPDDR4__DENALI_PHY_349_READ_MASK 0x03FF03FFU
  1338. #define LPDDR4__DENALI_PHY_349_WRITE_MASK 0x03FF03FFU
  1339. #define LPDDR4__DENALI_PHY_349__PHY_RDDQ0_SLAVE_DELAY_1_MASK 0x000003FFU
  1340. #define LPDDR4__DENALI_PHY_349__PHY_RDDQ0_SLAVE_DELAY_1_SHIFT 0U
  1341. #define LPDDR4__DENALI_PHY_349__PHY_RDDQ0_SLAVE_DELAY_1_WIDTH 10U
  1342. #define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_1__REG DENALI_PHY_349
  1343. #define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_349__PHY_RDDQ0_SLAVE_DELAY_1
  1344. #define LPDDR4__DENALI_PHY_349__PHY_RDDQ1_SLAVE_DELAY_1_MASK 0x03FF0000U
  1345. #define LPDDR4__DENALI_PHY_349__PHY_RDDQ1_SLAVE_DELAY_1_SHIFT 16U
  1346. #define LPDDR4__DENALI_PHY_349__PHY_RDDQ1_SLAVE_DELAY_1_WIDTH 10U
  1347. #define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_1__REG DENALI_PHY_349
  1348. #define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_349__PHY_RDDQ1_SLAVE_DELAY_1
  1349. #define LPDDR4__DENALI_PHY_350_READ_MASK 0x03FF03FFU
  1350. #define LPDDR4__DENALI_PHY_350_WRITE_MASK 0x03FF03FFU
  1351. #define LPDDR4__DENALI_PHY_350__PHY_RDDQ2_SLAVE_DELAY_1_MASK 0x000003FFU
  1352. #define LPDDR4__DENALI_PHY_350__PHY_RDDQ2_SLAVE_DELAY_1_SHIFT 0U
  1353. #define LPDDR4__DENALI_PHY_350__PHY_RDDQ2_SLAVE_DELAY_1_WIDTH 10U
  1354. #define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_1__REG DENALI_PHY_350
  1355. #define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_350__PHY_RDDQ2_SLAVE_DELAY_1
  1356. #define LPDDR4__DENALI_PHY_350__PHY_RDDQ3_SLAVE_DELAY_1_MASK 0x03FF0000U
  1357. #define LPDDR4__DENALI_PHY_350__PHY_RDDQ3_SLAVE_DELAY_1_SHIFT 16U
  1358. #define LPDDR4__DENALI_PHY_350__PHY_RDDQ3_SLAVE_DELAY_1_WIDTH 10U
  1359. #define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_1__REG DENALI_PHY_350
  1360. #define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_350__PHY_RDDQ3_SLAVE_DELAY_1
  1361. #define LPDDR4__DENALI_PHY_351_READ_MASK 0x03FF03FFU
  1362. #define LPDDR4__DENALI_PHY_351_WRITE_MASK 0x03FF03FFU
  1363. #define LPDDR4__DENALI_PHY_351__PHY_RDDQ4_SLAVE_DELAY_1_MASK 0x000003FFU
  1364. #define LPDDR4__DENALI_PHY_351__PHY_RDDQ4_SLAVE_DELAY_1_SHIFT 0U
  1365. #define LPDDR4__DENALI_PHY_351__PHY_RDDQ4_SLAVE_DELAY_1_WIDTH 10U
  1366. #define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_1__REG DENALI_PHY_351
  1367. #define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_351__PHY_RDDQ4_SLAVE_DELAY_1
  1368. #define LPDDR4__DENALI_PHY_351__PHY_RDDQ5_SLAVE_DELAY_1_MASK 0x03FF0000U
  1369. #define LPDDR4__DENALI_PHY_351__PHY_RDDQ5_SLAVE_DELAY_1_SHIFT 16U
  1370. #define LPDDR4__DENALI_PHY_351__PHY_RDDQ5_SLAVE_DELAY_1_WIDTH 10U
  1371. #define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_1__REG DENALI_PHY_351
  1372. #define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_351__PHY_RDDQ5_SLAVE_DELAY_1
  1373. #define LPDDR4__DENALI_PHY_352_READ_MASK 0x03FF03FFU
  1374. #define LPDDR4__DENALI_PHY_352_WRITE_MASK 0x03FF03FFU
  1375. #define LPDDR4__DENALI_PHY_352__PHY_RDDQ6_SLAVE_DELAY_1_MASK 0x000003FFU
  1376. #define LPDDR4__DENALI_PHY_352__PHY_RDDQ6_SLAVE_DELAY_1_SHIFT 0U
  1377. #define LPDDR4__DENALI_PHY_352__PHY_RDDQ6_SLAVE_DELAY_1_WIDTH 10U
  1378. #define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_1__REG DENALI_PHY_352
  1379. #define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_352__PHY_RDDQ6_SLAVE_DELAY_1
  1380. #define LPDDR4__DENALI_PHY_352__PHY_RDDQ7_SLAVE_DELAY_1_MASK 0x03FF0000U
  1381. #define LPDDR4__DENALI_PHY_352__PHY_RDDQ7_SLAVE_DELAY_1_SHIFT 16U
  1382. #define LPDDR4__DENALI_PHY_352__PHY_RDDQ7_SLAVE_DELAY_1_WIDTH 10U
  1383. #define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_1__REG DENALI_PHY_352
  1384. #define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_352__PHY_RDDQ7_SLAVE_DELAY_1
  1385. #define LPDDR4__DENALI_PHY_353_READ_MASK 0x000703FFU
  1386. #define LPDDR4__DENALI_PHY_353_WRITE_MASK 0x000703FFU
  1387. #define LPDDR4__DENALI_PHY_353__PHY_RDDM_SLAVE_DELAY_1_MASK 0x000003FFU
  1388. #define LPDDR4__DENALI_PHY_353__PHY_RDDM_SLAVE_DELAY_1_SHIFT 0U
  1389. #define LPDDR4__DENALI_PHY_353__PHY_RDDM_SLAVE_DELAY_1_WIDTH 10U
  1390. #define LPDDR4__PHY_RDDM_SLAVE_DELAY_1__REG DENALI_PHY_353
  1391. #define LPDDR4__PHY_RDDM_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_353__PHY_RDDM_SLAVE_DELAY_1
  1392. #define LPDDR4__DENALI_PHY_353__PHY_DATA_DC_CAL_CLK_SEL_1_MASK 0x00070000U
  1393. #define LPDDR4__DENALI_PHY_353__PHY_DATA_DC_CAL_CLK_SEL_1_SHIFT 16U
  1394. #define LPDDR4__DENALI_PHY_353__PHY_DATA_DC_CAL_CLK_SEL_1_WIDTH 3U
  1395. #define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_1__REG DENALI_PHY_353
  1396. #define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_1__FLD LPDDR4__DENALI_PHY_353__PHY_DATA_DC_CAL_CLK_SEL_1
  1397. #define LPDDR4__DENALI_PHY_354_READ_MASK 0xFFFFFFFFU
  1398. #define LPDDR4__DENALI_PHY_354_WRITE_MASK 0xFFFFFFFFU
  1399. #define LPDDR4__DENALI_PHY_354__PHY_DQ_OE_TIMING_1_MASK 0x000000FFU
  1400. #define LPDDR4__DENALI_PHY_354__PHY_DQ_OE_TIMING_1_SHIFT 0U
  1401. #define LPDDR4__DENALI_PHY_354__PHY_DQ_OE_TIMING_1_WIDTH 8U
  1402. #define LPDDR4__PHY_DQ_OE_TIMING_1__REG DENALI_PHY_354
  1403. #define LPDDR4__PHY_DQ_OE_TIMING_1__FLD LPDDR4__DENALI_PHY_354__PHY_DQ_OE_TIMING_1
  1404. #define LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_RD_TIMING_1_MASK 0x0000FF00U
  1405. #define LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_RD_TIMING_1_SHIFT 8U
  1406. #define LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_RD_TIMING_1_WIDTH 8U
  1407. #define LPDDR4__PHY_DQ_TSEL_RD_TIMING_1__REG DENALI_PHY_354
  1408. #define LPDDR4__PHY_DQ_TSEL_RD_TIMING_1__FLD LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_RD_TIMING_1
  1409. #define LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_WR_TIMING_1_MASK 0x00FF0000U
  1410. #define LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_WR_TIMING_1_SHIFT 16U
  1411. #define LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_WR_TIMING_1_WIDTH 8U
  1412. #define LPDDR4__PHY_DQ_TSEL_WR_TIMING_1__REG DENALI_PHY_354
  1413. #define LPDDR4__PHY_DQ_TSEL_WR_TIMING_1__FLD LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_WR_TIMING_1
  1414. #define LPDDR4__DENALI_PHY_354__PHY_DQS_OE_TIMING_1_MASK 0xFF000000U
  1415. #define LPDDR4__DENALI_PHY_354__PHY_DQS_OE_TIMING_1_SHIFT 24U
  1416. #define LPDDR4__DENALI_PHY_354__PHY_DQS_OE_TIMING_1_WIDTH 8U
  1417. #define LPDDR4__PHY_DQS_OE_TIMING_1__REG DENALI_PHY_354
  1418. #define LPDDR4__PHY_DQS_OE_TIMING_1__FLD LPDDR4__DENALI_PHY_354__PHY_DQS_OE_TIMING_1
  1419. #define LPDDR4__DENALI_PHY_355_READ_MASK 0xFFFFFF0FU
  1420. #define LPDDR4__DENALI_PHY_355_WRITE_MASK 0xFFFFFF0FU
  1421. #define LPDDR4__DENALI_PHY_355__PHY_IO_PAD_DELAY_TIMING_1_MASK 0x0000000FU
  1422. #define LPDDR4__DENALI_PHY_355__PHY_IO_PAD_DELAY_TIMING_1_SHIFT 0U
  1423. #define LPDDR4__DENALI_PHY_355__PHY_IO_PAD_DELAY_TIMING_1_WIDTH 4U
  1424. #define LPDDR4__PHY_IO_PAD_DELAY_TIMING_1__REG DENALI_PHY_355
  1425. #define LPDDR4__PHY_IO_PAD_DELAY_TIMING_1__FLD LPDDR4__DENALI_PHY_355__PHY_IO_PAD_DELAY_TIMING_1
  1426. #define LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_RD_TIMING_1_MASK 0x0000FF00U
  1427. #define LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_RD_TIMING_1_SHIFT 8U
  1428. #define LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_RD_TIMING_1_WIDTH 8U
  1429. #define LPDDR4__PHY_DQS_TSEL_RD_TIMING_1__REG DENALI_PHY_355
  1430. #define LPDDR4__PHY_DQS_TSEL_RD_TIMING_1__FLD LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_RD_TIMING_1
  1431. #define LPDDR4__DENALI_PHY_355__PHY_DQS_OE_RD_TIMING_1_MASK 0x00FF0000U
  1432. #define LPDDR4__DENALI_PHY_355__PHY_DQS_OE_RD_TIMING_1_SHIFT 16U
  1433. #define LPDDR4__DENALI_PHY_355__PHY_DQS_OE_RD_TIMING_1_WIDTH 8U
  1434. #define LPDDR4__PHY_DQS_OE_RD_TIMING_1__REG DENALI_PHY_355
  1435. #define LPDDR4__PHY_DQS_OE_RD_TIMING_1__FLD LPDDR4__DENALI_PHY_355__PHY_DQS_OE_RD_TIMING_1
  1436. #define LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_WR_TIMING_1_MASK 0xFF000000U
  1437. #define LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_WR_TIMING_1_SHIFT 24U
  1438. #define LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_WR_TIMING_1_WIDTH 8U
  1439. #define LPDDR4__PHY_DQS_TSEL_WR_TIMING_1__REG DENALI_PHY_355
  1440. #define LPDDR4__PHY_DQS_TSEL_WR_TIMING_1__FLD LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_WR_TIMING_1
  1441. #define LPDDR4__DENALI_PHY_356_READ_MASK 0x0FFFFFFFU
  1442. #define LPDDR4__DENALI_PHY_356_WRITE_MASK 0x0FFFFFFFU
  1443. #define LPDDR4__DENALI_PHY_356__PHY_VREF_SETTING_TIME_1_MASK 0x0000FFFFU
  1444. #define LPDDR4__DENALI_PHY_356__PHY_VREF_SETTING_TIME_1_SHIFT 0U
  1445. #define LPDDR4__DENALI_PHY_356__PHY_VREF_SETTING_TIME_1_WIDTH 16U
  1446. #define LPDDR4__PHY_VREF_SETTING_TIME_1__REG DENALI_PHY_356
  1447. #define LPDDR4__PHY_VREF_SETTING_TIME_1__FLD LPDDR4__DENALI_PHY_356__PHY_VREF_SETTING_TIME_1
  1448. #define LPDDR4__DENALI_PHY_356__PHY_PAD_VREF_CTRL_DQ_1_MASK 0x0FFF0000U
  1449. #define LPDDR4__DENALI_PHY_356__PHY_PAD_VREF_CTRL_DQ_1_SHIFT 16U
  1450. #define LPDDR4__DENALI_PHY_356__PHY_PAD_VREF_CTRL_DQ_1_WIDTH 12U
  1451. #define LPDDR4__PHY_PAD_VREF_CTRL_DQ_1__REG DENALI_PHY_356
  1452. #define LPDDR4__PHY_PAD_VREF_CTRL_DQ_1__FLD LPDDR4__DENALI_PHY_356__PHY_PAD_VREF_CTRL_DQ_1
  1453. #define LPDDR4__DENALI_PHY_357_READ_MASK 0x03FFFF01U
  1454. #define LPDDR4__DENALI_PHY_357_WRITE_MASK 0x03FFFF01U
  1455. #define LPDDR4__DENALI_PHY_357__PHY_PER_CS_TRAINING_EN_1_MASK 0x00000001U
  1456. #define LPDDR4__DENALI_PHY_357__PHY_PER_CS_TRAINING_EN_1_SHIFT 0U
  1457. #define LPDDR4__DENALI_PHY_357__PHY_PER_CS_TRAINING_EN_1_WIDTH 1U
  1458. #define LPDDR4__DENALI_PHY_357__PHY_PER_CS_TRAINING_EN_1_WOCLR 0U
  1459. #define LPDDR4__DENALI_PHY_357__PHY_PER_CS_TRAINING_EN_1_WOSET 0U
  1460. #define LPDDR4__PHY_PER_CS_TRAINING_EN_1__REG DENALI_PHY_357
  1461. #define LPDDR4__PHY_PER_CS_TRAINING_EN_1__FLD LPDDR4__DENALI_PHY_357__PHY_PER_CS_TRAINING_EN_1
  1462. #define LPDDR4__DENALI_PHY_357__PHY_DQ_IE_TIMING_1_MASK 0x0000FF00U
  1463. #define LPDDR4__DENALI_PHY_357__PHY_DQ_IE_TIMING_1_SHIFT 8U
  1464. #define LPDDR4__DENALI_PHY_357__PHY_DQ_IE_TIMING_1_WIDTH 8U
  1465. #define LPDDR4__PHY_DQ_IE_TIMING_1__REG DENALI_PHY_357
  1466. #define LPDDR4__PHY_DQ_IE_TIMING_1__FLD LPDDR4__DENALI_PHY_357__PHY_DQ_IE_TIMING_1
  1467. #define LPDDR4__DENALI_PHY_357__PHY_DQS_IE_TIMING_1_MASK 0x00FF0000U
  1468. #define LPDDR4__DENALI_PHY_357__PHY_DQS_IE_TIMING_1_SHIFT 16U
  1469. #define LPDDR4__DENALI_PHY_357__PHY_DQS_IE_TIMING_1_WIDTH 8U
  1470. #define LPDDR4__PHY_DQS_IE_TIMING_1__REG DENALI_PHY_357
  1471. #define LPDDR4__PHY_DQS_IE_TIMING_1__FLD LPDDR4__DENALI_PHY_357__PHY_DQS_IE_TIMING_1
  1472. #define LPDDR4__DENALI_PHY_357__PHY_RDDATA_EN_IE_DLY_1_MASK 0x03000000U
  1473. #define LPDDR4__DENALI_PHY_357__PHY_RDDATA_EN_IE_DLY_1_SHIFT 24U
  1474. #define LPDDR4__DENALI_PHY_357__PHY_RDDATA_EN_IE_DLY_1_WIDTH 2U
  1475. #define LPDDR4__PHY_RDDATA_EN_IE_DLY_1__REG DENALI_PHY_357
  1476. #define LPDDR4__PHY_RDDATA_EN_IE_DLY_1__FLD LPDDR4__DENALI_PHY_357__PHY_RDDATA_EN_IE_DLY_1
  1477. #define LPDDR4__DENALI_PHY_358_READ_MASK 0x1F1F0103U
  1478. #define LPDDR4__DENALI_PHY_358_WRITE_MASK 0x1F1F0103U
  1479. #define LPDDR4__DENALI_PHY_358__PHY_IE_MODE_1_MASK 0x00000003U
  1480. #define LPDDR4__DENALI_PHY_358__PHY_IE_MODE_1_SHIFT 0U
  1481. #define LPDDR4__DENALI_PHY_358__PHY_IE_MODE_1_WIDTH 2U
  1482. #define LPDDR4__PHY_IE_MODE_1__REG DENALI_PHY_358
  1483. #define LPDDR4__PHY_IE_MODE_1__FLD LPDDR4__DENALI_PHY_358__PHY_IE_MODE_1
  1484. #define LPDDR4__DENALI_PHY_358__PHY_DBI_MODE_1_MASK 0x00000100U
  1485. #define LPDDR4__DENALI_PHY_358__PHY_DBI_MODE_1_SHIFT 8U
  1486. #define LPDDR4__DENALI_PHY_358__PHY_DBI_MODE_1_WIDTH 1U
  1487. #define LPDDR4__DENALI_PHY_358__PHY_DBI_MODE_1_WOCLR 0U
  1488. #define LPDDR4__DENALI_PHY_358__PHY_DBI_MODE_1_WOSET 0U
  1489. #define LPDDR4__PHY_DBI_MODE_1__REG DENALI_PHY_358
  1490. #define LPDDR4__PHY_DBI_MODE_1__FLD LPDDR4__DENALI_PHY_358__PHY_DBI_MODE_1
  1491. #define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_TSEL_DLY_1_MASK 0x001F0000U
  1492. #define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_TSEL_DLY_1_SHIFT 16U
  1493. #define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_TSEL_DLY_1_WIDTH 5U
  1494. #define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_1__REG DENALI_PHY_358
  1495. #define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_1__FLD LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_TSEL_DLY_1
  1496. #define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_OE_DLY_1_MASK 0x1F000000U
  1497. #define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_OE_DLY_1_SHIFT 24U
  1498. #define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_OE_DLY_1_WIDTH 5U
  1499. #define LPDDR4__PHY_RDDATA_EN_OE_DLY_1__REG DENALI_PHY_358
  1500. #define LPDDR4__PHY_RDDATA_EN_OE_DLY_1__FLD LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_OE_DLY_1
  1501. #define LPDDR4__DENALI_PHY_359_READ_MASK 0x3F07FF0FU
  1502. #define LPDDR4__DENALI_PHY_359_WRITE_MASK 0x3F07FF0FU
  1503. #define LPDDR4__DENALI_PHY_359__PHY_SW_MASTER_MODE_1_MASK 0x0000000FU
  1504. #define LPDDR4__DENALI_PHY_359__PHY_SW_MASTER_MODE_1_SHIFT 0U
  1505. #define LPDDR4__DENALI_PHY_359__PHY_SW_MASTER_MODE_1_WIDTH 4U
  1506. #define LPDDR4__PHY_SW_MASTER_MODE_1__REG DENALI_PHY_359
  1507. #define LPDDR4__PHY_SW_MASTER_MODE_1__FLD LPDDR4__DENALI_PHY_359__PHY_SW_MASTER_MODE_1
  1508. #define LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_START_1_MASK 0x0007FF00U
  1509. #define LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_START_1_SHIFT 8U
  1510. #define LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_START_1_WIDTH 11U
  1511. #define LPDDR4__PHY_MASTER_DELAY_START_1__REG DENALI_PHY_359
  1512. #define LPDDR4__PHY_MASTER_DELAY_START_1__FLD LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_START_1
  1513. #define LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_STEP_1_MASK 0x3F000000U
  1514. #define LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_STEP_1_SHIFT 24U
  1515. #define LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_STEP_1_WIDTH 6U
  1516. #define LPDDR4__PHY_MASTER_DELAY_STEP_1__REG DENALI_PHY_359
  1517. #define LPDDR4__PHY_MASTER_DELAY_STEP_1__FLD LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_STEP_1
  1518. #define LPDDR4__DENALI_PHY_360_READ_MASK 0xFF0FFFFFU
  1519. #define LPDDR4__DENALI_PHY_360_WRITE_MASK 0xFF0FFFFFU
  1520. #define LPDDR4__DENALI_PHY_360__PHY_MASTER_DELAY_WAIT_1_MASK 0x000000FFU
  1521. #define LPDDR4__DENALI_PHY_360__PHY_MASTER_DELAY_WAIT_1_SHIFT 0U
  1522. #define LPDDR4__DENALI_PHY_360__PHY_MASTER_DELAY_WAIT_1_WIDTH 8U
  1523. #define LPDDR4__PHY_MASTER_DELAY_WAIT_1__REG DENALI_PHY_360
  1524. #define LPDDR4__PHY_MASTER_DELAY_WAIT_1__FLD LPDDR4__DENALI_PHY_360__PHY_MASTER_DELAY_WAIT_1
  1525. #define LPDDR4__DENALI_PHY_360__PHY_MASTER_DELAY_HALF_MEASURE_1_MASK 0x0000FF00U
  1526. #define LPDDR4__DENALI_PHY_360__PHY_MASTER_DELAY_HALF_MEASURE_1_SHIFT 8U
  1527. #define LPDDR4__DENALI_PHY_360__PHY_MASTER_DELAY_HALF_MEASURE_1_WIDTH 8U
  1528. #define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_1__REG DENALI_PHY_360
  1529. #define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_1__FLD LPDDR4__DENALI_PHY_360__PHY_MASTER_DELAY_HALF_MEASURE_1
  1530. #define LPDDR4__DENALI_PHY_360__PHY_RPTR_UPDATE_1_MASK 0x000F0000U
  1531. #define LPDDR4__DENALI_PHY_360__PHY_RPTR_UPDATE_1_SHIFT 16U
  1532. #define LPDDR4__DENALI_PHY_360__PHY_RPTR_UPDATE_1_WIDTH 4U
  1533. #define LPDDR4__PHY_RPTR_UPDATE_1__REG DENALI_PHY_360
  1534. #define LPDDR4__PHY_RPTR_UPDATE_1__FLD LPDDR4__DENALI_PHY_360__PHY_RPTR_UPDATE_1
  1535. #define LPDDR4__DENALI_PHY_360__PHY_WRLVL_DLY_STEP_1_MASK 0xFF000000U
  1536. #define LPDDR4__DENALI_PHY_360__PHY_WRLVL_DLY_STEP_1_SHIFT 24U
  1537. #define LPDDR4__DENALI_PHY_360__PHY_WRLVL_DLY_STEP_1_WIDTH 8U
  1538. #define LPDDR4__PHY_WRLVL_DLY_STEP_1__REG DENALI_PHY_360
  1539. #define LPDDR4__PHY_WRLVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_360__PHY_WRLVL_DLY_STEP_1
  1540. #define LPDDR4__DENALI_PHY_361_READ_MASK 0x1F0F3F0FU
  1541. #define LPDDR4__DENALI_PHY_361_WRITE_MASK 0x1F0F3F0FU
  1542. #define LPDDR4__DENALI_PHY_361__PHY_WRLVL_DLY_FINE_STEP_1_MASK 0x0000000FU
  1543. #define LPDDR4__DENALI_PHY_361__PHY_WRLVL_DLY_FINE_STEP_1_SHIFT 0U
  1544. #define LPDDR4__DENALI_PHY_361__PHY_WRLVL_DLY_FINE_STEP_1_WIDTH 4U
  1545. #define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_1__REG DENALI_PHY_361
  1546. #define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_1__FLD LPDDR4__DENALI_PHY_361__PHY_WRLVL_DLY_FINE_STEP_1
  1547. #define LPDDR4__DENALI_PHY_361__PHY_WRLVL_RESP_WAIT_CNT_1_MASK 0x00003F00U
  1548. #define LPDDR4__DENALI_PHY_361__PHY_WRLVL_RESP_WAIT_CNT_1_SHIFT 8U
  1549. #define LPDDR4__DENALI_PHY_361__PHY_WRLVL_RESP_WAIT_CNT_1_WIDTH 6U
  1550. #define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_1__REG DENALI_PHY_361
  1551. #define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_361__PHY_WRLVL_RESP_WAIT_CNT_1
  1552. #define LPDDR4__DENALI_PHY_361__PHY_GTLVL_DLY_STEP_1_MASK 0x000F0000U
  1553. #define LPDDR4__DENALI_PHY_361__PHY_GTLVL_DLY_STEP_1_SHIFT 16U
  1554. #define LPDDR4__DENALI_PHY_361__PHY_GTLVL_DLY_STEP_1_WIDTH 4U
  1555. #define LPDDR4__PHY_GTLVL_DLY_STEP_1__REG DENALI_PHY_361
  1556. #define LPDDR4__PHY_GTLVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_361__PHY_GTLVL_DLY_STEP_1
  1557. #define LPDDR4__DENALI_PHY_361__PHY_GTLVL_RESP_WAIT_CNT_1_MASK 0x1F000000U
  1558. #define LPDDR4__DENALI_PHY_361__PHY_GTLVL_RESP_WAIT_CNT_1_SHIFT 24U
  1559. #define LPDDR4__DENALI_PHY_361__PHY_GTLVL_RESP_WAIT_CNT_1_WIDTH 5U
  1560. #define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_1__REG DENALI_PHY_361
  1561. #define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_361__PHY_GTLVL_RESP_WAIT_CNT_1
  1562. #define LPDDR4__DENALI_PHY_362_READ_MASK 0x03FF03FFU
  1563. #define LPDDR4__DENALI_PHY_362_WRITE_MASK 0x03FF03FFU
  1564. #define LPDDR4__DENALI_PHY_362__PHY_GTLVL_BACK_STEP_1_MASK 0x000003FFU
  1565. #define LPDDR4__DENALI_PHY_362__PHY_GTLVL_BACK_STEP_1_SHIFT 0U
  1566. #define LPDDR4__DENALI_PHY_362__PHY_GTLVL_BACK_STEP_1_WIDTH 10U
  1567. #define LPDDR4__PHY_GTLVL_BACK_STEP_1__REG DENALI_PHY_362
  1568. #define LPDDR4__PHY_GTLVL_BACK_STEP_1__FLD LPDDR4__DENALI_PHY_362__PHY_GTLVL_BACK_STEP_1
  1569. #define LPDDR4__DENALI_PHY_362__PHY_GTLVL_FINAL_STEP_1_MASK 0x03FF0000U
  1570. #define LPDDR4__DENALI_PHY_362__PHY_GTLVL_FINAL_STEP_1_SHIFT 16U
  1571. #define LPDDR4__DENALI_PHY_362__PHY_GTLVL_FINAL_STEP_1_WIDTH 10U
  1572. #define LPDDR4__PHY_GTLVL_FINAL_STEP_1__REG DENALI_PHY_362
  1573. #define LPDDR4__PHY_GTLVL_FINAL_STEP_1__FLD LPDDR4__DENALI_PHY_362__PHY_GTLVL_FINAL_STEP_1
  1574. #define LPDDR4__DENALI_PHY_363_READ_MASK 0x0F010FFFU
  1575. #define LPDDR4__DENALI_PHY_363_WRITE_MASK 0x0F010FFFU
  1576. #define LPDDR4__DENALI_PHY_363__PHY_WDQLVL_DLY_STEP_1_MASK 0x000000FFU
  1577. #define LPDDR4__DENALI_PHY_363__PHY_WDQLVL_DLY_STEP_1_SHIFT 0U
  1578. #define LPDDR4__DENALI_PHY_363__PHY_WDQLVL_DLY_STEP_1_WIDTH 8U
  1579. #define LPDDR4__PHY_WDQLVL_DLY_STEP_1__REG DENALI_PHY_363
  1580. #define LPDDR4__PHY_WDQLVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_363__PHY_WDQLVL_DLY_STEP_1
  1581. #define LPDDR4__DENALI_PHY_363__PHY_WDQLVL_QTR_DLY_STEP_1_MASK 0x00000F00U
  1582. #define LPDDR4__DENALI_PHY_363__PHY_WDQLVL_QTR_DLY_STEP_1_SHIFT 8U
  1583. #define LPDDR4__DENALI_PHY_363__PHY_WDQLVL_QTR_DLY_STEP_1_WIDTH 4U
  1584. #define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_1__REG DENALI_PHY_363
  1585. #define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_363__PHY_WDQLVL_QTR_DLY_STEP_1
  1586. #define LPDDR4__DENALI_PHY_363__PHY_TOGGLE_PRE_SUPPORT_1_MASK 0x00010000U
  1587. #define LPDDR4__DENALI_PHY_363__PHY_TOGGLE_PRE_SUPPORT_1_SHIFT 16U
  1588. #define LPDDR4__DENALI_PHY_363__PHY_TOGGLE_PRE_SUPPORT_1_WIDTH 1U
  1589. #define LPDDR4__DENALI_PHY_363__PHY_TOGGLE_PRE_SUPPORT_1_WOCLR 0U
  1590. #define LPDDR4__DENALI_PHY_363__PHY_TOGGLE_PRE_SUPPORT_1_WOSET 0U
  1591. #define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_1__REG DENALI_PHY_363
  1592. #define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_1__FLD LPDDR4__DENALI_PHY_363__PHY_TOGGLE_PRE_SUPPORT_1
  1593. #define LPDDR4__DENALI_PHY_363__PHY_RDLVL_DLY_STEP_1_MASK 0x0F000000U
  1594. #define LPDDR4__DENALI_PHY_363__PHY_RDLVL_DLY_STEP_1_SHIFT 24U
  1595. #define LPDDR4__DENALI_PHY_363__PHY_RDLVL_DLY_STEP_1_WIDTH 4U
  1596. #define LPDDR4__PHY_RDLVL_DLY_STEP_1__REG DENALI_PHY_363
  1597. #define LPDDR4__PHY_RDLVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_363__PHY_RDLVL_DLY_STEP_1
  1598. #define LPDDR4__DENALI_PHY_364_READ_MASK 0x000003FFU
  1599. #define LPDDR4__DENALI_PHY_364_WRITE_MASK 0x000003FFU
  1600. #define LPDDR4__DENALI_PHY_364__PHY_RDLVL_MAX_EDGE_1_MASK 0x000003FFU
  1601. #define LPDDR4__DENALI_PHY_364__PHY_RDLVL_MAX_EDGE_1_SHIFT 0U
  1602. #define LPDDR4__DENALI_PHY_364__PHY_RDLVL_MAX_EDGE_1_WIDTH 10U
  1603. #define LPDDR4__PHY_RDLVL_MAX_EDGE_1__REG DENALI_PHY_364
  1604. #define LPDDR4__PHY_RDLVL_MAX_EDGE_1__FLD LPDDR4__DENALI_PHY_364__PHY_RDLVL_MAX_EDGE_1
  1605. #define LPDDR4__DENALI_PHY_365_READ_MASK 0x3F0103FFU
  1606. #define LPDDR4__DENALI_PHY_365_WRITE_MASK 0x3F0103FFU
  1607. #define LPDDR4__DENALI_PHY_365__PHY_RDLVL_DVW_MIN_1_MASK 0x000003FFU
  1608. #define LPDDR4__DENALI_PHY_365__PHY_RDLVL_DVW_MIN_1_SHIFT 0U
  1609. #define LPDDR4__DENALI_PHY_365__PHY_RDLVL_DVW_MIN_1_WIDTH 10U
  1610. #define LPDDR4__PHY_RDLVL_DVW_MIN_1__REG DENALI_PHY_365
  1611. #define LPDDR4__PHY_RDLVL_DVW_MIN_1__FLD LPDDR4__DENALI_PHY_365__PHY_RDLVL_DVW_MIN_1
  1612. #define LPDDR4__DENALI_PHY_365__PHY_SW_RDLVL_DVW_MIN_EN_1_MASK 0x00010000U
  1613. #define LPDDR4__DENALI_PHY_365__PHY_SW_RDLVL_DVW_MIN_EN_1_SHIFT 16U
  1614. #define LPDDR4__DENALI_PHY_365__PHY_SW_RDLVL_DVW_MIN_EN_1_WIDTH 1U
  1615. #define LPDDR4__DENALI_PHY_365__PHY_SW_RDLVL_DVW_MIN_EN_1_WOCLR 0U
  1616. #define LPDDR4__DENALI_PHY_365__PHY_SW_RDLVL_DVW_MIN_EN_1_WOSET 0U
  1617. #define LPDDR4__PHY_SW_RDLVL_DVW_MIN_EN_1__REG DENALI_PHY_365
  1618. #define LPDDR4__PHY_SW_RDLVL_DVW_MIN_EN_1__FLD LPDDR4__DENALI_PHY_365__PHY_SW_RDLVL_DVW_MIN_EN_1
  1619. #define LPDDR4__DENALI_PHY_365__PHY_RDLVL_PER_START_OFFSET_1_MASK 0x3F000000U
  1620. #define LPDDR4__DENALI_PHY_365__PHY_RDLVL_PER_START_OFFSET_1_SHIFT 24U
  1621. #define LPDDR4__DENALI_PHY_365__PHY_RDLVL_PER_START_OFFSET_1_WIDTH 6U
  1622. #define LPDDR4__PHY_RDLVL_PER_START_OFFSET_1__REG DENALI_PHY_365
  1623. #define LPDDR4__PHY_RDLVL_PER_START_OFFSET_1__FLD LPDDR4__DENALI_PHY_365__PHY_RDLVL_PER_START_OFFSET_1
  1624. #define LPDDR4__DENALI_PHY_366_READ_MASK 0x00030703U
  1625. #define LPDDR4__DENALI_PHY_366_WRITE_MASK 0x00030703U
  1626. #define LPDDR4__DENALI_PHY_366__PHY_WRPATH_GATE_DISABLE_1_MASK 0x00000003U
  1627. #define LPDDR4__DENALI_PHY_366__PHY_WRPATH_GATE_DISABLE_1_SHIFT 0U
  1628. #define LPDDR4__DENALI_PHY_366__PHY_WRPATH_GATE_DISABLE_1_WIDTH 2U
  1629. #define LPDDR4__PHY_WRPATH_GATE_DISABLE_1__REG DENALI_PHY_366
  1630. #define LPDDR4__PHY_WRPATH_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_366__PHY_WRPATH_GATE_DISABLE_1
  1631. #define LPDDR4__DENALI_PHY_366__PHY_WRPATH_GATE_TIMING_1_MASK 0x00000700U
  1632. #define LPDDR4__DENALI_PHY_366__PHY_WRPATH_GATE_TIMING_1_SHIFT 8U
  1633. #define LPDDR4__DENALI_PHY_366__PHY_WRPATH_GATE_TIMING_1_WIDTH 3U
  1634. #define LPDDR4__PHY_WRPATH_GATE_TIMING_1__REG DENALI_PHY_366
  1635. #define LPDDR4__PHY_WRPATH_GATE_TIMING_1__FLD LPDDR4__DENALI_PHY_366__PHY_WRPATH_GATE_TIMING_1
  1636. #define LPDDR4__DENALI_PHY_366__PHY_DATA_DC_INIT_DISABLE_1_MASK 0x00030000U
  1637. #define LPDDR4__DENALI_PHY_366__PHY_DATA_DC_INIT_DISABLE_1_SHIFT 16U
  1638. #define LPDDR4__DENALI_PHY_366__PHY_DATA_DC_INIT_DISABLE_1_WIDTH 2U
  1639. #define LPDDR4__PHY_DATA_DC_INIT_DISABLE_1__REG DENALI_PHY_366
  1640. #define LPDDR4__PHY_DATA_DC_INIT_DISABLE_1__FLD LPDDR4__DENALI_PHY_366__PHY_DATA_DC_INIT_DISABLE_1
  1641. #define LPDDR4__DENALI_PHY_367_READ_MASK 0x07FF03FFU
  1642. #define LPDDR4__DENALI_PHY_367_WRITE_MASK 0x07FF03FFU
  1643. #define LPDDR4__DENALI_PHY_367__PHY_DATA_DC_DQS_INIT_SLV_DELAY_1_MASK 0x000003FFU
  1644. #define LPDDR4__DENALI_PHY_367__PHY_DATA_DC_DQS_INIT_SLV_DELAY_1_SHIFT 0U
  1645. #define LPDDR4__DENALI_PHY_367__PHY_DATA_DC_DQS_INIT_SLV_DELAY_1_WIDTH 10U
  1646. #define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_1__REG DENALI_PHY_367
  1647. #define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_1__FLD LPDDR4__DENALI_PHY_367__PHY_DATA_DC_DQS_INIT_SLV_DELAY_1
  1648. #define LPDDR4__DENALI_PHY_367__PHY_DATA_DC_DQ_INIT_SLV_DELAY_1_MASK 0x07FF0000U
  1649. #define LPDDR4__DENALI_PHY_367__PHY_DATA_DC_DQ_INIT_SLV_DELAY_1_SHIFT 16U
  1650. #define LPDDR4__DENALI_PHY_367__PHY_DATA_DC_DQ_INIT_SLV_DELAY_1_WIDTH 11U
  1651. #define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_1__REG DENALI_PHY_367
  1652. #define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_1__FLD LPDDR4__DENALI_PHY_367__PHY_DATA_DC_DQ_INIT_SLV_DELAY_1
  1653. #define LPDDR4__DENALI_PHY_368_READ_MASK 0xFFFF0101U
  1654. #define LPDDR4__DENALI_PHY_368_WRITE_MASK 0xFFFF0101U
  1655. #define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WRLVL_ENABLE_1_MASK 0x00000001U
  1656. #define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WRLVL_ENABLE_1_SHIFT 0U
  1657. #define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WRLVL_ENABLE_1_WIDTH 1U
  1658. #define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WRLVL_ENABLE_1_WOCLR 0U
  1659. #define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WRLVL_ENABLE_1_WOSET 0U
  1660. #define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_1__REG DENALI_PHY_368
  1661. #define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_1__FLD LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WRLVL_ENABLE_1
  1662. #define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WDQLVL_ENABLE_1_MASK 0x00000100U
  1663. #define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WDQLVL_ENABLE_1_SHIFT 8U
  1664. #define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WDQLVL_ENABLE_1_WIDTH 1U
  1665. #define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WDQLVL_ENABLE_1_WOCLR 0U
  1666. #define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WDQLVL_ENABLE_1_WOSET 0U
  1667. #define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_1__REG DENALI_PHY_368
  1668. #define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_1__FLD LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WDQLVL_ENABLE_1
  1669. #define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_DM_CLK_SE_THRSHLD_1_MASK 0x00FF0000U
  1670. #define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_DM_CLK_SE_THRSHLD_1_SHIFT 16U
  1671. #define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_DM_CLK_SE_THRSHLD_1_WIDTH 8U
  1672. #define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_1__REG DENALI_PHY_368
  1673. #define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_1__FLD LPDDR4__DENALI_PHY_368__PHY_DATA_DC_DM_CLK_SE_THRSHLD_1
  1674. #define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1_MASK 0xFF000000U
  1675. #define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1_SHIFT 24U
  1676. #define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1_WIDTH 8U
  1677. #define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1__REG DENALI_PHY_368
  1678. #define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1__FLD LPDDR4__DENALI_PHY_368__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1
  1679. #define LPDDR4__DENALI_PHY_369_READ_MASK 0x001F3F7FU
  1680. #define LPDDR4__DENALI_PHY_369_WRITE_MASK 0x001F3F7FU
  1681. #define LPDDR4__DENALI_PHY_369__PHY_WDQ_OSC_DELTA_1_MASK 0x0000007FU
  1682. #define LPDDR4__DENALI_PHY_369__PHY_WDQ_OSC_DELTA_1_SHIFT 0U
  1683. #define LPDDR4__DENALI_PHY_369__PHY_WDQ_OSC_DELTA_1_WIDTH 7U
  1684. #define LPDDR4__PHY_WDQ_OSC_DELTA_1__REG DENALI_PHY_369
  1685. #define LPDDR4__PHY_WDQ_OSC_DELTA_1__FLD LPDDR4__DENALI_PHY_369__PHY_WDQ_OSC_DELTA_1
  1686. #define LPDDR4__DENALI_PHY_369__PHY_MEAS_DLY_STEP_ENABLE_1_MASK 0x00003F00U
  1687. #define LPDDR4__DENALI_PHY_369__PHY_MEAS_DLY_STEP_ENABLE_1_SHIFT 8U
  1688. #define LPDDR4__DENALI_PHY_369__PHY_MEAS_DLY_STEP_ENABLE_1_WIDTH 6U
  1689. #define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_1__REG DENALI_PHY_369
  1690. #define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_1__FLD LPDDR4__DENALI_PHY_369__PHY_MEAS_DLY_STEP_ENABLE_1
  1691. #define LPDDR4__DENALI_PHY_369__PHY_RDDATA_EN_DLY_1_MASK 0x001F0000U
  1692. #define LPDDR4__DENALI_PHY_369__PHY_RDDATA_EN_DLY_1_SHIFT 16U
  1693. #define LPDDR4__DENALI_PHY_369__PHY_RDDATA_EN_DLY_1_WIDTH 5U
  1694. #define LPDDR4__PHY_RDDATA_EN_DLY_1__REG DENALI_PHY_369
  1695. #define LPDDR4__PHY_RDDATA_EN_DLY_1__FLD LPDDR4__DENALI_PHY_369__PHY_RDDATA_EN_DLY_1
  1696. #define LPDDR4__DENALI_PHY_370_READ_MASK 0xFFFFFFFFU
  1697. #define LPDDR4__DENALI_PHY_370_WRITE_MASK 0xFFFFFFFFU
  1698. #define LPDDR4__DENALI_PHY_370__PHY_DQ_DM_SWIZZLE0_1_MASK 0xFFFFFFFFU
  1699. #define LPDDR4__DENALI_PHY_370__PHY_DQ_DM_SWIZZLE0_1_SHIFT 0U
  1700. #define LPDDR4__DENALI_PHY_370__PHY_DQ_DM_SWIZZLE0_1_WIDTH 32U
  1701. #define LPDDR4__PHY_DQ_DM_SWIZZLE0_1__REG DENALI_PHY_370
  1702. #define LPDDR4__PHY_DQ_DM_SWIZZLE0_1__FLD LPDDR4__DENALI_PHY_370__PHY_DQ_DM_SWIZZLE0_1
  1703. #define LPDDR4__DENALI_PHY_371_READ_MASK 0x0000000FU
  1704. #define LPDDR4__DENALI_PHY_371_WRITE_MASK 0x0000000FU
  1705. #define LPDDR4__DENALI_PHY_371__PHY_DQ_DM_SWIZZLE1_1_MASK 0x0000000FU
  1706. #define LPDDR4__DENALI_PHY_371__PHY_DQ_DM_SWIZZLE1_1_SHIFT 0U
  1707. #define LPDDR4__DENALI_PHY_371__PHY_DQ_DM_SWIZZLE1_1_WIDTH 4U
  1708. #define LPDDR4__PHY_DQ_DM_SWIZZLE1_1__REG DENALI_PHY_371
  1709. #define LPDDR4__PHY_DQ_DM_SWIZZLE1_1__FLD LPDDR4__DENALI_PHY_371__PHY_DQ_DM_SWIZZLE1_1
  1710. #define LPDDR4__DENALI_PHY_372_READ_MASK 0x07FF07FFU
  1711. #define LPDDR4__DENALI_PHY_372_WRITE_MASK 0x07FF07FFU
  1712. #define LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ0_SLAVE_DELAY_1_MASK 0x000007FFU
  1713. #define LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ0_SLAVE_DELAY_1_SHIFT 0U
  1714. #define LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ0_SLAVE_DELAY_1_WIDTH 11U
  1715. #define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_1__REG DENALI_PHY_372
  1716. #define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ0_SLAVE_DELAY_1
  1717. #define LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ1_SLAVE_DELAY_1_MASK 0x07FF0000U
  1718. #define LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ1_SLAVE_DELAY_1_SHIFT 16U
  1719. #define LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ1_SLAVE_DELAY_1_WIDTH 11U
  1720. #define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_1__REG DENALI_PHY_372
  1721. #define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ1_SLAVE_DELAY_1
  1722. #define LPDDR4__DENALI_PHY_373_READ_MASK 0x07FF07FFU
  1723. #define LPDDR4__DENALI_PHY_373_WRITE_MASK 0x07FF07FFU
  1724. #define LPDDR4__DENALI_PHY_373__PHY_CLK_WRDQ2_SLAVE_DELAY_1_MASK 0x000007FFU
  1725. #define LPDDR4__DENALI_PHY_373__PHY_CLK_WRDQ2_SLAVE_DELAY_1_SHIFT 0U
  1726. #define LPDDR4__DENALI_PHY_373__PHY_CLK_WRDQ2_SLAVE_DELAY_1_WIDTH 11U
  1727. #define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_1__REG DENALI_PHY_373
  1728. #define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_373__PHY_CLK_WRDQ2_SLAVE_DELAY_1
  1729. #define LPDDR4__DENALI_PHY_373__PHY_CLK_WRDQ3_SLAVE_DELAY_1_MASK 0x07FF0000U
  1730. #define LPDDR4__DENALI_PHY_373__PHY_CLK_WRDQ3_SLAVE_DELAY_1_SHIFT 16U
  1731. #define LPDDR4__DENALI_PHY_373__PHY_CLK_WRDQ3_SLAVE_DELAY_1_WIDTH 11U
  1732. #define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_1__REG DENALI_PHY_373
  1733. #define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_373__PHY_CLK_WRDQ3_SLAVE_DELAY_1
  1734. #define LPDDR4__DENALI_PHY_374_READ_MASK 0x07FF07FFU
  1735. #define LPDDR4__DENALI_PHY_374_WRITE_MASK 0x07FF07FFU
  1736. #define LPDDR4__DENALI_PHY_374__PHY_CLK_WRDQ4_SLAVE_DELAY_1_MASK 0x000007FFU
  1737. #define LPDDR4__DENALI_PHY_374__PHY_CLK_WRDQ4_SLAVE_DELAY_1_SHIFT 0U
  1738. #define LPDDR4__DENALI_PHY_374__PHY_CLK_WRDQ4_SLAVE_DELAY_1_WIDTH 11U
  1739. #define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_1__REG DENALI_PHY_374
  1740. #define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_374__PHY_CLK_WRDQ4_SLAVE_DELAY_1
  1741. #define LPDDR4__DENALI_PHY_374__PHY_CLK_WRDQ5_SLAVE_DELAY_1_MASK 0x07FF0000U
  1742. #define LPDDR4__DENALI_PHY_374__PHY_CLK_WRDQ5_SLAVE_DELAY_1_SHIFT 16U
  1743. #define LPDDR4__DENALI_PHY_374__PHY_CLK_WRDQ5_SLAVE_DELAY_1_WIDTH 11U
  1744. #define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_1__REG DENALI_PHY_374
  1745. #define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_374__PHY_CLK_WRDQ5_SLAVE_DELAY_1
  1746. #define LPDDR4__DENALI_PHY_375_READ_MASK 0x07FF07FFU
  1747. #define LPDDR4__DENALI_PHY_375_WRITE_MASK 0x07FF07FFU
  1748. #define LPDDR4__DENALI_PHY_375__PHY_CLK_WRDQ6_SLAVE_DELAY_1_MASK 0x000007FFU
  1749. #define LPDDR4__DENALI_PHY_375__PHY_CLK_WRDQ6_SLAVE_DELAY_1_SHIFT 0U
  1750. #define LPDDR4__DENALI_PHY_375__PHY_CLK_WRDQ6_SLAVE_DELAY_1_WIDTH 11U
  1751. #define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_1__REG DENALI_PHY_375
  1752. #define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_375__PHY_CLK_WRDQ6_SLAVE_DELAY_1
  1753. #define LPDDR4__DENALI_PHY_375__PHY_CLK_WRDQ7_SLAVE_DELAY_1_MASK 0x07FF0000U
  1754. #define LPDDR4__DENALI_PHY_375__PHY_CLK_WRDQ7_SLAVE_DELAY_1_SHIFT 16U
  1755. #define LPDDR4__DENALI_PHY_375__PHY_CLK_WRDQ7_SLAVE_DELAY_1_WIDTH 11U
  1756. #define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_1__REG DENALI_PHY_375
  1757. #define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_375__PHY_CLK_WRDQ7_SLAVE_DELAY_1
  1758. #define LPDDR4__DENALI_PHY_376_READ_MASK 0x03FF07FFU
  1759. #define LPDDR4__DENALI_PHY_376_WRITE_MASK 0x03FF07FFU
  1760. #define LPDDR4__DENALI_PHY_376__PHY_CLK_WRDM_SLAVE_DELAY_1_MASK 0x000007FFU
  1761. #define LPDDR4__DENALI_PHY_376__PHY_CLK_WRDM_SLAVE_DELAY_1_SHIFT 0U
  1762. #define LPDDR4__DENALI_PHY_376__PHY_CLK_WRDM_SLAVE_DELAY_1_WIDTH 11U
  1763. #define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_1__REG DENALI_PHY_376
  1764. #define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_376__PHY_CLK_WRDM_SLAVE_DELAY_1
  1765. #define LPDDR4__DENALI_PHY_376__PHY_CLK_WRDQS_SLAVE_DELAY_1_MASK 0x03FF0000U
  1766. #define LPDDR4__DENALI_PHY_376__PHY_CLK_WRDQS_SLAVE_DELAY_1_SHIFT 16U
  1767. #define LPDDR4__DENALI_PHY_376__PHY_CLK_WRDQS_SLAVE_DELAY_1_WIDTH 10U
  1768. #define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_1__REG DENALI_PHY_376
  1769. #define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_376__PHY_CLK_WRDQS_SLAVE_DELAY_1
  1770. #define LPDDR4__DENALI_PHY_377_READ_MASK 0x0003FF03U
  1771. #define LPDDR4__DENALI_PHY_377_WRITE_MASK 0x0003FF03U
  1772. #define LPDDR4__DENALI_PHY_377__PHY_WRLVL_THRESHOLD_ADJUST_1_MASK 0x00000003U
  1773. #define LPDDR4__DENALI_PHY_377__PHY_WRLVL_THRESHOLD_ADJUST_1_SHIFT 0U
  1774. #define LPDDR4__DENALI_PHY_377__PHY_WRLVL_THRESHOLD_ADJUST_1_WIDTH 2U
  1775. #define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_1__REG DENALI_PHY_377
  1776. #define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_1__FLD LPDDR4__DENALI_PHY_377__PHY_WRLVL_THRESHOLD_ADJUST_1
  1777. #define LPDDR4__DENALI_PHY_377__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1_MASK 0x0003FF00U
  1778. #define LPDDR4__DENALI_PHY_377__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1_SHIFT 8U
  1779. #define LPDDR4__DENALI_PHY_377__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1_WIDTH 10U
  1780. #define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1__REG DENALI_PHY_377
  1781. #define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_377__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1
  1782. #define LPDDR4__DENALI_PHY_378_READ_MASK 0x03FF03FFU
  1783. #define LPDDR4__DENALI_PHY_378_WRITE_MASK 0x03FF03FFU
  1784. #define LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
  1785. #define LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1_SHIFT 0U
  1786. #define LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1_WIDTH 10U
  1787. #define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1__REG DENALI_PHY_378
  1788. #define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1
  1789. #define LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
  1790. #define LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1_SHIFT 16U
  1791. #define LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1_WIDTH 10U
  1792. #define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1__REG DENALI_PHY_378
  1793. #define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1
  1794. #define LPDDR4__DENALI_PHY_379_READ_MASK 0x03FF03FFU
  1795. #define LPDDR4__DENALI_PHY_379_WRITE_MASK 0x03FF03FFU
  1796. #define LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
  1797. #define LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1_SHIFT 0U
  1798. #define LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1_WIDTH 10U
  1799. #define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1__REG DENALI_PHY_379
  1800. #define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1
  1801. #define LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
  1802. #define LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1_SHIFT 16U
  1803. #define LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1_WIDTH 10U
  1804. #define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1__REG DENALI_PHY_379
  1805. #define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1
  1806. #define LPDDR4__DENALI_PHY_380_READ_MASK 0x03FF03FFU
  1807. #define LPDDR4__DENALI_PHY_380_WRITE_MASK 0x03FF03FFU
  1808. #define LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
  1809. #define LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1_SHIFT 0U
  1810. #define LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1_WIDTH 10U
  1811. #define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1__REG DENALI_PHY_380
  1812. #define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1
  1813. #define LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
  1814. #define LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1_SHIFT 16U
  1815. #define LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1_WIDTH 10U
  1816. #define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1__REG DENALI_PHY_380
  1817. #define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1
  1818. #define LPDDR4__DENALI_PHY_381_READ_MASK 0x03FF03FFU
  1819. #define LPDDR4__DENALI_PHY_381_WRITE_MASK 0x03FF03FFU
  1820. #define LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
  1821. #define LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1_SHIFT 0U
  1822. #define LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1_WIDTH 10U
  1823. #define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1__REG DENALI_PHY_381
  1824. #define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1
  1825. #define LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
  1826. #define LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1_SHIFT 16U
  1827. #define LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1_WIDTH 10U
  1828. #define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1__REG DENALI_PHY_381
  1829. #define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1
  1830. #define LPDDR4__DENALI_PHY_382_READ_MASK 0x03FF03FFU
  1831. #define LPDDR4__DENALI_PHY_382_WRITE_MASK 0x03FF03FFU
  1832. #define LPDDR4__DENALI_PHY_382__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
  1833. #define LPDDR4__DENALI_PHY_382__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1_SHIFT 0U
  1834. #define LPDDR4__DENALI_PHY_382__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1_WIDTH 10U
  1835. #define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1__REG DENALI_PHY_382
  1836. #define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_382__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1
  1837. #define LPDDR4__DENALI_PHY_382__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
  1838. #define LPDDR4__DENALI_PHY_382__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1_SHIFT 16U
  1839. #define LPDDR4__DENALI_PHY_382__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1_WIDTH 10U
  1840. #define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1__REG DENALI_PHY_382
  1841. #define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_382__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1
  1842. #define LPDDR4__DENALI_PHY_383_READ_MASK 0x03FF03FFU
  1843. #define LPDDR4__DENALI_PHY_383_WRITE_MASK 0x03FF03FFU
  1844. #define LPDDR4__DENALI_PHY_383__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
  1845. #define LPDDR4__DENALI_PHY_383__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1_SHIFT 0U
  1846. #define LPDDR4__DENALI_PHY_383__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1_WIDTH 10U
  1847. #define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1__REG DENALI_PHY_383
  1848. #define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_383__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1
  1849. #define LPDDR4__DENALI_PHY_383__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
  1850. #define LPDDR4__DENALI_PHY_383__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1_SHIFT 16U
  1851. #define LPDDR4__DENALI_PHY_383__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1_WIDTH 10U
  1852. #define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1__REG DENALI_PHY_383
  1853. #define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_383__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1
  1854. #define LPDDR4__DENALI_PHY_384_READ_MASK 0x03FF03FFU
  1855. #define LPDDR4__DENALI_PHY_384_WRITE_MASK 0x03FF03FFU
  1856. #define LPDDR4__DENALI_PHY_384__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
  1857. #define LPDDR4__DENALI_PHY_384__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1_SHIFT 0U
  1858. #define LPDDR4__DENALI_PHY_384__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1_WIDTH 10U
  1859. #define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1__REG DENALI_PHY_384
  1860. #define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_384__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1
  1861. #define LPDDR4__DENALI_PHY_384__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
  1862. #define LPDDR4__DENALI_PHY_384__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1_SHIFT 16U
  1863. #define LPDDR4__DENALI_PHY_384__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1_WIDTH 10U
  1864. #define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1__REG DENALI_PHY_384
  1865. #define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_384__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1
  1866. #define LPDDR4__DENALI_PHY_385_READ_MASK 0x03FF03FFU
  1867. #define LPDDR4__DENALI_PHY_385_WRITE_MASK 0x03FF03FFU
  1868. #define LPDDR4__DENALI_PHY_385__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
  1869. #define LPDDR4__DENALI_PHY_385__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1_SHIFT 0U
  1870. #define LPDDR4__DENALI_PHY_385__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1_WIDTH 10U
  1871. #define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1__REG DENALI_PHY_385
  1872. #define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_385__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1
  1873. #define LPDDR4__DENALI_PHY_385__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
  1874. #define LPDDR4__DENALI_PHY_385__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1_SHIFT 16U
  1875. #define LPDDR4__DENALI_PHY_385__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1_WIDTH 10U
  1876. #define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1__REG DENALI_PHY_385
  1877. #define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_385__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1
  1878. #define LPDDR4__DENALI_PHY_386_READ_MASK 0x03FF03FFU
  1879. #define LPDDR4__DENALI_PHY_386_WRITE_MASK 0x03FF03FFU
  1880. #define LPDDR4__DENALI_PHY_386__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
  1881. #define LPDDR4__DENALI_PHY_386__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1_SHIFT 0U
  1882. #define LPDDR4__DENALI_PHY_386__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1_WIDTH 10U
  1883. #define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1__REG DENALI_PHY_386
  1884. #define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_386__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1
  1885. #define LPDDR4__DENALI_PHY_386__PHY_RDDQS_GATE_SLAVE_DELAY_1_MASK 0x03FF0000U
  1886. #define LPDDR4__DENALI_PHY_386__PHY_RDDQS_GATE_SLAVE_DELAY_1_SHIFT 16U
  1887. #define LPDDR4__DENALI_PHY_386__PHY_RDDQS_GATE_SLAVE_DELAY_1_WIDTH 10U
  1888. #define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_1__REG DENALI_PHY_386
  1889. #define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_386__PHY_RDDQS_GATE_SLAVE_DELAY_1
  1890. #define LPDDR4__DENALI_PHY_387_READ_MASK 0x03FF070FU
  1891. #define LPDDR4__DENALI_PHY_387_WRITE_MASK 0x03FF070FU
  1892. #define LPDDR4__DENALI_PHY_387__PHY_RDDQS_LATENCY_ADJUST_1_MASK 0x0000000FU
  1893. #define LPDDR4__DENALI_PHY_387__PHY_RDDQS_LATENCY_ADJUST_1_SHIFT 0U
  1894. #define LPDDR4__DENALI_PHY_387__PHY_RDDQS_LATENCY_ADJUST_1_WIDTH 4U
  1895. #define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_1__REG DENALI_PHY_387
  1896. #define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_1__FLD LPDDR4__DENALI_PHY_387__PHY_RDDQS_LATENCY_ADJUST_1
  1897. #define LPDDR4__DENALI_PHY_387__PHY_WRITE_PATH_LAT_ADD_1_MASK 0x00000700U
  1898. #define LPDDR4__DENALI_PHY_387__PHY_WRITE_PATH_LAT_ADD_1_SHIFT 8U
  1899. #define LPDDR4__DENALI_PHY_387__PHY_WRITE_PATH_LAT_ADD_1_WIDTH 3U
  1900. #define LPDDR4__PHY_WRITE_PATH_LAT_ADD_1__REG DENALI_PHY_387
  1901. #define LPDDR4__PHY_WRITE_PATH_LAT_ADD_1__FLD LPDDR4__DENALI_PHY_387__PHY_WRITE_PATH_LAT_ADD_1
  1902. #define LPDDR4__DENALI_PHY_387__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1_MASK 0x03FF0000U
  1903. #define LPDDR4__DENALI_PHY_387__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1_SHIFT 16U
  1904. #define LPDDR4__DENALI_PHY_387__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1_WIDTH 10U
  1905. #define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1__REG DENALI_PHY_387
  1906. #define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_387__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1
  1907. #define LPDDR4__DENALI_PHY_388_READ_MASK 0x000103FFU
  1908. #define LPDDR4__DENALI_PHY_388_WRITE_MASK 0x000103FFU
  1909. #define LPDDR4__DENALI_PHY_388__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1_MASK 0x000003FFU
  1910. #define LPDDR4__DENALI_PHY_388__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1_SHIFT 0U
  1911. #define LPDDR4__DENALI_PHY_388__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1_WIDTH 10U
  1912. #define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1__REG DENALI_PHY_388
  1913. #define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_388__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1
  1914. #define LPDDR4__DENALI_PHY_388__PHY_WRLVL_EARLY_FORCE_ZERO_1_MASK 0x00010000U
  1915. #define LPDDR4__DENALI_PHY_388__PHY_WRLVL_EARLY_FORCE_ZERO_1_SHIFT 16U
  1916. #define LPDDR4__DENALI_PHY_388__PHY_WRLVL_EARLY_FORCE_ZERO_1_WIDTH 1U
  1917. #define LPDDR4__DENALI_PHY_388__PHY_WRLVL_EARLY_FORCE_ZERO_1_WOCLR 0U
  1918. #define LPDDR4__DENALI_PHY_388__PHY_WRLVL_EARLY_FORCE_ZERO_1_WOSET 0U
  1919. #define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_1__REG DENALI_PHY_388
  1920. #define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_1__FLD LPDDR4__DENALI_PHY_388__PHY_WRLVL_EARLY_FORCE_ZERO_1
  1921. #define LPDDR4__DENALI_PHY_389_READ_MASK 0x000F03FFU
  1922. #define LPDDR4__DENALI_PHY_389_WRITE_MASK 0x000F03FFU
  1923. #define LPDDR4__DENALI_PHY_389__PHY_GTLVL_RDDQS_SLV_DLY_START_1_MASK 0x000003FFU
  1924. #define LPDDR4__DENALI_PHY_389__PHY_GTLVL_RDDQS_SLV_DLY_START_1_SHIFT 0U
  1925. #define LPDDR4__DENALI_PHY_389__PHY_GTLVL_RDDQS_SLV_DLY_START_1_WIDTH 10U
  1926. #define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_1__REG DENALI_PHY_389
  1927. #define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_1__FLD LPDDR4__DENALI_PHY_389__PHY_GTLVL_RDDQS_SLV_DLY_START_1
  1928. #define LPDDR4__DENALI_PHY_389__PHY_GTLVL_LAT_ADJ_START_1_MASK 0x000F0000U
  1929. #define LPDDR4__DENALI_PHY_389__PHY_GTLVL_LAT_ADJ_START_1_SHIFT 16U
  1930. #define LPDDR4__DENALI_PHY_389__PHY_GTLVL_LAT_ADJ_START_1_WIDTH 4U
  1931. #define LPDDR4__PHY_GTLVL_LAT_ADJ_START_1__REG DENALI_PHY_389
  1932. #define LPDDR4__PHY_GTLVL_LAT_ADJ_START_1__FLD LPDDR4__DENALI_PHY_389__PHY_GTLVL_LAT_ADJ_START_1
  1933. #define LPDDR4__DENALI_PHY_390_READ_MASK 0x010F07FFU
  1934. #define LPDDR4__DENALI_PHY_390_WRITE_MASK 0x010F07FFU
  1935. #define LPDDR4__DENALI_PHY_390__PHY_WDQLVL_DQDM_SLV_DLY_START_1_MASK 0x000007FFU
  1936. #define LPDDR4__DENALI_PHY_390__PHY_WDQLVL_DQDM_SLV_DLY_START_1_SHIFT 0U
  1937. #define LPDDR4__DENALI_PHY_390__PHY_WDQLVL_DQDM_SLV_DLY_START_1_WIDTH 11U
  1938. #define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_1__REG DENALI_PHY_390
  1939. #define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_1__FLD LPDDR4__DENALI_PHY_390__PHY_WDQLVL_DQDM_SLV_DLY_START_1
  1940. #define LPDDR4__DENALI_PHY_390__PHY_NTP_WRLAT_START_1_MASK 0x000F0000U
  1941. #define LPDDR4__DENALI_PHY_390__PHY_NTP_WRLAT_START_1_SHIFT 16U
  1942. #define LPDDR4__DENALI_PHY_390__PHY_NTP_WRLAT_START_1_WIDTH 4U
  1943. #define LPDDR4__PHY_NTP_WRLAT_START_1__REG DENALI_PHY_390
  1944. #define LPDDR4__PHY_NTP_WRLAT_START_1__FLD LPDDR4__DENALI_PHY_390__PHY_NTP_WRLAT_START_1
  1945. #define LPDDR4__DENALI_PHY_390__PHY_NTP_PASS_1_MASK 0x01000000U
  1946. #define LPDDR4__DENALI_PHY_390__PHY_NTP_PASS_1_SHIFT 24U
  1947. #define LPDDR4__DENALI_PHY_390__PHY_NTP_PASS_1_WIDTH 1U
  1948. #define LPDDR4__DENALI_PHY_390__PHY_NTP_PASS_1_WOCLR 0U
  1949. #define LPDDR4__DENALI_PHY_390__PHY_NTP_PASS_1_WOSET 0U
  1950. #define LPDDR4__PHY_NTP_PASS_1__REG DENALI_PHY_390
  1951. #define LPDDR4__PHY_NTP_PASS_1__FLD LPDDR4__DENALI_PHY_390__PHY_NTP_PASS_1
  1952. #define LPDDR4__DENALI_PHY_391_READ_MASK 0x000003FFU
  1953. #define LPDDR4__DENALI_PHY_391_WRITE_MASK 0x000003FFU
  1954. #define LPDDR4__DENALI_PHY_391__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1_MASK 0x000003FFU
  1955. #define LPDDR4__DENALI_PHY_391__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1_SHIFT 0U
  1956. #define LPDDR4__DENALI_PHY_391__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1_WIDTH 10U
  1957. #define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1__REG DENALI_PHY_391
  1958. #define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1__FLD LPDDR4__DENALI_PHY_391__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1
  1959. #define LPDDR4__DENALI_PHY_392_READ_MASK 0xFFFFFFFFU
  1960. #define LPDDR4__DENALI_PHY_392_WRITE_MASK 0xFFFFFFFFU
  1961. #define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQS_CLK_ADJUST_1_MASK 0x000000FFU
  1962. #define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQS_CLK_ADJUST_1_SHIFT 0U
  1963. #define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQS_CLK_ADJUST_1_WIDTH 8U
  1964. #define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_1__REG DENALI_PHY_392
  1965. #define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQS_CLK_ADJUST_1
  1966. #define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQ0_CLK_ADJUST_1_MASK 0x0000FF00U
  1967. #define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQ0_CLK_ADJUST_1_SHIFT 8U
  1968. #define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQ0_CLK_ADJUST_1_WIDTH 8U
  1969. #define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_1__REG DENALI_PHY_392
  1970. #define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQ0_CLK_ADJUST_1
  1971. #define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQ1_CLK_ADJUST_1_MASK 0x00FF0000U
  1972. #define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQ1_CLK_ADJUST_1_SHIFT 16U
  1973. #define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQ1_CLK_ADJUST_1_WIDTH 8U
  1974. #define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_1__REG DENALI_PHY_392
  1975. #define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQ1_CLK_ADJUST_1
  1976. #define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQ2_CLK_ADJUST_1_MASK 0xFF000000U
  1977. #define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQ2_CLK_ADJUST_1_SHIFT 24U
  1978. #define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQ2_CLK_ADJUST_1_WIDTH 8U
  1979. #define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_1__REG DENALI_PHY_392
  1980. #define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQ2_CLK_ADJUST_1
  1981. #define LPDDR4__DENALI_PHY_393_READ_MASK 0xFFFFFFFFU
  1982. #define LPDDR4__DENALI_PHY_393_WRITE_MASK 0xFFFFFFFFU
  1983. #define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ3_CLK_ADJUST_1_MASK 0x000000FFU
  1984. #define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ3_CLK_ADJUST_1_SHIFT 0U
  1985. #define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ3_CLK_ADJUST_1_WIDTH 8U
  1986. #define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_1__REG DENALI_PHY_393
  1987. #define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ3_CLK_ADJUST_1
  1988. #define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ4_CLK_ADJUST_1_MASK 0x0000FF00U
  1989. #define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ4_CLK_ADJUST_1_SHIFT 8U
  1990. #define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ4_CLK_ADJUST_1_WIDTH 8U
  1991. #define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_1__REG DENALI_PHY_393
  1992. #define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ4_CLK_ADJUST_1
  1993. #define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ5_CLK_ADJUST_1_MASK 0x00FF0000U
  1994. #define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ5_CLK_ADJUST_1_SHIFT 16U
  1995. #define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ5_CLK_ADJUST_1_WIDTH 8U
  1996. #define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_1__REG DENALI_PHY_393
  1997. #define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ5_CLK_ADJUST_1
  1998. #define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ6_CLK_ADJUST_1_MASK 0xFF000000U
  1999. #define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ6_CLK_ADJUST_1_SHIFT 24U
  2000. #define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ6_CLK_ADJUST_1_WIDTH 8U
  2001. #define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_1__REG DENALI_PHY_393
  2002. #define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ6_CLK_ADJUST_1
  2003. #define LPDDR4__DENALI_PHY_394_READ_MASK 0xFFFFFFFFU
  2004. #define LPDDR4__DENALI_PHY_394_WRITE_MASK 0xFFFFFFFFU
  2005. #define LPDDR4__DENALI_PHY_394__PHY_DATA_DC_DQ7_CLK_ADJUST_1_MASK 0x000000FFU
  2006. #define LPDDR4__DENALI_PHY_394__PHY_DATA_DC_DQ7_CLK_ADJUST_1_SHIFT 0U
  2007. #define LPDDR4__DENALI_PHY_394__PHY_DATA_DC_DQ7_CLK_ADJUST_1_WIDTH 8U
  2008. #define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_1__REG DENALI_PHY_394
  2009. #define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_394__PHY_DATA_DC_DQ7_CLK_ADJUST_1
  2010. #define LPDDR4__DENALI_PHY_394__PHY_DATA_DC_DM_CLK_ADJUST_1_MASK 0x0000FF00U
  2011. #define LPDDR4__DENALI_PHY_394__PHY_DATA_DC_DM_CLK_ADJUST_1_SHIFT 8U
  2012. #define LPDDR4__DENALI_PHY_394__PHY_DATA_DC_DM_CLK_ADJUST_1_WIDTH 8U
  2013. #define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_1__REG DENALI_PHY_394
  2014. #define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_394__PHY_DATA_DC_DM_CLK_ADJUST_1
  2015. #define LPDDR4__DENALI_PHY_394__PHY_DSLICE_PAD_BOOSTPN_SETTING_1_MASK 0xFFFF0000U
  2016. #define LPDDR4__DENALI_PHY_394__PHY_DSLICE_PAD_BOOSTPN_SETTING_1_SHIFT 16U
  2017. #define LPDDR4__DENALI_PHY_394__PHY_DSLICE_PAD_BOOSTPN_SETTING_1_WIDTH 16U
  2018. #define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_1__REG DENALI_PHY_394
  2019. #define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_1__FLD LPDDR4__DENALI_PHY_394__PHY_DSLICE_PAD_BOOSTPN_SETTING_1
  2020. #define LPDDR4__DENALI_PHY_395_READ_MASK 0x0003033FU
  2021. #define LPDDR4__DENALI_PHY_395_WRITE_MASK 0x0003033FU
  2022. #define LPDDR4__DENALI_PHY_395__PHY_DSLICE_PAD_RX_CTLE_SETTING_1_MASK 0x0000003FU
  2023. #define LPDDR4__DENALI_PHY_395__PHY_DSLICE_PAD_RX_CTLE_SETTING_1_SHIFT 0U
  2024. #define LPDDR4__DENALI_PHY_395__PHY_DSLICE_PAD_RX_CTLE_SETTING_1_WIDTH 6U
  2025. #define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_1__REG DENALI_PHY_395
  2026. #define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_1__FLD LPDDR4__DENALI_PHY_395__PHY_DSLICE_PAD_RX_CTLE_SETTING_1
  2027. #define LPDDR4__DENALI_PHY_395__PHY_DQ_FFE_1_MASK 0x00000300U
  2028. #define LPDDR4__DENALI_PHY_395__PHY_DQ_FFE_1_SHIFT 8U
  2029. #define LPDDR4__DENALI_PHY_395__PHY_DQ_FFE_1_WIDTH 2U
  2030. #define LPDDR4__PHY_DQ_FFE_1__REG DENALI_PHY_395
  2031. #define LPDDR4__PHY_DQ_FFE_1__FLD LPDDR4__DENALI_PHY_395__PHY_DQ_FFE_1
  2032. #define LPDDR4__DENALI_PHY_395__PHY_DQS_FFE_1_MASK 0x00030000U
  2033. #define LPDDR4__DENALI_PHY_395__PHY_DQS_FFE_1_SHIFT 16U
  2034. #define LPDDR4__DENALI_PHY_395__PHY_DQS_FFE_1_WIDTH 2U
  2035. #define LPDDR4__PHY_DQS_FFE_1__REG DENALI_PHY_395
  2036. #define LPDDR4__PHY_DQS_FFE_1__FLD LPDDR4__DENALI_PHY_395__PHY_DQS_FFE_1
  2037. #endif /* REG_LPDDR4_DATA_SLICE_1_MACROS_H_ */