lpddr4.c 61 KB

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  1. // SPDX-License-Identifier: BSD-3-Clause
  2. /******************************************************************************
  3. * Copyright (C) 2012-2018 Cadence Design Systems, Inc.
  4. * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
  5. *
  6. * lpddr4.c
  7. *
  8. *****************************************************************************
  9. */
  10. #include "cps_drv_lpddr4.h"
  11. #include "lpddr4_ctl_regs.h"
  12. #include "lpddr4_if.h"
  13. #include "lpddr4_private.h"
  14. #include "lpddr4_sanity.h"
  15. #include "lpddr4_structs_if.h"
  16. #define LPDDR4_CUSTOM_TIMEOUT_DELAY 100000000U
  17. /**
  18. * Internal Function:Poll for status of interrupt received by the Controller.
  19. * @param[in] pD Driver state info specific to this instance.
  20. * @param[in] irqBit Interrupt status bit to be checked.
  21. * @param[in] delay time delay.
  22. * @return CDN_EOK on success (Interrupt status high).
  23. * @return EIO on poll time out.
  24. * @return EINVAL checking status was not successful.
  25. */
  26. static uint32_t lpddr4_pollctlirq(const lpddr4_privatedata * pd,
  27. lpddr4_ctlinterrupt irqbit, uint32_t delay)
  28. {
  29. uint32_t result = 0U;
  30. uint32_t timeout = 0U;
  31. bool irqstatus = false;
  32. /* Loop until irqStatus found to be 1 or if value of 'result' !=CDN_EOK */
  33. do {
  34. if (++timeout == delay) {
  35. result = EIO;
  36. break;
  37. }
  38. /* cps_delayns(10000000U); */
  39. result = lpddr4_checkctlinterrupt(pd, irqbit, &irqstatus);
  40. } while ((irqstatus == false) && (result == (uint32_t) CDN_EOK));
  41. return result;
  42. }
  43. /**
  44. * Internal Function:Poll for status of interrupt received by the PHY Independent Module.
  45. * @param[in] pD Driver state info specific to this instance.
  46. * @param[in] irqBit Interrupt status bit to be checked.
  47. * @param[in] delay time delay.
  48. * @return CDN_EOK on success (Interrupt status high).
  49. * @return EIO on poll time out.
  50. * @return EINVAL checking status was not successful.
  51. */
  52. static uint32_t lpddr4_pollphyindepirq(const lpddr4_privatedata * pd,
  53. lpddr4_phyindepinterrupt irqbit,
  54. uint32_t delay)
  55. {
  56. uint32_t result = 0U;
  57. uint32_t timeout = 0U;
  58. bool irqstatus = false;
  59. /* Loop until irqStatus found to be 1 or if value of 'result' !=CDN_EOK */
  60. do {
  61. if (++timeout == delay) {
  62. result = EIO;
  63. break;
  64. }
  65. /* cps_delayns(10000000U); */
  66. result = lpddr4_checkphyindepinterrupt(pd, irqbit, &irqstatus);
  67. } while ((irqstatus == false) && (result == (uint32_t) CDN_EOK));
  68. return result;
  69. }
  70. /**
  71. * Internal Function:Trigger function to poll and Ack IRQs
  72. * @param[in] pD Driver state info specific to this instance.
  73. * @return CDN_EOK on success (Interrupt status high).
  74. * @return EIO on poll time out.
  75. * @return EINVAL checking status was not successful.
  76. */
  77. static uint32_t lpddr4_pollandackirq(const lpddr4_privatedata * pd)
  78. {
  79. uint32_t result = 0U;
  80. /* Wait for PhyIndependent module to finish up ctl init sequence */
  81. result =
  82. lpddr4_pollphyindepirq(pd, LPDDR4_PHY_INDEP_INIT_DONE_BIT,
  83. LPDDR4_CUSTOM_TIMEOUT_DELAY);
  84. /* Ack to clear the PhyIndependent interrupt bit */
  85. if (result == (uint32_t) CDN_EOK) {
  86. result =
  87. lpddr4_ackphyindepinterrupt(pd,
  88. LPDDR4_PHY_INDEP_INIT_DONE_BIT);
  89. }
  90. /* Wait for the CTL end of initialization */
  91. if (result == (uint32_t) CDN_EOK) {
  92. result =
  93. lpddr4_pollctlirq(pd, LPDDR4_MC_INIT_DONE,
  94. LPDDR4_CUSTOM_TIMEOUT_DELAY);
  95. }
  96. /* Ack to clear the Ctl interrupt bit */
  97. if (result == (uint32_t) CDN_EOK) {
  98. result = lpddr4_ackctlinterrupt(pd, LPDDR4_MC_INIT_DONE);
  99. }
  100. return result;
  101. }
  102. /**
  103. * Internal Function: Controller start sequence.
  104. * @param[in] pD Driver state info specific to this instance.
  105. * @return CDN_EOK on success.
  106. * @return EINVAL starting controller was not successful.
  107. */
  108. static uint32_t lpddr4_startsequencecontroller(const lpddr4_privatedata * pd)
  109. {
  110. uint32_t result = 0U;
  111. uint32_t regval = 0U;
  112. lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
  113. lpddr4_infotype infotype;
  114. /* Set the PI_start to initiate leveling procedure */
  115. regval =
  116. CPS_FLD_SET(LPDDR4__PI_START__FLD,
  117. CPS_REG_READ(&(ctlregbase->LPDDR4__PI_START__REG)));
  118. CPS_REG_WRITE((&(ctlregbase->LPDDR4__PI_START__REG)), regval);
  119. /* Set the Ctl_start */
  120. regval =
  121. CPS_FLD_SET(LPDDR4__START__FLD,
  122. CPS_REG_READ(&(ctlregbase->LPDDR4__START__REG)));
  123. CPS_REG_WRITE(&(ctlregbase->LPDDR4__START__REG), regval);
  124. if (pd->infohandler != NULL) {
  125. /* If a handler is registered, call it with the relevant information type */
  126. infotype = LPDDR4_DRV_SOC_PLL_UPDATE;
  127. pd->infohandler(pd, infotype);
  128. }
  129. result = lpddr4_pollandackirq(pd);
  130. return result;
  131. }
  132. /**
  133. * Internal Function: To add the offset to given address.
  134. * @param[in] addr Address to which the offset has to be added.
  135. * @param[in] regOffset The offset
  136. * @return regAddr The address value after the summation.
  137. */
  138. static volatile uint32_t *lpddr4_addoffset(volatile uint32_t * addr,
  139. uint32_t regoffset)
  140. {
  141. volatile uint32_t *local_addr = addr;
  142. /* Declaring as array to add the offset value. */
  143. volatile uint32_t *regaddr = &local_addr[regoffset];
  144. return regaddr;
  145. }
  146. /**
  147. * Checks configuration object.
  148. * @param[in] config Driver/hardware configuration required.
  149. * @param[out] configSize Size of memory allocations required.
  150. * @return CDN_EOK on success (requirements structure filled).
  151. * @return ENOTSUP if configuration cannot be supported due to driver/hardware constraints.
  152. */
  153. uint32_t lpddr4_probe(const lpddr4_config * config, uint16_t * configsize)
  154. {
  155. uint32_t result;
  156. result = (uint32_t) (lpddr4_probesf(config, configsize));
  157. if (result == (uint32_t) CDN_EOK) {
  158. *configsize = (uint16_t) (sizeof(lpddr4_privatedata));
  159. }
  160. return result;
  161. }
  162. /**
  163. * Init function to be called after LPDDR4_probe() to set up the driver configuration.
  164. * Memory should be allocated for drv_data (using the size determined using LPDDR4_probe) before
  165. * calling this API, init_settings should be initialized with base addresses for PHY Independent Module,
  166. * Controller and PHY before calling this function.
  167. * If callbacks are required for interrupt handling, these should also be configured in init_settings.
  168. * @param[in] pD Driver state info specific to this instance.
  169. * @param[in] cfg Specifies driver/hardware configuration.
  170. * @return CDN_EOK on success
  171. * @return EINVAL if illegal/inconsistent values in cfg.
  172. * @return ENOTSUP if hardware has an inconsistent configuration or doesn't support feature(s)
  173. * required by 'config' parameters.
  174. */
  175. uint32_t lpddr4_init(lpddr4_privatedata * pd, const lpddr4_config * cfg)
  176. {
  177. uint32_t result = 0U;
  178. uint16_t productid = 0U;
  179. result = lpddr4_initsf(pd, cfg);
  180. if (result == (uint32_t) CDN_EOK) {
  181. /* Validate Magic number */
  182. lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) cfg->ctlbase;
  183. productid = (uint16_t) (CPS_FLD_READ(LPDDR4__CONTROLLER_ID__FLD,
  184. CPS_REG_READ(&
  185. (ctlregbase->
  186. LPDDR4__CONTROLLER_ID__REG))));
  187. if (productid == PRODUCT_ID) {
  188. /* Populating configuration data to pD */
  189. pd->ctlbase = ctlregbase;
  190. pd->infohandler =
  191. (lpddr4_infocallback) cfg->infohandler;
  192. pd->ctlinterrupthandler =
  193. (lpddr4_ctlcallback) cfg->ctlinterrupthandler;
  194. pd->phyindepinterrupthandler =
  195. (lpddr4_phyindepcallback) cfg->
  196. phyindepinterrupthandler;
  197. } else {
  198. /* Magic number validation failed - Driver doesn't support given IP version */
  199. result = (uint32_t) EOPNOTSUPP;
  200. }
  201. }
  202. return result;
  203. }
  204. /**
  205. * Start the driver.
  206. * @param[in] pD Driver state info specific to this instance.
  207. */
  208. uint32_t lpddr4_start(const lpddr4_privatedata * pd)
  209. {
  210. uint32_t result = 0U;
  211. uint32_t regval = 0U;
  212. result = lpddr4_startsf(pd);
  213. if (result == (uint32_t) CDN_EOK) {
  214. lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
  215. /* Enable PI as the initiator for DRAM */
  216. regval =
  217. CPS_FLD_SET(LPDDR4__PI_INIT_LVL_EN__FLD,
  218. CPS_REG_READ(&
  219. (ctlregbase->
  220. LPDDR4__PI_INIT_LVL_EN__REG)));
  221. regval = CPS_FLD_SET(LPDDR4__PI_NORMAL_LVL_SEQ__FLD, regval);
  222. CPS_REG_WRITE((&(ctlregbase->LPDDR4__PI_INIT_LVL_EN__REG)),
  223. regval);
  224. /* Start PI init sequence. */
  225. result = lpddr4_startsequencecontroller(pd);
  226. }
  227. return result;
  228. }
  229. /**
  230. * Read a register from the controller, PHY or PHY Independent Module
  231. * @param[in] pD Driver state info specific to this instance.
  232. * @param[in] cpp Indicates whether controller, PHY or PHY Independent Module register
  233. * @param[in] regOffset Register offset
  234. * @param[out] regValue Register value read
  235. * @return CDN_EOK on success.
  236. * @return EINVAL if regOffset if out of range or regValue is NULL
  237. */
  238. uint32_t lpddr4_readreg(const lpddr4_privatedata * pd, lpddr4_regblock cpp,
  239. uint32_t regoffset, uint32_t * regvalue)
  240. {
  241. uint32_t result = 0U;
  242. result = lpddr4_readregsf(pd, cpp, regvalue);
  243. if (result == (uint32_t) CDN_EOK) {
  244. lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
  245. if (cpp == LPDDR4_CTL_REGS) {
  246. if (regoffset >= LPDDR4_CTL_REG_COUNT) {
  247. /* Return if user provider invalid register number */
  248. result = EINVAL;
  249. } else {
  250. *regvalue =
  251. CPS_REG_READ(lpddr4_addoffset
  252. (&(ctlregbase->DENALI_CTL_0),
  253. regoffset));
  254. }
  255. } else if (cpp == LPDDR4_PHY_REGS) {
  256. if (regoffset >= LPDDR4_PHY_REG_COUNT) {
  257. /* Return if user provider invalid register number */
  258. result = EINVAL;
  259. } else {
  260. *regvalue =
  261. CPS_REG_READ(lpddr4_addoffset
  262. (&(ctlregbase->DENALI_PHY_0),
  263. regoffset));
  264. }
  265. } else {
  266. if (regoffset >= LPDDR4_PHY_INDEP_REG_COUNT) {
  267. /* Return if user provider invalid register number */
  268. result = EINVAL;
  269. } else {
  270. *regvalue =
  271. CPS_REG_READ(lpddr4_addoffset
  272. (&(ctlregbase->DENALI_PI_0),
  273. regoffset));
  274. }
  275. }
  276. }
  277. return result;
  278. }
  279. uint32_t lpddr4_writereg(const lpddr4_privatedata * pd, lpddr4_regblock cpp,
  280. uint32_t regoffset, uint32_t regvalue)
  281. {
  282. uint32_t result = 0U;
  283. result = lpddr4_writeregsf(pd, cpp);
  284. if (result == (uint32_t) CDN_EOK) {
  285. lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
  286. if (cpp == LPDDR4_CTL_REGS) {
  287. if (regoffset >= LPDDR4_CTL_REG_COUNT) {
  288. /* Return if user provider invalid register number */
  289. result = EINVAL;
  290. } else {
  291. CPS_REG_WRITE(lpddr4_addoffset
  292. (&(ctlregbase->DENALI_CTL_0),
  293. regoffset), regvalue);
  294. }
  295. } else if (cpp == LPDDR4_PHY_REGS) {
  296. if (regoffset >= LPDDR4_PHY_REG_COUNT) {
  297. /* Return if user provider invalid register number */
  298. result = EINVAL;
  299. } else {
  300. CPS_REG_WRITE(lpddr4_addoffset
  301. (&(ctlregbase->DENALI_PHY_0),
  302. regoffset), regvalue);
  303. }
  304. } else {
  305. if (regoffset >= LPDDR4_PHY_INDEP_REG_COUNT) {
  306. /* Return if user provider invalid register number */
  307. result = EINVAL;
  308. } else {
  309. CPS_REG_WRITE(lpddr4_addoffset
  310. (&(ctlregbase->DENALI_PI_0),
  311. regoffset), regvalue);
  312. }
  313. }
  314. }
  315. return result;
  316. }
  317. static uint32_t lpddr4_checkmmrreaderror(const lpddr4_privatedata * pd,
  318. uint64_t * mmrvalue,
  319. uint8_t * mrrstatus)
  320. {
  321. uint64_t lowerdata;
  322. lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
  323. uint32_t result = (uint32_t) CDN_EOK;
  324. /* Check if mode register read error interrupt occurred */
  325. if (lpddr4_pollctlirq(pd, LPDDR4_MRR_ERROR, 100) == 0U) {
  326. /* Mode register read error interrupt, read MRR status register and return. */
  327. *mrrstatus =
  328. (uint8_t) CPS_FLD_READ(LPDDR4__MRR_ERROR_STATUS__FLD,
  329. CPS_REG_READ(&
  330. (ctlregbase->
  331. LPDDR4__MRR_ERROR_STATUS__REG)));
  332. *mmrvalue = 0;
  333. result = EIO;
  334. } else {
  335. *mrrstatus = 0;
  336. /* Mode register read was successful, read DATA */
  337. lowerdata =
  338. CPS_REG_READ(&
  339. (ctlregbase->
  340. LPDDR4__PERIPHERAL_MRR_DATA_0__REG));
  341. *mmrvalue =
  342. CPS_REG_READ(&
  343. (ctlregbase->
  344. LPDDR4__PERIPHERAL_MRR_DATA_1__REG));
  345. *mmrvalue = (uint64_t) ((*mmrvalue << WORD_SHIFT) | lowerdata);
  346. /* Acknowledge MR_READ_DONE interrupt to clear it */
  347. result = lpddr4_ackctlinterrupt(pd, LPDDR4_MR_READ_DONE);
  348. }
  349. return result;
  350. }
  351. uint32_t lpddr4_getmmrregister(const lpddr4_privatedata * pd,
  352. uint32_t readmoderegval, uint64_t * mmrvalue,
  353. uint8_t * mmrstatus)
  354. {
  355. uint32_t result = 0U;
  356. uint32_t tdelay = 1000U;
  357. uint32_t regval = 0U;
  358. result = lpddr4_getmmrregistersf(pd, mmrvalue, mmrstatus);
  359. if (result == (uint32_t) CDN_EOK) {
  360. lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
  361. /* Populate the calculated value to the register */
  362. regval =
  363. CPS_FLD_WRITE(LPDDR4__READ_MODEREG__FLD,
  364. CPS_REG_READ(&
  365. (ctlregbase->
  366. LPDDR4__READ_MODEREG__REG)),
  367. readmoderegval);
  368. CPS_REG_WRITE(&(ctlregbase->LPDDR4__READ_MODEREG__REG), regval);
  369. /* Wait until the Read is done */
  370. result = lpddr4_pollctlirq(pd, LPDDR4_MR_READ_DONE, tdelay);
  371. }
  372. if (result == (uint32_t) CDN_EOK) {
  373. result = lpddr4_checkmmrreaderror(pd, mmrvalue, mmrstatus);
  374. }
  375. return result;
  376. }
  377. static uint32_t lpddr4_writemmrregister(const lpddr4_privatedata * pd,
  378. uint32_t writemoderegval)
  379. {
  380. uint32_t result = (uint32_t) CDN_EOK;
  381. uint32_t tdelay = 1000U;
  382. uint32_t regval = 0U;
  383. lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
  384. /* Populate the calculated value to the register */
  385. regval =
  386. CPS_FLD_WRITE(LPDDR4__WRITE_MODEREG__FLD,
  387. CPS_REG_READ(&
  388. (ctlregbase->
  389. LPDDR4__WRITE_MODEREG__REG)),
  390. writemoderegval);
  391. CPS_REG_WRITE(&(ctlregbase->LPDDR4__WRITE_MODEREG__REG), regval);
  392. result = lpddr4_pollctlirq(pd, LPDDR4_MR_WRITE_DONE, tdelay);
  393. return result;
  394. }
  395. uint32_t lpddr4_setmmrregister(const lpddr4_privatedata * pd,
  396. uint32_t writemoderegval, uint8_t * mrwstatus)
  397. {
  398. uint32_t result = 0U;
  399. result = lpddr4_setmmrregistersf(pd, mrwstatus);
  400. if (result == (uint32_t) CDN_EOK) {
  401. /* Function call to trigger Mode register write */
  402. result = lpddr4_writemmrregister(pd, writemoderegval);
  403. if (result == (uint32_t) CDN_EOK) {
  404. result =
  405. lpddr4_ackctlinterrupt(pd, LPDDR4_MR_WRITE_DONE);
  406. }
  407. /* Read the status of mode register write */
  408. if (result == (uint32_t) CDN_EOK) {
  409. lpddr4_ctlregs *ctlregbase =
  410. (lpddr4_ctlregs *) pd->ctlbase;
  411. *mrwstatus =
  412. (uint8_t) CPS_FLD_READ(LPDDR4__MRW_STATUS__FLD,
  413. CPS_REG_READ(&
  414. (ctlregbase->
  415. LPDDR4__MRW_STATUS__REG)));
  416. if ((*mrwstatus) != 0U) {
  417. result = EIO;
  418. }
  419. }
  420. }
  421. return result;
  422. }
  423. uint32_t lpddr4_writectlconfig(const lpddr4_privatedata * pd,
  424. const lpddr4_reginitdata * regvalues)
  425. {
  426. uint32_t result;
  427. uint32_t regnum;
  428. result = lpddr4_writectlconfigsf(pd, regvalues);
  429. if (result == (uint32_t) CDN_EOK) {
  430. /* Iterate through CTL register numbers. */
  431. for (regnum = 0; regnum < LPDDR4_CTL_REG_COUNT; regnum++) {
  432. /* Check if the user has requested update */
  433. if (regvalues->updatectlreg[regnum]) {
  434. result =
  435. lpddr4_writereg(pd, LPDDR4_CTL_REGS, regnum,
  436. (uint32_t) (regvalues->
  437. denalictlreg
  438. [regnum]));
  439. }
  440. }
  441. }
  442. return result;
  443. }
  444. uint32_t lpddr4_writephyindepconfig(const lpddr4_privatedata * pd,
  445. const lpddr4_reginitdata * regvalues)
  446. {
  447. uint32_t result;
  448. uint32_t regnum;
  449. result = lpddr4_writephyindepconfigsf(pd, regvalues);
  450. if (result == (uint32_t) CDN_EOK) {
  451. /* Iterate through PHY Independent module register numbers. */
  452. for (regnum = 0; regnum < LPDDR4_PHY_INDEP_REG_COUNT; regnum++) {
  453. /* Check if the user has requested update */
  454. if (regvalues->updatephyindepreg[regnum]) {
  455. result =
  456. lpddr4_writereg(pd, LPDDR4_PHY_INDEP_REGS,
  457. regnum,
  458. (uint32_t) (regvalues->
  459. denaliphyindepreg
  460. [regnum]));
  461. }
  462. }
  463. }
  464. return result;
  465. }
  466. uint32_t lpddr4_writephyconfig(const lpddr4_privatedata * pd,
  467. const lpddr4_reginitdata * regvalues)
  468. {
  469. uint32_t result;
  470. uint32_t regnum;
  471. result = lpddr4_writephyconfigsf(pd, regvalues);
  472. if (result == (uint32_t) CDN_EOK) {
  473. /* Iterate through PHY register numbers. */
  474. for (regnum = 0; regnum < LPDDR4_PHY_REG_COUNT; regnum++) {
  475. /* Check if the user has requested update */
  476. if (regvalues->updatephyreg[regnum]) {
  477. result =
  478. lpddr4_writereg(pd, LPDDR4_PHY_REGS, regnum,
  479. (uint32_t) (regvalues->
  480. denaliphyreg
  481. [regnum]));
  482. }
  483. }
  484. }
  485. return result;
  486. }
  487. uint32_t lpddr4_readctlconfig(const lpddr4_privatedata * pd,
  488. lpddr4_reginitdata * regvalues)
  489. {
  490. uint32_t result;
  491. uint32_t regnum;
  492. result = lpddr4_readctlconfigsf(pd, regvalues);
  493. if (result == (uint32_t) CDN_EOK) {
  494. /* Iterate through CTL register numbers. */
  495. for (regnum = 0; regnum < LPDDR4_CTL_REG_COUNT; regnum++) {
  496. /* Check if the user has requested read (updateCtlReg=1) */
  497. if (regvalues->updatectlreg[regnum]) {
  498. result =
  499. lpddr4_readreg(pd, LPDDR4_CTL_REGS, regnum,
  500. (uint32_t *) (&regvalues->
  501. denalictlreg
  502. [regnum]));
  503. }
  504. }
  505. }
  506. return result;
  507. }
  508. uint32_t lpddr4_readphyindepconfig(const lpddr4_privatedata * pd,
  509. lpddr4_reginitdata * regvalues)
  510. {
  511. uint32_t result;
  512. uint32_t regnum;
  513. result = lpddr4_readphyindepconfigsf(pd, regvalues);
  514. if (result == (uint32_t) CDN_EOK) {
  515. /* Iterate through PHY Independent module register numbers. */
  516. for (regnum = 0; regnum < LPDDR4_PHY_INDEP_REG_COUNT; regnum++) {
  517. /* Check if the user has requested read (updateCtlReg=1) */
  518. if (regvalues->updatephyindepreg[regnum]) {
  519. result =
  520. lpddr4_readreg(pd, LPDDR4_PHY_INDEP_REGS,
  521. regnum,
  522. (uint32_t *) (&regvalues->
  523. denaliphyindepreg
  524. [regnum]));
  525. }
  526. }
  527. }
  528. return result;
  529. }
  530. uint32_t lpddr4_readphyconfig(const lpddr4_privatedata * pd,
  531. lpddr4_reginitdata * regvalues)
  532. {
  533. uint32_t result;
  534. uint32_t regnum;
  535. result = lpddr4_readphyconfigsf(pd, regvalues);
  536. if (result == (uint32_t) CDN_EOK) {
  537. /* Iterate through PHY register numbers. */
  538. for (regnum = 0; regnum < LPDDR4_PHY_REG_COUNT; regnum++) {
  539. /* Check if the user has requested read (updateCtlReg=1) */
  540. if (regvalues->updatephyreg[regnum]) {
  541. result =
  542. lpddr4_readreg(pd, LPDDR4_PHY_REGS, regnum,
  543. (uint32_t *) (&regvalues->
  544. denaliphyreg
  545. [regnum]));
  546. }
  547. }
  548. }
  549. return result;
  550. }
  551. uint32_t lpddr4_getctlinterruptmask(const lpddr4_privatedata * pd,
  552. uint64_t * mask)
  553. {
  554. uint32_t result = 0U;
  555. uint64_t lowermask = 0U;
  556. result = lpddr4_getctlinterruptmasksf(pd, mask);
  557. if (result == (uint32_t) CDN_EOK) {
  558. lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
  559. /* Reading the lower mask register */
  560. lowermask =
  561. (uint64_t) (CPS_FLD_READ
  562. (LPDDR4__INT_MASK_0__FLD,
  563. CPS_REG_READ(&
  564. (ctlregbase->
  565. LPDDR4__INT_MASK_0__REG))));
  566. /* Reading the upper mask register */
  567. *mask =
  568. (uint64_t) (CPS_FLD_READ
  569. (LPDDR4__INT_MASK_1__FLD,
  570. CPS_REG_READ(&
  571. (ctlregbase->
  572. LPDDR4__INT_MASK_1__REG))));
  573. /* Concatenate both register informations */
  574. *mask = (uint64_t) ((*mask << WORD_SHIFT) | lowermask);
  575. }
  576. return result;
  577. }
  578. uint32_t lpddr4_setctlinterruptmask(const lpddr4_privatedata * pd,
  579. const uint64_t * mask)
  580. {
  581. uint32_t result;
  582. uint32_t regval = 0;
  583. const uint64_t ui64one = 1ULL;
  584. const uint32_t ui32irqcount = (uint32_t) LPDDR4_LOR_BITS + 1U;
  585. result = lpddr4_setctlinterruptmasksf(pd, mask);
  586. if ((result == (uint32_t) CDN_EOK) && (ui32irqcount < 64U)) {
  587. /* Return if the user given value is higher than the field width */
  588. if (*mask >= (ui64one << ui32irqcount)) {
  589. result = EINVAL;
  590. }
  591. }
  592. if (result == (uint32_t) CDN_EOK) {
  593. lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
  594. /* Extracting the lower 32 bits and writing to lower mask register */
  595. regval = (uint32_t) (*mask & WORD_MASK);
  596. regval =
  597. CPS_FLD_WRITE(LPDDR4__INT_MASK_0__FLD,
  598. CPS_REG_READ(&
  599. (ctlregbase->
  600. LPDDR4__INT_MASK_0__REG)),
  601. regval);
  602. CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_MASK_0__REG), regval);
  603. /* Extracting the upper 32 bits and writing to upper mask register */
  604. regval = (uint32_t) ((*mask >> WORD_SHIFT) & WORD_MASK);
  605. regval =
  606. CPS_FLD_WRITE(LPDDR4__INT_MASK_1__FLD,
  607. CPS_REG_READ(&
  608. (ctlregbase->
  609. LPDDR4__INT_MASK_1__REG)),
  610. regval);
  611. CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_MASK_1__REG), regval);
  612. }
  613. return result;
  614. }
  615. uint32_t lpddr4_checkctlinterrupt(const lpddr4_privatedata * pd,
  616. lpddr4_ctlinterrupt intr, bool * irqstatus)
  617. {
  618. uint32_t result;
  619. uint32_t ctlirqstatus = 0;
  620. uint32_t fieldshift = 0;
  621. /* NOTE:This function assume irq status is mentioned in NOT more than 2 registers.
  622. * Value of 'interrupt' should be less than 64 */
  623. result = lpddr4_checkctlinterruptsf(pd, intr, irqstatus);
  624. if (result == (uint32_t) CDN_EOK) {
  625. lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
  626. if ((uint32_t) intr >= WORD_SHIFT) {
  627. ctlirqstatus =
  628. CPS_REG_READ(&
  629. (ctlregbase->
  630. LPDDR4__INT_STATUS_1__REG));
  631. /* Reduce the shift value as we are considering upper register */
  632. fieldshift = (uint32_t) intr - ((uint32_t) WORD_SHIFT);
  633. } else {
  634. ctlirqstatus =
  635. CPS_REG_READ(&
  636. (ctlregbase->
  637. LPDDR4__INT_STATUS_0__REG));
  638. /* The shift value remains same for lower interrupt register */
  639. fieldshift = (uint32_t) intr;
  640. }
  641. /* MISRA compliance (Shifting operation) check */
  642. if (fieldshift < WORD_SHIFT) {
  643. if (((ctlirqstatus >> fieldshift) & BIT_MASK) > 0U) {
  644. *irqstatus = true;
  645. } else {
  646. *irqstatus = false;
  647. }
  648. }
  649. }
  650. return result;
  651. }
  652. uint32_t lpddr4_ackctlinterrupt(const lpddr4_privatedata * pd,
  653. lpddr4_ctlinterrupt intr)
  654. {
  655. uint32_t result = 0;
  656. uint32_t regval = 0;
  657. uint32_t localinterrupt = (uint32_t) intr;
  658. /* NOTE:This function assume irq status is mentioned in NOT more than 2 registers.
  659. * Value of 'interrupt' should be less than 64 */
  660. result = lpddr4_ackctlinterruptsf(pd, intr);
  661. if (result == (uint32_t) CDN_EOK) {
  662. lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
  663. /* Check if the requested bit is in upper register */
  664. if (localinterrupt > WORD_SHIFT) {
  665. localinterrupt =
  666. (localinterrupt - (uint32_t) WORD_SHIFT);
  667. regval = ((uint32_t) BIT_MASK << localinterrupt);
  668. CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_1__REG),
  669. regval);
  670. } else {
  671. regval = ((uint32_t) BIT_MASK << localinterrupt);
  672. CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_0__REG),
  673. regval);
  674. }
  675. }
  676. return result;
  677. }
  678. uint32_t lpddr4_getphyindepinterruptmask(const lpddr4_privatedata * pd,
  679. uint32_t * mask)
  680. {
  681. uint32_t result;
  682. result = lpddr4_getphyindepinterruptmsf(pd, mask);
  683. if (result == (uint32_t) CDN_EOK) {
  684. lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
  685. /* Reading mask register */
  686. *mask =
  687. CPS_FLD_READ(LPDDR4__PI_INT_MASK__FLD,
  688. CPS_REG_READ(&
  689. (ctlregbase->
  690. LPDDR4__PI_INT_MASK__REG)));
  691. }
  692. return result;
  693. }
  694. uint32_t lpddr4_setphyindepinterruptmask(const lpddr4_privatedata * pd,
  695. const uint32_t * mask)
  696. {
  697. uint32_t result;
  698. uint32_t regval = 0;
  699. const uint32_t ui32irqcount =
  700. (uint32_t) LPDDR4_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT + 1U;
  701. result = lpddr4_setphyindepinterruptmsf(pd, mask);
  702. if ((result == (uint32_t) CDN_EOK) && (ui32irqcount < WORD_SHIFT)) {
  703. /* Return if the user given value is higher than the field width */
  704. if (*mask >= (1U << ui32irqcount)) {
  705. result = EINVAL;
  706. }
  707. }
  708. if (result == (uint32_t) CDN_EOK) {
  709. lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
  710. /* Writing to the user requested interrupt mask */
  711. regval =
  712. CPS_FLD_WRITE(LPDDR4__PI_INT_MASK__FLD,
  713. CPS_REG_READ(&
  714. (ctlregbase->
  715. LPDDR4__PI_INT_MASK__REG)),
  716. *mask);
  717. CPS_REG_WRITE(&(ctlregbase->LPDDR4__PI_INT_MASK__REG), regval);
  718. }
  719. return result;
  720. }
  721. uint32_t lpddr4_checkphyindepinterrupt(const lpddr4_privatedata * pd,
  722. lpddr4_phyindepinterrupt intr,
  723. bool * irqstatus)
  724. {
  725. uint32_t result = 0;
  726. uint32_t phyindepirqstatus = 0;
  727. result = lpddr4_checkphyindepinterrupsf(pd, intr, irqstatus);
  728. /* Confirming that the value of interrupt is less than register width */
  729. if ((result == (uint32_t) CDN_EOK) && ((uint32_t) intr < WORD_SHIFT)) {
  730. lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
  731. /* Reading the requested bit to check interrupt status */
  732. phyindepirqstatus =
  733. CPS_REG_READ(&(ctlregbase->LPDDR4__PI_INT_STATUS__REG));
  734. *irqstatus =
  735. (((phyindepirqstatus >> (uint32_t) intr) & BIT_MASK) > 0U);
  736. }
  737. return result;
  738. }
  739. uint32_t lpddr4_ackphyindepinterrupt(const lpddr4_privatedata * pd,
  740. lpddr4_phyindepinterrupt intr)
  741. {
  742. uint32_t result = 0U;
  743. uint32_t regval = 0U;
  744. uint32_t ui32shiftinterrupt = (uint32_t) intr;
  745. result = lpddr4_ackphyindepinterruptsf(pd, intr);
  746. /* Confirming that the value of interrupt is less than register width */
  747. if ((result == (uint32_t) CDN_EOK) && (ui32shiftinterrupt < WORD_SHIFT)) {
  748. lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
  749. /* Write 1 to the requested bit to ACk the interrupt */
  750. regval = ((uint32_t) BIT_MASK << ui32shiftinterrupt);
  751. CPS_REG_WRITE(&(ctlregbase->LPDDR4__PI_INT_ACK__REG), regval);
  752. }
  753. return result;
  754. }
  755. /* Check for caTrainingError */
  756. static void lpddr4_checkcatrainingerror(lpddr4_ctlregs * ctlregbase,
  757. lpddr4_debuginfo * debuginfo,
  758. bool * errfoundptr)
  759. {
  760. uint32_t regval;
  761. uint32_t errbitmask = 0U;
  762. uint32_t snum;
  763. volatile uint32_t *regaddress;
  764. regaddress =
  765. (volatile uint32_t
  766. *)(&(ctlregbase->LPDDR4__PHY_ADR_CALVL_OBS1_0__REG));
  767. errbitmask = (CA_TRAIN_RL) | (NIBBLE_MASK);
  768. /* PHY_ADR_CALVL_OBS1[4] – Right found
  769. PHY_ADR_CALVL_OBS1[5] – left found
  770. both the above fields should be high and below field should be zero.
  771. PHY_ADR_CALVL_OBS1[3:0] – calvl_state
  772. */
  773. for (snum = 0U; snum < ASLICE_NUM; snum++) {
  774. regval = CPS_REG_READ(regaddress);
  775. if ((regval & errbitmask) != CA_TRAIN_RL) {
  776. debuginfo->catraingerror = true;
  777. *errfoundptr = true;
  778. }
  779. regaddress =
  780. lpddr4_addoffset(regaddress, (uint32_t) SLICE_WIDTH);
  781. }
  782. }
  783. /* Check for wrLvlError */
  784. static void lpddr4_checkwrlvlerror(lpddr4_ctlregs * ctlregbase,
  785. lpddr4_debuginfo * debuginfo,
  786. bool * errfoundptr)
  787. {
  788. uint32_t regval;
  789. uint32_t errbitmask = 0U;
  790. uint32_t snum;
  791. volatile uint32_t *regaddress;
  792. regaddress =
  793. (volatile uint32_t
  794. *)(&(ctlregbase->LPDDR4__PHY_WRLVL_ERROR_OBS_0__REG));
  795. /* PHY_WRLVL_ERROR_OBS_X[1:0] should be zero */
  796. errbitmask = (BIT_MASK << 1) | (BIT_MASK);
  797. for (snum = 0U; snum < DSLICE_NUM; snum++) {
  798. regval = CPS_REG_READ(regaddress);
  799. if ((regval & errbitmask) != 0U) {
  800. debuginfo->wrlvlerror = true;
  801. *errfoundptr = true;
  802. }
  803. regaddress =
  804. lpddr4_addoffset(regaddress, (uint32_t) SLICE_WIDTH);
  805. }
  806. }
  807. /* Check for GateLvlError */
  808. static void lpddr4_checkgatelvlerror(lpddr4_ctlregs * ctlregbase,
  809. lpddr4_debuginfo * debuginfo,
  810. bool * errfoundptr)
  811. {
  812. uint32_t regval;
  813. uint32_t errbitmask = 0U;
  814. uint32_t snum;
  815. volatile uint32_t *regaddress;
  816. regaddress =
  817. (volatile uint32_t
  818. *)(&(ctlregbase->LPDDR4__PHY_GTLVL_STATUS_OBS_0__REG));
  819. /* PHY_GTLVL_STATUS_OBS[6] – gate_level min error
  820. * PHY_GTLVL_STATUS_OBS[7] – gate_level max error
  821. * All the above bit fields should be zero */
  822. errbitmask = GATE_LVL_ERROR_FIELDS;
  823. for (snum = 0U; snum < DSLICE_NUM; snum++) {
  824. regval = CPS_REG_READ(regaddress);
  825. if ((regval & errbitmask) != 0U) {
  826. debuginfo->gatelvlerror = true;
  827. *errfoundptr = true;
  828. }
  829. regaddress =
  830. lpddr4_addoffset(regaddress, (uint32_t) SLICE_WIDTH);
  831. }
  832. }
  833. /* Check for ReadLvlError */
  834. static void lpddr4_checkreadlvlerror(lpddr4_ctlregs * ctlregbase,
  835. lpddr4_debuginfo * debuginfo,
  836. bool * errfoundptr)
  837. {
  838. uint32_t regval;
  839. uint32_t errbitmask = 0U;
  840. uint32_t snum;
  841. volatile uint32_t *regaddress;
  842. regaddress =
  843. (volatile uint32_t
  844. *)(&(ctlregbase->LPDDR4__PHY_RDLVL_STATUS_OBS_0__REG));
  845. /* PHY_RDLVL_STATUS_OBS[23:16] – failed bits : should be zero.
  846. PHY_RDLVL_STATUS_OBS[31:28] – rdlvl_state : should be zero */
  847. errbitmask = READ_LVL_ERROR_FIELDS;
  848. for (snum = 0U; snum < DSLICE_NUM; snum++) {
  849. regval = CPS_REG_READ(regaddress);
  850. if ((regval & errbitmask) != 0U) {
  851. debuginfo->readlvlerror = true;
  852. *errfoundptr = true;
  853. }
  854. regaddress =
  855. lpddr4_addoffset(regaddress, (uint32_t) SLICE_WIDTH);
  856. }
  857. }
  858. /* Check for DqTrainingError */
  859. static void lpddr4_checkdqtrainingerror(lpddr4_ctlregs * ctlregbase,
  860. lpddr4_debuginfo * debuginfo,
  861. bool * errfoundptr)
  862. {
  863. uint32_t regval;
  864. uint32_t errbitmask = 0U;
  865. uint32_t snum;
  866. volatile uint32_t *regaddress;
  867. regaddress =
  868. (volatile uint32_t
  869. *)(&(ctlregbase->LPDDR4__PHY_WDQLVL_STATUS_OBS_0__REG));
  870. /* PHY_WDQLVL_STATUS_OBS[26:18] should all be zero. */
  871. errbitmask = DQ_LVL_STATUS;
  872. for (snum = 0U; snum < DSLICE_NUM; snum++) {
  873. regval = CPS_REG_READ(regaddress);
  874. if ((regval & errbitmask) != 0U) {
  875. debuginfo->dqtrainingerror = true;
  876. *errfoundptr = true;
  877. }
  878. regaddress =
  879. lpddr4_addoffset(regaddress, (uint32_t) SLICE_WIDTH);
  880. }
  881. }
  882. /**
  883. * Internal Function:For checking errors in training/levelling sequence.
  884. * @param[in] pD Driver state info specific to this instance.
  885. * @param[in] debugInfo pointer to debug information.
  886. * @param[out] errFoundPtr pointer to return if error found.
  887. * @return CDN_EOK on success (Interrupt status high).
  888. * @return EINVAL checking or unmasking was not successful.
  889. */
  890. static bool lpddr4_checklvlerrors(const lpddr4_privatedata * pd,
  891. lpddr4_debuginfo * debuginfo, bool errfound)
  892. {
  893. bool localerrfound = errfound;
  894. lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
  895. if (localerrfound == false) {
  896. /* Check for ca training error */
  897. lpddr4_checkcatrainingerror(ctlregbase, debuginfo,
  898. &localerrfound);
  899. }
  900. if (localerrfound == false) {
  901. /* Check for Write leveling error */
  902. lpddr4_checkwrlvlerror(ctlregbase, debuginfo, &localerrfound);
  903. }
  904. if (localerrfound == false) {
  905. /* Check for Gate leveling error */
  906. lpddr4_checkgatelvlerror(ctlregbase, debuginfo, &localerrfound);
  907. }
  908. if (localerrfound == false) {
  909. /* Check for Read leveling error */
  910. lpddr4_checkreadlvlerror(ctlregbase, debuginfo, &localerrfound);
  911. }
  912. if (localerrfound == false) {
  913. /* Check for DQ training error */
  914. lpddr4_checkdqtrainingerror(ctlregbase, debuginfo,
  915. &localerrfound);
  916. }
  917. return localerrfound;
  918. }
  919. static bool lpddr4_seterror(volatile uint32_t * reg, uint32_t errbitmask,
  920. bool * errfoundptr, const uint32_t errorinfobits)
  921. {
  922. uint32_t regval = 0U;
  923. /* Read the respective observation register */
  924. regval = CPS_REG_READ(reg);
  925. /* Compare the error bit values */
  926. if ((regval & errbitmask) != errorinfobits) {
  927. *errfoundptr = true;
  928. }
  929. return *errfoundptr;
  930. }
  931. static void lpddr4_seterrors(lpddr4_ctlregs * ctlregbase,
  932. lpddr4_debuginfo * debuginfo, bool * errfoundptr)
  933. {
  934. uint32_t errbitmask = (BIT_MASK << 0x1U) | (BIT_MASK);
  935. /* Check PLL observation registers for PLL lock errors */
  936. debuginfo->pllerror =
  937. lpddr4_seterror(&(ctlregbase->LPDDR4__PHY_PLL_OBS_0__REG),
  938. errbitmask, errfoundptr, PLL_READY);
  939. if (*errfoundptr == false) {
  940. debuginfo->pllerror =
  941. lpddr4_seterror(&(ctlregbase->LPDDR4__PHY_PLL_OBS_1__REG),
  942. errbitmask, errfoundptr, PLL_READY);
  943. }
  944. /* Check for IO Calibration errors */
  945. if (*errfoundptr == false) {
  946. debuginfo->iocaliberror =
  947. lpddr4_seterror(&
  948. (ctlregbase->
  949. LPDDR4__PHY_CAL_RESULT_OBS_0__REG),
  950. IO_CALIB_DONE, errfoundptr, IO_CALIB_DONE);
  951. }
  952. if (*errfoundptr == false) {
  953. debuginfo->iocaliberror =
  954. lpddr4_seterror(&
  955. (ctlregbase->
  956. LPDDR4__PHY_CAL_RESULT2_OBS_0__REG),
  957. IO_CALIB_DONE, errfoundptr, IO_CALIB_DONE);
  958. }
  959. if (*errfoundptr == false) {
  960. debuginfo->iocaliberror =
  961. lpddr4_seterror(&
  962. (ctlregbase->
  963. LPDDR4__PHY_CAL_RESULT3_OBS_0__REG),
  964. IO_CALIB_FIELD, errfoundptr,
  965. IO_CALIB_STATE);
  966. }
  967. }
  968. static void lpddr4_setphysnapsettings(lpddr4_ctlregs * ctlregbase,
  969. const bool errorfound)
  970. {
  971. uint32_t snum = 0U;
  972. volatile uint32_t *regaddress;
  973. uint32_t regval = 0U;
  974. /* Setting SC_PHY_SNAP_OBS_REGS_x to get a snapshot */
  975. if (errorfound == false) {
  976. regaddress =
  977. (volatile uint32_t
  978. *)(&(ctlregbase->LPDDR4__SC_PHY_SNAP_OBS_REGS_0__REG));
  979. /* Iterate through each PHY Data Slice */
  980. for (snum = 0U; snum < DSLICE_NUM; snum++) {
  981. regval =
  982. CPS_FLD_SET(LPDDR4__SC_PHY_SNAP_OBS_REGS_0__FLD,
  983. CPS_REG_READ(regaddress));
  984. CPS_REG_WRITE(regaddress, regval);
  985. regaddress =
  986. lpddr4_addoffset(regaddress,
  987. (uint32_t) SLICE_WIDTH);
  988. }
  989. }
  990. }
  991. static void lpddr4_setphyadrsnapsettings(lpddr4_ctlregs * ctlregbase,
  992. const bool errorfound)
  993. {
  994. uint32_t snum = 0U;
  995. volatile uint32_t *regaddress;
  996. uint32_t regval = 0U;
  997. /* Setting SC_PHY ADR_SNAP_OBS_REGS_x to get a snapshot */
  998. if (errorfound == false) {
  999. regaddress =
  1000. (volatile uint32_t
  1001. *)(&(ctlregbase->LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__REG));
  1002. /* Iterate through each PHY Address Slice */
  1003. for (snum = 0U; snum < ASLICE_NUM; snum++) {
  1004. regval =
  1005. CPS_FLD_SET(LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__FLD,
  1006. CPS_REG_READ(regaddress));
  1007. CPS_REG_WRITE(regaddress, regval);
  1008. regaddress =
  1009. lpddr4_addoffset(regaddress,
  1010. (uint32_t) SLICE_WIDTH);
  1011. }
  1012. }
  1013. }
  1014. static void lpddr4_setsettings(lpddr4_ctlregs * ctlregbase,
  1015. const bool errorfound)
  1016. {
  1017. /* Calling functions to enable snap shots of OBS registers */
  1018. lpddr4_setphysnapsettings(ctlregbase, errorfound);
  1019. lpddr4_setphyadrsnapsettings(ctlregbase, errorfound);
  1020. }
  1021. static void lpddr4_setrxoffseterror(lpddr4_ctlregs * ctlregbase,
  1022. lpddr4_debuginfo * debuginfo,
  1023. bool * errorfound)
  1024. {
  1025. volatile uint32_t *regaddress;
  1026. uint32_t snum = 0U;
  1027. uint32_t errbitmask = 0U;
  1028. uint32_t regval = 0U;
  1029. /* Check for rxOffsetError */
  1030. if (*errorfound == false) {
  1031. regaddress =
  1032. (volatile uint32_t
  1033. *)(&(ctlregbase->LPDDR4__PHY_RX_CAL_LOCK_OBS_0__REG));
  1034. errbitmask = (RX_CAL_DONE) | (NIBBLE_MASK);
  1035. /* PHY_RX_CAL_LOCK_OBS_x[4] – RX_CAL_DONE : should be high
  1036. phy_rx_cal_lock_obs_x[3:0] – RX_CAL_STATE : should be zero. */
  1037. for (snum = 0U; snum < DSLICE_NUM; snum++) {
  1038. regval =
  1039. CPS_FLD_READ(LPDDR4__PHY_RX_CAL_LOCK_OBS_0__FLD,
  1040. CPS_REG_READ(regaddress));
  1041. if ((regval & errbitmask) != RX_CAL_DONE) {
  1042. debuginfo->rxoffseterror = true;
  1043. *errorfound = true;
  1044. }
  1045. regaddress =
  1046. lpddr4_addoffset(regaddress,
  1047. (uint32_t) SLICE_WIDTH);
  1048. }
  1049. }
  1050. }
  1051. uint32_t lpddr4_getdebuginitinfo(const lpddr4_privatedata * pd,
  1052. lpddr4_debuginfo * debuginfo)
  1053. {
  1054. uint32_t result = 0U;
  1055. bool errorfound = false;
  1056. /* Calling Sanity Function to verify the input variables */
  1057. result = lpddr4_getdebuginitinfosf(pd, debuginfo);
  1058. if (result == (uint32_t) CDN_EOK) {
  1059. lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
  1060. lpddr4_seterrors(ctlregbase, debuginfo, &errorfound);
  1061. /* Function to setup Snap for OBS registers */
  1062. lpddr4_setsettings(ctlregbase, errorfound);
  1063. /* Function to check for Rx offset error */
  1064. lpddr4_setrxoffseterror(ctlregbase, debuginfo, &errorfound);
  1065. /* Function Check various levelling errors */
  1066. errorfound = lpddr4_checklvlerrors(pd, debuginfo, errorfound);
  1067. }
  1068. if (errorfound == true) {
  1069. result = (uint32_t) EPROTO;
  1070. }
  1071. return result;
  1072. }
  1073. static void readpdwakeup(const lpddr4_ctlfspnum * fspnum,
  1074. lpddr4_ctlregs * ctlregbase, uint32_t * cycles)
  1075. {
  1076. /* Read the appropriate register, based on user given frequency. */
  1077. if (*fspnum == LPDDR4_FSP_0) {
  1078. *cycles =
  1079. CPS_FLD_READ(LPDDR4__LPI_PD_WAKEUP_F0__FLD,
  1080. CPS_REG_READ(&
  1081. (ctlregbase->
  1082. LPDDR4__LPI_PD_WAKEUP_F0__REG)));
  1083. } else if (*fspnum == LPDDR4_FSP_1) {
  1084. *cycles =
  1085. CPS_FLD_READ(LPDDR4__LPI_PD_WAKEUP_F1__FLD,
  1086. CPS_REG_READ(&
  1087. (ctlregbase->
  1088. LPDDR4__LPI_PD_WAKEUP_F1__REG)));
  1089. } else {
  1090. /* Default register (sanity function already confirmed the variable value) */
  1091. *cycles =
  1092. CPS_FLD_READ(LPDDR4__LPI_PD_WAKEUP_F2__FLD,
  1093. CPS_REG_READ(&
  1094. (ctlregbase->
  1095. LPDDR4__LPI_PD_WAKEUP_F2__REG)));
  1096. }
  1097. }
  1098. static void readsrshortwakeup(const lpddr4_ctlfspnum * fspnum,
  1099. lpddr4_ctlregs * ctlregbase, uint32_t * cycles)
  1100. {
  1101. /* Read the appropriate register, based on user given frequency. */
  1102. if (*fspnum == LPDDR4_FSP_0) {
  1103. *cycles =
  1104. CPS_FLD_READ(LPDDR4__LPI_SR_SHORT_WAKEUP_F0__FLD,
  1105. CPS_REG_READ(&
  1106. (ctlregbase->
  1107. LPDDR4__LPI_SR_SHORT_WAKEUP_F0__REG)));
  1108. } else if (*fspnum == LPDDR4_FSP_1) {
  1109. *cycles =
  1110. CPS_FLD_READ(LPDDR4__LPI_SR_SHORT_WAKEUP_F1__FLD,
  1111. CPS_REG_READ(&
  1112. (ctlregbase->
  1113. LPDDR4__LPI_SR_SHORT_WAKEUP_F1__REG)));
  1114. } else {
  1115. /* Default register (sanity function already confirmed the variable value) */
  1116. *cycles =
  1117. CPS_FLD_READ(LPDDR4__LPI_SR_SHORT_WAKEUP_F2__FLD,
  1118. CPS_REG_READ(&
  1119. (ctlregbase->
  1120. LPDDR4__LPI_SR_SHORT_WAKEUP_F2__REG)));
  1121. }
  1122. }
  1123. static void readsrlongwakeup(const lpddr4_ctlfspnum * fspnum,
  1124. lpddr4_ctlregs * ctlregbase, uint32_t * cycles)
  1125. {
  1126. /* Read the appropriate register, based on user given frequency. */
  1127. if (*fspnum == LPDDR4_FSP_0) {
  1128. *cycles =
  1129. CPS_FLD_READ(LPDDR4__LPI_SR_LONG_WAKEUP_F0__FLD,
  1130. CPS_REG_READ(&
  1131. (ctlregbase->
  1132. LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG)));
  1133. } else if (*fspnum == LPDDR4_FSP_1) {
  1134. *cycles =
  1135. CPS_FLD_READ(LPDDR4__LPI_SR_LONG_WAKEUP_F1__FLD,
  1136. CPS_REG_READ(&
  1137. (ctlregbase->
  1138. LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG)));
  1139. } else {
  1140. /* Default register (sanity function already confirmed the variable value) */
  1141. *cycles =
  1142. CPS_FLD_READ(LPDDR4__LPI_SR_LONG_WAKEUP_F2__FLD,
  1143. CPS_REG_READ(&
  1144. (ctlregbase->
  1145. LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG)));
  1146. }
  1147. }
  1148. static void readsrlonggatewakeup(const lpddr4_ctlfspnum * fspnum,
  1149. lpddr4_ctlregs * ctlregbase, uint32_t * cycles)
  1150. {
  1151. /* Read the appropriate register, based on user given frequency. */
  1152. if (*fspnum == LPDDR4_FSP_0) {
  1153. *cycles =
  1154. CPS_FLD_READ(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__FLD,
  1155. CPS_REG_READ(&
  1156. (ctlregbase->
  1157. LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__REG)));
  1158. } else if (*fspnum == LPDDR4_FSP_1) {
  1159. *cycles =
  1160. CPS_FLD_READ(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__FLD,
  1161. CPS_REG_READ(&
  1162. (ctlregbase->
  1163. LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__REG)));
  1164. } else {
  1165. /* Default register (sanity function already confirmed the variable value) */
  1166. *cycles =
  1167. CPS_FLD_READ(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__FLD,
  1168. CPS_REG_READ(&
  1169. (ctlregbase->
  1170. LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__REG)));
  1171. }
  1172. }
  1173. static void readsrdpshortwakeup(const lpddr4_ctlfspnum * fspnum,
  1174. lpddr4_ctlregs * ctlregbase, uint32_t * cycles)
  1175. {
  1176. /* Read the appropriate register, based on user given frequency. */
  1177. if (*fspnum == LPDDR4_FSP_0) {
  1178. *cycles =
  1179. CPS_FLD_READ(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__FLD,
  1180. CPS_REG_READ(&
  1181. (ctlregbase->
  1182. LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__REG)));
  1183. } else if (*fspnum == LPDDR4_FSP_1) {
  1184. *cycles =
  1185. CPS_FLD_READ(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__FLD,
  1186. CPS_REG_READ(&
  1187. (ctlregbase->
  1188. LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__REG)));
  1189. } else {
  1190. /* Default register (sanity function already confirmed the variable value) */
  1191. *cycles =
  1192. CPS_FLD_READ(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__FLD,
  1193. CPS_REG_READ(&
  1194. (ctlregbase->
  1195. LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__REG)));
  1196. }
  1197. }
  1198. static void readsrdplongwakeup(const lpddr4_ctlfspnum * fspnum,
  1199. lpddr4_ctlregs * ctlregbase, uint32_t * cycles)
  1200. {
  1201. /* Read the appropriate register, based on user given frequency. */
  1202. if (*fspnum == LPDDR4_FSP_0) {
  1203. *cycles =
  1204. CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__FLD,
  1205. CPS_REG_READ(&
  1206. (ctlregbase->
  1207. LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__REG)));
  1208. } else if (*fspnum == LPDDR4_FSP_1) {
  1209. *cycles =
  1210. CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__FLD,
  1211. CPS_REG_READ(&
  1212. (ctlregbase->
  1213. LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__REG)));
  1214. } else {
  1215. /* Default register (sanity function already confirmed the variable value) */
  1216. *cycles =
  1217. CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__FLD,
  1218. CPS_REG_READ(&
  1219. (ctlregbase->
  1220. LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__REG)));
  1221. }
  1222. }
  1223. static void readsrdplonggatewakeup(const lpddr4_ctlfspnum * fspnum,
  1224. lpddr4_ctlregs * ctlregbase,
  1225. uint32_t * cycles)
  1226. {
  1227. /* Read the appropriate register, based on user given frequency. */
  1228. if (*fspnum == LPDDR4_FSP_0) {
  1229. *cycles =
  1230. CPS_FLD_READ
  1231. (LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__FLD,
  1232. CPS_REG_READ(&
  1233. (ctlregbase->
  1234. LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__REG)));
  1235. } else if (*fspnum == LPDDR4_FSP_1) {
  1236. *cycles =
  1237. CPS_FLD_READ
  1238. (LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__FLD,
  1239. CPS_REG_READ(&
  1240. (ctlregbase->
  1241. LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__REG)));
  1242. } else {
  1243. /* Default register (sanity function already confirmed the variable value) */
  1244. *cycles =
  1245. CPS_FLD_READ
  1246. (LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__FLD,
  1247. CPS_REG_READ(&
  1248. (ctlregbase->
  1249. LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__REG)));
  1250. }
  1251. }
  1252. static void lpddr4_readlpiwakeuptime(lpddr4_ctlregs * ctlregbase,
  1253. const lpddr4_lpiwakeupparam *
  1254. lpiwakeupparam,
  1255. const lpddr4_ctlfspnum * fspnum,
  1256. uint32_t * cycles)
  1257. {
  1258. /* Iterate through each of the Wake up parameter type */
  1259. if (*lpiwakeupparam == LPDDR4_LPI_PD_WAKEUP_FN) {
  1260. /* Calling appropriate function for register read */
  1261. readpdwakeup(fspnum, ctlregbase, cycles);
  1262. } else if (*lpiwakeupparam == LPDDR4_LPI_SR_SHORT_WAKEUP_FN) {
  1263. readsrshortwakeup(fspnum, ctlregbase, cycles);
  1264. } else if (*lpiwakeupparam == LPDDR4_LPI_SR_LONG_WAKEUP_FN) {
  1265. readsrlongwakeup(fspnum, ctlregbase, cycles);
  1266. } else if (*lpiwakeupparam == LPDDR4_LPI_SR_LONG_MCCLK_GATE_WAKEUP_FN) {
  1267. readsrlonggatewakeup(fspnum, ctlregbase, cycles);
  1268. } else if (*lpiwakeupparam == LPDDR4_LPI_SRPD_SHORT_WAKEUP_FN) {
  1269. readsrdpshortwakeup(fspnum, ctlregbase, cycles);
  1270. } else if (*lpiwakeupparam == LPDDR4_LPI_SRPD_LONG_WAKEUP_FN) {
  1271. readsrdplongwakeup(fspnum, ctlregbase, cycles);
  1272. } else {
  1273. /* Default function (sanity function already confirmed the variable value) */
  1274. readsrdplonggatewakeup(fspnum, ctlregbase, cycles);
  1275. }
  1276. }
  1277. uint32_t lpddr4_getlpiwakeuptime(const lpddr4_privatedata * pd,
  1278. const lpddr4_lpiwakeupparam * lpiwakeupparam,
  1279. const lpddr4_ctlfspnum * fspnum,
  1280. uint32_t * cycles)
  1281. {
  1282. uint32_t result = 0U;
  1283. /* Calling Sanity Function to verify the input variables */
  1284. result = lpddr4_getlpiwakeuptimesf(pd, lpiwakeupparam, fspnum, cycles);
  1285. if (result == (uint32_t) CDN_EOK) {
  1286. lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
  1287. lpddr4_readlpiwakeuptime(ctlregbase, lpiwakeupparam, fspnum,
  1288. cycles);
  1289. }
  1290. return result;
  1291. }
  1292. static void writepdwakeup(const lpddr4_ctlfspnum * fspnum,
  1293. lpddr4_ctlregs * ctlregbase, const uint32_t * cycles)
  1294. {
  1295. uint32_t regval = 0U;
  1296. /* Write to appropriate register ,based on user given frequency. */
  1297. if (*fspnum == LPDDR4_FSP_0) {
  1298. regval =
  1299. CPS_FLD_WRITE(LPDDR4__LPI_PD_WAKEUP_F0__FLD,
  1300. CPS_REG_READ(&
  1301. (ctlregbase->
  1302. LPDDR4__LPI_PD_WAKEUP_F0__REG)),
  1303. *cycles);
  1304. CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F0__REG),
  1305. regval);
  1306. } else if (*fspnum == LPDDR4_FSP_1) {
  1307. regval =
  1308. CPS_FLD_WRITE(LPDDR4__LPI_PD_WAKEUP_F1__FLD,
  1309. CPS_REG_READ(&
  1310. (ctlregbase->
  1311. LPDDR4__LPI_PD_WAKEUP_F1__REG)),
  1312. *cycles);
  1313. CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F1__REG),
  1314. regval);
  1315. } else {
  1316. /* Default register (sanity function already confirmed the variable value) */
  1317. regval =
  1318. CPS_FLD_WRITE(LPDDR4__LPI_PD_WAKEUP_F2__FLD,
  1319. CPS_REG_READ(&
  1320. (ctlregbase->
  1321. LPDDR4__LPI_PD_WAKEUP_F2__REG)),
  1322. *cycles);
  1323. CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F2__REG),
  1324. regval);
  1325. }
  1326. }
  1327. static void writesrshortwakeup(const lpddr4_ctlfspnum * fspnum,
  1328. lpddr4_ctlregs * ctlregbase,
  1329. const uint32_t * cycles)
  1330. {
  1331. uint32_t regval = 0U;
  1332. /* Write to appropriate register ,based on user given frequency. */
  1333. if (*fspnum == LPDDR4_FSP_0) {
  1334. regval =
  1335. CPS_FLD_WRITE(LPDDR4__LPI_SR_SHORT_WAKEUP_F0__FLD,
  1336. CPS_REG_READ(&
  1337. (ctlregbase->
  1338. LPDDR4__LPI_SR_SHORT_WAKEUP_F0__REG)),
  1339. *cycles);
  1340. CPS_REG_WRITE(&
  1341. (ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F0__REG),
  1342. regval);
  1343. } else if (*fspnum == LPDDR4_FSP_1) {
  1344. regval =
  1345. CPS_FLD_WRITE(LPDDR4__LPI_SR_SHORT_WAKEUP_F1__FLD,
  1346. CPS_REG_READ(&
  1347. (ctlregbase->
  1348. LPDDR4__LPI_SR_SHORT_WAKEUP_F1__REG)),
  1349. *cycles);
  1350. CPS_REG_WRITE(&
  1351. (ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F1__REG),
  1352. regval);
  1353. } else {
  1354. /* Default register (sanity function already confirmed the variable value) */
  1355. regval =
  1356. CPS_FLD_WRITE(LPDDR4__LPI_SR_SHORT_WAKEUP_F2__FLD,
  1357. CPS_REG_READ(&
  1358. (ctlregbase->
  1359. LPDDR4__LPI_SR_SHORT_WAKEUP_F2__REG)),
  1360. *cycles);
  1361. CPS_REG_WRITE(&
  1362. (ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F2__REG),
  1363. regval);
  1364. }
  1365. }
  1366. static void writesrlongwakeup(const lpddr4_ctlfspnum * fspnum,
  1367. lpddr4_ctlregs * ctlregbase,
  1368. const uint32_t * cycles)
  1369. {
  1370. uint32_t regval = 0U;
  1371. /* Write to appropriate register ,based on user given frequency. */
  1372. if (*fspnum == LPDDR4_FSP_0) {
  1373. regval =
  1374. CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_WAKEUP_F0__FLD,
  1375. CPS_REG_READ(&
  1376. (ctlregbase->
  1377. LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG)),
  1378. *cycles);
  1379. CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG),
  1380. regval);
  1381. } else if (*fspnum == LPDDR4_FSP_1) {
  1382. regval =
  1383. CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_WAKEUP_F1__FLD,
  1384. CPS_REG_READ(&
  1385. (ctlregbase->
  1386. LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG)),
  1387. *cycles);
  1388. CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG),
  1389. regval);
  1390. } else {
  1391. /* Default register (sanity function already confirmed the variable value) */
  1392. regval =
  1393. CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_WAKEUP_F2__FLD,
  1394. CPS_REG_READ(&
  1395. (ctlregbase->
  1396. LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG)),
  1397. *cycles);
  1398. CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG),
  1399. regval);
  1400. }
  1401. }
  1402. static void writesrlonggatewakeup(const lpddr4_ctlfspnum * fspnum,
  1403. lpddr4_ctlregs * ctlregbase,
  1404. const uint32_t * cycles)
  1405. {
  1406. uint32_t regval = 0U;
  1407. /* Write to appropriate register ,based on user given frequency. */
  1408. if (*fspnum == LPDDR4_FSP_0) {
  1409. regval =
  1410. CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__FLD,
  1411. CPS_REG_READ(&
  1412. (ctlregbase->
  1413. LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__REG)),
  1414. *cycles);
  1415. CPS_REG_WRITE(&
  1416. (ctlregbase->
  1417. LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__REG),
  1418. regval);
  1419. } else if (*fspnum == LPDDR4_FSP_1) {
  1420. regval =
  1421. CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__FLD,
  1422. CPS_REG_READ(&
  1423. (ctlregbase->
  1424. LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__REG)),
  1425. *cycles);
  1426. CPS_REG_WRITE(&
  1427. (ctlregbase->
  1428. LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__REG),
  1429. regval);
  1430. } else {
  1431. /* Default register (sanity function already confirmed the variable value) */
  1432. regval =
  1433. CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__FLD,
  1434. CPS_REG_READ(&
  1435. (ctlregbase->
  1436. LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__REG)),
  1437. *cycles);
  1438. CPS_REG_WRITE(&
  1439. (ctlregbase->
  1440. LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__REG),
  1441. regval);
  1442. }
  1443. }
  1444. static void writesrdpshortwakeup(const lpddr4_ctlfspnum * fspnum,
  1445. lpddr4_ctlregs * ctlregbase,
  1446. const uint32_t * cycles)
  1447. {
  1448. uint32_t regval = 0U;
  1449. /* Write to appropriate register ,based on user given frequency. */
  1450. if (*fspnum == LPDDR4_FSP_0) {
  1451. regval =
  1452. CPS_FLD_WRITE(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__FLD,
  1453. CPS_REG_READ(&
  1454. (ctlregbase->
  1455. LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__REG)),
  1456. *cycles);
  1457. CPS_REG_WRITE(&
  1458. (ctlregbase->
  1459. LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__REG), regval);
  1460. } else if (*fspnum == LPDDR4_FSP_1) {
  1461. regval =
  1462. CPS_FLD_WRITE(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__FLD,
  1463. CPS_REG_READ(&
  1464. (ctlregbase->
  1465. LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__REG)),
  1466. *cycles);
  1467. CPS_REG_WRITE(&
  1468. (ctlregbase->
  1469. LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__REG), regval);
  1470. } else {
  1471. /* Default register (sanity function already confirmed the variable value) */
  1472. regval =
  1473. CPS_FLD_WRITE(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__FLD,
  1474. CPS_REG_READ(&
  1475. (ctlregbase->
  1476. LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__REG)),
  1477. *cycles);
  1478. CPS_REG_WRITE(&
  1479. (ctlregbase->
  1480. LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__REG), regval);
  1481. }
  1482. }
  1483. static void writesrdplongwakeup(const lpddr4_ctlfspnum * fspnum,
  1484. lpddr4_ctlregs * ctlregbase,
  1485. const uint32_t * cycles)
  1486. {
  1487. uint32_t regval = 0U;
  1488. /* Write to appropriate register ,based on user given frequency. */
  1489. if (*fspnum == LPDDR4_FSP_0) {
  1490. regval =
  1491. CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__FLD,
  1492. CPS_REG_READ(&
  1493. (ctlregbase->
  1494. LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__REG)),
  1495. *cycles);
  1496. CPS_REG_WRITE(&
  1497. (ctlregbase->
  1498. LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__REG), regval);
  1499. } else if (*fspnum == LPDDR4_FSP_1) {
  1500. regval =
  1501. CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__FLD,
  1502. CPS_REG_READ(&
  1503. (ctlregbase->
  1504. LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__REG)),
  1505. *cycles);
  1506. CPS_REG_WRITE(&
  1507. (ctlregbase->
  1508. LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__REG), regval);
  1509. } else {
  1510. /* Default register (sanity function already confirmed the variable value) */
  1511. regval =
  1512. CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__FLD,
  1513. CPS_REG_READ(&
  1514. (ctlregbase->
  1515. LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__REG)),
  1516. *cycles);
  1517. CPS_REG_WRITE(&
  1518. (ctlregbase->
  1519. LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__REG), regval);
  1520. }
  1521. }
  1522. static void writesrdplonggatewakeup(const lpddr4_ctlfspnum * fspnum,
  1523. lpddr4_ctlregs * ctlregbase,
  1524. const uint32_t * cycles)
  1525. {
  1526. uint32_t regval = 0U;
  1527. /* Write to appropriate register ,based on user given frequency. */
  1528. if (*fspnum == LPDDR4_FSP_0) {
  1529. regval =
  1530. CPS_FLD_WRITE
  1531. (LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__FLD,
  1532. CPS_REG_READ(&
  1533. (ctlregbase->
  1534. LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__REG)),
  1535. *cycles);
  1536. CPS_REG_WRITE(&
  1537. (ctlregbase->
  1538. LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__REG),
  1539. regval);
  1540. } else if (*fspnum == LPDDR4_FSP_1) {
  1541. regval =
  1542. CPS_FLD_WRITE
  1543. (LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__FLD,
  1544. CPS_REG_READ(&
  1545. (ctlregbase->
  1546. LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__REG)),
  1547. *cycles);
  1548. CPS_REG_WRITE(&
  1549. (ctlregbase->
  1550. LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__REG),
  1551. regval);
  1552. } else {
  1553. /* Default register (sanity function already confirmed the variable value) */
  1554. regval =
  1555. CPS_FLD_WRITE
  1556. (LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__FLD,
  1557. CPS_REG_READ(&
  1558. (ctlregbase->
  1559. LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__REG)),
  1560. *cycles);
  1561. CPS_REG_WRITE(&
  1562. (ctlregbase->
  1563. LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__REG),
  1564. regval);
  1565. }
  1566. }
  1567. static void lpddr4_writelpiwakeuptime(lpddr4_ctlregs * ctlregbase,
  1568. const lpddr4_lpiwakeupparam *
  1569. lpiwakeupparam,
  1570. const lpddr4_ctlfspnum * fspnum,
  1571. const uint32_t * cycles)
  1572. {
  1573. /* Iterate through each of the Wake up parameter type */
  1574. if (*lpiwakeupparam == LPDDR4_LPI_PD_WAKEUP_FN) {
  1575. /* Calling appropriate function for register write */
  1576. writepdwakeup(fspnum, ctlregbase, cycles);
  1577. } else if (*lpiwakeupparam == LPDDR4_LPI_SR_SHORT_WAKEUP_FN) {
  1578. writesrshortwakeup(fspnum, ctlregbase, cycles);
  1579. } else if (*lpiwakeupparam == LPDDR4_LPI_SR_LONG_WAKEUP_FN) {
  1580. writesrlongwakeup(fspnum, ctlregbase, cycles);
  1581. } else if (*lpiwakeupparam == LPDDR4_LPI_SR_LONG_MCCLK_GATE_WAKEUP_FN) {
  1582. writesrlonggatewakeup(fspnum, ctlregbase, cycles);
  1583. } else if (*lpiwakeupparam == LPDDR4_LPI_SRPD_SHORT_WAKEUP_FN) {
  1584. writesrdpshortwakeup(fspnum, ctlregbase, cycles);
  1585. } else if (*lpiwakeupparam == LPDDR4_LPI_SRPD_LONG_WAKEUP_FN) {
  1586. writesrdplongwakeup(fspnum, ctlregbase, cycles);
  1587. } else {
  1588. /* Default function (sanity function already confirmed the variable value) */
  1589. writesrdplonggatewakeup(fspnum, ctlregbase, cycles);
  1590. }
  1591. }
  1592. uint32_t lpddr4_setlpiwakeuptime(const lpddr4_privatedata * pd,
  1593. const lpddr4_lpiwakeupparam * lpiwakeupparam,
  1594. const lpddr4_ctlfspnum * fspnum,
  1595. const uint32_t * cycles)
  1596. {
  1597. uint32_t result = 0U;
  1598. /* Calling Sanity Function to verify the input variables */
  1599. result = lpddr4_setlpiwakeuptimesf(pd, lpiwakeupparam, fspnum, cycles);
  1600. if (result == (uint32_t) CDN_EOK) {
  1601. /* Return if the user given value is higher than the field width */
  1602. if (*cycles > NIBBLE_MASK) {
  1603. result = EINVAL;
  1604. }
  1605. }
  1606. if (result == (uint32_t) CDN_EOK) {
  1607. lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
  1608. lpddr4_writelpiwakeuptime(ctlregbase, lpiwakeupparam, fspnum,
  1609. cycles);
  1610. }
  1611. return result;
  1612. }
  1613. uint32_t lpddr4_geteccenable(const lpddr4_privatedata * pd,
  1614. lpddr4_eccenable * eccparam)
  1615. {
  1616. uint32_t result = 0U;
  1617. uint32_t fldval = 0U;
  1618. /* Calling Sanity Function to verify the input variables */
  1619. result = lpddr4_geteccenablesf(pd, eccparam);
  1620. if (result == (uint32_t) CDN_EOK) {
  1621. lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
  1622. /* Reading the ECC_Enable field from the register. */
  1623. fldval =
  1624. CPS_FLD_READ(LPDDR4__ECC_ENABLE__FLD,
  1625. CPS_REG_READ(&
  1626. (ctlregbase->
  1627. LPDDR4__ECC_ENABLE__REG)));
  1628. switch (fldval) {
  1629. case 3:
  1630. *eccparam = LPDDR4_ECC_ERR_DETECT_CORRECT;
  1631. break;
  1632. case 2:
  1633. *eccparam = LPDDR4_ECC_ERR_DETECT;
  1634. break;
  1635. case 1:
  1636. *eccparam = LPDDR4_ECC_ENABLED;
  1637. break;
  1638. default:
  1639. /* Default ECC (Sanity function already confirmed the value to be in expected range.) */
  1640. *eccparam = LPDDR4_ECC_DISABLED;
  1641. break;
  1642. }
  1643. }
  1644. return result;
  1645. }
  1646. uint32_t lpddr4_seteccenable(const lpddr4_privatedata * pd,
  1647. const lpddr4_eccenable * eccparam)
  1648. {
  1649. uint32_t result = 0U;
  1650. uint32_t regval = 0U;
  1651. /* Calling Sanity Function to verify the input variables */
  1652. result = lpddr4_seteccenablesf(pd, eccparam);
  1653. if (result == (uint32_t) CDN_EOK) {
  1654. lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
  1655. /* Updating the ECC_Enable field based on the user given value. */
  1656. regval =
  1657. CPS_FLD_WRITE(LPDDR4__ECC_ENABLE__FLD,
  1658. CPS_REG_READ(&
  1659. (ctlregbase->
  1660. LPDDR4__ECC_ENABLE__REG)),
  1661. *eccparam);
  1662. CPS_REG_WRITE(&(ctlregbase->LPDDR4__ECC_ENABLE__REG), regval);
  1663. }
  1664. return result;
  1665. }
  1666. uint32_t lpddr4_getreducmode(const lpddr4_privatedata * pd,
  1667. lpddr4_reducmode * mode)
  1668. {
  1669. uint32_t result = 0U;
  1670. /* Calling Sanity Function to verify the input variables */
  1671. result = lpddr4_getreducmodesf(pd, mode);
  1672. if (result == (uint32_t) CDN_EOK) {
  1673. lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
  1674. /* Read the value of reduc parameter. */
  1675. if (CPS_FLD_READ
  1676. (LPDDR4__REDUC__FLD,
  1677. CPS_REG_READ(&(ctlregbase->LPDDR4__REDUC__REG))) == 0U) {
  1678. *mode = LPDDR4_REDUC_ON;
  1679. } else {
  1680. *mode = LPDDR4_REDUC_OFF;
  1681. }
  1682. }
  1683. return result;
  1684. }
  1685. uint32_t lpddr4_setreducmode(const lpddr4_privatedata * pd,
  1686. const lpddr4_reducmode * mode)
  1687. {
  1688. uint32_t result = 0U;
  1689. uint32_t regval = 0U;
  1690. /* Calling Sanity Function to verify the input variables */
  1691. result = lpddr4_setreducmodesf(pd, mode);
  1692. if (result == (uint32_t) CDN_EOK) {
  1693. lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
  1694. /* Setting to enable Half data path. */
  1695. regval =
  1696. CPS_FLD_WRITE(LPDDR4__REDUC__FLD,
  1697. CPS_REG_READ(&
  1698. (ctlregbase->
  1699. LPDDR4__REDUC__REG)), *mode);
  1700. CPS_REG_WRITE(&(ctlregbase->LPDDR4__REDUC__REG), regval);
  1701. }
  1702. return result;
  1703. }
  1704. uint32_t lpddr4_getdbireadmode(const lpddr4_privatedata * pd, bool * on_off)
  1705. {
  1706. uint32_t result = 0U;
  1707. /* Calling Sanity Function to verify the input variables */
  1708. result = lpddr4_getdbireadmodesf(pd, on_off);
  1709. if (result == (uint32_t) CDN_EOK) {
  1710. lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
  1711. /* Reading the field value from the register. */
  1712. if (CPS_FLD_READ
  1713. (LPDDR4__RD_DBI_EN__FLD,
  1714. CPS_REG_READ(&(ctlregbase->LPDDR4__RD_DBI_EN__REG))) ==
  1715. 0U) {
  1716. *on_off = false;
  1717. } else {
  1718. *on_off = true;
  1719. }
  1720. }
  1721. return result;
  1722. }
  1723. uint32_t lpddr4_getdbiwritemode(const lpddr4_privatedata * pd, bool * on_off)
  1724. {
  1725. uint32_t result = 0U;
  1726. /* Calling Sanity Function to verify the input variables */
  1727. result = lpddr4_getdbireadmodesf(pd, on_off);
  1728. if (result == (uint32_t) CDN_EOK) {
  1729. lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
  1730. /* Reading the field value from the register. */
  1731. if (CPS_FLD_READ
  1732. (LPDDR4__WR_DBI_EN__FLD,
  1733. CPS_REG_READ(&(ctlregbase->LPDDR4__WR_DBI_EN__REG))) ==
  1734. 0U) {
  1735. *on_off = false;
  1736. } else {
  1737. *on_off = true;
  1738. }
  1739. }
  1740. return result;
  1741. }
  1742. uint32_t lpddr4_setdbimode(const lpddr4_privatedata * pd,
  1743. const lpddr4_dbimode * mode)
  1744. {
  1745. uint32_t result = 0U;
  1746. uint32_t regval = 0U;
  1747. /* Calling Sanity Function to verify the input variables */
  1748. result = lpddr4_setdbimodesf(pd, mode);
  1749. if (result == (uint32_t) CDN_EOK) {
  1750. lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
  1751. /* Updating the appropriate field value based on the user given mode */
  1752. if (*mode == LPDDR4_DBI_RD_ON) {
  1753. regval =
  1754. CPS_FLD_WRITE(LPDDR4__RD_DBI_EN__FLD,
  1755. CPS_REG_READ(&
  1756. (ctlregbase->
  1757. LPDDR4__RD_DBI_EN__REG)),
  1758. 1U);
  1759. } else if (*mode == LPDDR4_DBI_RD_OFF) {
  1760. regval =
  1761. CPS_FLD_WRITE(LPDDR4__RD_DBI_EN__FLD,
  1762. CPS_REG_READ(&
  1763. (ctlregbase->
  1764. LPDDR4__RD_DBI_EN__REG)),
  1765. 0U);
  1766. } else if (*mode == LPDDR4_DBI_WR_ON) {
  1767. regval =
  1768. CPS_FLD_WRITE(LPDDR4__WR_DBI_EN__FLD,
  1769. CPS_REG_READ(&
  1770. (ctlregbase->
  1771. LPDDR4__WR_DBI_EN__REG)),
  1772. 1U);
  1773. } else {
  1774. /* Default field (Sanity function already confirmed the value to be in expected range.) */
  1775. regval =
  1776. CPS_FLD_WRITE(LPDDR4__WR_DBI_EN__FLD,
  1777. CPS_REG_READ(&
  1778. (ctlregbase->
  1779. LPDDR4__WR_DBI_EN__REG)),
  1780. 0U);
  1781. }
  1782. CPS_REG_WRITE(&(ctlregbase->LPDDR4__RD_DBI_EN__REG), regval);
  1783. }
  1784. return result;
  1785. }
  1786. uint32_t lpddr4_getrefreshrate(const lpddr4_privatedata * pd,
  1787. const lpddr4_ctlfspnum * fspnum,
  1788. uint32_t * cycles)
  1789. {
  1790. uint32_t result = 0U;
  1791. /* Calling Sanity Function to verify the input variables */
  1792. result = lpddr4_getrefreshratesf(pd, fspnum, cycles);
  1793. if (result == (uint32_t) CDN_EOK) {
  1794. lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
  1795. /* Selecting the appropriate register for the user requested Frequency */
  1796. switch (*fspnum) {
  1797. case LPDDR4_FSP_2:
  1798. *cycles =
  1799. CPS_FLD_READ(LPDDR4__TREF_F2__FLD,
  1800. CPS_REG_READ(&
  1801. (ctlregbase->
  1802. LPDDR4__TREF_F2__REG)));
  1803. break;
  1804. case LPDDR4_FSP_1:
  1805. *cycles =
  1806. CPS_FLD_READ(LPDDR4__TREF_F1__FLD,
  1807. CPS_REG_READ(&
  1808. (ctlregbase->
  1809. LPDDR4__TREF_F1__REG)));
  1810. break;
  1811. default:
  1812. /* FSP_0 is considered as the default (sanity check already confirmed it as valid FSP) */
  1813. *cycles =
  1814. CPS_FLD_READ(LPDDR4__TREF_F0__FLD,
  1815. CPS_REG_READ(&
  1816. (ctlregbase->
  1817. LPDDR4__TREF_F0__REG)));
  1818. break;
  1819. }
  1820. }
  1821. return result;
  1822. }
  1823. uint32_t lpddr4_setrefreshrate(const lpddr4_privatedata * pd,
  1824. const lpddr4_ctlfspnum * fspnum,
  1825. const uint32_t * cycles)
  1826. {
  1827. uint32_t result = 0U;
  1828. uint32_t regval = 0U;
  1829. /* Calling Sanity Function to verify the input variables */
  1830. result = lpddr4_setrefreshratesf(pd, fspnum, cycles);
  1831. if (result == (uint32_t) CDN_EOK) {
  1832. lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
  1833. /* Selecting the appropriate register for the user requested Frequency */
  1834. switch (*fspnum) {
  1835. case LPDDR4_FSP_2:
  1836. regval =
  1837. CPS_FLD_WRITE(LPDDR4__TREF_F2__FLD,
  1838. CPS_REG_READ(&
  1839. (ctlregbase->
  1840. LPDDR4__TREF_F2__REG)),
  1841. *cycles);
  1842. CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_F2__REG),
  1843. regval);
  1844. break;
  1845. case LPDDR4_FSP_1:
  1846. regval =
  1847. CPS_FLD_WRITE(LPDDR4__TREF_F1__FLD,
  1848. CPS_REG_READ(&
  1849. (ctlregbase->
  1850. LPDDR4__TREF_F1__REG)),
  1851. *cycles);
  1852. CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_F1__REG),
  1853. regval);
  1854. break;
  1855. default:
  1856. /* FSP_0 is considered as the default (sanity check already confirmed it as valid FSP) */
  1857. regval =
  1858. CPS_FLD_WRITE(LPDDR4__TREF_F0__FLD,
  1859. CPS_REG_READ(&
  1860. (ctlregbase->
  1861. LPDDR4__TREF_F0__REG)),
  1862. *cycles);
  1863. CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_F0__REG),
  1864. regval);
  1865. break;
  1866. }
  1867. }
  1868. return result;
  1869. }
  1870. uint32_t lpddr4_refreshperchipselect(const lpddr4_privatedata * pd,
  1871. const uint32_t trefinterval)
  1872. {
  1873. uint32_t result = 0U;
  1874. uint32_t regval = 0U;
  1875. /* Calling Sanity Function to verify the input variables */
  1876. result = lpddr4_refreshperchipselectsf(pd);
  1877. if (result == (uint32_t) CDN_EOK) {
  1878. lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
  1879. /* Setting tref_interval parameter to enable/disable Refresh per chip select. */
  1880. regval =
  1881. CPS_FLD_WRITE(LPDDR4__TREF_INTERVAL__FLD,
  1882. CPS_REG_READ(&
  1883. (ctlregbase->
  1884. LPDDR4__TREF_INTERVAL__REG)),
  1885. trefinterval);
  1886. CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_INTERVAL__REG),
  1887. regval);
  1888. }
  1889. return result;
  1890. }