k3-am654-ddrss.c 30 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Texas Instruments' AM654 DDRSS driver
  4. *
  5. * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
  6. * Lokesh Vutla <lokeshvutla@ti.com>
  7. */
  8. #include <common.h>
  9. #include <clk.h>
  10. #include <dm.h>
  11. #include <log.h>
  12. #include <ram.h>
  13. #include <asm/io.h>
  14. #include <power-domain.h>
  15. #include <asm/arch/sys_proto.h>
  16. #include <dm/device_compat.h>
  17. #include <power/regulator.h>
  18. #include "k3-am654-ddrss.h"
  19. #define LDELAY 10000
  20. /* DDRSS PHY configuration register fixed values */
  21. #define DDRSS_DDRPHY_RANKIDR_RANK0 0
  22. /**
  23. * struct am654_ddrss_desc - Description of ddrss integration.
  24. * @dev: DDRSS device pointer
  25. * @ddrss_ss_cfg: DDRSS wrapper logic region base address
  26. * @ddrss_ctl_cfg: DDRSS controller region base address
  27. * @ddrss_phy_cfg: DDRSS PHY region base address
  28. * @ddrss_clk: DDRSS clock description
  29. * @vtt_supply: VTT Supply regulator
  30. * @ddrss_pwrdmn: DDRSS power domain description
  31. * @params: SDRAM configuration parameters
  32. */
  33. struct am654_ddrss_desc {
  34. struct udevice *dev;
  35. void __iomem *ddrss_ss_cfg;
  36. void __iomem *ddrss_ctl_cfg;
  37. void __iomem *ddrss_phy_cfg;
  38. struct clk ddrss_clk;
  39. struct udevice *vtt_supply;
  40. struct power_domain ddrcfg_pwrdmn;
  41. struct power_domain ddrdata_pwrdmn;
  42. struct ddrss_params params;
  43. };
  44. static inline u32 ddrss_readl(void __iomem *addr, unsigned int offset)
  45. {
  46. return readl(addr + offset);
  47. }
  48. static inline void ddrss_writel(void __iomem *addr, unsigned int offset,
  49. u32 data)
  50. {
  51. debug("%s: addr = 0x%p, value = 0x%x\n", __func__, addr + offset, data);
  52. writel(data, addr + offset);
  53. }
  54. #define ddrss_ctl_writel(off, val) ddrss_writel(ddrss->ddrss_ctl_cfg, off, val)
  55. #define ddrss_ctl_readl(off) ddrss_readl(ddrss->ddrss_ctl_cfg, off)
  56. static inline u32 am654_ddrss_get_type(struct am654_ddrss_desc *ddrss)
  57. {
  58. return ddrss_ctl_readl(DDRSS_DDRCTL_MSTR) & MSTR_DDR_TYPE_MASK;
  59. }
  60. /**
  61. * am654_ddrss_dram_wait_for_init_complete() - Wait for init to complete
  62. *
  63. * After detecting the DDR type this function will pause until the
  64. * initialization is complete. Each DDR type has mask of multiple bits.
  65. * The size of the field depends on the DDR Type. If the initialization
  66. * does not complete and error will be returned and will cause the boot to halt.
  67. *
  68. */
  69. static int am654_ddrss_dram_wait_for_init_complt(struct am654_ddrss_desc *ddrss)
  70. {
  71. u32 val, mask;
  72. val = am654_ddrss_get_type(ddrss);
  73. switch (val) {
  74. case DDR_TYPE_LPDDR4:
  75. case DDR_TYPE_DDR4:
  76. mask = DDR4_STAT_MODE_MASK;
  77. break;
  78. case DDR_TYPE_DDR3:
  79. mask = DDR3_STAT_MODE_MASK;
  80. break;
  81. default:
  82. printf("Unsupported DDR type 0x%x\n", val);
  83. return -EINVAL;
  84. }
  85. if (!wait_on_value(mask, DDR_MODE_NORMAL,
  86. ddrss->ddrss_ctl_cfg + DDRSS_DDRCTL_STAT, LDELAY))
  87. return -ETIMEDOUT;
  88. return 0;
  89. }
  90. /**
  91. * am654_ddrss_ctrl_configuration() - Configure Controller specific registers
  92. * @dev: corresponding ddrss device
  93. */
  94. static void am654_ddrss_ctrl_configuration(struct am654_ddrss_desc *ddrss)
  95. {
  96. struct ddrss_ddrctl_timing_params *tmg = &ddrss->params.ctl_timing;
  97. struct ddrss_ddrctl_reg_params *reg = &ddrss->params.ctl_reg;
  98. struct ddrss_ddrctl_ecc_params *ecc = &ddrss->params.ctl_ecc;
  99. struct ddrss_ddrctl_crc_params *crc = &ddrss->params.ctl_crc;
  100. struct ddrss_ddrctl_map_params *map = &ddrss->params.ctl_map;
  101. u32 val;
  102. debug("%s: DDR controller register configuration started\n", __func__);
  103. ddrss_ctl_writel(DDRSS_DDRCTL_MSTR, reg->ddrctl_mstr);
  104. ddrss_ctl_writel(DDRSS_DDRCTL_RFSHCTL0, reg->ddrctl_rfshctl0);
  105. ddrss_ctl_writel(DDRSS_DDRCTL_RFSHTMG, reg->ddrctl_rfshtmg);
  106. ddrss_ctl_writel(DDRSS_DDRCTL_ECCCFG0, ecc->ddrctl_ecccfg0);
  107. ddrss_ctl_writel(DDRSS_DDRCTL_CRCPARCTL0, crc->ddrctl_crcparctl0);
  108. ddrss_ctl_writel(DDRSS_DDRCTL_CRCPARCTL1, crc->ddrctl_crcparctl1);
  109. ddrss_ctl_writel(DDRSS_DDRCTL_CRCPARCTL2, crc->ddrctl_crcparctl2);
  110. ddrss_ctl_writel(DDRSS_DDRCTL_INIT0, reg->ddrctl_init0);
  111. ddrss_ctl_writel(DDRSS_DDRCTL_INIT1, reg->ddrctl_init1);
  112. ddrss_ctl_writel(DDRSS_DDRCTL_INIT3, reg->ddrctl_init3);
  113. ddrss_ctl_writel(DDRSS_DDRCTL_INIT4, reg->ddrctl_init4);
  114. ddrss_ctl_writel(DDRSS_DDRCTL_INIT5, reg->ddrctl_init5);
  115. ddrss_ctl_writel(DDRSS_DDRCTL_INIT6, reg->ddrctl_init6);
  116. ddrss_ctl_writel(DDRSS_DDRCTL_INIT7, reg->ddrctl_init7);
  117. ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG0, tmg->ddrctl_dramtmg0);
  118. ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG1, tmg->ddrctl_dramtmg1);
  119. ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG2, tmg->ddrctl_dramtmg2);
  120. ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG3, tmg->ddrctl_dramtmg3);
  121. ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG4, tmg->ddrctl_dramtmg4);
  122. ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG5, tmg->ddrctl_dramtmg5);
  123. ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG8, tmg->ddrctl_dramtmg8);
  124. ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG9, tmg->ddrctl_dramtmg9);
  125. ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG11, tmg->ddrctl_dramtmg11);
  126. ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG12, tmg->ddrctl_dramtmg12);
  127. ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG13, tmg->ddrctl_dramtmg13);
  128. ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG14, tmg->ddrctl_dramtmg14);
  129. ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG15, tmg->ddrctl_dramtmg15);
  130. ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG17, tmg->ddrctl_dramtmg17);
  131. ddrss_ctl_writel(DDRSS_DDRCTL_ZQCTL0, reg->ddrctl_zqctl0);
  132. ddrss_ctl_writel(DDRSS_DDRCTL_ZQCTL1, reg->ddrctl_zqctl1);
  133. ddrss_ctl_writel(DDRSS_DDRCTL_DFITMG0, reg->ddrctl_dfitmg0);
  134. ddrss_ctl_writel(DDRSS_DDRCTL_DFITMG1, reg->ddrctl_dfitmg1);
  135. ddrss_ctl_writel(DDRSS_DDRCTL_DFITMG2, reg->ddrctl_dfitmg2);
  136. ddrss_ctl_writel(DDRSS_DDRCTL_DFIMISC, reg->ddrctl_dfimisc);
  137. ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP0, map->ddrctl_addrmap0);
  138. ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP1, map->ddrctl_addrmap1);
  139. ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP2, map->ddrctl_addrmap2);
  140. ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP3, map->ddrctl_addrmap3);
  141. ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP4, map->ddrctl_addrmap4);
  142. ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP5, map->ddrctl_addrmap5);
  143. ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP6, map->ddrctl_addrmap6);
  144. ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP7, map->ddrctl_addrmap7);
  145. ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP8, map->ddrctl_addrmap8);
  146. ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP9, map->ddrctl_addrmap9);
  147. ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP10, map->ddrctl_addrmap10);
  148. ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP11, map->ddrctl_addrmap11);
  149. ddrss_ctl_writel(DDRSS_DDRCTL_ODTCFG, reg->ddrctl_odtcfg);
  150. ddrss_ctl_writel(DDRSS_DDRCTL_ODTMAP, reg->ddrctl_odtmap);
  151. /* Disable refreshes */
  152. val = ddrss_ctl_readl(DDRSS_DDRCTL_RFSHCTL3);
  153. val |= 0x01;
  154. ddrss_ctl_writel(DDRSS_DDRCTL_RFSHCTL3, val);
  155. debug("%s: DDR controller configuration completed\n", __func__);
  156. }
  157. #define ddrss_phy_writel(off, val) \
  158. do { \
  159. ddrss_writel(ddrss->ddrss_phy_cfg, off, val); \
  160. sdelay(10); /* Delay at least 20 clock cycles */ \
  161. } while (0)
  162. #define ddrss_phy_readl(off) \
  163. ({ \
  164. u32 val = ddrss_readl(ddrss->ddrss_phy_cfg, off); \
  165. sdelay(10); /* Delay at least 20 clock cycles */ \
  166. val; \
  167. })
  168. /**
  169. * am654_ddrss_phy_configuration() - Configure PHY specific registers
  170. * @ddrss: corresponding ddrss device
  171. */
  172. static void am654_ddrss_phy_configuration(struct am654_ddrss_desc *ddrss)
  173. {
  174. struct ddrss_ddrphy_ioctl_params *ioctl = &ddrss->params.phy_ioctl;
  175. struct ddrss_ddrphy_timing_params *tmg = &ddrss->params.phy_timing;
  176. struct ddrss_ddrphy_ctrl_params *ctrl = &ddrss->params.phy_ctrl;
  177. struct ddrss_ddrphy_cfg_params *cfg = &ddrss->params.phy_cfg;
  178. struct ddrss_ddrphy_zq_params *zq = &ddrss->params.phy_zq;
  179. debug("%s: DDR phy register configuration started\n", __func__);
  180. ddrss_phy_writel(DDRSS_DDRPHY_PGCR0, cfg->ddrphy_pgcr0);
  181. ddrss_phy_writel(DDRSS_DDRPHY_PGCR1, cfg->ddrphy_pgcr1);
  182. ddrss_phy_writel(DDRSS_DDRPHY_PGCR2, cfg->ddrphy_pgcr2);
  183. ddrss_phy_writel(DDRSS_DDRPHY_PGCR3, cfg->ddrphy_pgcr3);
  184. ddrss_phy_writel(DDRSS_DDRPHY_PGCR6, cfg->ddrphy_pgcr6);
  185. ddrss_phy_writel(DDRSS_DDRPHY_PTR2, tmg->ddrphy_ptr2);
  186. ddrss_phy_writel(DDRSS_DDRPHY_PTR3, tmg->ddrphy_ptr3);
  187. ddrss_phy_writel(DDRSS_DDRPHY_PTR4, tmg->ddrphy_ptr4);
  188. ddrss_phy_writel(DDRSS_DDRPHY_PTR5, tmg->ddrphy_ptr5);
  189. ddrss_phy_writel(DDRSS_DDRPHY_PTR6, tmg->ddrphy_ptr6);
  190. ddrss_phy_writel(DDRSS_DDRPHY_PLLCR0, ctrl->ddrphy_pllcr0);
  191. ddrss_phy_writel(DDRSS_DDRPHY_DXCCR, cfg->ddrphy_dxccr);
  192. ddrss_phy_writel(DDRSS_DDRPHY_DSGCR, cfg->ddrphy_dsgcr);
  193. ddrss_phy_writel(DDRSS_DDRPHY_DCR, cfg->ddrphy_dcr);
  194. ddrss_phy_writel(DDRSS_DDRPHY_DTPR0, tmg->ddrphy_dtpr0);
  195. ddrss_phy_writel(DDRSS_DDRPHY_DTPR1, tmg->ddrphy_dtpr1);
  196. ddrss_phy_writel(DDRSS_DDRPHY_DTPR2, tmg->ddrphy_dtpr2);
  197. ddrss_phy_writel(DDRSS_DDRPHY_DTPR3, tmg->ddrphy_dtpr3);
  198. ddrss_phy_writel(DDRSS_DDRPHY_DTPR4, tmg->ddrphy_dtpr4);
  199. ddrss_phy_writel(DDRSS_DDRPHY_DTPR5, tmg->ddrphy_dtpr5);
  200. ddrss_phy_writel(DDRSS_DDRPHY_DTPR6, tmg->ddrphy_dtpr6);
  201. ddrss_phy_writel(DDRSS_DDRPHY_ZQCR, zq->ddrphy_zqcr);
  202. ddrss_phy_writel(DDRSS_DDRPHY_ZQ0PR0, zq->ddrphy_zq0pr0);
  203. ddrss_phy_writel(DDRSS_DDRPHY_ZQ1PR0, zq->ddrphy_zq1pr0);
  204. ddrss_phy_writel(DDRSS_DDRPHY_MR0, ctrl->ddrphy_mr0);
  205. ddrss_phy_writel(DDRSS_DDRPHY_MR1, ctrl->ddrphy_mr1);
  206. ddrss_phy_writel(DDRSS_DDRPHY_MR2, ctrl->ddrphy_mr2);
  207. ddrss_phy_writel(DDRSS_DDRPHY_MR3, ctrl->ddrphy_mr3);
  208. ddrss_phy_writel(DDRSS_DDRPHY_MR4, ctrl->ddrphy_mr4);
  209. ddrss_phy_writel(DDRSS_DDRPHY_MR5, ctrl->ddrphy_mr5);
  210. ddrss_phy_writel(DDRSS_DDRPHY_MR6, ctrl->ddrphy_mr6);
  211. ddrss_phy_writel(DDRSS_DDRPHY_MR11, ctrl->ddrphy_mr11);
  212. ddrss_phy_writel(DDRSS_DDRPHY_MR12, ctrl->ddrphy_mr12);
  213. ddrss_phy_writel(DDRSS_DDRPHY_MR13, ctrl->ddrphy_mr13);
  214. ddrss_phy_writel(DDRSS_DDRPHY_MR14, ctrl->ddrphy_mr14);
  215. ddrss_phy_writel(DDRSS_DDRPHY_MR22, ctrl->ddrphy_mr22);
  216. ddrss_phy_writel(DDRSS_DDRPHY_VTCR0, ctrl->ddrphy_vtcr0);
  217. ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0PLLCR0, cfg->ddrphy_dx8sl0pllcr0);
  218. ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1PLLCR0, cfg->ddrphy_dx8sl1pllcr0);
  219. ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2PLLCR0, cfg->ddrphy_dx8sl2pllcr0);
  220. ddrss_phy_writel(DDRSS_DDRPHY_DTCR0, ctrl->ddrphy_dtcr0);
  221. ddrss_phy_writel(DDRSS_DDRPHY_DTCR1, ctrl->ddrphy_dtcr1);
  222. ddrss_phy_writel(DDRSS_DDRPHY_ACIOCR0, ioctl->ddrphy_aciocr0);
  223. ddrss_phy_writel(DDRSS_DDRPHY_ACIOCR3, ioctl->ddrphy_aciocr3);
  224. ddrss_phy_writel(DDRSS_DDRPHY_ACIOCR5, ioctl->ddrphy_aciocr5);
  225. ddrss_phy_writel(DDRSS_DDRPHY_IOVCR0, ioctl->ddrphy_iovcr0);
  226. ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR0, cfg->ddrphy_dx4gcr0);
  227. ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR1, cfg->ddrphy_dx4gcr1);
  228. ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR2, cfg->ddrphy_dx4gcr2);
  229. ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR3, cfg->ddrphy_dx4gcr3);
  230. ddrss_phy_writel(DDRSS_DDRPHY_DX0GCR4, cfg->ddrphy_dx0gcr4);
  231. ddrss_phy_writel(DDRSS_DDRPHY_DX1GCR4, cfg->ddrphy_dx1gcr4);
  232. ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR4, cfg->ddrphy_dx2gcr4);
  233. ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR4, cfg->ddrphy_dx3gcr4);
  234. ddrss_phy_writel(DDRSS_DDRPHY_PGCR5, cfg->ddrphy_pgcr5);
  235. ddrss_phy_writel(DDRSS_DDRPHY_DX0GCR5, cfg->ddrphy_dx0gcr5);
  236. ddrss_phy_writel(DDRSS_DDRPHY_DX1GCR5, cfg->ddrphy_dx1gcr5);
  237. ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR5, cfg->ddrphy_dx2gcr5);
  238. ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR5, cfg->ddrphy_dx3gcr5);
  239. ddrss_phy_writel(DDRSS_DDRPHY_RANKIDR, DDRSS_DDRPHY_RANKIDR_RANK0);
  240. ddrss_phy_writel(DDRSS_DDRPHY_DX0GTR0, cfg->ddrphy_dx0gtr0);
  241. ddrss_phy_writel(DDRSS_DDRPHY_DX1GTR0, cfg->ddrphy_dx1gtr0);
  242. ddrss_phy_writel(DDRSS_DDRPHY_DX2GTR0, cfg->ddrphy_dx2gtr0);
  243. ddrss_phy_writel(DDRSS_DDRPHY_DX3GTR0, cfg->ddrphy_dx3gtr0);
  244. ddrss_phy_writel(DDRSS_DDRPHY_ODTCR, cfg->ddrphy_odtcr);
  245. ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0IOCR, cfg->ddrphy_dx8sl0iocr);
  246. ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1IOCR, cfg->ddrphy_dx8sl1iocr);
  247. ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2IOCR, cfg->ddrphy_dx8sl2iocr);
  248. ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DXCTL2, cfg->ddrphy_dx8sl0dxctl2);
  249. ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DXCTL2, cfg->ddrphy_dx8sl1dxctl2);
  250. ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DXCTL2, cfg->ddrphy_dx8sl2dxctl2);
  251. ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DQSCTL, cfg->ddrphy_dx8sl0dqsctl);
  252. ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DQSCTL, cfg->ddrphy_dx8sl1dqsctl);
  253. ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DQSCTL, cfg->ddrphy_dx8sl2dqsctl);
  254. debug("%s: DDR phy register configuration completed\n", __func__);
  255. }
  256. static int __phy_builtin_init_routine(struct am654_ddrss_desc *ddrss,
  257. u32 init_value, u32 sts_mask,
  258. u32 err_mask)
  259. {
  260. int ret;
  261. ddrss_phy_writel(DDRSS_DDRPHY_PIR, init_value | PIR_INIT_MASK);
  262. sdelay(5); /* Delay at least 10 clock cycles */
  263. if (!wait_on_value(sts_mask, sts_mask,
  264. ddrss->ddrss_phy_cfg + DDRSS_DDRPHY_PGSR0, LDELAY))
  265. return -ETIMEDOUT;
  266. sdelay(16); /* Delay at least 32 clock cycles */
  267. ret = ddrss_phy_readl(DDRSS_DDRPHY_PGSR0);
  268. debug("%s: PGSR0 val = 0x%x\n", __func__, ret);
  269. if (ret & err_mask)
  270. return -EINVAL;
  271. return 0;
  272. }
  273. int write_leveling(struct am654_ddrss_desc *ddrss)
  274. {
  275. int ret;
  276. debug("%s: Write leveling started\n", __func__);
  277. ret = __phy_builtin_init_routine(ddrss, PIR_WL_MASK, PGSR0_WLDONE_MASK,
  278. PGSR0_WLERR_MASK);
  279. if (ret) {
  280. if (ret == -ETIMEDOUT)
  281. printf("%s: ERROR: Write leveling timedout\n",
  282. __func__);
  283. else
  284. printf("%s:ERROR: Write leveling failed\n", __func__);
  285. return ret;
  286. }
  287. debug("%s: Write leveling completed\n", __func__);
  288. return 0;
  289. }
  290. int read_dqs_training(struct am654_ddrss_desc *ddrss)
  291. {
  292. int ret;
  293. debug("%s: Read DQS training started\n", __func__);
  294. ret = __phy_builtin_init_routine(ddrss, PIR_QSGATE_MASK,
  295. PGSR0_QSGDONE_MASK, PGSR0_QSGERR_MASK);
  296. if (ret) {
  297. if (ret == -ETIMEDOUT)
  298. printf("%s: ERROR: Read DQS timedout\n", __func__);
  299. else
  300. printf("%s:ERROR: Read DQS Gate training failed\n",
  301. __func__);
  302. return ret;
  303. }
  304. debug("%s: Read DQS training completed\n", __func__);
  305. return 0;
  306. }
  307. int dqs2dq_training(struct am654_ddrss_desc *ddrss)
  308. {
  309. int ret;
  310. debug("%s: DQS2DQ training started\n", __func__);
  311. ret = __phy_builtin_init_routine(ddrss, PIR_DQS2DQ_MASK,
  312. PGSR0_DQS2DQDONE_MASK,
  313. PGSR0_DQS2DQERR_MASK);
  314. if (ret) {
  315. if (ret == -ETIMEDOUT)
  316. printf("%s: ERROR: DQS2DQ training timedout\n",
  317. __func__);
  318. else
  319. printf("%s:ERROR: DQS2DQ training failed\n",
  320. __func__);
  321. return ret;
  322. }
  323. debug("%s: DQS2DQ training completed\n", __func__);
  324. return 0;
  325. }
  326. int write_leveling_adjustment(struct am654_ddrss_desc *ddrss)
  327. {
  328. int ret;
  329. debug("%s: Write Leveling adjustment\n", __func__);
  330. ret = __phy_builtin_init_routine(ddrss, PIR_WLADJ_MASK,
  331. PGSR0_WLADONE_MASK, PGSR0_WLAERR_MASK);
  332. if (ret) {
  333. if (ret == -ETIMEDOUT)
  334. printf("%s:ERROR: Write Leveling adjustment timedout\n",
  335. __func__);
  336. else
  337. printf("%s: ERROR: Write Leveling adjustment failed\n",
  338. __func__);
  339. return ret;
  340. }
  341. return 0;
  342. }
  343. int rest_training(struct am654_ddrss_desc *ddrss)
  344. {
  345. int ret;
  346. debug("%s: Rest of the training started\n", __func__);
  347. debug("%s: Read Deskew adjustment\n", __func__);
  348. ret = __phy_builtin_init_routine(ddrss, PIR_RDDSKW_MASK,
  349. PGSR0_RDDONE_MASK, PGSR0_RDERR_MASK);
  350. if (ret) {
  351. if (ret == -ETIMEDOUT)
  352. printf("%s: ERROR: Read Deskew timedout\n", __func__);
  353. else
  354. printf("%s: ERROR: Read Deskew failed\n", __func__);
  355. return ret;
  356. }
  357. debug("%s: Write Deskew adjustment\n", __func__);
  358. ret = __phy_builtin_init_routine(ddrss, PIR_WRDSKW_MASK,
  359. PGSR0_WDDONE_MASK, PGSR0_WDERR_MASK);
  360. if (ret) {
  361. if (ret == -ETIMEDOUT)
  362. printf("%s: ERROR: Write Deskew timedout\n", __func__);
  363. else
  364. printf("%s: ERROR: Write Deskew failed\n", __func__);
  365. return ret;
  366. }
  367. debug("%s: Read Eye training\n", __func__);
  368. ret = __phy_builtin_init_routine(ddrss, PIR_RDEYE_MASK,
  369. PGSR0_REDONE_MASK, PGSR0_REERR_MASK);
  370. if (ret) {
  371. if (ret == -ETIMEDOUT)
  372. printf("%s: ERROR: Read Eye training timedout\n",
  373. __func__);
  374. else
  375. printf("%s: ERROR: Read Eye training failed\n",
  376. __func__);
  377. return ret;
  378. }
  379. debug("%s: Write Eye training\n", __func__);
  380. ret = __phy_builtin_init_routine(ddrss, PIR_WREYE_MASK,
  381. PGSR0_WEDONE_MASK, PGSR0_WEERR_MASK);
  382. if (ret) {
  383. if (ret == -ETIMEDOUT)
  384. printf("%s: ERROR: Write Eye training timedout\n",
  385. __func__);
  386. else
  387. printf("%s: ERROR: Write Eye training failed\n",
  388. __func__);
  389. return ret;
  390. }
  391. return 0;
  392. }
  393. int VREF_training(struct am654_ddrss_desc *ddrss)
  394. {
  395. int ret;
  396. debug("%s: VREF training\n", __func__);
  397. ret = __phy_builtin_init_routine(ddrss, PIR_VREF_MASK, PGSR0_VDONE_MASK,
  398. PGSR0_VERR_MASK);
  399. if (ret) {
  400. if (ret == -ETIMEDOUT)
  401. printf("%s: ERROR: VREF training timedout\n", __func__);
  402. else
  403. printf("%s: ERROR: VREF training failed\n", __func__);
  404. return ret;
  405. }
  406. return 0;
  407. }
  408. int enable_dqs_pd(struct am654_ddrss_desc *ddrss)
  409. {
  410. u32 val;
  411. val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL0DQSCTL);
  412. val &= ~0xFF;
  413. val |= 0xF7;
  414. ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DQSCTL, val);
  415. val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL1DQSCTL);
  416. val &= ~0xFF;
  417. val |= 0xF7;
  418. ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DQSCTL, val);
  419. val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL2DQSCTL);
  420. val &= ~0xFF;
  421. val |= 0xF7;
  422. ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DQSCTL, val);
  423. sdelay(16);
  424. return 0;
  425. }
  426. int disable_dqs_pd(struct am654_ddrss_desc *ddrss)
  427. {
  428. u32 val;
  429. val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL0DQSCTL);
  430. val &= ~0xFF;
  431. ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DQSCTL, val);
  432. val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL1DQSCTL);
  433. val &= ~0xFF;
  434. ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DQSCTL, val);
  435. val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL2DQSCTL);
  436. val &= ~0xFF;
  437. ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DQSCTL, val);
  438. sdelay(16);
  439. return 0;
  440. }
  441. int cleanup_training(struct am654_ddrss_desc *ddrss)
  442. {
  443. u32 val;
  444. u32 dgsl0, dgsl1, dgsl2, dgsl3, rddly, rd2wr_wr2rd;
  445. ddrss_phy_writel(DDRSS_DDRPHY_RANKIDR, 0x00000000);
  446. dgsl0 = (ddrss_phy_readl(DDRSS_DDRPHY_DX0GTR0) & 0x1F) >> 2;
  447. dgsl1 = (ddrss_phy_readl(DDRSS_DDRPHY_DX1GTR0) & 0x1F) >> 2;
  448. dgsl2 = (ddrss_phy_readl(DDRSS_DDRPHY_DX2GTR0) & 0x1F) >> 2;
  449. dgsl3 = (ddrss_phy_readl(DDRSS_DDRPHY_DX3GTR0) & 0x1F) >> 2;
  450. rddly = dgsl0;
  451. if (dgsl1 < rddly)
  452. rddly = dgsl1;
  453. if (dgsl2 < rddly)
  454. rddly = dgsl2;
  455. if (dgsl3 < rddly)
  456. rddly = dgsl3;
  457. rddly += 5;
  458. /* Update rddly based on dgsl values */
  459. val = (ddrss_phy_readl(DDRSS_DDRPHY_DX0GCR0) & ~0xF00000);
  460. val |= (rddly << 20);
  461. ddrss_phy_writel(DDRSS_DDRPHY_DX0GCR0, val);
  462. val = (ddrss_phy_readl(DDRSS_DDRPHY_DX1GCR0) & ~0xF00000);
  463. val |= (rddly << 20);
  464. ddrss_phy_writel(DDRSS_DDRPHY_DX1GCR0, val);
  465. val = (ddrss_phy_readl(DDRSS_DDRPHY_DX2GCR0) & ~0xF00000);
  466. val |= (rddly << 20);
  467. ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR0, val);
  468. val = (ddrss_phy_readl(DDRSS_DDRPHY_DX3GCR0) & ~0xF00000);
  469. val |= (rddly << 20);
  470. ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR0, val);
  471. /*
  472. * Add system latency derived from training back into rd2wr and wr2rd
  473. * rd2wr = RL + BL/2 + 1 + WR_PREAMBLE - WL + max(DXnGTR0.DGSL) / 2
  474. * wr2rd = CWL + PL + BL/2 + tWTR_L + max(DXnGTR0.DGSL) / 2
  475. */
  476. /* Select rank 0 */
  477. ddrss_phy_writel(DDRSS_DDRPHY_RANKIDR, 0x00000000);
  478. dgsl0 = (ddrss_phy_readl(DDRSS_DDRPHY_DX0GTR0) & 0x1F);
  479. dgsl1 = (ddrss_phy_readl(DDRSS_DDRPHY_DX1GTR0) & 0x1F);
  480. dgsl2 = (ddrss_phy_readl(DDRSS_DDRPHY_DX2GTR0) & 0x1F);
  481. dgsl3 = (ddrss_phy_readl(DDRSS_DDRPHY_DX3GTR0) & 0x1F);
  482. /* Find maximum value across all bytes */
  483. rd2wr_wr2rd = dgsl0;
  484. if (dgsl1 > rd2wr_wr2rd)
  485. rd2wr_wr2rd = dgsl1;
  486. if (dgsl2 > rd2wr_wr2rd)
  487. rd2wr_wr2rd = dgsl2;
  488. if (dgsl3 > rd2wr_wr2rd)
  489. rd2wr_wr2rd = dgsl3;
  490. rd2wr_wr2rd >>= 1;
  491. /* Now add in adjustment to DRAMTMG2 bit fields for rd2wr and wr2rd */
  492. /* Clear VSWCTL.sw_done */
  493. ddrss_ctl_writel(DDRSS_DDRCTL_SWCTL,
  494. ddrss_ctl_readl(DDRSS_DDRCTL_SWCTL) & ~0x1);
  495. /* Adjust rd2wr */
  496. ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG2,
  497. ddrss_ctl_readl(DDRSS_DDRCTL_DRAMTMG2) +
  498. (rd2wr_wr2rd << 8));
  499. /* Adjust wr2rd */
  500. ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG2,
  501. ddrss_ctl_readl(DDRSS_DDRCTL_DRAMTMG2) +
  502. rd2wr_wr2rd);
  503. /* Set VSWCTL.sw_done */
  504. ddrss_ctl_writel(DDRSS_DDRCTL_SWCTL,
  505. ddrss_ctl_readl(DDRSS_DDRCTL_SWCTL) | 0x1);
  506. /* Wait until settings are applied */
  507. while (!(ddrss_ctl_readl(DDRSS_DDRCTL_SWSTAT) & 0x1)) {
  508. /* Do nothing */
  509. };
  510. debug("%s: Rest of the training completed\n", __func__);
  511. return 0;
  512. }
  513. /**
  514. * am654_ddrss_init() - Initialization sequence for enabling the SDRAM
  515. * device attached to ddrss.
  516. * @dev: corresponding ddrss device
  517. *
  518. * Does all the initialization sequence that is required to get attached
  519. * ddr in a working state. After this point, ddr should be accessible.
  520. * Return: 0 if all went ok, else corresponding error message.
  521. */
  522. static int am654_ddrss_init(struct am654_ddrss_desc *ddrss)
  523. {
  524. int ret;
  525. u32 val;
  526. struct ddrss_ss_reg_params *reg = &ddrss->params.ss_reg;
  527. debug("Starting DDR initialization...\n");
  528. debug("%s(ddrss=%p)\n", __func__, ddrss);
  529. ddrss_writel(ddrss->ddrss_ss_cfg, DDRSS_V2H_CTL_REG,
  530. reg->ddrss_v2h_ctl_reg);
  531. am654_ddrss_ctrl_configuration(ddrss);
  532. /* Release the reset to the controller */
  533. clrbits_le32(ddrss->ddrss_ss_cfg + DDRSS_SS_CTL_REG,
  534. SS_CTL_REG_CTL_ARST_MASK);
  535. am654_ddrss_phy_configuration(ddrss);
  536. debug("Starting DDR training...\n");
  537. ret = __phy_builtin_init_routine(ddrss, PIR_PHY_INIT, 0x1, 0);
  538. if (ret) {
  539. dev_err(ddrss->dev, "PHY initialization failed %d\n", ret);
  540. return ret;
  541. }
  542. ret = __phy_builtin_init_routine(ddrss, PIR_DRAM_INIT,
  543. PGSR0_DRAM_INIT_MASK, 0);
  544. if (ret) {
  545. dev_err(ddrss->dev, "DRAM initialization failed %d\n", ret);
  546. return ret;
  547. }
  548. ret = am654_ddrss_dram_wait_for_init_complt(ddrss);
  549. if (ret) {
  550. printf("%s: ERROR: DRAM Wait for init complete timedout\n",
  551. __func__);
  552. return ret;
  553. }
  554. val = am654_ddrss_get_type(ddrss);
  555. switch (val) {
  556. case DDR_TYPE_LPDDR4:
  557. ret = __phy_builtin_init_routine(ddrss, PIR_DRAM_INIT,
  558. PGSR0_DRAM_INIT_MASK, 0);
  559. if (ret) {
  560. dev_err(ddrss->dev, "DRAM initialization failed %d\n",
  561. ret);
  562. return ret;
  563. }
  564. /* must perform DRAM_INIT twice for LPDDR4 */
  565. ret = __phy_builtin_init_routine(ddrss, PIR_DRAM_INIT,
  566. PGSR0_DRAM_INIT_MASK, 0);
  567. if (ret) {
  568. dev_err(ddrss->dev, "DRAM initialization failed %d\n",
  569. ret);
  570. return ret;
  571. }
  572. ret = am654_ddrss_dram_wait_for_init_complt(ddrss);
  573. if (ret) {
  574. printf("%s: ERROR: DRAM Wait for init complete timedout\n",
  575. __func__);
  576. return ret;
  577. }
  578. ret = write_leveling(ddrss);
  579. if (ret)
  580. return ret;
  581. ret = enable_dqs_pd(ddrss);
  582. if (ret)
  583. return ret;
  584. ret = read_dqs_training(ddrss);
  585. if (ret)
  586. return ret;
  587. ret = disable_dqs_pd(ddrss);
  588. if (ret)
  589. return ret;
  590. ret = dqs2dq_training(ddrss);
  591. if (ret)
  592. return ret;
  593. ret = write_leveling_adjustment(ddrss);
  594. if (ret)
  595. return ret;
  596. ret = rest_training(ddrss);
  597. if (ret)
  598. return ret;
  599. ret = VREF_training(ddrss);
  600. if (ret)
  601. return ret;
  602. debug("LPDDR4 training complete\n");
  603. break;
  604. case DDR_TYPE_DDR4:
  605. debug("Starting DDR4 training\n");
  606. ret = __phy_builtin_init_routine(ddrss, PIR_DRAM_INIT,
  607. PGSR0_DRAM_INIT_MASK, 0);
  608. if (ret) {
  609. dev_err(ddrss->dev, "DRAM initialization failed %d\n",
  610. ret);
  611. return ret;
  612. }
  613. ret = am654_ddrss_dram_wait_for_init_complt(ddrss);
  614. if (ret) {
  615. printf("%s: ERROR: DRAM Wait for init complete timedout\n",
  616. __func__);
  617. return ret;
  618. }
  619. ret = write_leveling(ddrss);
  620. if (ret)
  621. return ret;
  622. ret = read_dqs_training(ddrss);
  623. if (ret)
  624. return ret;
  625. ret = write_leveling_adjustment(ddrss);
  626. if (ret)
  627. return ret;
  628. ret = rest_training(ddrss);
  629. if (ret)
  630. return ret;
  631. ret = VREF_training(ddrss);
  632. if (ret)
  633. return ret;
  634. debug("DDR4 training complete\n");
  635. break;
  636. case DDR_TYPE_DDR3:
  637. debug("Starting DDR3 training\n");
  638. ret = __phy_builtin_init_routine(ddrss, PIR_DRAM_INIT,
  639. PGSR0_DRAM_INIT_MASK, 0);
  640. if (ret) {
  641. dev_err(ddrss->dev, "DRAM initialization failed %d\n",
  642. ret);
  643. return ret;
  644. }
  645. ret = am654_ddrss_dram_wait_for_init_complt(ddrss);
  646. if (ret) {
  647. printf("%s: ERROR: DRAM Wait for init complete timedout\n",
  648. __func__);
  649. return ret;
  650. }
  651. ret = write_leveling(ddrss);
  652. if (ret)
  653. return ret;
  654. ret = enable_dqs_pd(ddrss);
  655. if (ret)
  656. return ret;
  657. ret = read_dqs_training(ddrss);
  658. if (ret)
  659. return ret;
  660. ret = disable_dqs_pd(ddrss);
  661. if (ret)
  662. return ret;
  663. ret = write_leveling_adjustment(ddrss);
  664. if (ret)
  665. return ret;
  666. ret = rest_training(ddrss);
  667. if (ret)
  668. return ret;
  669. debug("DDR3 training complete\n");
  670. break;
  671. default:
  672. printf("%s: ERROR: Unsupported DDR type\n", __func__);
  673. return -EINVAL;
  674. }
  675. ret = cleanup_training(ddrss);
  676. if (ret)
  677. return ret;
  678. /* Enabling refreshes after training is done */
  679. ddrss_ctl_writel(DDRSS_DDRCTL_RFSHCTL3,
  680. ddrss_ctl_readl(DDRSS_DDRCTL_RFSHCTL3) & ~0x1);
  681. /* Disable PUBMODE after training is done */
  682. ddrss_phy_writel(DDRSS_DDRPHY_PGCR1,
  683. ddrss_phy_readl(DDRSS_DDRPHY_PGCR1) & ~0x40);
  684. debug("Completed DDR training\n");
  685. return 0;
  686. }
  687. /**
  688. * am654_ddrss_power_on() - Enable power and clocks for ddrss
  689. * @dev: corresponding ddrss device
  690. *
  691. * Tries to enable all the corresponding clocks to the ddrss and sets it
  692. * to the right frequency and then power on the ddrss.
  693. * Return: 0 if all went ok, else corresponding error message.
  694. */
  695. static int am654_ddrss_power_on(struct am654_ddrss_desc *ddrss)
  696. {
  697. int ret;
  698. debug("%s(ddrss=%p)\n", __func__, ddrss);
  699. ret = clk_enable(&ddrss->ddrss_clk);
  700. if (ret) {
  701. dev_err(ddrss->dev, "clk_enable() failed: %d\n", ret);
  702. return ret;
  703. }
  704. ret = power_domain_on(&ddrss->ddrcfg_pwrdmn);
  705. if (ret) {
  706. dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret);
  707. return ret;
  708. }
  709. ret = power_domain_on(&ddrss->ddrdata_pwrdmn);
  710. if (ret) {
  711. dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret);
  712. return ret;
  713. }
  714. /* VTT enable */
  715. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  716. device_get_supply_regulator(ddrss->dev, "vtt-supply",
  717. &ddrss->vtt_supply);
  718. ret = regulator_set_value(ddrss->vtt_supply, 3300000);
  719. if (ret)
  720. return ret;
  721. debug("VTT regulator enabled\n");
  722. #endif
  723. return 0;
  724. }
  725. /**
  726. * am654_ddrss_ofdata_to_priv() - generate private data from device tree
  727. * @dev: corresponding ddrss device
  728. *
  729. * Return: 0 if all went ok, else corresponding error message.
  730. */
  731. static int am654_ddrss_ofdata_to_priv(struct udevice *dev)
  732. {
  733. struct am654_ddrss_desc *ddrss = dev_get_priv(dev);
  734. phys_addr_t reg;
  735. int ret;
  736. debug("%s(dev=%p)\n", __func__, dev);
  737. ret = clk_get_by_index(dev, 0, &ddrss->ddrss_clk);
  738. if (ret) {
  739. dev_err(dev, "clk_get failed: %d\n", ret);
  740. return ret;
  741. }
  742. ret = power_domain_get_by_index(dev, &ddrss->ddrcfg_pwrdmn, 0);
  743. if (ret) {
  744. dev_err(dev, "power_domain_get() failed: %d\n", ret);
  745. return ret;
  746. }
  747. ret = power_domain_get_by_index(dev, &ddrss->ddrdata_pwrdmn, 1);
  748. if (ret) {
  749. dev_err(dev, "power_domain_get() failed: %d\n", ret);
  750. return ret;
  751. }
  752. reg = devfdt_get_addr_name(dev, "ss");
  753. if (reg == FDT_ADDR_T_NONE) {
  754. dev_err(dev, "No reg property for DDRSS wrapper logic\n");
  755. return -EINVAL;
  756. }
  757. ddrss->ddrss_ss_cfg = (void *)reg;
  758. reg = devfdt_get_addr_name(dev, "ctl");
  759. if (reg == FDT_ADDR_T_NONE) {
  760. dev_err(dev, "No reg property for Controller region\n");
  761. return -EINVAL;
  762. }
  763. ddrss->ddrss_ctl_cfg = (void *)reg;
  764. reg = devfdt_get_addr_name(dev, "phy");
  765. if (reg == FDT_ADDR_T_NONE) {
  766. dev_err(dev, "No reg property for PHY region\n");
  767. return -EINVAL;
  768. }
  769. ddrss->ddrss_phy_cfg = (void *)reg;
  770. ret = dev_read_u32_array(dev, "ti,ss-reg",
  771. (u32 *)&ddrss->params.ss_reg,
  772. sizeof(ddrss->params.ss_reg) / sizeof(u32));
  773. if (ret) {
  774. dev_err(dev, "Cannot read ti,ss-reg params\n");
  775. return ret;
  776. }
  777. ret = dev_read_u32_array(dev, "ti,ctl-reg",
  778. (u32 *)&ddrss->params.ctl_reg,
  779. sizeof(ddrss->params.ctl_reg) / sizeof(u32));
  780. if (ret) {
  781. dev_err(dev, "Cannot read ti,ctl-reg params\n");
  782. return ret;
  783. }
  784. ret = dev_read_u32_array(dev, "ti,ctl-crc",
  785. (u32 *)&ddrss->params.ctl_crc,
  786. sizeof(ddrss->params.ctl_crc) / sizeof(u32));
  787. if (ret) {
  788. dev_err(dev, "Cannot read ti,ctl-crc params\n");
  789. return ret;
  790. }
  791. ret = dev_read_u32_array(dev, "ti,ctl-ecc",
  792. (u32 *)&ddrss->params.ctl_ecc,
  793. sizeof(ddrss->params.ctl_ecc) / sizeof(u32));
  794. if (ret) {
  795. dev_err(dev, "Cannot read ti,ctl-ecc params\n");
  796. return ret;
  797. }
  798. ret = dev_read_u32_array(dev, "ti,ctl-map",
  799. (u32 *)&ddrss->params.ctl_map,
  800. sizeof(ddrss->params.ctl_map) / sizeof(u32));
  801. if (ret) {
  802. dev_err(dev, "Cannot read ti,ctl-map params\n");
  803. return ret;
  804. }
  805. ret = dev_read_u32_array(dev, "ti,ctl-pwr",
  806. (u32 *)&ddrss->params.ctl_pwr,
  807. sizeof(ddrss->params.ctl_pwr) / sizeof(u32));
  808. if (ret) {
  809. dev_err(dev, "Cannot read ti,ctl-pwr params\n");
  810. return ret;
  811. }
  812. ret = dev_read_u32_array(dev, "ti,ctl-timing",
  813. (u32 *)&ddrss->params.ctl_timing,
  814. sizeof(ddrss->params.ctl_timing) /
  815. sizeof(u32));
  816. if (ret) {
  817. dev_err(dev, "Cannot read ti,ctl-timing params\n");
  818. return ret;
  819. }
  820. ret = dev_read_u32_array(dev, "ti,phy-cfg",
  821. (u32 *)&ddrss->params.phy_cfg,
  822. sizeof(ddrss->params.phy_cfg) / sizeof(u32));
  823. if (ret) {
  824. dev_err(dev, "Cannot read ti,phy-cfg params\n");
  825. return ret;
  826. }
  827. ret = dev_read_u32_array(dev, "ti,phy-ctl",
  828. (u32 *)&ddrss->params.phy_ctrl,
  829. sizeof(ddrss->params.phy_ctrl) / sizeof(u32));
  830. if (ret) {
  831. dev_err(dev, "Cannot read ti,phy-ctl params\n");
  832. return ret;
  833. }
  834. ret = dev_read_u32_array(dev, "ti,phy-ioctl",
  835. (u32 *)&ddrss->params.phy_ioctl,
  836. sizeof(ddrss->params.phy_ioctl) / sizeof(u32));
  837. if (ret) {
  838. dev_err(dev, "Cannot read ti,phy-ioctl params\n");
  839. return ret;
  840. }
  841. ret = dev_read_u32_array(dev, "ti,phy-timing",
  842. (u32 *)&ddrss->params.phy_timing,
  843. sizeof(ddrss->params.phy_timing) /
  844. sizeof(u32));
  845. if (ret) {
  846. dev_err(dev, "Cannot read ti,phy-timing params\n");
  847. return ret;
  848. }
  849. ret = dev_read_u32_array(dev, "ti,phy-zq", (u32 *)&ddrss->params.phy_zq,
  850. sizeof(ddrss->params.phy_zq) / sizeof(u32));
  851. if (ret) {
  852. dev_err(dev, "Cannot read ti,phy-zq params\n");
  853. return ret;
  854. }
  855. return ret;
  856. }
  857. /**
  858. * am654_ddrss_probe() - Basic probe
  859. * @dev: corresponding ddrss device
  860. *
  861. * Return: 0 if all went ok, else corresponding error message
  862. */
  863. static int am654_ddrss_probe(struct udevice *dev)
  864. {
  865. struct am654_ddrss_desc *ddrss = dev_get_priv(dev);
  866. int ret;
  867. debug("%s(dev=%p)\n", __func__, dev);
  868. ret = am654_ddrss_ofdata_to_priv(dev);
  869. if (ret)
  870. return ret;
  871. ddrss->dev = dev;
  872. ret = am654_ddrss_power_on(ddrss);
  873. if (ret)
  874. return ret;
  875. ret = am654_ddrss_init(ddrss);
  876. return ret;
  877. }
  878. static int am654_ddrss_get_info(struct udevice *dev, struct ram_info *info)
  879. {
  880. return 0;
  881. }
  882. static struct ram_ops am654_ddrss_ops = {
  883. .get_info = am654_ddrss_get_info,
  884. };
  885. static const struct udevice_id am654_ddrss_ids[] = {
  886. { .compatible = "ti,am654-ddrss" },
  887. { }
  888. };
  889. U_BOOT_DRIVER(am654_ddrss) = {
  890. .name = "am654_ddrss",
  891. .id = UCLASS_RAM,
  892. .of_match = am654_ddrss_ids,
  893. .ops = &am654_ddrss_ops,
  894. .probe = am654_ddrss_probe,
  895. .priv_auto_alloc_size = sizeof(struct am654_ddrss_desc),
  896. };