uec_phy.h 6.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2005, 2011 Freescale Semiconductor, Inc.
  4. *
  5. * Author: Shlomi Gridish <gridish@freescale.com>
  6. *
  7. * Description: UCC ethernet driver -- PHY handling
  8. * Driver for UEC on QE
  9. * Based on 8260_io/fcc_enet.c
  10. */
  11. #ifndef __UEC_PHY_H__
  12. #define __UEC_PHY_H__
  13. #include <linux/bitops.h>
  14. #define MII_end ((u32)-2)
  15. #define MII_read ((u32)-1)
  16. #define MIIMIND_BUSY 0x00000001
  17. #define MIIMIND_NOTVALID 0x00000004
  18. #define UGETH_AN_TIMEOUT 2000
  19. /* Cicada Extended Control Register 1 */
  20. #define MII_CIS8201_EXT_CON1 0x17
  21. #define MII_CIS8201_EXTCON1_INIT 0x0000
  22. /* Cicada Interrupt Mask Register */
  23. #define MII_CIS8201_IMASK 0x19
  24. #define MII_CIS8201_IMASK_IEN 0x8000
  25. #define MII_CIS8201_IMASK_SPEED 0x4000
  26. #define MII_CIS8201_IMASK_LINK 0x2000
  27. #define MII_CIS8201_IMASK_DUPLEX 0x1000
  28. #define MII_CIS8201_IMASK_MASK 0xf000
  29. /* Cicada Interrupt Status Register */
  30. #define MII_CIS8201_ISTAT 0x1a
  31. #define MII_CIS8201_ISTAT_STATUS 0x8000
  32. #define MII_CIS8201_ISTAT_SPEED 0x4000
  33. #define MII_CIS8201_ISTAT_LINK 0x2000
  34. #define MII_CIS8201_ISTAT_DUPLEX 0x1000
  35. /* Cicada Auxiliary Control/Status Register */
  36. #define MII_CIS8201_AUX_CONSTAT 0x1c
  37. #define MII_CIS8201_AUXCONSTAT_INIT 0x0004
  38. #define MII_CIS8201_AUXCONSTAT_DUPLEX 0x0020
  39. #define MII_CIS8201_AUXCONSTAT_SPEED 0x0018
  40. #define MII_CIS8201_AUXCONSTAT_GBIT 0x0010
  41. #define MII_CIS8201_AUXCONSTAT_100 0x0008
  42. /* 88E1011 PHY Status Register */
  43. #define MII_M1011_PHY_SPEC_STATUS 0x11
  44. #define MII_M1011_PHY_SPEC_STATUS_1000 0x8000
  45. #define MII_M1011_PHY_SPEC_STATUS_100 0x4000
  46. #define MII_M1011_PHY_SPEC_STATUS_SPD_MASK 0xc000
  47. #define MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX 0x2000
  48. #define MII_M1011_PHY_SPEC_STATUS_RESOLVED 0x0800
  49. #define MII_M1011_PHY_SPEC_STATUS_LINK 0x0400
  50. #define MII_M1011_IEVENT 0x13
  51. #define MII_M1011_IEVENT_CLEAR 0x0000
  52. #define MII_M1011_IMASK 0x12
  53. #define MII_M1011_IMASK_INIT 0x6400
  54. #define MII_M1011_IMASK_CLEAR 0x0000
  55. /* 88E1111 PHY Register */
  56. #define MII_M1111_PHY_EXT_CR 0x14
  57. #define MII_M1111_RX_DELAY 0x80
  58. #define MII_M1111_TX_DELAY 0x2
  59. #define MII_M1111_PHY_EXT_SR 0x1b
  60. #define MII_M1111_HWCFG_MODE_MASK 0xf
  61. #define MII_M1111_HWCFG_MODE_RGMII 0xb
  62. #define MII_DM9161_SCR 0x10
  63. #define MII_DM9161_SCR_INIT 0x0610
  64. #define MII_DM9161_SCR_RMII_INIT 0x0710
  65. /* DM9161 Specified Configuration and Status Register */
  66. #define MII_DM9161_SCSR 0x11
  67. #define MII_DM9161_SCSR_100F 0x8000
  68. #define MII_DM9161_SCSR_100H 0x4000
  69. #define MII_DM9161_SCSR_10F 0x2000
  70. #define MII_DM9161_SCSR_10H 0x1000
  71. /* DM9161 Interrupt Register */
  72. #define MII_DM9161_INTR 0x15
  73. #define MII_DM9161_INTR_PEND 0x8000
  74. #define MII_DM9161_INTR_DPLX_MASK 0x0800
  75. #define MII_DM9161_INTR_SPD_MASK 0x0400
  76. #define MII_DM9161_INTR_LINK_MASK 0x0200
  77. #define MII_DM9161_INTR_MASK 0x0100
  78. #define MII_DM9161_INTR_DPLX_CHANGE 0x0010
  79. #define MII_DM9161_INTR_SPD_CHANGE 0x0008
  80. #define MII_DM9161_INTR_LINK_CHANGE 0x0004
  81. #define MII_DM9161_INTR_INIT 0x0000
  82. #define MII_DM9161_INTR_STOP \
  83. (MII_DM9161_INTR_DPLX_MASK | MII_DM9161_INTR_SPD_MASK | \
  84. MII_DM9161_INTR_LINK_MASK | MII_DM9161_INTR_MASK)
  85. /* DM9161 10BT Configuration/Status */
  86. #define MII_DM9161_10BTCSR 0x12
  87. #define MII_DM9161_10BTCSR_INIT 0x7800
  88. #define MII_BASIC_FEATURES (SUPPORTED_10baseT_Half | \
  89. SUPPORTED_10baseT_Full | \
  90. SUPPORTED_100baseT_Half | \
  91. SUPPORTED_100baseT_Full | \
  92. SUPPORTED_Autoneg | \
  93. SUPPORTED_TP | \
  94. SUPPORTED_MII)
  95. #define MII_GBIT_FEATURES (MII_BASIC_FEATURES | \
  96. SUPPORTED_1000baseT_Half | \
  97. SUPPORTED_1000baseT_Full)
  98. #define MII_READ_COMMAND 0x00000001
  99. #define MII_INTERRUPT_DISABLED 0x0
  100. #define MII_INTERRUPT_ENABLED 0x1
  101. #define SPEED_10 10
  102. #define SPEED_100 100
  103. #define SPEED_1000 1000
  104. /* Duplex, half or full. */
  105. #define DUPLEX_HALF 0x00
  106. #define DUPLEX_FULL 0x01
  107. /* Taken from mii_if_info and sungem_phy.h */
  108. struct uec_mii_info {
  109. /* Information about the PHY type */
  110. /* And management functions */
  111. struct phy_info *phyinfo;
  112. struct eth_device *dev;
  113. /* forced speed & duplex (no autoneg)
  114. * partner speed & duplex & pause (autoneg)
  115. */
  116. int speed;
  117. int duplex;
  118. int pause;
  119. /* The most recently read link state */
  120. int link;
  121. /* Enabled Interrupts */
  122. u32 interrupts;
  123. u32 advertising;
  124. int autoneg;
  125. int mii_id;
  126. /* private data pointer */
  127. /* For use by PHYs to maintain extra state */
  128. void *priv;
  129. /* Provided by ethernet driver */
  130. int (*mdio_read)(struct eth_device *dev, int mii_id, int reg);
  131. void (*mdio_write)(struct eth_device *dev, int mii_id, int reg,
  132. int val);
  133. };
  134. /* struct phy_info: a structure which defines attributes for a PHY
  135. *
  136. * id will contain a number which represents the PHY. During
  137. * startup, the driver will poll the PHY to find out what its
  138. * UID--as defined by registers 2 and 3--is. The 32-bit result
  139. * gotten from the PHY will be ANDed with phy_id_mask to
  140. * discard any bits which may change based on revision numbers
  141. * unimportant to functionality
  142. *
  143. * There are 6 commands which take a ugeth_mii_info structure.
  144. * Each PHY must declare config_aneg, and read_status.
  145. */
  146. struct phy_info {
  147. u32 phy_id;
  148. char *name;
  149. unsigned int phy_id_mask;
  150. u32 features;
  151. /* Called to initialize the PHY */
  152. int (*init)(struct uec_mii_info *mii_info);
  153. /* Called to suspend the PHY for power */
  154. int (*suspend)(struct uec_mii_info *mii_info);
  155. /* Reconfigures autonegotiation (or disables it) */
  156. int (*config_aneg)(struct uec_mii_info *mii_info);
  157. /* Determines the negotiated speed and duplex */
  158. int (*read_status)(struct uec_mii_info *mii_info);
  159. /* Clears any pending interrupts */
  160. int (*ack_interrupt)(struct uec_mii_info *mii_info);
  161. /* Enables or disables interrupts */
  162. int (*config_intr)(struct uec_mii_info *mii_info);
  163. /* Clears up any memory if needed */
  164. void (*close)(struct uec_mii_info *mii_info);
  165. };
  166. struct phy_info *uec_get_phy_info(struct uec_mii_info *mii_info);
  167. void uec_write_phy_reg(struct eth_device *dev, int mii_id, int regnum,
  168. int value);
  169. int uec_read_phy_reg(struct eth_device *dev, int mii_id, int regnum);
  170. void mii_clear_phy_interrupt(struct uec_mii_info *mii_info);
  171. void mii_configure_phy_interrupt(struct uec_mii_info *mii_info,
  172. u32 interrupts);
  173. void change_phy_interface_mode(struct eth_device *dev,
  174. phy_interface_t type, int speed);
  175. #endif /* __UEC_PHY_H__ */