rk_pwm.c 5.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2016 Google, Inc
  4. * Written by Simon Glass <sjg@chromium.org>
  5. */
  6. #include <common.h>
  7. #include <clk.h>
  8. #include <div64.h>
  9. #include <dm.h>
  10. #include <log.h>
  11. #include <pwm.h>
  12. #include <regmap.h>
  13. #include <syscon.h>
  14. #include <asm/io.h>
  15. #include <asm/arch-rockchip/pwm.h>
  16. #include <linux/bitops.h>
  17. #include <power/regulator.h>
  18. DECLARE_GLOBAL_DATA_PTR;
  19. struct rockchip_pwm_data {
  20. struct rockchip_pwm_regs regs;
  21. unsigned int prescaler;
  22. bool supports_polarity;
  23. bool supports_lock;
  24. u32 enable_conf;
  25. u32 enable_conf_mask;
  26. };
  27. struct rk_pwm_priv {
  28. fdt_addr_t base;
  29. ulong freq;
  30. u32 conf_polarity;
  31. const struct rockchip_pwm_data *data;
  32. };
  33. static int rk_pwm_set_invert(struct udevice *dev, uint channel, bool polarity)
  34. {
  35. struct rk_pwm_priv *priv = dev_get_priv(dev);
  36. if (!priv->data->supports_polarity) {
  37. debug("%s: Do not support polarity\n", __func__);
  38. return 0;
  39. }
  40. debug("%s: polarity=%u\n", __func__, polarity);
  41. if (polarity)
  42. priv->conf_polarity = PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSTIVE;
  43. else
  44. priv->conf_polarity = PWM_DUTY_POSTIVE | PWM_INACTIVE_NEGATIVE;
  45. return 0;
  46. }
  47. static int rk_pwm_set_config(struct udevice *dev, uint channel, uint period_ns,
  48. uint duty_ns)
  49. {
  50. struct rk_pwm_priv *priv = dev_get_priv(dev);
  51. const struct rockchip_pwm_regs *regs = &priv->data->regs;
  52. unsigned long period, duty;
  53. u32 ctrl;
  54. debug("%s: period_ns=%u, duty_ns=%u\n", __func__, period_ns, duty_ns);
  55. ctrl = readl(priv->base + regs->ctrl);
  56. /*
  57. * Lock the period and duty of previous configuration, then
  58. * change the duty and period, that would not be effective.
  59. */
  60. if (priv->data->supports_lock) {
  61. ctrl |= PWM_LOCK;
  62. writel(ctrl, priv->base + regs->ctrl);
  63. }
  64. period = lldiv((uint64_t)priv->freq * period_ns,
  65. priv->data->prescaler * 1000000000);
  66. duty = lldiv((uint64_t)priv->freq * duty_ns,
  67. priv->data->prescaler * 1000000000);
  68. writel(period, priv->base + regs->period);
  69. writel(duty, priv->base + regs->duty);
  70. if (priv->data->supports_polarity) {
  71. ctrl &= ~(PWM_DUTY_MASK | PWM_INACTIVE_MASK);
  72. ctrl |= priv->conf_polarity;
  73. }
  74. /*
  75. * Unlock and set polarity at the same time,
  76. * the configuration of duty, period and polarity
  77. * would be effective together at next period.
  78. */
  79. if (priv->data->supports_lock)
  80. ctrl &= ~PWM_LOCK;
  81. writel(ctrl, priv->base + regs->ctrl);
  82. debug("%s: period=%lu, duty=%lu\n", __func__, period, duty);
  83. return 0;
  84. }
  85. static int rk_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
  86. {
  87. struct rk_pwm_priv *priv = dev_get_priv(dev);
  88. const struct rockchip_pwm_regs *regs = &priv->data->regs;
  89. u32 ctrl;
  90. debug("%s: Enable '%s'\n", __func__, dev->name);
  91. ctrl = readl(priv->base + regs->ctrl);
  92. ctrl &= ~priv->data->enable_conf_mask;
  93. if (enable)
  94. ctrl |= priv->data->enable_conf;
  95. else
  96. ctrl &= ~priv->data->enable_conf;
  97. writel(ctrl, priv->base + regs->ctrl);
  98. return 0;
  99. }
  100. static int rk_pwm_ofdata_to_platdata(struct udevice *dev)
  101. {
  102. struct rk_pwm_priv *priv = dev_get_priv(dev);
  103. priv->base = dev_read_addr(dev);
  104. return 0;
  105. }
  106. static int rk_pwm_probe(struct udevice *dev)
  107. {
  108. struct rk_pwm_priv *priv = dev_get_priv(dev);
  109. struct clk clk;
  110. int ret = 0;
  111. ret = clk_get_by_index(dev, 0, &clk);
  112. if (ret < 0) {
  113. debug("%s get clock fail!\n", __func__);
  114. return -EINVAL;
  115. }
  116. priv->freq = clk_get_rate(&clk);
  117. priv->data = (struct rockchip_pwm_data *)dev_get_driver_data(dev);
  118. if (priv->data->supports_polarity)
  119. priv->conf_polarity = PWM_DUTY_POSTIVE | PWM_INACTIVE_POSTIVE;
  120. return 0;
  121. }
  122. static const struct pwm_ops rk_pwm_ops = {
  123. .set_invert = rk_pwm_set_invert,
  124. .set_config = rk_pwm_set_config,
  125. .set_enable = rk_pwm_set_enable,
  126. };
  127. static const struct rockchip_pwm_data pwm_data_v1 = {
  128. .regs = {
  129. .duty = 0x04,
  130. .period = 0x08,
  131. .cntr = 0x00,
  132. .ctrl = 0x0c,
  133. },
  134. .prescaler = 2,
  135. .supports_polarity = false,
  136. .supports_lock = false,
  137. .enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN,
  138. .enable_conf_mask = BIT(1) | BIT(3),
  139. };
  140. static const struct rockchip_pwm_data pwm_data_v2 = {
  141. .regs = {
  142. .duty = 0x08,
  143. .period = 0x04,
  144. .cntr = 0x00,
  145. .ctrl = 0x0c,
  146. },
  147. .prescaler = 1,
  148. .supports_polarity = true,
  149. .supports_lock = false,
  150. .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | RK_PWM_ENABLE |
  151. PWM_CONTINUOUS,
  152. .enable_conf_mask = GENMASK(2, 0) | BIT(5) | BIT(8),
  153. };
  154. static const struct rockchip_pwm_data pwm_data_v3 = {
  155. .regs = {
  156. .duty = 0x08,
  157. .period = 0x04,
  158. .cntr = 0x00,
  159. .ctrl = 0x0c,
  160. },
  161. .prescaler = 1,
  162. .supports_polarity = true,
  163. .supports_lock = true,
  164. .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | RK_PWM_ENABLE |
  165. PWM_CONTINUOUS,
  166. .enable_conf_mask = GENMASK(2, 0) | BIT(5) | BIT(8),
  167. };
  168. static const struct udevice_id rk_pwm_ids[] = {
  169. { .compatible = "rockchip,rk2928-pwm", .data = (ulong)&pwm_data_v1},
  170. { .compatible = "rockchip,rk3288-pwm", .data = (ulong)&pwm_data_v2},
  171. { .compatible = "rockchip,rk3328-pwm", .data = (ulong)&pwm_data_v3},
  172. { }
  173. };
  174. U_BOOT_DRIVER(rk_pwm) = {
  175. .name = "rk_pwm",
  176. .id = UCLASS_PWM,
  177. .of_match = rk_pwm_ids,
  178. .ops = &rk_pwm_ops,
  179. .ofdata_to_platdata = rk_pwm_ofdata_to_platdata,
  180. .probe = rk_pwm_probe,
  181. .priv_auto_alloc_size = sizeof(struct rk_pwm_priv),
  182. };