exynos_pwm.c 2.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2016 Google Inc.
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <log.h>
  8. #include <pwm.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/clk.h>
  11. #include <asm/arch/clock.h>
  12. #include <asm/arch/pwm.h>
  13. struct exynos_pwm_priv {
  14. struct s5p_timer *regs;
  15. };
  16. static int exynos_pwm_set_config(struct udevice *dev, uint channel,
  17. uint period_ns, uint duty_ns)
  18. {
  19. struct exynos_pwm_priv *priv = dev_get_priv(dev);
  20. struct s5p_timer *regs = priv->regs;
  21. unsigned int offset, prescaler;
  22. uint div = 4, rate, rate_ns;
  23. u32 val;
  24. u32 tcnt, tcmp, tcon;
  25. if (channel >= 5)
  26. return -EINVAL;
  27. debug("%s: Configure '%s' channel %u, period_ns %u, duty_ns %u\n",
  28. __func__, dev->name, channel, period_ns, duty_ns);
  29. val = readl(&regs->tcfg0);
  30. prescaler = (channel < 2 ? val : (val >> 8)) & 0xff;
  31. div = (readl(&regs->tcfg1) >> MUX_DIV_SHIFT(channel)) & 0xf;
  32. rate = get_pwm_clk() / ((prescaler + 1) * (1 << div));
  33. debug("%s: pwm_clk %lu, rate %u\n", __func__, get_pwm_clk(), rate);
  34. if (channel < 4) {
  35. rate_ns = 1000000000 / rate;
  36. tcnt = period_ns / rate_ns;
  37. tcmp = duty_ns / rate_ns;
  38. debug("%s: tcnt %u, tcmp %u\n", __func__, tcnt, tcmp);
  39. offset = channel * 3;
  40. writel(tcnt, &regs->tcntb0 + offset);
  41. writel(tcmp, &regs->tcmpb0 + offset);
  42. }
  43. tcon = readl(&regs->tcon);
  44. tcon |= TCON_UPDATE(channel);
  45. if (channel < 4)
  46. tcon |= TCON_AUTO_RELOAD(channel);
  47. else
  48. tcon |= TCON4_AUTO_RELOAD;
  49. writel(tcon, &regs->tcon);
  50. tcon &= ~TCON_UPDATE(channel);
  51. writel(tcon, &regs->tcon);
  52. return 0;
  53. }
  54. static int exynos_pwm_set_enable(struct udevice *dev, uint channel,
  55. bool enable)
  56. {
  57. struct exynos_pwm_priv *priv = dev_get_priv(dev);
  58. struct s5p_timer *regs = priv->regs;
  59. u32 mask;
  60. if (channel >= 4)
  61. return -EINVAL;
  62. debug("%s: Enable '%s' channel %u\n", __func__, dev->name, channel);
  63. mask = TCON_START(channel);
  64. clrsetbits_le32(&regs->tcon, mask, enable ? mask : 0);
  65. return 0;
  66. }
  67. static int exynos_pwm_probe(struct udevice *dev)
  68. {
  69. struct exynos_pwm_priv *priv = dev_get_priv(dev);
  70. struct s5p_timer *regs = priv->regs;
  71. writel(PRESCALER_0 | PRESCALER_1 << 8, &regs->tcfg0);
  72. return 0;
  73. }
  74. static int exynos_pwm_ofdata_to_platdata(struct udevice *dev)
  75. {
  76. struct exynos_pwm_priv *priv = dev_get_priv(dev);
  77. priv->regs = dev_read_addr_ptr(dev);
  78. return 0;
  79. }
  80. static const struct pwm_ops exynos_pwm_ops = {
  81. .set_config = exynos_pwm_set_config,
  82. .set_enable = exynos_pwm_set_enable,
  83. };
  84. static const struct udevice_id exynos_channels[] = {
  85. { .compatible = "samsung,exynos4210-pwm" },
  86. { }
  87. };
  88. U_BOOT_DRIVER(exynos_pwm) = {
  89. .name = "exynos_pwm",
  90. .id = UCLASS_PWM,
  91. .of_match = exynos_channels,
  92. .ops = &exynos_pwm_ops,
  93. .probe = exynos_pwm_probe,
  94. .ofdata_to_platdata = exynos_pwm_ofdata_to_platdata,
  95. .priv_auto_alloc_size = sizeof(struct exynos_pwm_priv),
  96. };