pbias_regulator.c 7.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2016 Texas Instruments Incorporated, <www.ti.com>
  4. * Jean-Jacques Hiblot <jjhiblot@ti.com>
  5. */
  6. #include <common.h>
  7. #include <errno.h>
  8. #include <dm.h>
  9. #include <log.h>
  10. #include <linux/delay.h>
  11. #include <linux/err.h>
  12. #include <power/pmic.h>
  13. #include <power/regulator.h>
  14. #include <regmap.h>
  15. #include <syscon.h>
  16. #include <linux/bitops.h>
  17. #include <linux/ioport.h>
  18. #include <dm/read.h>
  19. #ifdef CONFIG_MMC_OMAP36XX_PINS
  20. #include <asm/arch/sys_proto.h>
  21. #include <asm/io.h>
  22. #include <asm/arch/mux.h>
  23. #endif
  24. struct pbias_reg_info {
  25. u32 enable;
  26. u32 enable_mask;
  27. u32 disable_val;
  28. u32 vmode;
  29. unsigned int enable_time;
  30. char *name;
  31. };
  32. struct pbias_priv {
  33. struct regmap *regmap;
  34. int offset;
  35. };
  36. static const struct pmic_child_info pmic_children_info[] = {
  37. { .prefix = "pbias", .driver = "pbias_regulator"},
  38. { },
  39. };
  40. static int pbias_write(struct udevice *dev, uint reg, const uint8_t *buff,
  41. int len)
  42. {
  43. struct pbias_priv *priv = dev_get_priv(dev);
  44. u32 val = *(u32 *)buff;
  45. if (len != 4)
  46. return -EINVAL;
  47. return regmap_write(priv->regmap, priv->offset, val);
  48. }
  49. static int pbias_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
  50. {
  51. struct pbias_priv *priv = dev_get_priv(dev);
  52. if (len != 4)
  53. return -EINVAL;
  54. return regmap_read(priv->regmap, priv->offset, (u32 *)buff);
  55. }
  56. static int pbias_ofdata_to_platdata(struct udevice *dev)
  57. {
  58. struct pbias_priv *priv = dev_get_priv(dev);
  59. struct udevice *syscon;
  60. struct regmap *regmap;
  61. struct resource res;
  62. int err;
  63. err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
  64. "syscon", &syscon);
  65. if (err) {
  66. pr_err("%s: unable to find syscon device (%d)\n", __func__,
  67. err);
  68. return err;
  69. }
  70. regmap = syscon_get_regmap(syscon);
  71. if (IS_ERR(regmap)) {
  72. pr_err("%s: unable to find regmap (%ld)\n", __func__,
  73. PTR_ERR(regmap));
  74. return PTR_ERR(regmap);
  75. }
  76. priv->regmap = regmap;
  77. err = dev_read_resource(dev, 0, &res);
  78. if (err) {
  79. pr_err("%s: unable to find offset (%d)\n", __func__, err);
  80. return err;
  81. }
  82. priv->offset = res.start;
  83. return 0;
  84. }
  85. static int pbias_bind(struct udevice *dev)
  86. {
  87. int children;
  88. children = pmic_bind_children(dev, dev->node, pmic_children_info);
  89. if (!children)
  90. debug("%s: %s - no child found\n", __func__, dev->name);
  91. return 0;
  92. }
  93. static struct dm_pmic_ops pbias_ops = {
  94. .read = pbias_read,
  95. .write = pbias_write,
  96. };
  97. static const struct udevice_id pbias_ids[] = {
  98. { .compatible = "ti,pbias-dra7" },
  99. { .compatible = "ti,pbias-omap2" },
  100. { .compatible = "ti,pbias-omap3" },
  101. { .compatible = "ti,pbias-omap4" },
  102. { .compatible = "ti,pbias-omap5" },
  103. { }
  104. };
  105. U_BOOT_DRIVER(pbias_pmic) = {
  106. .name = "pbias_pmic",
  107. .id = UCLASS_PMIC,
  108. .of_match = pbias_ids,
  109. .bind = pbias_bind,
  110. .ops = &pbias_ops,
  111. .ofdata_to_platdata = pbias_ofdata_to_platdata,
  112. .priv_auto_alloc_size = sizeof(struct pbias_priv),
  113. };
  114. static const struct pbias_reg_info pbias_mmc_omap2430 = {
  115. .enable = BIT(1),
  116. .enable_mask = BIT(1),
  117. .vmode = BIT(0),
  118. .disable_val = 0,
  119. .enable_time = 100,
  120. .name = "pbias_mmc_omap2430"
  121. };
  122. static const struct pbias_reg_info pbias_sim_omap3 = {
  123. .enable = BIT(9),
  124. .enable_mask = BIT(9),
  125. .vmode = BIT(8),
  126. .enable_time = 100,
  127. .name = "pbias_sim_omap3"
  128. };
  129. static const struct pbias_reg_info pbias_mmc_omap4 = {
  130. .enable = BIT(26) | BIT(22),
  131. .enable_mask = BIT(26) | BIT(25) | BIT(22),
  132. .disable_val = BIT(25),
  133. .vmode = BIT(21),
  134. .enable_time = 100,
  135. .name = "pbias_mmc_omap4"
  136. };
  137. static const struct pbias_reg_info pbias_mmc_omap5 = {
  138. .enable = BIT(27) | BIT(26),
  139. .enable_mask = BIT(27) | BIT(25) | BIT(26),
  140. .disable_val = BIT(25),
  141. .vmode = BIT(21),
  142. .enable_time = 100,
  143. .name = "pbias_mmc_omap5"
  144. };
  145. static const struct pbias_reg_info *pbias_reg_infos[] = {
  146. &pbias_mmc_omap5,
  147. &pbias_mmc_omap4,
  148. &pbias_sim_omap3,
  149. &pbias_mmc_omap2430,
  150. NULL
  151. };
  152. static int pbias_regulator_probe(struct udevice *dev)
  153. {
  154. const struct pbias_reg_info **p = pbias_reg_infos;
  155. struct dm_regulator_uclass_platdata *uc_pdata;
  156. uc_pdata = dev_get_uclass_platdata(dev);
  157. while (*p) {
  158. int rc;
  159. rc = dev_read_stringlist_search(dev, "regulator-name",
  160. (*p)->name);
  161. if (rc >= 0) {
  162. debug("found regulator %s\n", (*p)->name);
  163. break;
  164. } else if (rc != -ENODATA) {
  165. return rc;
  166. }
  167. p++;
  168. }
  169. if (!*p) {
  170. int i = 0;
  171. const char *s;
  172. debug("regulator ");
  173. while (dev_read_string_index(dev, "regulator-name", i++, &s) >= 0)
  174. debug("%s'%s' ", (i > 1) ? ", " : "", s);
  175. debug("%s not supported\n", (i > 2) ? "are" : "is");
  176. return -EINVAL;
  177. }
  178. uc_pdata->type = REGULATOR_TYPE_OTHER;
  179. dev->priv = (void *)*p;
  180. return 0;
  181. }
  182. static int pbias_regulator_get_value(struct udevice *dev)
  183. {
  184. const struct pbias_reg_info *p = dev_get_priv(dev);
  185. int rc;
  186. u32 reg;
  187. rc = pmic_read(dev->parent, 0, (uint8_t *)&reg, sizeof(reg));
  188. if (rc)
  189. return rc;
  190. debug("%s voltage id %s\n", p->name,
  191. (reg & p->vmode) ? "3.0v" : "1.8v");
  192. return (reg & p->vmode) ? 3000000 : 1800000;
  193. }
  194. static int pbias_regulator_set_value(struct udevice *dev, int uV)
  195. {
  196. const struct pbias_reg_info *p = dev_get_priv(dev);
  197. int rc, ret;
  198. u32 reg;
  199. #ifdef CONFIG_MMC_OMAP36XX_PINS
  200. u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
  201. #endif
  202. rc = pmic_read(dev->parent, 0, (uint8_t *)&reg, sizeof(reg));
  203. if (rc)
  204. return rc;
  205. if (uV == 3300000)
  206. reg |= p->vmode;
  207. else if (uV == 1800000)
  208. reg &= ~p->vmode;
  209. else
  210. return -EINVAL;
  211. debug("Setting %s voltage to %s\n", p->name,
  212. (reg & p->vmode) ? "3.0v" : "1.8v");
  213. #ifdef CONFIG_MMC_OMAP36XX_PINS
  214. if (get_cpu_family() == CPU_OMAP36XX) {
  215. /* Disable extended drain IO before changing PBIAS */
  216. wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
  217. writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
  218. }
  219. #endif
  220. ret = pmic_write(dev->parent, 0, (uint8_t *)&reg, sizeof(reg));
  221. #ifdef CONFIG_MMC_OMAP36XX_PINS
  222. if (get_cpu_family() == CPU_OMAP36XX) {
  223. /* Enable extended drain IO after changing PBIAS */
  224. writel(wkup_ctrl |
  225. OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
  226. OMAP34XX_CTRL_WKUP_CTRL);
  227. }
  228. #endif
  229. return ret;
  230. }
  231. static int pbias_regulator_get_enable(struct udevice *dev)
  232. {
  233. const struct pbias_reg_info *p = dev_get_priv(dev);
  234. int rc;
  235. u32 reg;
  236. rc = pmic_read(dev->parent, 0, (uint8_t *)&reg, sizeof(reg));
  237. if (rc)
  238. return rc;
  239. debug("%s id %s\n", p->name,
  240. (reg & p->enable_mask) == (p->disable_val) ? "on" : "off");
  241. return (reg & p->enable_mask) == (p->disable_val);
  242. }
  243. static int pbias_regulator_set_enable(struct udevice *dev, bool enable)
  244. {
  245. const struct pbias_reg_info *p = dev_get_priv(dev);
  246. int rc;
  247. u32 reg;
  248. #ifdef CONFIG_MMC_OMAP36XX_PINS
  249. u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
  250. #endif
  251. debug("Turning %s %s\n", enable ? "on" : "off", p->name);
  252. #ifdef CONFIG_MMC_OMAP36XX_PINS
  253. if (get_cpu_family() == CPU_OMAP36XX) {
  254. /* Disable extended drain IO before changing PBIAS */
  255. wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
  256. writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
  257. }
  258. #endif
  259. rc = pmic_read(dev->parent, 0, (uint8_t *)&reg, sizeof(reg));
  260. if (rc)
  261. return rc;
  262. reg &= ~p->enable_mask;
  263. if (enable)
  264. reg |= p->enable;
  265. else
  266. reg |= p->disable_val;
  267. rc = pmic_write(dev->parent, 0, (uint8_t *)&reg, sizeof(reg));
  268. #ifdef CONFIG_MMC_OMAP36XX_PINS
  269. if (get_cpu_family() == CPU_OMAP36XX) {
  270. /* Enable extended drain IO after changing PBIAS */
  271. writel(wkup_ctrl |
  272. OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
  273. OMAP34XX_CTRL_WKUP_CTRL);
  274. }
  275. #endif
  276. if (rc)
  277. return rc;
  278. if (enable)
  279. udelay(p->enable_time);
  280. return 0;
  281. }
  282. static const struct dm_regulator_ops pbias_regulator_ops = {
  283. .get_value = pbias_regulator_get_value,
  284. .set_value = pbias_regulator_set_value,
  285. .get_enable = pbias_regulator_get_enable,
  286. .set_enable = pbias_regulator_set_enable,
  287. };
  288. U_BOOT_DRIVER(pbias_regulator) = {
  289. .name = "pbias_regulator",
  290. .id = UCLASS_REGULATOR,
  291. .ops = &pbias_regulator_ops,
  292. .probe = pbias_regulator_probe,
  293. };