pinctrl-stmfx.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
  4. *
  5. * Driver for STMicroelectronics Multi-Function eXpander (STMFX) GPIO expander
  6. * based on Linux driver : pinctrl/pinctrl-stmfx.c
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <i2c.h>
  11. #include <asm/gpio.h>
  12. #include <dm/device.h>
  13. #include <dm/device-internal.h>
  14. #include <dm/device_compat.h>
  15. #include <dm/lists.h>
  16. #include <dm/pinctrl.h>
  17. #include <linux/bitfield.h>
  18. #include <linux/bitops.h>
  19. #include <linux/delay.h>
  20. #include <power/regulator.h>
  21. /* STMFX pins = GPIO[15:0] + aGPIO[7:0] */
  22. #define STMFX_MAX_GPIO 16
  23. #define STMFX_MAX_AGPIO 8
  24. /* General */
  25. #define STMFX_REG_CHIP_ID 0x00 /* R */
  26. #define STMFX_REG_FW_VERSION_MSB 0x01 /* R */
  27. #define STMFX_REG_FW_VERSION_LSB 0x02 /* R */
  28. #define STMFX_REG_SYS_CTRL 0x40 /* RW */
  29. /* MFX boot time is around 10ms, so after reset, we have to wait this delay */
  30. #define STMFX_BOOT_TIME_MS 10
  31. /* GPIOs expander */
  32. /* GPIO_STATE1 0x10, GPIO_STATE2 0x11, GPIO_STATE3 0x12 */
  33. #define STMFX_REG_GPIO_STATE 0x10 /* R */
  34. /* GPIO_DIR1 0x60, GPIO_DIR2 0x61, GPIO_DIR3 0x63 */
  35. #define STMFX_REG_GPIO_DIR 0x60 /* RW */
  36. /* GPIO_TYPE1 0x64, GPIO_TYPE2 0x65, GPIO_TYPE3 0x66 */
  37. #define STMFX_REG_GPIO_TYPE 0x64 /* RW */
  38. /* GPIO_PUPD1 0x68, GPIO_PUPD2 0x69, GPIO_PUPD3 0x6A */
  39. #define STMFX_REG_GPIO_PUPD 0x68 /* RW */
  40. /* GPO_SET1 0x6C, GPO_SET2 0x6D, GPO_SET3 0x6E */
  41. #define STMFX_REG_GPO_SET 0x6C /* RW */
  42. /* GPO_CLR1 0x70, GPO_CLR2 0x71, GPO_CLR3 0x72 */
  43. #define STMFX_REG_GPO_CLR 0x70 /* RW */
  44. /* STMFX_REG_CHIP_ID bitfields */
  45. #define STMFX_REG_CHIP_ID_MASK GENMASK(7, 0)
  46. /* STMFX_REG_SYS_CTRL bitfields */
  47. #define STMFX_REG_SYS_CTRL_GPIO_EN BIT(0)
  48. #define STMFX_REG_SYS_CTRL_ALTGPIO_EN BIT(3)
  49. #define STMFX_REG_SYS_CTRL_SWRST BIT(7)
  50. #define NR_GPIO_REGS 3
  51. #define NR_GPIOS_PER_REG 8
  52. #define get_reg(offset) ((offset) / NR_GPIOS_PER_REG)
  53. #define get_shift(offset) ((offset) % NR_GPIOS_PER_REG)
  54. #define get_mask(offset) (BIT(get_shift(offset)))
  55. struct stmfx_pinctrl {
  56. struct udevice *gpio;
  57. };
  58. static int stmfx_read(struct udevice *dev, uint offset)
  59. {
  60. return dm_i2c_reg_read(dev_get_parent(dev), offset);
  61. }
  62. static int stmfx_write(struct udevice *dev, uint offset, unsigned int val)
  63. {
  64. return dm_i2c_reg_write(dev_get_parent(dev), offset, val);
  65. }
  66. static int stmfx_read_reg(struct udevice *dev, u8 reg_base, uint offset)
  67. {
  68. u8 reg = reg_base + get_reg(offset);
  69. u32 mask = get_mask(offset);
  70. int ret;
  71. ret = stmfx_read(dev, reg);
  72. if (ret < 0)
  73. return ret;
  74. return ret < 0 ? ret : !!(ret & mask);
  75. }
  76. static int stmfx_write_reg(struct udevice *dev, u8 reg_base, uint offset,
  77. uint val)
  78. {
  79. u8 reg = reg_base + get_reg(offset);
  80. u32 mask = get_mask(offset);
  81. int ret;
  82. ret = stmfx_read(dev, reg);
  83. if (ret < 0)
  84. return ret;
  85. ret = (ret & ~mask) | (val ? mask : 0);
  86. return stmfx_write(dev, reg, ret);
  87. }
  88. static int stmfx_conf_set_pupd(struct udevice *dev, unsigned int offset,
  89. uint pupd)
  90. {
  91. return stmfx_write_reg(dev, STMFX_REG_GPIO_PUPD, offset, pupd);
  92. }
  93. static int stmfx_conf_get_pupd(struct udevice *dev, unsigned int offset)
  94. {
  95. return stmfx_read_reg(dev, STMFX_REG_GPIO_PUPD, offset);
  96. }
  97. static int stmfx_conf_set_type(struct udevice *dev, unsigned int offset,
  98. uint type)
  99. {
  100. return stmfx_write_reg(dev, STMFX_REG_GPIO_TYPE, offset, type);
  101. }
  102. static int stmfx_conf_get_type(struct udevice *dev, unsigned int offset)
  103. {
  104. return stmfx_read_reg(dev, STMFX_REG_GPIO_TYPE, offset);
  105. }
  106. static int stmfx_gpio_get(struct udevice *dev, unsigned int offset)
  107. {
  108. return stmfx_read_reg(dev, STMFX_REG_GPIO_STATE, offset);
  109. }
  110. static int stmfx_gpio_set(struct udevice *dev, unsigned int offset, int value)
  111. {
  112. u32 reg = value ? STMFX_REG_GPO_SET : STMFX_REG_GPO_CLR;
  113. u32 mask = get_mask(offset);
  114. return stmfx_write(dev, reg + get_reg(offset), mask);
  115. }
  116. static int stmfx_gpio_get_function(struct udevice *dev, unsigned int offset)
  117. {
  118. int ret = stmfx_read_reg(dev, STMFX_REG_GPIO_DIR, offset);
  119. if (ret < 0)
  120. return ret;
  121. /* On stmfx, gpio pins direction is (0)input, (1)output. */
  122. return ret ? GPIOF_OUTPUT : GPIOF_INPUT;
  123. }
  124. static int stmfx_gpio_direction_input(struct udevice *dev, unsigned int offset)
  125. {
  126. return stmfx_write_reg(dev, STMFX_REG_GPIO_DIR, offset, 0);
  127. }
  128. static int stmfx_gpio_direction_output(struct udevice *dev,
  129. unsigned int offset, int value)
  130. {
  131. int ret = stmfx_gpio_set(dev, offset, value);
  132. if (ret < 0)
  133. return ret;
  134. return stmfx_write_reg(dev, STMFX_REG_GPIO_DIR, offset, 1);
  135. }
  136. static int stmfx_gpio_set_dir_flags(struct udevice *dev, unsigned int offset,
  137. ulong flags)
  138. {
  139. int ret = -ENOTSUPP;
  140. if (flags & GPIOD_IS_OUT) {
  141. if (flags & GPIOD_OPEN_SOURCE)
  142. return -ENOTSUPP;
  143. if (flags & GPIOD_OPEN_DRAIN)
  144. ret = stmfx_conf_set_type(dev, offset, 0);
  145. else /* PUSH-PULL */
  146. ret = stmfx_conf_set_type(dev, offset, 1);
  147. if (ret)
  148. return ret;
  149. ret = stmfx_gpio_direction_output(dev, offset,
  150. GPIOD_FLAGS_OUTPUT(flags));
  151. } else if (flags & GPIOD_IS_IN) {
  152. ret = stmfx_gpio_direction_input(dev, offset);
  153. if (ret)
  154. return ret;
  155. if (flags & GPIOD_PULL_UP) {
  156. ret = stmfx_conf_set_type(dev, offset, 1);
  157. if (ret)
  158. return ret;
  159. ret = stmfx_conf_set_pupd(dev, offset, 1);
  160. } else if (flags & GPIOD_PULL_DOWN) {
  161. ret = stmfx_conf_set_type(dev, offset, 1);
  162. if (ret)
  163. return ret;
  164. ret = stmfx_conf_set_pupd(dev, offset, 0);
  165. }
  166. }
  167. return ret;
  168. }
  169. static int stmfx_gpio_get_dir_flags(struct udevice *dev, unsigned int offset,
  170. ulong *flags)
  171. {
  172. ulong dir_flags = 0;
  173. int ret;
  174. if (stmfx_gpio_get_function(dev, offset) == GPIOF_OUTPUT) {
  175. dir_flags |= GPIOD_IS_OUT;
  176. ret = stmfx_conf_get_type(dev, offset);
  177. if (ret < 0)
  178. return ret;
  179. if (ret == 0)
  180. dir_flags |= GPIOD_OPEN_DRAIN;
  181. /* 1 = push-pull (default), open source not supported */
  182. ret = stmfx_gpio_get(dev, offset);
  183. if (ret < 0)
  184. return ret;
  185. if (ret)
  186. dir_flags |= GPIOD_IS_OUT_ACTIVE;
  187. } else {
  188. dir_flags |= GPIOD_IS_IN;
  189. ret = stmfx_conf_get_type(dev, offset);
  190. if (ret < 0)
  191. return ret;
  192. if (ret == 1) {
  193. ret = stmfx_conf_get_pupd(dev, offset);
  194. if (ret < 0)
  195. return ret;
  196. if (ret == 1)
  197. dir_flags |= GPIOD_PULL_UP;
  198. else
  199. dir_flags |= GPIOD_PULL_DOWN;
  200. }
  201. }
  202. *flags = dir_flags;
  203. return 0;
  204. }
  205. static int stmfx_gpio_probe(struct udevice *dev)
  206. {
  207. struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  208. struct ofnode_phandle_args args;
  209. u8 sys_ctrl;
  210. uc_priv->bank_name = "stmfx";
  211. uc_priv->gpio_count = STMFX_MAX_GPIO + STMFX_MAX_AGPIO;
  212. if (!dev_read_phandle_with_args(dev, "gpio-ranges",
  213. NULL, 3, 0, &args)) {
  214. uc_priv->gpio_count = args.args[2];
  215. }
  216. /* enable GPIO function */
  217. sys_ctrl = STMFX_REG_SYS_CTRL_GPIO_EN;
  218. if (uc_priv->gpio_count > STMFX_MAX_GPIO)
  219. sys_ctrl |= STMFX_REG_SYS_CTRL_ALTGPIO_EN;
  220. stmfx_write(dev, STMFX_REG_SYS_CTRL, sys_ctrl);
  221. return 0;
  222. }
  223. static const struct dm_gpio_ops stmfx_gpio_ops = {
  224. .set_value = stmfx_gpio_set,
  225. .get_value = stmfx_gpio_get,
  226. .get_function = stmfx_gpio_get_function,
  227. .direction_input = stmfx_gpio_direction_input,
  228. .direction_output = stmfx_gpio_direction_output,
  229. .set_dir_flags = stmfx_gpio_set_dir_flags,
  230. .get_dir_flags = stmfx_gpio_get_dir_flags,
  231. };
  232. U_BOOT_DRIVER(stmfx_gpio) = {
  233. .name = "stmfx-gpio",
  234. .id = UCLASS_GPIO,
  235. .probe = stmfx_gpio_probe,
  236. .ops = &stmfx_gpio_ops,
  237. };
  238. #if CONFIG_IS_ENABLED(PINCONF)
  239. static const struct pinconf_param stmfx_pinctrl_conf_params[] = {
  240. { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
  241. { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 0 },
  242. { "bias-pull-pin-default", PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, 0 },
  243. { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 0 },
  244. { "drive-open-drain", PIN_CONFIG_DRIVE_OPEN_DRAIN, 0 },
  245. { "drive-push-pull", PIN_CONFIG_DRIVE_PUSH_PULL, 0 },
  246. { "output-high", PIN_CONFIG_OUTPUT, 1 },
  247. { "output-low", PIN_CONFIG_OUTPUT, 0 },
  248. };
  249. static int stmfx_pinctrl_conf_set(struct udevice *dev, unsigned int pin,
  250. unsigned int param, unsigned int arg)
  251. {
  252. int ret, dir;
  253. struct stmfx_pinctrl *plat = dev_get_platdata(dev);
  254. dir = stmfx_gpio_get_function(plat->gpio, pin);
  255. if (dir < 0)
  256. return dir;
  257. switch (param) {
  258. case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
  259. case PIN_CONFIG_BIAS_DISABLE:
  260. case PIN_CONFIG_DRIVE_PUSH_PULL:
  261. ret = stmfx_conf_set_type(dev, pin, 0);
  262. break;
  263. case PIN_CONFIG_BIAS_PULL_DOWN:
  264. ret = stmfx_conf_set_type(dev, pin, 1);
  265. if (ret)
  266. return ret;
  267. ret = stmfx_conf_set_pupd(dev, pin, 0);
  268. break;
  269. case PIN_CONFIG_BIAS_PULL_UP:
  270. ret = stmfx_conf_set_type(dev, pin, 1);
  271. if (ret)
  272. return ret;
  273. ret = stmfx_conf_set_pupd(dev, pin, 1);
  274. break;
  275. case PIN_CONFIG_DRIVE_OPEN_DRAIN:
  276. ret = stmfx_conf_set_type(dev, pin, 1);
  277. break;
  278. case PIN_CONFIG_OUTPUT:
  279. ret = stmfx_gpio_direction_output(plat->gpio, pin, arg);
  280. break;
  281. default:
  282. return -ENOTSUPP;
  283. }
  284. return ret;
  285. }
  286. #endif
  287. static int stmfx_pinctrl_get_pins_count(struct udevice *dev)
  288. {
  289. struct stmfx_pinctrl *plat = dev_get_platdata(dev);
  290. struct gpio_dev_priv *uc_priv;
  291. uc_priv = dev_get_uclass_priv(plat->gpio);
  292. return uc_priv->gpio_count;
  293. }
  294. /*
  295. * STMFX pins[15:0] are called "stmfx_gpio[15:0]"
  296. * and STMFX pins[23:16] are called "stmfx_agpio[7:0]"
  297. */
  298. #define MAX_PIN_NAME_LEN 7
  299. static char pin_name[MAX_PIN_NAME_LEN];
  300. static const char *stmfx_pinctrl_get_pin_name(struct udevice *dev,
  301. unsigned int selector)
  302. {
  303. if (selector < STMFX_MAX_GPIO)
  304. snprintf(pin_name, MAX_PIN_NAME_LEN, "stmfx_gpio%u", selector);
  305. else
  306. snprintf(pin_name, MAX_PIN_NAME_LEN, "stmfx_agpio%u", selector - 16);
  307. return pin_name;
  308. }
  309. static const char *stmfx_pinctrl_get_pin_conf(struct udevice *dev,
  310. unsigned int pin, int func)
  311. {
  312. int pupd, type;
  313. type = stmfx_conf_get_type(dev, pin);
  314. if (type < 0)
  315. return "";
  316. if (func == GPIOF_OUTPUT) {
  317. if (type)
  318. return "drive-open-drain";
  319. else
  320. return ""; /* default: push-pull*/
  321. }
  322. if (!type)
  323. return ""; /* default: bias-disable*/
  324. pupd = stmfx_conf_get_pupd(dev, pin);
  325. if (pupd < 0)
  326. return "";
  327. if (pupd)
  328. return "bias-pull-up";
  329. else
  330. return "bias-pull-down";
  331. }
  332. static int stmfx_pinctrl_get_pin_muxing(struct udevice *dev,
  333. unsigned int selector,
  334. char *buf, int size)
  335. {
  336. struct stmfx_pinctrl *plat = dev_get_platdata(dev);
  337. int func;
  338. func = stmfx_gpio_get_function(plat->gpio, selector);
  339. if (func < 0)
  340. return func;
  341. snprintf(buf, size, "%s ", func == GPIOF_INPUT ? "input" : "output");
  342. strncat(buf, stmfx_pinctrl_get_pin_conf(dev, selector, func), size);
  343. return 0;
  344. }
  345. static int stmfx_pinctrl_bind(struct udevice *dev)
  346. {
  347. struct stmfx_pinctrl *plat = dev_get_platdata(dev);
  348. /* subnode name is not explicit: use father name */
  349. device_set_name(dev, dev->parent->name);
  350. return device_bind_driver_to_node(dev->parent,
  351. "stmfx-gpio", dev->parent->name,
  352. dev_ofnode(dev), &plat->gpio);
  353. };
  354. static int stmfx_pinctrl_probe(struct udevice *dev)
  355. {
  356. struct stmfx_pinctrl *plat = dev_get_platdata(dev);
  357. return device_probe(plat->gpio);
  358. };
  359. const struct pinctrl_ops stmfx_pinctrl_ops = {
  360. .get_pins_count = stmfx_pinctrl_get_pins_count,
  361. .get_pin_name = stmfx_pinctrl_get_pin_name,
  362. .set_state = pinctrl_generic_set_state,
  363. .get_pin_muxing = stmfx_pinctrl_get_pin_muxing,
  364. #if CONFIG_IS_ENABLED(PINCONF)
  365. .pinconf_set = stmfx_pinctrl_conf_set,
  366. .pinconf_num_params = ARRAY_SIZE(stmfx_pinctrl_conf_params),
  367. .pinconf_params = stmfx_pinctrl_conf_params,
  368. #endif
  369. };
  370. static const struct udevice_id stmfx_pinctrl_match[] = {
  371. { .compatible = "st,stmfx-0300-pinctrl", },
  372. };
  373. U_BOOT_DRIVER(stmfx_pinctrl) = {
  374. .name = "stmfx-pinctrl",
  375. .id = UCLASS_PINCTRL,
  376. .of_match = of_match_ptr(stmfx_pinctrl_match),
  377. .bind = stmfx_pinctrl_bind,
  378. .probe = stmfx_pinctrl_probe,
  379. .ops = &stmfx_pinctrl_ops,
  380. .platdata_auto_alloc_size = sizeof(struct stmfx_pinctrl),
  381. };
  382. static int stmfx_chip_init(struct udevice *dev)
  383. {
  384. u8 id;
  385. u8 version[2];
  386. int ret;
  387. struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
  388. ret = dm_i2c_reg_read(dev, STMFX_REG_CHIP_ID);
  389. if (ret < 0) {
  390. dev_err(dev, "error reading chip id: %d\n", ret);
  391. return ret;
  392. }
  393. id = (u8)ret;
  394. /*
  395. * Check that ID is the complement of the I2C address:
  396. * STMFX I2C address follows the 7-bit format (MSB), that's why
  397. * client->addr is shifted.
  398. *
  399. * STMFX_I2C_ADDR| STMFX | Linux
  400. * input pin | I2C device address | I2C device address
  401. *---------------------------------------------------------
  402. * 0 | b: 1000 010x h:0x84 | 0x42
  403. * 1 | b: 1000 011x h:0x86 | 0x43
  404. */
  405. if (FIELD_GET(STMFX_REG_CHIP_ID_MASK, ~id) != (chip->chip_addr << 1)) {
  406. dev_err(dev, "unknown chip id: %#x\n", id);
  407. return -EINVAL;
  408. }
  409. ret = dm_i2c_read(dev, STMFX_REG_FW_VERSION_MSB,
  410. version, sizeof(version));
  411. if (ret) {
  412. dev_err(dev, "error reading fw version: %d\n", ret);
  413. return ret;
  414. }
  415. dev_info(dev, "STMFX id: %#x, fw version: %x.%02x\n",
  416. id, version[0], version[1]);
  417. ret = dm_i2c_reg_read(dev, STMFX_REG_SYS_CTRL);
  418. if (ret < 0)
  419. return ret;
  420. ret = dm_i2c_reg_write(dev, STMFX_REG_SYS_CTRL,
  421. ret | STMFX_REG_SYS_CTRL_SWRST);
  422. if (ret)
  423. return ret;
  424. mdelay(STMFX_BOOT_TIME_MS);
  425. return ret;
  426. }
  427. static int stmfx_probe(struct udevice *dev)
  428. {
  429. struct udevice *vdd;
  430. int ret;
  431. ret = device_get_supply_regulator(dev, "vdd-supply", &vdd);
  432. if (ret && ret != -ENOENT) {
  433. dev_err(dev, "vdd regulator error:%d\n", ret);
  434. return ret;
  435. }
  436. if (!ret) {
  437. ret = regulator_set_enable(vdd, true);
  438. if (ret) {
  439. dev_err(dev, "vdd enable failed: %d\n", ret);
  440. return ret;
  441. }
  442. }
  443. return stmfx_chip_init(dev);
  444. }
  445. static const struct udevice_id stmfx_match[] = {
  446. { .compatible = "st,stmfx-0300", },
  447. };
  448. U_BOOT_DRIVER(stmfx) = {
  449. .name = "stmfx",
  450. .id = UCLASS_I2C_GENERIC,
  451. .of_match = of_match_ptr(stmfx_match),
  452. .probe = stmfx_probe,
  453. .bind = dm_scan_fdt_dev,
  454. };