pinctrl-sti.c 7.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Pinctrl driver for STMicroelectronics STi SoCs
  4. *
  5. * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
  6. * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
  7. */
  8. #include <common.h>
  9. #include <bitfield.h>
  10. #include <dm.h>
  11. #include <errno.h>
  12. #include <regmap.h>
  13. #include <syscon.h>
  14. #include <asm/io.h>
  15. #include <dm/pinctrl.h>
  16. #include <linux/bug.h>
  17. #include <linux/libfdt.h>
  18. DECLARE_GLOBAL_DATA_PTR;
  19. #define MAX_STI_PINCONF_ENTRIES 7
  20. /* Output enable */
  21. #define OE (1 << 27)
  22. /* Pull Up */
  23. #define PU (1 << 26)
  24. /* Open Drain */
  25. #define OD (1 << 25)
  26. /* User-frendly defines for Pin Direction */
  27. /* oe = 0, pu = 0, od = 0 */
  28. #define IN (0)
  29. /* oe = 0, pu = 1, od = 0 */
  30. #define IN_PU (PU)
  31. /* oe = 1, pu = 0, od = 0 */
  32. #define OUT (OE)
  33. /* oe = 1, pu = 1, od = 0 */
  34. #define OUT_PU (OE | PU)
  35. /* oe = 1, pu = 0, od = 1 */
  36. #define BIDIR (OE | OD)
  37. /* oe = 1, pu = 1, od = 1 */
  38. #define BIDIR_PU (OE | PU | OD)
  39. struct sti_pinctrl_platdata {
  40. struct regmap *regmap;
  41. };
  42. struct sti_pin_desc {
  43. unsigned char bank;
  44. unsigned char pin;
  45. unsigned char alt;
  46. int dir;
  47. };
  48. /*
  49. * PIO alternative Function selector
  50. */
  51. void sti_alternate_select(struct udevice *dev, struct sti_pin_desc *pin_desc)
  52. {
  53. struct sti_pinctrl_platdata *plat = dev_get_platdata(dev);
  54. unsigned long sysconf, *sysconfreg;
  55. int alt = pin_desc->alt;
  56. int bank = pin_desc->bank;
  57. int pin = pin_desc->pin;
  58. sysconfreg = (unsigned long *)plat->regmap->ranges[0].start;
  59. switch (bank) {
  60. case 0 ... 5: /* in "SBC Bank" */
  61. sysconfreg += bank;
  62. break;
  63. case 10 ... 20: /* in "FRONT Bank" */
  64. sysconfreg += bank - 10;
  65. break;
  66. case 30 ... 35: /* in "REAR Bank" */
  67. sysconfreg += bank - 30;
  68. break;
  69. case 40 ... 42: /* in "FLASH Bank" */
  70. sysconfreg += bank - 40;
  71. break;
  72. default:
  73. BUG();
  74. return;
  75. }
  76. sysconf = readl(sysconfreg);
  77. sysconf = bitfield_replace(sysconf, pin * 4, 3, alt);
  78. writel(sysconf, sysconfreg);
  79. }
  80. /* pin configuration */
  81. void sti_pin_configure(struct udevice *dev, struct sti_pin_desc *pin_desc)
  82. {
  83. struct sti_pinctrl_platdata *plat = dev_get_platdata(dev);
  84. int bit;
  85. int oe = 0, pu = 0, od = 0;
  86. unsigned long *sysconfreg;
  87. int bank = pin_desc->bank;
  88. sysconfreg = (unsigned long *)plat->regmap->ranges[0].start + 40;
  89. /*
  90. * NOTE: The PIO configuration for the PIO pins in the
  91. * "FLASH Bank" are different from all the other banks!
  92. * Specifically, the output-enable pin control register
  93. * (SYS_CFG_3040) and the pull-up pin control register
  94. * (SYS_CFG_3050), are both classed as being "reserved".
  95. * Hence, we do not write to these registers to configure
  96. * the OE and PU features for PIOs in this bank. However,
  97. * the open-drain pin control register (SYS_CFG_3060)
  98. * follows the style of the other banks, and so we can
  99. * treat that register normally.
  100. *
  101. * Being pedantic, we should configure the PU and PD features
  102. * in the "FLASH Bank" explicitly instead using the four
  103. * SYS_CFG registers: 3080, 3081, 3085, and 3086. However, this
  104. * would necessitate passing in the alternate function number
  105. * to this function, and adding some horrible complexity here.
  106. * Alternatively, we could just perform 4 32-bit "pokes" to
  107. * these four SYS_CFG registers early in the initialization.
  108. * In practice, these four SYS_CFG registers are correct
  109. * after a reset, and U-Boot does not need to change them, so
  110. * we (cheat and) rely on these registers being correct.
  111. * WARNING: Please be aware of this (pragmatic) behaviour!
  112. */
  113. int flashss = 0; /* bool: PIO in the Flash Sub-System ? */
  114. switch (pin_desc->dir) {
  115. case IN:
  116. oe = 0; pu = 0; od = 0;
  117. break;
  118. case IN_PU:
  119. oe = 0; pu = 1; od = 0;
  120. break;
  121. case OUT:
  122. oe = 1; pu = 0; od = 0;
  123. break;
  124. case BIDIR:
  125. oe = 1; pu = 0; od = 1;
  126. break;
  127. case BIDIR_PU:
  128. oe = 1; pu = 1; od = 1;
  129. break;
  130. default:
  131. pr_err("%s invalid direction value: 0x%x\n",
  132. __func__, pin_desc->dir);
  133. BUG();
  134. break;
  135. }
  136. switch (bank) {
  137. case 0 ... 5: /* in "SBC Bank" */
  138. sysconfreg += bank / 4;
  139. break;
  140. case 10 ... 20: /* in "FRONT Bank" */
  141. bank -= 10;
  142. sysconfreg += bank / 4;
  143. break;
  144. case 30 ... 35: /* in "REAR Bank" */
  145. bank -= 30;
  146. sysconfreg += bank / 4;
  147. break;
  148. case 40 ... 42: /* in "FLASH Bank" */
  149. bank -= 40;
  150. sysconfreg += bank / 4;
  151. flashss = 1; /* pin is in the Flash Sub-System */
  152. break;
  153. default:
  154. BUG();
  155. return;
  156. }
  157. bit = ((bank * 8) + pin_desc->pin) % 32;
  158. /*
  159. * set the "Output Enable" pin control
  160. * but, do nothing if in the flashSS
  161. */
  162. if (!flashss) {
  163. if (oe)
  164. generic_set_bit(bit, sysconfreg);
  165. else
  166. generic_clear_bit(bit, sysconfreg);
  167. }
  168. sysconfreg += 10; /* skip to next set of syscfg registers */
  169. /*
  170. * set the "Pull Up" pin control
  171. * but, do nothing if in the FlashSS
  172. */
  173. if (!flashss) {
  174. if (pu)
  175. generic_set_bit(bit, sysconfreg);
  176. else
  177. generic_clear_bit(bit, sysconfreg);
  178. }
  179. sysconfreg += 10; /* skip to next set of syscfg registers */
  180. /* set the "Open Drain Enable" pin control */
  181. if (od)
  182. generic_set_bit(bit, sysconfreg);
  183. else
  184. generic_clear_bit(bit, sysconfreg);
  185. }
  186. static int sti_pinctrl_set_state(struct udevice *dev, struct udevice *config)
  187. {
  188. struct fdtdec_phandle_args args;
  189. const void *blob = gd->fdt_blob;
  190. const char *prop_name;
  191. int node = dev_of_offset(config);
  192. int property_offset, prop_len;
  193. int pinconf_node, ret, count;
  194. const char *bank_name;
  195. u32 cells[MAX_STI_PINCONF_ENTRIES];
  196. struct sti_pin_desc pin_desc;
  197. /* go to next node "st,pins" which contains the pins configuration */
  198. pinconf_node = fdt_subnode_offset(blob, node, "st,pins");
  199. /*
  200. * parse each pins configuration which looks like :
  201. * pin_name = <bank_phandle pin_nb alt dir rt_type rt_delay rt_clk>
  202. */
  203. fdt_for_each_property_offset(property_offset, blob, pinconf_node) {
  204. fdt_getprop_by_offset(blob, property_offset, &prop_name,
  205. &prop_len);
  206. /* extract the bank of the pin description */
  207. ret = fdtdec_parse_phandle_with_args(blob, pinconf_node,
  208. prop_name, "#gpio-cells",
  209. 0, 0, &args);
  210. if (ret < 0) {
  211. pr_err("Can't get the gpio bank phandle: %d\n", ret);
  212. return ret;
  213. }
  214. bank_name = fdt_getprop(blob, args.node, "st,bank-name",
  215. &count);
  216. if (count < 0) {
  217. pr_err("Can't find bank-name property %d\n", count);
  218. return -EINVAL;
  219. }
  220. pin_desc.bank = trailing_strtoln(bank_name, NULL);
  221. count = fdtdec_get_int_array_count(blob, pinconf_node,
  222. prop_name, cells,
  223. ARRAY_SIZE(cells));
  224. if (count < 0) {
  225. pr_err("Bad pin configuration array %d\n", count);
  226. return -EINVAL;
  227. }
  228. if (count > MAX_STI_PINCONF_ENTRIES) {
  229. pr_err("Unsupported pinconf array count %d\n", count);
  230. return -EINVAL;
  231. }
  232. pin_desc.pin = cells[1];
  233. pin_desc.alt = cells[2];
  234. pin_desc.dir = cells[3];
  235. sti_alternate_select(dev, &pin_desc);
  236. sti_pin_configure(dev, &pin_desc);
  237. };
  238. return 0;
  239. }
  240. static int sti_pinctrl_probe(struct udevice *dev)
  241. {
  242. struct sti_pinctrl_platdata *plat = dev_get_platdata(dev);
  243. struct udevice *syscon;
  244. int err;
  245. /* get corresponding syscon phandle */
  246. err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
  247. "st,syscfg", &syscon);
  248. if (err) {
  249. pr_err("unable to find syscon device\n");
  250. return err;
  251. }
  252. plat->regmap = syscon_get_regmap(syscon);
  253. if (!plat->regmap) {
  254. pr_err("unable to find regmap\n");
  255. return -ENODEV;
  256. }
  257. return 0;
  258. }
  259. static const struct udevice_id sti_pinctrl_ids[] = {
  260. { .compatible = "st,stih407-sbc-pinctrl" },
  261. { .compatible = "st,stih407-front-pinctrl" },
  262. { .compatible = "st,stih407-rear-pinctrl" },
  263. { .compatible = "st,stih407-flash-pinctrl" },
  264. { }
  265. };
  266. const struct pinctrl_ops sti_pinctrl_ops = {
  267. .set_state = sti_pinctrl_set_state,
  268. };
  269. U_BOOT_DRIVER(pinctrl_sti) = {
  270. .name = "pinctrl_sti",
  271. .id = UCLASS_PINCTRL,
  272. .of_match = sti_pinctrl_ids,
  273. .ops = &sti_pinctrl_ops,
  274. .probe = sti_pinctrl_probe,
  275. .platdata_auto_alloc_size = sizeof(struct sti_pinctrl_platdata),
  276. .ops = &sti_pinctrl_ops,
  277. };