pinctrl-at91.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Atmel PIO pinctrl driver
  4. *
  5. * Copyright (C) 2016 Atmel Corporation
  6. * Wenyou.Yang <wenyou.yang@atmel.com>
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <log.h>
  11. #include <dm/pinctrl.h>
  12. #include <asm/hardware.h>
  13. #include <linux/bitops.h>
  14. #include <linux/io.h>
  15. #include <linux/err.h>
  16. #include <mach/at91_pio.h>
  17. DECLARE_GLOBAL_DATA_PTR;
  18. #define MAX_GPIO_BANKS 5
  19. #define MAX_NB_GPIO_PER_BANK 32
  20. #define MAX_PINMUX_ENTRIES 200
  21. struct at91_pinctrl_priv {
  22. struct at91_port *reg_base[MAX_GPIO_BANKS];
  23. u32 nbanks;
  24. };
  25. #define PULL_UP BIT(0)
  26. #define MULTI_DRIVE BIT(1)
  27. #define DEGLITCH BIT(2)
  28. #define PULL_DOWN BIT(3)
  29. #define DIS_SCHMIT BIT(4)
  30. #define DRIVE_STRENGTH_SHIFT 5
  31. #define DRIVE_STRENGTH_MASK 0x3
  32. #define DRIVE_STRENGTH (DRIVE_STRENGTH_MASK << DRIVE_STRENGTH_SHIFT)
  33. #define OUTPUT BIT(7)
  34. #define OUTPUT_VAL_SHIFT 8
  35. #define OUTPUT_VAL (0x1 << OUTPUT_VAL_SHIFT)
  36. #define SLEWRATE_SHIFT 9
  37. #define SLEWRATE_MASK 0x1
  38. #define SLEWRATE (SLEWRATE_MASK << SLEWRATE_SHIFT)
  39. #define DEBOUNCE BIT(16)
  40. #define DEBOUNCE_VAL_SHIFT 17
  41. #define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT)
  42. /**
  43. * These defines will translated the dt binding settings to our internal
  44. * settings. They are not necessarily the same value as the register setting.
  45. * The actual drive strength current of low, medium and high must be looked up
  46. * from the corresponding device datasheet. This value is different for pins
  47. * that are even in the same banks. It is also dependent on VCC.
  48. * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
  49. * strength when there is no dt config for it.
  50. */
  51. enum drive_strength_bit {
  52. DRIVE_STRENGTH_BIT_DEF,
  53. DRIVE_STRENGTH_BIT_LOW,
  54. DRIVE_STRENGTH_BIT_MED,
  55. DRIVE_STRENGTH_BIT_HI,
  56. };
  57. #define DRIVE_STRENGTH_BIT_MSK(name) (DRIVE_STRENGTH_BIT_##name << \
  58. DRIVE_STRENGTH_SHIFT)
  59. enum slewrate_bit {
  60. SLEWRATE_BIT_DIS,
  61. SLEWRATE_BIT_ENA,
  62. };
  63. #define SLEWRATE_BIT_MSK(name) (SLEWRATE_BIT_##name << SLEWRATE_SHIFT)
  64. enum at91_mux {
  65. AT91_MUX_GPIO = 0,
  66. AT91_MUX_PERIPH_A = 1,
  67. AT91_MUX_PERIPH_B = 2,
  68. AT91_MUX_PERIPH_C = 3,
  69. AT91_MUX_PERIPH_D = 4,
  70. };
  71. /**
  72. * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group
  73. * on new IP with support for periph C and D the way to mux in
  74. * periph A and B has changed
  75. * So provide the right callbacks
  76. * if not present means the IP does not support it
  77. * @mux_A_periph: assign the corresponding pin to the peripheral A function.
  78. * @mux_B_periph: assign the corresponding pin to the peripheral B function.
  79. * @mux_C_periph: assign the corresponding pin to the peripheral C function.
  80. * @mux_D_periph: assign the corresponding pin to the peripheral D function.
  81. * @set_deglitch: enable/disable the deglitch feature.
  82. * @set_debounce: enable/disable the debounce feature.
  83. * @set_pulldown: enable/disable the pulldown feature.
  84. * @disable_schmitt_trig: disable schmitt trigger
  85. */
  86. struct at91_pinctrl_mux_ops {
  87. void (*mux_A_periph)(struct at91_port *pio, u32 mask);
  88. void (*mux_B_periph)(struct at91_port *pio, u32 mask);
  89. void (*mux_C_periph)(struct at91_port *pio, u32 mask);
  90. void (*mux_D_periph)(struct at91_port *pio, u32 mask);
  91. void (*set_deglitch)(struct at91_port *pio, u32 mask, bool is_on);
  92. void (*set_debounce)(struct at91_port *pio, u32 mask, bool is_on,
  93. u32 div);
  94. void (*set_pulldown)(struct at91_port *pio, u32 mask, bool is_on);
  95. void (*disable_schmitt_trig)(struct at91_port *pio, u32 mask);
  96. void (*set_drivestrength)(struct at91_port *pio, u32 pin,
  97. u32 strength);
  98. void (*set_slewrate)(struct at91_port *pio, u32 pin, u32 slewrate);
  99. };
  100. static u32 two_bit_pin_value_shift_amount(u32 pin)
  101. {
  102. /* return the shift value for a pin for "two bit" per pin registers,
  103. * i.e. drive strength */
  104. return 2 * ((pin >= MAX_NB_GPIO_PER_BANK/2)
  105. ? pin - MAX_NB_GPIO_PER_BANK/2 : pin);
  106. }
  107. static void at91_mux_disable_interrupt(struct at91_port *pio, u32 mask)
  108. {
  109. writel(mask, &pio->idr);
  110. }
  111. static void at91_mux_set_pullup(struct at91_port *pio, u32 mask, bool on)
  112. {
  113. if (on)
  114. writel(mask, &pio->mux.pio3.ppddr);
  115. writel(mask, (on ? &pio->puer : &pio->pudr));
  116. }
  117. static void at91_mux_set_output(struct at91_port *pio, unsigned mask,
  118. bool is_on, bool val)
  119. {
  120. writel(mask, (val ? &pio->sodr : &pio->codr));
  121. writel(mask, (is_on ? &pio->oer : &pio->odr));
  122. }
  123. static void at91_mux_set_multidrive(struct at91_port *pio, u32 mask, bool on)
  124. {
  125. writel(mask, (on ? &pio->mder : &pio->mddr));
  126. }
  127. static void at91_mux_set_A_periph(struct at91_port *pio, u32 mask)
  128. {
  129. writel(mask, &pio->mux.pio2.asr);
  130. }
  131. static void at91_mux_set_B_periph(struct at91_port *pio, u32 mask)
  132. {
  133. writel(mask, &pio->mux.pio2.bsr);
  134. }
  135. static void at91_mux_pio3_set_A_periph(struct at91_port *pio, u32 mask)
  136. {
  137. writel(readl(&pio->mux.pio3.abcdsr1) & ~mask, &pio->mux.pio3.abcdsr1);
  138. writel(readl(&pio->mux.pio3.abcdsr2) & ~mask, &pio->mux.pio3.abcdsr2);
  139. }
  140. static void at91_mux_pio3_set_B_periph(struct at91_port *pio, u32 mask)
  141. {
  142. writel(readl(&pio->mux.pio3.abcdsr1) | mask, &pio->mux.pio3.abcdsr1);
  143. writel(readl(&pio->mux.pio3.abcdsr2) & ~mask, &pio->mux.pio3.abcdsr2);
  144. }
  145. static void at91_mux_pio3_set_C_periph(struct at91_port *pio, u32 mask)
  146. {
  147. writel(readl(&pio->mux.pio3.abcdsr1) & ~mask, &pio->mux.pio3.abcdsr1);
  148. writel(readl(&pio->mux.pio3.abcdsr2) | mask, &pio->mux.pio3.abcdsr2);
  149. }
  150. static void at91_mux_pio3_set_D_periph(struct at91_port *pio, u32 mask)
  151. {
  152. writel(readl(&pio->mux.pio3.abcdsr1) | mask, &pio->mux.pio3.abcdsr1);
  153. writel(readl(&pio->mux.pio3.abcdsr2) | mask, &pio->mux.pio3.abcdsr2);
  154. }
  155. static void at91_mux_set_deglitch(struct at91_port *pio, u32 mask, bool is_on)
  156. {
  157. writel(mask, (is_on ? &pio->ifer : &pio->ifdr));
  158. }
  159. static void at91_mux_pio3_set_deglitch(struct at91_port *pio,
  160. u32 mask, bool is_on)
  161. {
  162. if (is_on)
  163. writel(mask, &pio->mux.pio3.ifscdr);
  164. at91_mux_set_deglitch(pio, mask, is_on);
  165. }
  166. static void at91_mux_pio3_set_debounce(struct at91_port *pio, u32 mask,
  167. bool is_on, u32 div)
  168. {
  169. if (is_on) {
  170. writel(mask, &pio->mux.pio3.ifscer);
  171. writel(div & PIO_SCDR_DIV, &pio->mux.pio3.scdr);
  172. writel(mask, &pio->ifer);
  173. } else {
  174. writel(mask, &pio->mux.pio3.ifscdr);
  175. }
  176. }
  177. static void at91_mux_pio3_set_pulldown(struct at91_port *pio,
  178. u32 mask, bool is_on)
  179. {
  180. if (is_on)
  181. writel(mask, &pio->pudr);
  182. writel(mask, (is_on ? &pio->mux.pio3.ppder : &pio->mux.pio3.ppddr));
  183. }
  184. static void at91_mux_pio3_disable_schmitt_trig(struct at91_port *pio,
  185. u32 mask)
  186. {
  187. writel(readl(&pio->schmitt) | mask, &pio->schmitt);
  188. }
  189. static void set_drive_strength(void *reg, u32 pin, u32 strength)
  190. {
  191. u32 shift = two_bit_pin_value_shift_amount(pin);
  192. clrsetbits_le32(reg, DRIVE_STRENGTH_MASK << shift, strength << shift);
  193. }
  194. static void at91_mux_sama5d3_set_drivestrength(struct at91_port *pio,
  195. u32 pin, u32 setting)
  196. {
  197. void *reg;
  198. reg = &pio->driver12;
  199. if (pin >= MAX_NB_GPIO_PER_BANK / 2)
  200. reg = &pio->driver2;
  201. /* do nothing if setting is zero */
  202. if (!setting)
  203. return;
  204. /* strength is 1 to 1 with setting for SAMA5 */
  205. set_drive_strength(reg, pin, setting);
  206. }
  207. static void at91_mux_sam9x5_set_drivestrength(struct at91_port *pio,
  208. u32 pin, u32 setting)
  209. {
  210. void *reg;
  211. reg = &pio->driver1;
  212. if (pin >= MAX_NB_GPIO_PER_BANK / 2)
  213. reg = &pio->driver12;
  214. /* do nothing if setting is zero */
  215. if (!setting)
  216. return;
  217. /* strength is inverse on SAM9x5s with our defines
  218. * 0 = hi, 1 = med, 2 = low, 3 = rsvd */
  219. setting = DRIVE_STRENGTH_BIT_MSK(HI) - setting;
  220. set_drive_strength(reg, pin, setting);
  221. }
  222. static void at91_mux_sam9x60_set_drivestrength(struct at91_port *pio, u32 pin,
  223. u32 setting)
  224. {
  225. void *reg = &pio->driver12;
  226. u32 tmp;
  227. if (setting <= DRIVE_STRENGTH_BIT_DEF ||
  228. setting == DRIVE_STRENGTH_BIT_MED ||
  229. setting > DRIVE_STRENGTH_BIT_HI)
  230. return;
  231. tmp = readl(reg);
  232. /* Strength is 0: low, 1: hi */
  233. if (setting == DRIVE_STRENGTH_BIT_LOW)
  234. tmp &= ~BIT(pin);
  235. else
  236. tmp |= BIT(pin);
  237. writel(tmp, reg);
  238. }
  239. static void at91_mux_sam9x60_set_slewrate(struct at91_port *pio, u32 pin,
  240. u32 setting)
  241. {
  242. void *reg = &pio->reserved12[3];
  243. u32 tmp;
  244. if (setting < SLEWRATE_BIT_DIS || setting > SLEWRATE_BIT_ENA)
  245. return;
  246. tmp = readl(reg);
  247. if (setting == SLEWRATE_BIT_DIS)
  248. tmp &= ~BIT(pin);
  249. else
  250. tmp |= BIT(pin);
  251. writel(tmp, reg);
  252. }
  253. static struct at91_pinctrl_mux_ops at91rm9200_ops = {
  254. .mux_A_periph = at91_mux_set_A_periph,
  255. .mux_B_periph = at91_mux_set_B_periph,
  256. .set_deglitch = at91_mux_set_deglitch,
  257. };
  258. static struct at91_pinctrl_mux_ops at91sam9x5_ops = {
  259. .mux_A_periph = at91_mux_pio3_set_A_periph,
  260. .mux_B_periph = at91_mux_pio3_set_B_periph,
  261. .mux_C_periph = at91_mux_pio3_set_C_periph,
  262. .mux_D_periph = at91_mux_pio3_set_D_periph,
  263. .set_deglitch = at91_mux_pio3_set_deglitch,
  264. .set_debounce = at91_mux_pio3_set_debounce,
  265. .set_pulldown = at91_mux_pio3_set_pulldown,
  266. .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
  267. .set_drivestrength = at91_mux_sam9x5_set_drivestrength,
  268. };
  269. static struct at91_pinctrl_mux_ops sama5d3_ops = {
  270. .mux_A_periph = at91_mux_pio3_set_A_periph,
  271. .mux_B_periph = at91_mux_pio3_set_B_periph,
  272. .mux_C_periph = at91_mux_pio3_set_C_periph,
  273. .mux_D_periph = at91_mux_pio3_set_D_periph,
  274. .set_deglitch = at91_mux_pio3_set_deglitch,
  275. .set_debounce = at91_mux_pio3_set_debounce,
  276. .set_pulldown = at91_mux_pio3_set_pulldown,
  277. .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
  278. .set_drivestrength = at91_mux_sama5d3_set_drivestrength,
  279. };
  280. static struct at91_pinctrl_mux_ops sam9x60_ops = {
  281. .mux_A_periph = at91_mux_pio3_set_A_periph,
  282. .mux_B_periph = at91_mux_pio3_set_B_periph,
  283. .mux_C_periph = at91_mux_pio3_set_C_periph,
  284. .mux_D_periph = at91_mux_pio3_set_D_periph,
  285. .set_deglitch = at91_mux_pio3_set_deglitch,
  286. .set_debounce = at91_mux_pio3_set_debounce,
  287. .set_pulldown = at91_mux_pio3_set_pulldown,
  288. .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
  289. .set_drivestrength = at91_mux_sam9x60_set_drivestrength,
  290. .set_slewrate = at91_mux_sam9x60_set_slewrate,
  291. };
  292. static void at91_mux_gpio_disable(struct at91_port *pio, u32 mask)
  293. {
  294. writel(mask, &pio->pdr);
  295. }
  296. static void at91_mux_gpio_enable(struct at91_port *pio, u32 mask, bool input)
  297. {
  298. writel(mask, &pio->per);
  299. writel(mask, (input ? &pio->odr : &pio->oer));
  300. }
  301. static int at91_pmx_set(struct at91_pinctrl_mux_ops *ops,
  302. struct at91_port *pio, u32 mask, enum at91_mux mux)
  303. {
  304. at91_mux_disable_interrupt(pio, mask);
  305. switch (mux) {
  306. case AT91_MUX_GPIO:
  307. at91_mux_gpio_enable(pio, mask, 1);
  308. break;
  309. case AT91_MUX_PERIPH_A:
  310. ops->mux_A_periph(pio, mask);
  311. break;
  312. case AT91_MUX_PERIPH_B:
  313. ops->mux_B_periph(pio, mask);
  314. break;
  315. case AT91_MUX_PERIPH_C:
  316. if (!ops->mux_C_periph)
  317. return -EINVAL;
  318. ops->mux_C_periph(pio, mask);
  319. break;
  320. case AT91_MUX_PERIPH_D:
  321. if (!ops->mux_D_periph)
  322. return -EINVAL;
  323. ops->mux_D_periph(pio, mask);
  324. break;
  325. }
  326. if (mux)
  327. at91_mux_gpio_disable(pio, mask);
  328. return 0;
  329. }
  330. static int at91_pinconf_set(struct at91_pinctrl_mux_ops *ops,
  331. struct at91_port *pio, u32 pin, u32 config)
  332. {
  333. u32 mask = BIT(pin);
  334. if ((config & PULL_UP) && (config & PULL_DOWN))
  335. return -EINVAL;
  336. at91_mux_set_output(pio, mask, config & OUTPUT,
  337. (config & OUTPUT_VAL) >> OUTPUT_VAL_SHIFT);
  338. at91_mux_set_pullup(pio, mask, config & PULL_UP);
  339. at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE);
  340. if (ops->set_deglitch)
  341. ops->set_deglitch(pio, mask, config & DEGLITCH);
  342. if (ops->set_debounce)
  343. ops->set_debounce(pio, mask, config & DEBOUNCE,
  344. (config & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT);
  345. if (ops->set_pulldown)
  346. ops->set_pulldown(pio, mask, config & PULL_DOWN);
  347. if (ops->disable_schmitt_trig && config & DIS_SCHMIT)
  348. ops->disable_schmitt_trig(pio, mask);
  349. if (ops->set_drivestrength)
  350. ops->set_drivestrength(pio, pin,
  351. (config & DRIVE_STRENGTH) >> DRIVE_STRENGTH_SHIFT);
  352. if (ops->set_slewrate)
  353. ops->set_slewrate(pio, pin,
  354. (config & SLEWRATE) >> SLEWRATE_SHIFT);
  355. return 0;
  356. }
  357. static int at91_pin_check_config(struct udevice *dev, u32 bank, u32 pin)
  358. {
  359. struct at91_pinctrl_priv *priv = dev_get_priv(dev);
  360. if (bank >= priv->nbanks) {
  361. debug("pin conf bank %d >= nbanks %d\n", bank, priv->nbanks);
  362. return -EINVAL;
  363. }
  364. if (pin >= MAX_NB_GPIO_PER_BANK) {
  365. debug("pin conf pin %d >= %d\n", pin, MAX_NB_GPIO_PER_BANK);
  366. return -EINVAL;
  367. }
  368. return 0;
  369. }
  370. static int at91_pinctrl_set_state(struct udevice *dev, struct udevice *config)
  371. {
  372. struct at91_pinctrl_priv *priv = dev_get_priv(dev);
  373. const void *blob = gd->fdt_blob;
  374. int node = dev_of_offset(config);
  375. u32 cells[MAX_PINMUX_ENTRIES];
  376. const u32 *list = cells;
  377. u32 bank, pin;
  378. u32 conf, mask, count, i;
  379. int size;
  380. int ret;
  381. enum at91_mux mux;
  382. struct at91_port *pio;
  383. struct at91_pinctrl_mux_ops *ops =
  384. (struct at91_pinctrl_mux_ops *)dev_get_driver_data(dev);
  385. /*
  386. * the binding format is atmel,pins = <bank pin mux CONFIG ...>,
  387. * do sanity check and calculate pins number
  388. */
  389. size = fdtdec_get_int_array_count(blob, node, "atmel,pins",
  390. cells, ARRAY_SIZE(cells));
  391. /* we do not check return since it's safe node passed down */
  392. count = size >> 2;
  393. if (!count)
  394. return -EINVAL;
  395. for (i = 0; i < count; i++) {
  396. bank = *list++;
  397. pin = *list++;
  398. mux = *list++;
  399. conf = *list++;
  400. ret = at91_pin_check_config(dev, bank, pin);
  401. if (ret)
  402. return ret;
  403. pio = priv->reg_base[bank];
  404. mask = BIT(pin);
  405. ret = at91_pmx_set(ops, pio, mask, mux);
  406. if (ret)
  407. return ret;
  408. ret = at91_pinconf_set(ops, pio, pin, conf);
  409. if (ret)
  410. return ret;
  411. }
  412. return 0;
  413. }
  414. const struct pinctrl_ops at91_pinctrl_ops = {
  415. .set_state = at91_pinctrl_set_state,
  416. };
  417. static int at91_pinctrl_probe(struct udevice *dev)
  418. {
  419. struct at91_pinctrl_priv *priv = dev_get_priv(dev);
  420. fdt_addr_t addr_base;
  421. int index;
  422. for (index = 0; index < MAX_GPIO_BANKS; index++) {
  423. addr_base = devfdt_get_addr_index(dev, index);
  424. if (addr_base == FDT_ADDR_T_NONE)
  425. break;
  426. priv->reg_base[index] = (struct at91_port *)addr_base;
  427. }
  428. priv->nbanks = index;
  429. return 0;
  430. }
  431. static const struct udevice_id at91_pinctrl_match[] = {
  432. { .compatible = "atmel,sama5d3-pinctrl", .data = (ulong)&sama5d3_ops },
  433. { .compatible = "atmel,at91sam9x5-pinctrl", .data = (ulong)&at91sam9x5_ops },
  434. { .compatible = "atmel,at91rm9200-pinctrl", .data = (ulong)&at91rm9200_ops },
  435. { .compatible = "microchip,sam9x60-pinctrl", .data = (ulong)&sam9x60_ops },
  436. {}
  437. };
  438. U_BOOT_DRIVER(atmel_sama5d3_pinctrl) = {
  439. .name = "atmel_sama5d3_pinctrl",
  440. .id = UCLASS_PINCTRL,
  441. .of_match = at91_pinctrl_match,
  442. .probe = at91_pinctrl_probe,
  443. .priv_auto_alloc_size = sizeof(struct at91_pinctrl_priv),
  444. .ops = &at91_pinctrl_ops,
  445. };
  446. U_BOOT_DRIVER_ALIAS(atmel_sama5d3_pinctrl, atmel_at91rm9200_pinctrl)