pinctrl-imx.h 1.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2016 Peng Fan <van.freenix@gmail.com>
  4. */
  5. #ifndef __DRIVERS_PINCTRL_IMX_H
  6. #define __DRIVERS_PINCTRL_IMX_H
  7. /**
  8. * @base: the address to the controller in virtual memory
  9. * @input_sel_base: the address of the select input in virtual memory.
  10. * @flags: flags specific for each soc
  11. * @mux_mask: Used when SHARE_MUX_CONF_REG flag is added
  12. */
  13. struct imx_pinctrl_soc_info {
  14. void __iomem *base;
  15. void __iomem *input_sel_base;
  16. unsigned int flags;
  17. unsigned int mux_mask;
  18. };
  19. /**
  20. * @dev: a pointer back to containing device
  21. * @info: the soc info
  22. */
  23. struct imx_pinctrl_priv {
  24. struct udevice *dev;
  25. struct imx_pinctrl_soc_info *info;
  26. };
  27. extern const struct pinctrl_ops imx_pinctrl_ops;
  28. #define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */
  29. #define IMX_PAD_SION 0x40000000 /* set SION */
  30. /*
  31. * Each pin represented in fsl,pins consists of 5 u32 PIN_FUNC_ID and
  32. * 1 u32 CONFIG, so 24 types in total for each pin.
  33. */
  34. #define FSL_PIN_SIZE 24
  35. #define SHARE_FSL_PIN_SIZE 20
  36. /* Each pin on imx8qm/qxp consists of 2 u32 PIN_FUNC_ID and 1 u32 CONFIG */
  37. #define SHARE_IMX8_PIN_SIZE 12
  38. #define SHARE_MUX_CONF_REG 0x1
  39. #define ZERO_OFFSET_VALID 0x2
  40. #define CONFIG_IBE_OBE 0x4
  41. #define IMX8_USE_SCU 0x8
  42. #define IOMUXC_CONFIG_SION (0x1 << 4)
  43. int imx_pinctrl_probe(struct udevice *dev, struct imx_pinctrl_soc_info *info);
  44. int imx_pinctrl_remove(struct udevice *dev);
  45. #ifdef CONFIG_PINCTRL_IMX_SCU
  46. int imx_pinctrl_scu_conf_pins(struct imx_pinctrl_soc_info *info,
  47. u32 *pin_data, int npins);
  48. #else
  49. static inline int imx_pinctrl_scu_conf_pins(struct imx_pinctrl_soc_info *info,
  50. u32 *pin_data, int npins)
  51. {
  52. return 0;
  53. }
  54. #endif
  55. #endif /* __DRIVERS_PINCTRL_IMX_H */