pinctrl-imx.c 6.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Peng Fan <van.freenix@gmail.com>
  4. */
  5. #include <common.h>
  6. #include <malloc.h>
  7. #include <mapmem.h>
  8. #include <dm/device_compat.h>
  9. #include <dm/devres.h>
  10. #include <linux/bitops.h>
  11. #include <linux/io.h>
  12. #include <linux/err.h>
  13. #include <dm.h>
  14. #include <dm/pinctrl.h>
  15. #include "pinctrl-imx.h"
  16. DECLARE_GLOBAL_DATA_PTR;
  17. static int imx_pinctrl_set_state(struct udevice *dev, struct udevice *config)
  18. {
  19. struct imx_pinctrl_priv *priv = dev_get_priv(dev);
  20. struct imx_pinctrl_soc_info *info = priv->info;
  21. int node = dev_of_offset(config);
  22. const struct fdt_property *prop;
  23. u32 *pin_data;
  24. int npins, size, pin_size;
  25. int mux_reg, conf_reg, input_reg;
  26. u32 input_val, mux_mode, config_val;
  27. u32 mux_shift = info->mux_mask ? ffs(info->mux_mask) - 1 : 0;
  28. int i, j = 0;
  29. dev_dbg(dev, "%s: %s\n", __func__, config->name);
  30. if (info->flags & IMX8_USE_SCU)
  31. pin_size = SHARE_IMX8_PIN_SIZE;
  32. else if (info->flags & SHARE_MUX_CONF_REG)
  33. pin_size = SHARE_FSL_PIN_SIZE;
  34. else
  35. pin_size = FSL_PIN_SIZE;
  36. prop = fdt_getprop(gd->fdt_blob, node, "fsl,pins", &size);
  37. if (!prop) {
  38. dev_err(dev, "No fsl,pins property in node %s\n", config->name);
  39. return -EINVAL;
  40. }
  41. if (!size || size % pin_size) {
  42. dev_err(dev, "Invalid fsl,pins property in node %s\n",
  43. config->name);
  44. return -EINVAL;
  45. }
  46. pin_data = devm_kzalloc(dev, size, 0);
  47. if (!pin_data)
  48. return -ENOMEM;
  49. if (fdtdec_get_int_array(gd->fdt_blob, node, "fsl,pins",
  50. pin_data, size >> 2)) {
  51. dev_err(dev, "Error reading pin data.\n");
  52. devm_kfree(dev, pin_data);
  53. return -EINVAL;
  54. }
  55. npins = size / pin_size;
  56. if (info->flags & IMX8_USE_SCU) {
  57. imx_pinctrl_scu_conf_pins(info, pin_data, npins);
  58. } else {
  59. /*
  60. * Refer to linux documentation for details:
  61. * Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
  62. */
  63. for (i = 0; i < npins; i++) {
  64. mux_reg = pin_data[j++];
  65. if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
  66. mux_reg = -1;
  67. if (info->flags & SHARE_MUX_CONF_REG) {
  68. conf_reg = mux_reg;
  69. } else {
  70. conf_reg = pin_data[j++];
  71. if (!(info->flags & ZERO_OFFSET_VALID) &&
  72. !conf_reg)
  73. conf_reg = -1;
  74. }
  75. if ((mux_reg == -1) || (conf_reg == -1)) {
  76. dev_err(dev, "Error mux_reg or conf_reg\n");
  77. devm_kfree(dev, pin_data);
  78. return -EINVAL;
  79. }
  80. input_reg = pin_data[j++];
  81. mux_mode = pin_data[j++];
  82. input_val = pin_data[j++];
  83. config_val = pin_data[j++];
  84. dev_dbg(dev, "mux_reg 0x%x, conf_reg 0x%x, "
  85. "input_reg 0x%x, mux_mode 0x%x, "
  86. "input_val 0x%x, config_val 0x%x\n",
  87. mux_reg, conf_reg, input_reg, mux_mode,
  88. input_val, config_val);
  89. if (config_val & IMX_PAD_SION)
  90. mux_mode |= IOMUXC_CONFIG_SION;
  91. config_val &= ~IMX_PAD_SION;
  92. /* Set Mux */
  93. if (info->flags & SHARE_MUX_CONF_REG) {
  94. clrsetbits_le32(info->base + mux_reg,
  95. info->mux_mask,
  96. mux_mode << mux_shift);
  97. } else {
  98. writel(mux_mode, info->base + mux_reg);
  99. }
  100. dev_dbg(dev, "write mux: offset 0x%x val 0x%x\n",
  101. mux_reg, mux_mode);
  102. /*
  103. * Set select input
  104. *
  105. * If the select input value begins with 0xff,
  106. * it's a quirky select input and the value should
  107. * be interpreted as below.
  108. * 31 23 15 7 0
  109. * | 0xff | shift | width | select |
  110. * It's used to work around the problem that the
  111. * select input for some pin is not implemented in
  112. * the select input register but in some general
  113. * purpose register. We encode the select input
  114. * value, width and shift of the bit field into
  115. * input_val cell of pin function ID in device tree,
  116. * and then decode them here for setting up the select
  117. * input bits in general purpose register.
  118. */
  119. if (input_val >> 24 == 0xff) {
  120. u32 val = input_val;
  121. u8 select = val & 0xff;
  122. u8 width = (val >> 8) & 0xff;
  123. u8 shift = (val >> 16) & 0xff;
  124. u32 mask = ((1 << width) - 1) << shift;
  125. /*
  126. * The input_reg[i] here is actually some
  127. * IOMUXC general purpose register, not
  128. * regular select input register.
  129. */
  130. val = readl(info->base + input_reg);
  131. val &= ~mask;
  132. val |= select << shift;
  133. writel(val, info->base + input_reg);
  134. } else if (input_reg) {
  135. /*
  136. * Regular select input register can never be
  137. * at offset 0, and we only print register
  138. * value for regular case.
  139. */
  140. if (info->input_sel_base)
  141. writel(input_val,
  142. info->input_sel_base +
  143. input_reg);
  144. else
  145. writel(input_val,
  146. info->base + input_reg);
  147. dev_dbg(dev, "select_input: offset 0x%x val "
  148. "0x%x\n", input_reg, input_val);
  149. }
  150. /* Set config */
  151. if (!(config_val & IMX_NO_PAD_CTL)) {
  152. if (info->flags & SHARE_MUX_CONF_REG) {
  153. clrsetbits_le32(info->base + conf_reg,
  154. ~info->mux_mask,
  155. config_val);
  156. } else {
  157. writel(config_val,
  158. info->base + conf_reg);
  159. }
  160. dev_dbg(dev, "write config: offset 0x%x val "
  161. "0x%x\n", conf_reg, config_val);
  162. }
  163. }
  164. }
  165. devm_kfree(dev, pin_data);
  166. return 0;
  167. }
  168. const struct pinctrl_ops imx_pinctrl_ops = {
  169. .set_state = imx_pinctrl_set_state,
  170. };
  171. int imx_pinctrl_probe(struct udevice *dev,
  172. struct imx_pinctrl_soc_info *info)
  173. {
  174. struct imx_pinctrl_priv *priv = dev_get_priv(dev);
  175. int node = dev_of_offset(dev), ret;
  176. struct fdtdec_phandle_args arg;
  177. fdt_addr_t addr;
  178. fdt_size_t size;
  179. if (!info) {
  180. dev_err(dev, "wrong pinctrl info\n");
  181. return -EINVAL;
  182. }
  183. priv->dev = dev;
  184. priv->info = info;
  185. if (info->flags & IMX8_USE_SCU)
  186. return 0;
  187. addr = devfdt_get_addr_size_index(dev, 0, &size);
  188. if (addr == FDT_ADDR_T_NONE)
  189. return -EINVAL;
  190. info->base = map_sysmem(addr, size);
  191. if (!info->base)
  192. return -ENOMEM;
  193. priv->info = info;
  194. info->mux_mask = fdtdec_get_int(gd->fdt_blob, node, "fsl,mux_mask", 0);
  195. /*
  196. * Refer to linux documentation for details:
  197. * Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
  198. */
  199. if (fdtdec_get_bool(gd->fdt_blob, node, "fsl,input-sel")) {
  200. ret = fdtdec_parse_phandle_with_args(gd->fdt_blob,
  201. node, "fsl,input-sel",
  202. NULL, 0, 0, &arg);
  203. if (ret) {
  204. dev_err(dev, "iomuxc fsl,input-sel property not found\n");
  205. return -EINVAL;
  206. }
  207. addr = fdtdec_get_addr_size(gd->fdt_blob, arg.node, "reg",
  208. &size);
  209. if (addr == FDT_ADDR_T_NONE)
  210. return -EINVAL;
  211. info->input_sel_base = map_sysmem(addr, size);
  212. if (!info->input_sel_base)
  213. return -ENOMEM;
  214. }
  215. dev_dbg(dev, "initialized IMX pinctrl driver\n");
  216. return 0;
  217. }
  218. int imx_pinctrl_remove(struct udevice *dev)
  219. {
  220. struct imx_pinctrl_priv *priv = dev_get_priv(dev);
  221. struct imx_pinctrl_soc_info *info = priv->info;
  222. if (info->flags & IMX8_USE_SCU)
  223. return 0;
  224. if (info->input_sel_base)
  225. unmap_sysmem(info->input_sel_base);
  226. if (info->base)
  227. unmap_sysmem(info->base);
  228. return 0;
  229. }