pinctrl-armada-37xx.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * U-Boot Marvell 37xx SoC pinctrl driver
  4. *
  5. * Copyright (C) 2017 Stefan Roese <sr@denx.de>
  6. *
  7. * This driver is based on the Linux driver version, which is:
  8. * Copyright (C) 2017 Marvell
  9. * Gregory CLEMENT <gregory.clement@free-electrons.com>
  10. *
  11. * Additionally parts are derived from the Meson U-Boot pinctrl driver,
  12. * which is:
  13. * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
  14. * Based on code from Linux kernel:
  15. * Copyright (C) 2016 Endless Mobile, Inc.
  16. * https://spdx.org/licenses
  17. */
  18. #include <common.h>
  19. #include <config.h>
  20. #include <dm.h>
  21. #include <malloc.h>
  22. #include <dm/device-internal.h>
  23. #include <dm/device_compat.h>
  24. #include <dm/devres.h>
  25. #include <dm/lists.h>
  26. #include <dm/pinctrl.h>
  27. #include <dm/root.h>
  28. #include <errno.h>
  29. #include <fdtdec.h>
  30. #include <regmap.h>
  31. #include <asm/gpio.h>
  32. #include <asm/system.h>
  33. #include <asm/io.h>
  34. #include <linux/bitops.h>
  35. #include <linux/libfdt.h>
  36. DECLARE_GLOBAL_DATA_PTR;
  37. #define OUTPUT_EN 0x0
  38. #define INPUT_VAL 0x10
  39. #define OUTPUT_VAL 0x18
  40. #define OUTPUT_CTL 0x20
  41. #define SELECTION 0x30
  42. #define IRQ_EN 0x0
  43. #define IRQ_POL 0x08
  44. #define IRQ_STATUS 0x10
  45. #define IRQ_WKUP 0x18
  46. #define NB_FUNCS 3
  47. #define GPIO_PER_REG 32
  48. /**
  49. * struct armada_37xx_pin_group: represents group of pins of a pinmux function.
  50. * The pins of a pinmux groups are composed of one or two groups of contiguous
  51. * pins.
  52. * @name: Name of the pin group, used to lookup the group.
  53. * @start_pins: Index of the first pin of the main range of pins belonging to
  54. * the group
  55. * @npins: Number of pins included in the first range
  56. * @reg_mask: Bit mask matching the group in the selection register
  57. * @extra_pins: Index of the first pin of the optional second range of pins
  58. * belonging to the group
  59. * @npins: Number of pins included in the second optional range
  60. * @funcs: A list of pinmux functions that can be selected for this group.
  61. * @pins: List of the pins included in the group
  62. */
  63. struct armada_37xx_pin_group {
  64. const char *name;
  65. unsigned int start_pin;
  66. unsigned int npins;
  67. u32 reg_mask;
  68. u32 val[NB_FUNCS];
  69. unsigned int extra_pin;
  70. unsigned int extra_npins;
  71. const char *funcs[NB_FUNCS];
  72. unsigned int *pins;
  73. };
  74. struct armada_37xx_pin_data {
  75. u8 nr_pins;
  76. char *name;
  77. struct armada_37xx_pin_group *groups;
  78. int ngroups;
  79. };
  80. struct armada_37xx_pmx_func {
  81. const char *name;
  82. const char **groups;
  83. unsigned int ngroups;
  84. };
  85. struct armada_37xx_pinctrl {
  86. void __iomem *base;
  87. const struct armada_37xx_pin_data *data;
  88. struct udevice *dev;
  89. struct pinctrl_dev *pctl_dev;
  90. struct armada_37xx_pin_group *groups;
  91. unsigned int ngroups;
  92. struct armada_37xx_pmx_func *funcs;
  93. unsigned int nfuncs;
  94. };
  95. #define PIN_GRP(_name, _start, _nr, _mask, _func1, _func2) \
  96. { \
  97. .name = _name, \
  98. .start_pin = _start, \
  99. .npins = _nr, \
  100. .reg_mask = _mask, \
  101. .val = {0, _mask}, \
  102. .funcs = {_func1, _func2} \
  103. }
  104. #define PIN_GRP_GPIO(_name, _start, _nr, _mask, _func1) \
  105. { \
  106. .name = _name, \
  107. .start_pin = _start, \
  108. .npins = _nr, \
  109. .reg_mask = _mask, \
  110. .val = {0, _mask}, \
  111. .funcs = {_func1, "gpio"} \
  112. }
  113. #define PIN_GRP_GPIO_2(_name, _start, _nr, _mask, _val1, _val2, _func1) \
  114. { \
  115. .name = _name, \
  116. .start_pin = _start, \
  117. .npins = _nr, \
  118. .reg_mask = _mask, \
  119. .val = {_val1, _val2}, \
  120. .funcs = {_func1, "gpio"} \
  121. }
  122. #define PIN_GRP_GPIO_3(_name, _start, _nr, _mask, _v1, _v2, _v3, _f1, _f2) \
  123. { \
  124. .name = _name, \
  125. .start_pin = _start, \
  126. .npins = _nr, \
  127. .reg_mask = _mask, \
  128. .val = {_v1, _v2, _v3}, \
  129. .funcs = {_f1, _f2, "gpio"} \
  130. }
  131. #define PIN_GRP_EXTRA(_name, _start, _nr, _mask, _v1, _v2, _start2, _nr2, \
  132. _f1, _f2) \
  133. { \
  134. .name = _name, \
  135. .start_pin = _start, \
  136. .npins = _nr, \
  137. .reg_mask = _mask, \
  138. .val = {_v1, _v2}, \
  139. .extra_pin = _start2, \
  140. .extra_npins = _nr2, \
  141. .funcs = {_f1, _f2} \
  142. }
  143. static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
  144. PIN_GRP_GPIO("jtag", 20, 5, BIT(0), "jtag"),
  145. PIN_GRP_GPIO("sdio0", 8, 3, BIT(1), "sdio"),
  146. PIN_GRP_GPIO("emmc_nb", 27, 9, BIT(2), "emmc"),
  147. PIN_GRP_GPIO("pwm0", 11, 1, BIT(3), "pwm"),
  148. PIN_GRP_GPIO("pwm1", 12, 1, BIT(4), "pwm"),
  149. PIN_GRP_GPIO("pwm2", 13, 1, BIT(5), "pwm"),
  150. PIN_GRP_GPIO("pwm3", 14, 1, BIT(6), "pwm"),
  151. PIN_GRP_GPIO("pmic1", 7, 1, BIT(7), "pmic"),
  152. PIN_GRP_GPIO("pmic0", 6, 1, BIT(8), "pmic"),
  153. PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"),
  154. PIN_GRP_GPIO("i2c1", 0, 2, BIT(10), "i2c"),
  155. PIN_GRP_GPIO("spi_cs1", 17, 1, BIT(12), "spi"),
  156. PIN_GRP_GPIO_2("spi_cs2", 18, 1, BIT(13) | BIT(19), 0, BIT(13), "spi"),
  157. PIN_GRP_GPIO_2("spi_cs3", 19, 1, BIT(14) | BIT(19), 0, BIT(14), "spi"),
  158. PIN_GRP_GPIO("onewire", 4, 1, BIT(16), "onewire"),
  159. PIN_GRP_GPIO("uart1", 25, 2, BIT(17), "uart"),
  160. PIN_GRP_GPIO("spi_quad", 15, 2, BIT(18), "spi"),
  161. PIN_GRP_EXTRA("uart2", 9, 2, BIT(1) | BIT(13) | BIT(14) | BIT(19),
  162. BIT(1) | BIT(13) | BIT(14), BIT(1) | BIT(19),
  163. 18, 2, "gpio", "uart"),
  164. PIN_GRP_GPIO("led0_od", 11, 1, BIT(20), "led"),
  165. PIN_GRP_GPIO("led1_od", 12, 1, BIT(21), "led"),
  166. PIN_GRP_GPIO("led2_od", 13, 1, BIT(22), "led"),
  167. PIN_GRP_GPIO("led3_od", 14, 1, BIT(23), "led"),
  168. };
  169. static struct armada_37xx_pin_group armada_37xx_sb_groups[] = {
  170. PIN_GRP_GPIO("usb32_drvvbus0", 0, 1, BIT(0), "drvbus"),
  171. PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"),
  172. PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"),
  173. PIN_GRP_GPIO("rgmii", 6, 12, BIT(3), "mii"),
  174. PIN_GRP_GPIO("smi", 18, 2, BIT(4), "smi"),
  175. PIN_GRP_GPIO("pcie1", 3, 3, BIT(5) | BIT(9) | BIT(10), "pcie"),
  176. PIN_GRP_GPIO("ptp", 20, 3, BIT(11) | BIT(12) | BIT(13), "ptp"),
  177. PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"),
  178. PIN_GRP("ptp_trig", 22, 1, BIT(7), "ptp", "mii"),
  179. PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14),
  180. "mii", "mii_err"),
  181. };
  182. const struct armada_37xx_pin_data armada_37xx_pin_nb = {
  183. .nr_pins = 36,
  184. .name = "GPIO1",
  185. .groups = armada_37xx_nb_groups,
  186. .ngroups = ARRAY_SIZE(armada_37xx_nb_groups),
  187. };
  188. const struct armada_37xx_pin_data armada_37xx_pin_sb = {
  189. .nr_pins = 30,
  190. .name = "GPIO2",
  191. .groups = armada_37xx_sb_groups,
  192. .ngroups = ARRAY_SIZE(armada_37xx_sb_groups),
  193. };
  194. static inline void armada_37xx_update_reg(unsigned int *reg,
  195. unsigned int *offset)
  196. {
  197. /* We never have more than 2 registers */
  198. if (*offset >= GPIO_PER_REG) {
  199. *offset -= GPIO_PER_REG;
  200. *reg += sizeof(u32);
  201. }
  202. }
  203. static int armada_37xx_get_func_reg(struct armada_37xx_pin_group *grp,
  204. const char *func)
  205. {
  206. int f;
  207. for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++)
  208. if (!strcmp(grp->funcs[f], func))
  209. return f;
  210. return -ENOTSUPP;
  211. }
  212. static int armada_37xx_pmx_get_groups_count(struct udevice *dev)
  213. {
  214. struct armada_37xx_pinctrl *info = dev_get_priv(dev);
  215. return info->ngroups;
  216. }
  217. static const char *armada_37xx_pmx_dummy_name = "_dummy";
  218. static const char *armada_37xx_pmx_get_group_name(struct udevice *dev,
  219. unsigned selector)
  220. {
  221. struct armada_37xx_pinctrl *info = dev_get_priv(dev);
  222. if (!info->groups[selector].name)
  223. return armada_37xx_pmx_dummy_name;
  224. return info->groups[selector].name;
  225. }
  226. static int armada_37xx_pmx_get_funcs_count(struct udevice *dev)
  227. {
  228. struct armada_37xx_pinctrl *info = dev_get_priv(dev);
  229. return info->nfuncs;
  230. }
  231. static const char *armada_37xx_pmx_get_func_name(struct udevice *dev,
  232. unsigned selector)
  233. {
  234. struct armada_37xx_pinctrl *info = dev_get_priv(dev);
  235. return info->funcs[selector].name;
  236. }
  237. static int armada_37xx_pmx_set_by_name(struct udevice *dev,
  238. const char *name,
  239. struct armada_37xx_pin_group *grp)
  240. {
  241. struct armada_37xx_pinctrl *info = dev_get_priv(dev);
  242. unsigned int reg = SELECTION;
  243. unsigned int mask = grp->reg_mask;
  244. int func, val;
  245. dev_dbg(info->dev, "enable function %s group %s\n",
  246. name, grp->name);
  247. func = armada_37xx_get_func_reg(grp, name);
  248. if (func < 0)
  249. return func;
  250. val = grp->val[func];
  251. clrsetbits_le32(info->base + reg, mask, val);
  252. return 0;
  253. }
  254. static int armada_37xx_pmx_group_set(struct udevice *dev,
  255. unsigned group_selector,
  256. unsigned func_selector)
  257. {
  258. struct armada_37xx_pinctrl *info = dev_get_priv(dev);
  259. struct armada_37xx_pin_group *grp = &info->groups[group_selector];
  260. const char *name = info->funcs[func_selector].name;
  261. return armada_37xx_pmx_set_by_name(dev, name, grp);
  262. }
  263. /**
  264. * armada_37xx_add_function() - Add a new function to the list
  265. * @funcs: array of function to add the new one
  266. * @funcsize: size of the remaining space for the function
  267. * @name: name of the function to add
  268. *
  269. * If it is a new function then create it by adding its name else
  270. * increment the number of group associated to this function.
  271. */
  272. static int armada_37xx_add_function(struct armada_37xx_pmx_func *funcs,
  273. int *funcsize, const char *name)
  274. {
  275. int i = 0;
  276. if (*funcsize <= 0)
  277. return -EOVERFLOW;
  278. while (funcs->ngroups) {
  279. /* function already there */
  280. if (strcmp(funcs->name, name) == 0) {
  281. funcs->ngroups++;
  282. return -EEXIST;
  283. }
  284. funcs++;
  285. i++;
  286. }
  287. /* append new unique function */
  288. funcs->name = name;
  289. funcs->ngroups = 1;
  290. (*funcsize)--;
  291. return 0;
  292. }
  293. /**
  294. * armada_37xx_fill_group() - complete the group array
  295. * @info: info driver instance
  296. *
  297. * Based on the data available from the armada_37xx_pin_group array
  298. * completes the last member of the struct for each function: the list
  299. * of the groups associated to this function.
  300. *
  301. */
  302. static int armada_37xx_fill_group(struct armada_37xx_pinctrl *info)
  303. {
  304. int n, num = 0, funcsize = info->data->nr_pins;
  305. for (n = 0; n < info->ngroups; n++) {
  306. struct armada_37xx_pin_group *grp = &info->groups[n];
  307. int i, j, f;
  308. grp->pins = devm_kzalloc(info->dev,
  309. (grp->npins + grp->extra_npins) *
  310. sizeof(*grp->pins), GFP_KERNEL);
  311. if (!grp->pins)
  312. return -ENOMEM;
  313. for (i = 0; i < grp->npins; i++)
  314. grp->pins[i] = grp->start_pin + i;
  315. for (j = 0; j < grp->extra_npins; j++)
  316. grp->pins[i+j] = grp->extra_pin + j;
  317. for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++) {
  318. int ret;
  319. /* check for unique functions and count groups */
  320. ret = armada_37xx_add_function(info->funcs, &funcsize,
  321. grp->funcs[f]);
  322. if (ret == -EOVERFLOW)
  323. dev_err(info->dev,
  324. "More functions than pins(%d)\n",
  325. info->data->nr_pins);
  326. if (ret < 0)
  327. continue;
  328. num++;
  329. }
  330. }
  331. info->nfuncs = num;
  332. return 0;
  333. }
  334. /**
  335. * armada_37xx_fill_funcs() - complete the funcs array
  336. * @info: info driver instance
  337. *
  338. * Based on the data available from the armada_37xx_pin_group array
  339. * completes the last two member of the struct for each group:
  340. * - the list of the pins included in the group
  341. * - the list of pinmux functions that can be selected for this group
  342. *
  343. */
  344. static int armada_37xx_fill_func(struct armada_37xx_pinctrl *info)
  345. {
  346. struct armada_37xx_pmx_func *funcs = info->funcs;
  347. int n;
  348. for (n = 0; n < info->nfuncs; n++) {
  349. const char *name = funcs[n].name;
  350. const char **groups;
  351. int g;
  352. funcs[n].groups = devm_kzalloc(info->dev, funcs[n].ngroups *
  353. sizeof(*(funcs[n].groups)),
  354. GFP_KERNEL);
  355. if (!funcs[n].groups)
  356. return -ENOMEM;
  357. groups = funcs[n].groups;
  358. for (g = 0; g < info->ngroups; g++) {
  359. struct armada_37xx_pin_group *gp = &info->groups[g];
  360. int f;
  361. for (f = 0; (f < NB_FUNCS) && gp->funcs[f]; f++) {
  362. if (strcmp(gp->funcs[f], name) == 0) {
  363. *groups = gp->name;
  364. groups++;
  365. }
  366. }
  367. }
  368. }
  369. return 0;
  370. }
  371. static int armada_37xx_gpio_get(struct udevice *dev, unsigned int offset)
  372. {
  373. struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
  374. unsigned int reg = INPUT_VAL;
  375. unsigned int val, mask;
  376. armada_37xx_update_reg(&reg, &offset);
  377. mask = BIT(offset);
  378. val = readl(info->base + reg);
  379. return (val & mask) != 0;
  380. }
  381. static int armada_37xx_gpio_set(struct udevice *dev, unsigned int offset,
  382. int value)
  383. {
  384. struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
  385. unsigned int reg = OUTPUT_VAL;
  386. unsigned int mask, val;
  387. armada_37xx_update_reg(&reg, &offset);
  388. mask = BIT(offset);
  389. val = value ? mask : 0;
  390. clrsetbits_le32(info->base + reg, mask, val);
  391. return 0;
  392. }
  393. static int armada_37xx_gpio_get_direction(struct udevice *dev,
  394. unsigned int offset)
  395. {
  396. struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
  397. unsigned int reg = OUTPUT_EN;
  398. unsigned int val, mask;
  399. armada_37xx_update_reg(&reg, &offset);
  400. mask = BIT(offset);
  401. val = readl(info->base + reg);
  402. if (val & mask)
  403. return GPIOF_OUTPUT;
  404. else
  405. return GPIOF_INPUT;
  406. }
  407. static int armada_37xx_gpio_direction_input(struct udevice *dev,
  408. unsigned int offset)
  409. {
  410. struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
  411. unsigned int reg = OUTPUT_EN;
  412. unsigned int mask;
  413. armada_37xx_update_reg(&reg, &offset);
  414. mask = BIT(offset);
  415. clrbits_le32(info->base + reg, mask);
  416. return 0;
  417. }
  418. static int armada_37xx_gpio_direction_output(struct udevice *dev,
  419. unsigned int offset, int value)
  420. {
  421. struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
  422. unsigned int reg = OUTPUT_EN;
  423. unsigned int mask;
  424. armada_37xx_update_reg(&reg, &offset);
  425. mask = BIT(offset);
  426. setbits_le32(info->base + reg, mask);
  427. /* And set the requested value */
  428. return armada_37xx_gpio_set(dev, offset, value);
  429. }
  430. static int armada_37xx_gpio_probe(struct udevice *dev)
  431. {
  432. struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
  433. struct gpio_dev_priv *uc_priv;
  434. uc_priv = dev_get_uclass_priv(dev);
  435. uc_priv->bank_name = info->data->name;
  436. uc_priv->gpio_count = info->data->nr_pins;
  437. return 0;
  438. }
  439. static const struct dm_gpio_ops armada_37xx_gpio_ops = {
  440. .set_value = armada_37xx_gpio_set,
  441. .get_value = armada_37xx_gpio_get,
  442. .get_function = armada_37xx_gpio_get_direction,
  443. .direction_input = armada_37xx_gpio_direction_input,
  444. .direction_output = armada_37xx_gpio_direction_output,
  445. };
  446. static struct driver armada_37xx_gpio_driver = {
  447. .name = "armada-37xx-gpio",
  448. .id = UCLASS_GPIO,
  449. .probe = armada_37xx_gpio_probe,
  450. .ops = &armada_37xx_gpio_ops,
  451. };
  452. static int armada_37xx_gpiochip_register(struct udevice *parent,
  453. struct armada_37xx_pinctrl *info)
  454. {
  455. const void *blob = gd->fdt_blob;
  456. int node = dev_of_offset(parent);
  457. struct uclass_driver *drv;
  458. struct udevice *dev;
  459. int ret = -ENODEV;
  460. int subnode;
  461. char *name;
  462. /* Lookup GPIO driver */
  463. drv = lists_uclass_lookup(UCLASS_GPIO);
  464. if (!drv) {
  465. puts("Cannot find GPIO driver\n");
  466. return -ENOENT;
  467. }
  468. fdt_for_each_subnode(subnode, blob, node) {
  469. if (fdtdec_get_bool(blob, subnode, "gpio-controller")) {
  470. ret = 0;
  471. break;
  472. }
  473. };
  474. if (ret)
  475. return ret;
  476. name = calloc(1, 32);
  477. sprintf(name, "armada-37xx-gpio");
  478. /* Create child device UCLASS_GPIO and bind it */
  479. device_bind(parent, &armada_37xx_gpio_driver, name, NULL, subnode,
  480. &dev);
  481. dev_set_of_offset(dev, subnode);
  482. return 0;
  483. }
  484. const struct pinctrl_ops armada_37xx_pinctrl_ops = {
  485. .get_groups_count = armada_37xx_pmx_get_groups_count,
  486. .get_group_name = armada_37xx_pmx_get_group_name,
  487. .get_functions_count = armada_37xx_pmx_get_funcs_count,
  488. .get_function_name = armada_37xx_pmx_get_func_name,
  489. .pinmux_group_set = armada_37xx_pmx_group_set,
  490. .set_state = pinctrl_generic_set_state,
  491. };
  492. int armada_37xx_pinctrl_probe(struct udevice *dev)
  493. {
  494. struct armada_37xx_pinctrl *info = dev_get_priv(dev);
  495. const struct armada_37xx_pin_data *pin_data;
  496. int ret;
  497. info->data = (struct armada_37xx_pin_data *)dev_get_driver_data(dev);
  498. pin_data = info->data;
  499. info->base = dev_read_addr_ptr(dev);
  500. if (!info->base) {
  501. pr_err("unable to find regmap\n");
  502. return -ENODEV;
  503. }
  504. info->groups = pin_data->groups;
  505. info->ngroups = pin_data->ngroups;
  506. /*
  507. * we allocate functions for number of pins and hope there are
  508. * fewer unique functions than pins available
  509. */
  510. info->funcs = devm_kzalloc(info->dev, pin_data->nr_pins *
  511. sizeof(struct armada_37xx_pmx_func), GFP_KERNEL);
  512. if (!info->funcs)
  513. return -ENOMEM;
  514. ret = armada_37xx_fill_group(info);
  515. if (ret)
  516. return ret;
  517. ret = armada_37xx_fill_func(info);
  518. if (ret)
  519. return ret;
  520. ret = armada_37xx_gpiochip_register(dev, info);
  521. if (ret)
  522. return ret;
  523. return 0;
  524. }
  525. static const struct udevice_id armada_37xx_pinctrl_of_match[] = {
  526. {
  527. .compatible = "marvell,armada3710-sb-pinctrl",
  528. .data = (ulong)&armada_37xx_pin_sb,
  529. },
  530. {
  531. .compatible = "marvell,armada3710-nb-pinctrl",
  532. .data = (ulong)&armada_37xx_pin_nb,
  533. },
  534. { /* sentinel */ }
  535. };
  536. U_BOOT_DRIVER(armada_37xx_pinctrl) = {
  537. .name = "armada-37xx-pinctrl",
  538. .id = UCLASS_PINCTRL,
  539. .of_match = of_match_ptr(armada_37xx_pinctrl_of_match),
  540. .probe = armada_37xx_pinctrl_probe,
  541. .priv_auto_alloc_size = sizeof(struct armada_37xx_pinctrl),
  542. .ops = &armada_37xx_pinctrl_ops,
  543. };