pinctrl-ocelot.c 4.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202
  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /*
  3. * Microsemi SoCs pinctrl driver
  4. *
  5. * Author: <alexandre.belloni@free-electrons.com>
  6. * Author: <gregory.clement@bootlin.com>
  7. * License: Dual MIT/GPL
  8. * Copyright (c) 2017 Microsemi Corporation
  9. */
  10. #include <asm/gpio.h>
  11. #include <asm/system.h>
  12. #include <common.h>
  13. #include <config.h>
  14. #include <dm.h>
  15. #include <dm/device-internal.h>
  16. #include <dm/lists.h>
  17. #include <dm/pinctrl.h>
  18. #include <dm/root.h>
  19. #include <errno.h>
  20. #include <fdtdec.h>
  21. #include <linux/io.h>
  22. #include "mscc-common.h"
  23. enum {
  24. FUNC_NONE,
  25. FUNC_GPIO,
  26. FUNC_IRQ0_IN,
  27. FUNC_IRQ0_OUT,
  28. FUNC_IRQ1_IN,
  29. FUNC_IRQ1_OUT,
  30. FUNC_MIIM1,
  31. FUNC_PCI_WAKE,
  32. FUNC_PTP0,
  33. FUNC_PTP1,
  34. FUNC_PTP2,
  35. FUNC_PTP3,
  36. FUNC_PWM,
  37. FUNC_RECO_CLK0,
  38. FUNC_RECO_CLK1,
  39. FUNC_SFP0,
  40. FUNC_SFP1,
  41. FUNC_SFP2,
  42. FUNC_SFP3,
  43. FUNC_SFP4,
  44. FUNC_SFP5,
  45. FUNC_SG0,
  46. FUNC_SI,
  47. FUNC_TACHO,
  48. FUNC_TWI,
  49. FUNC_TWI_SCL_M,
  50. FUNC_UART,
  51. FUNC_UART2,
  52. FUNC_MAX
  53. };
  54. static char * const ocelot_function_names[] = {
  55. [FUNC_NONE] = "none",
  56. [FUNC_GPIO] = "gpio",
  57. [FUNC_IRQ0_IN] = "irq0_in",
  58. [FUNC_IRQ0_OUT] = "irq0_out",
  59. [FUNC_IRQ1_IN] = "irq1_in",
  60. [FUNC_IRQ1_OUT] = "irq1_out",
  61. [FUNC_MIIM1] = "miim1",
  62. [FUNC_PCI_WAKE] = "pci_wake",
  63. [FUNC_PTP0] = "ptp0",
  64. [FUNC_PTP1] = "ptp1",
  65. [FUNC_PTP2] = "ptp2",
  66. [FUNC_PTP3] = "ptp3",
  67. [FUNC_PWM] = "pwm",
  68. [FUNC_RECO_CLK0] = "reco_clk0",
  69. [FUNC_RECO_CLK1] = "reco_clk1",
  70. [FUNC_SFP0] = "sfp0",
  71. [FUNC_SFP1] = "sfp1",
  72. [FUNC_SFP2] = "sfp2",
  73. [FUNC_SFP3] = "sfp3",
  74. [FUNC_SFP4] = "sfp4",
  75. [FUNC_SFP5] = "sfp5",
  76. [FUNC_SG0] = "sg0",
  77. [FUNC_SI] = "si",
  78. [FUNC_TACHO] = "tacho",
  79. [FUNC_TWI] = "twi",
  80. [FUNC_TWI_SCL_M] = "twi_scl_m",
  81. [FUNC_UART] = "uart",
  82. [FUNC_UART2] = "uart2",
  83. };
  84. MSCC_P(0, SG0, NONE, NONE);
  85. MSCC_P(1, SG0, NONE, NONE);
  86. MSCC_P(2, SG0, NONE, NONE);
  87. MSCC_P(3, SG0, NONE, NONE);
  88. MSCC_P(4, IRQ0_IN, IRQ0_OUT, TWI);
  89. MSCC_P(5, IRQ1_IN, IRQ1_OUT, PCI_WAKE);
  90. MSCC_P(6, UART, TWI_SCL_M, NONE);
  91. MSCC_P(7, UART, TWI_SCL_M, NONE);
  92. MSCC_P(8, SI, TWI_SCL_M, IRQ0_OUT);
  93. MSCC_P(9, SI, TWI_SCL_M, IRQ1_OUT);
  94. MSCC_P(10, PTP2, TWI_SCL_M, SFP0);
  95. MSCC_P(11, PTP3, TWI_SCL_M, SFP1);
  96. MSCC_P(12, UART2, TWI_SCL_M, SFP2);
  97. MSCC_P(13, UART2, TWI_SCL_M, SFP3);
  98. MSCC_P(14, MIIM1, TWI_SCL_M, SFP4);
  99. MSCC_P(15, MIIM1, TWI_SCL_M, SFP5);
  100. MSCC_P(16, TWI, NONE, SI);
  101. MSCC_P(17, TWI, TWI_SCL_M, SI);
  102. MSCC_P(18, PTP0, TWI_SCL_M, NONE);
  103. MSCC_P(19, PTP1, TWI_SCL_M, NONE);
  104. MSCC_P(20, RECO_CLK0, TACHO, NONE);
  105. MSCC_P(21, RECO_CLK1, PWM, NONE);
  106. #define OCELOT_PIN(n) { \
  107. .name = "GPIO_"#n, \
  108. .drv_data = &mscc_pin_##n \
  109. }
  110. static const struct mscc_pin_data ocelot_pins[] = {
  111. OCELOT_PIN(0),
  112. OCELOT_PIN(1),
  113. OCELOT_PIN(2),
  114. OCELOT_PIN(3),
  115. OCELOT_PIN(4),
  116. OCELOT_PIN(5),
  117. OCELOT_PIN(6),
  118. OCELOT_PIN(7),
  119. OCELOT_PIN(8),
  120. OCELOT_PIN(9),
  121. OCELOT_PIN(10),
  122. OCELOT_PIN(11),
  123. OCELOT_PIN(12),
  124. OCELOT_PIN(13),
  125. OCELOT_PIN(14),
  126. OCELOT_PIN(15),
  127. OCELOT_PIN(16),
  128. OCELOT_PIN(17),
  129. OCELOT_PIN(18),
  130. OCELOT_PIN(19),
  131. OCELOT_PIN(20),
  132. OCELOT_PIN(21),
  133. };
  134. static const unsigned long ocelot_gpios[] = {
  135. [MSCC_GPIO_OUT_SET] = 0x00,
  136. [MSCC_GPIO_OUT_CLR] = 0x04,
  137. [MSCC_GPIO_OUT] = 0x08,
  138. [MSCC_GPIO_IN] = 0x0c,
  139. [MSCC_GPIO_OE] = 0x10,
  140. [MSCC_GPIO_INTR] = 0x14,
  141. [MSCC_GPIO_INTR_ENA] = 0x18,
  142. [MSCC_GPIO_INTR_IDENT] = 0x1c,
  143. [MSCC_GPIO_ALT0] = 0x20,
  144. [MSCC_GPIO_ALT1] = 0x24,
  145. };
  146. static int ocelot_gpio_probe(struct udevice *dev)
  147. {
  148. struct gpio_dev_priv *uc_priv;
  149. uc_priv = dev_get_uclass_priv(dev);
  150. uc_priv->bank_name = "ocelot-gpio";
  151. uc_priv->gpio_count = ARRAY_SIZE(ocelot_pins);
  152. return 0;
  153. }
  154. static struct driver ocelot_gpio_driver = {
  155. .name = "ocelot-gpio",
  156. .id = UCLASS_GPIO,
  157. .probe = ocelot_gpio_probe,
  158. .ops = &mscc_gpio_ops,
  159. };
  160. int ocelot_pinctrl_probe(struct udevice *dev)
  161. {
  162. int ret;
  163. ret = mscc_pinctrl_probe(dev, FUNC_MAX, ocelot_pins,
  164. ARRAY_SIZE(ocelot_pins),
  165. ocelot_function_names,
  166. ocelot_gpios);
  167. if (ret)
  168. return ret;
  169. ret = device_bind(dev, &ocelot_gpio_driver, "ocelot-gpio", NULL,
  170. dev_of_offset(dev), NULL);
  171. return ret;
  172. }
  173. static const struct udevice_id ocelot_pinctrl_of_match[] = {
  174. {.compatible = "mscc,ocelot-pinctrl"},
  175. {},
  176. };
  177. U_BOOT_DRIVER(ocelot_pinctrl) = {
  178. .name = "ocelot-pinctrl",
  179. .id = UCLASS_PINCTRL,
  180. .of_match = of_match_ptr(ocelot_pinctrl_of_match),
  181. .probe = ocelot_pinctrl_probe,
  182. .priv_auto_alloc_size = sizeof(struct mscc_pinctrl),
  183. .ops = &mscc_pinctrl_ops,
  184. };